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gem5/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt

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Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
---------- Begin Simulation Statistics ----------
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
sim_seconds 0.000009 # Number of seconds simulated
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
sim_ticks 9350000 # Number of ticks simulated
final_tick 9350000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
host_inst_rate 14656 # Simulator instruction rate (inst/s)
host_op_rate 14654 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 57391857 # Simulator tick rate (ticks/s)
host_mem_usage 269408 # Number of bytes of host memory used
host_seconds 0.16 # Real time elapsed on the host
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
sim_insts 2387 # Number of instructions simulated
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
sim_ops 2387 # Number of ops (including micro ops) simulated
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.physmem.bytes_read::cpu.inst 11968 # Number of bytes read from this memory
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.physmem.bytes_read::cpu.data 5440 # Number of bytes read from this memory
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.physmem.bytes_read::total 17408 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 11968 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 11968 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 187 # Number of read requests responded to by this memory
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.physmem.num_reads::total 272 # Number of read requests responded to by this memory
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.bw_read::cpu.inst 1280000000 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 581818182 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1861818182 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1280000000 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1280000000 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1280000000 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 581818182 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1861818182 # Total bandwidth to/from this memory (bytes/s)
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.physmem.readReqs 272 # Total number of read requests seen
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.writeReqs 0 # Total number of write requests seen
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.physmem.cpureqs 272 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 17408 # Total number of bytes read from memory
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.bytesWritten 0 # Total number of bytes written to memory
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.physmem.bytesConsumedRd 17408 # bytesRead derated as per pkt->getSize()
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.perBankRdReqs::0 39 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 25 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 22 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 9 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 22 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 7 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 6 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 19 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 6 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 17 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 29 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 16 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 16 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 18 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 21 # Track reads on a per bank basis
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.totGap 9280500 # Total gap between requests
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.physmem.readPktSize::6 272 # Categorize read packet sizes
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 0 # Categorize write packet sizes
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.rdQLenPdf::0 148 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 87 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 26 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 9 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.physmem.totQLat 1327750 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 7871500 # Sum of mem lat for all requests
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.totBusLat 1360000 # Total cycles spent in databus access
system.physmem.totBankLat 5183750 # Total cycles spent in bank access
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.physmem.avgQLat 4881.43 # Average queueing delay per request
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.avgBankLat 19057.90 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.physmem.avgMemAccLat 28939.34 # Average memory access latency
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.avgRdBW 1861.82 # Average achieved read bandwidth in MB/s
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.avgConsumedRdBW 1861.82 # Average consumed read bandwidth in MB/s
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 14.55 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.84 # Average read queue length over time
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.avgWrQLen 0.00 # Average write queue length over time
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.readRowHits 207 # Number of row buffer hits during reads
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.readRowHitRate 76.10 # Row buffer hit rate for reads
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.avgGap 34119.49 # Average gap between requests
system.cpu.branchPred.lookups 1154 # Number of BP lookups
system.cpu.branchPred.condPredicted 581 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 258 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 791 # Number of BTB lookups
system.cpu.branchPred.BTBHits 226 # Number of BTB hits
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.branchPred.BTBHitPct 28.571429 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 224 # Number of times the RAS was used to get a target.
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu.branchPred.RASInCorrect 39 # Number of incorrect RAS predictions.
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.dtb.read_hits 708 # DTB read hits
system.cpu.dtb.read_misses 28 # DTB read misses
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.dtb.read_acv 1 # DTB read access violations
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.dtb.read_accesses 736 # DTB read accesses
system.cpu.dtb.write_hits 357 # DTB write hits
system.cpu.dtb.write_misses 20 # DTB write misses
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.dtb.write_acv 0 # DTB write access violations
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.dtb.write_accesses 377 # DTB write accesses
system.cpu.dtb.data_hits 1065 # DTB hits
system.cpu.dtb.data_misses 48 # DTB misses
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.dtb.data_acv 1 # DTB access violations
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.dtb.data_accesses 1113 # DTB accesses
system.cpu.itb.fetch_hits 1043 # ITB hits
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.itb.fetch_misses 30 # ITB misses
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.itb.fetch_acv 0 # ITB acv
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.itb.fetch_accesses 1073 # ITB accesses
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4 # Number of system calls
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.numCycles 18701 # number of cpu cycles simulated
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu.fetch.icacheStallCycles 4191 # Number of cycles fetch is stalled on an Icache miss
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.fetch.Insts 6947 # Number of instructions fetch has processed
system.cpu.fetch.Branches 1154 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 450 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 1194 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 869 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 306 # Number of cycles fetch has spent blocked
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.fetch.MiscStallCycles 18 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.fetch.PendingTrapStallCycles 1024 # Number of stall cycles due to pending traps
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.fetch.CacheLines 1043 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 182 # Number of outstanding Icache misses that were squashed
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu.fetch.rateDist::samples 7322 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 0.948784 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.362451 # Number of instructions fetched each cycle (Total)
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu.fetch.rateDist::0 6128 83.69% 83.69% # Number of instructions fetched each cycle (Total)
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.fetch.rateDist::1 54 0.74% 84.43% # Number of instructions fetched each cycle (Total)
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu.fetch.rateDist::2 114 1.56% 85.99% # Number of instructions fetched each cycle (Total)
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.fetch.rateDist::3 92 1.26% 87.24% # Number of instructions fetched each cycle (Total)
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu.fetch.rateDist::4 168 2.29% 89.54% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 73 1.00% 90.54% # Number of instructions fetched each cycle (Total)
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.fetch.rateDist::6 64 0.87% 91.41% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 64 0.87% 92.28% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 565 7.72% 100.00% # Number of instructions fetched each cycle (Total)
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu.fetch.rateDist::total 7322 # Number of instructions fetched each cycle (Total)
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.fetch.branchRate 0.061708 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.371477 # Number of inst fetches per cycle
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu.decode.IdleCycles 5334 # Number of cycles decode is idle
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.decode.BlockedCycles 332 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 1148 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 8 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 500 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 167 # Number of times decode resolved a branch
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.decode.BranchMispred 81 # Number of times decode detected a branch misprediction
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.decode.DecodedInsts 6173 # Number of instructions handled by decode
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.decode.SquashedInsts 293 # Number of squashed instructions handled by decode
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.rename.SquashCycles 500 # Number of cycles rename is squashing
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu.rename.IdleCycles 5434 # Number of cycles rename is idle
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.rename.BlockCycles 109 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 186 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 1056 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 37 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 5903 # Number of instructions processed by rename
system.cpu.rename.IQFullEvents 10 # Number of times rename has blocked due to IQ full
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.rename.LSQFullEvents 16 # Number of times rename has blocked due to LSQ full
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.rename.RenamedOperands 4293 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 6642 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 6630 # Number of integer rename lookups
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.rename.fp_rename_lookups 12 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.rename.UndoneMaps 2525 # Number of HB maps that are undone due to squashing
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.rename.serializingInsts 8 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.rename.skidInsts 133 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 964 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 466 # Number of stores inserted to the mem dependence unit.
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores.
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.iq.iqInstsAdded 5010 # Number of instructions added to the IQ (excludes non-spec)
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.iq.iqInstsIssued 4065 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 53 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 2458 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 1421 # Number of squashed operands that are examined and possibly removed from graph
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu.iq.issued_per_cycle::samples 7322 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.555176 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.266886 # Number of insts issued each cycle
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu.iq.issued_per_cycle::0 5697 77.81% 77.81% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 561 7.66% 85.47% # Number of insts issued each cycle
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.iq.issued_per_cycle::2 397 5.42% 90.89% # Number of insts issued each cycle
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu.iq.issued_per_cycle::3 261 3.56% 94.46% # Number of insts issued each cycle
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.iq.issued_per_cycle::4 207 2.83% 97.28% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 126 1.72% 99.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 50 0.68% 99.69% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 15 0.20% 99.89% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 8 0.11% 100.00% # Number of insts issued each cycle
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu.iq.issued_per_cycle::total 7322 # Number of insts issued each cycle
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.iq.fu_full::IntAlu 2 4.35% 4.35% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 4.35% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 4.35% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.35% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.35% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.35% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 4.35% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.35% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.35% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.35% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.35% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.35% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.35% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.35% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.35% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 4.35% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.35% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 4.35% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.35% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.35% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.35% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.35% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.35% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.35% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.35% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.35% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.35% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.35% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.35% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 21 45.65% 50.00% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 23 50.00% 100.00% # attempts to use FU when none available
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.iq.FU_type_0::IntAlu 2890 71.09% 71.09% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 1 0.02% 71.12% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.12% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.12% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.12% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.12% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.12% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.12% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.12% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 787 19.36% 90.48% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 387 9.52% 100.00% # Type of FU issued
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.iq.FU_type_0::total 4065 # Type of FU issued
system.cpu.iq.rate 0.217368 # Inst issue rate
system.cpu.iq.fu_busy_cnt 46 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.011316 # FU busy rate (busy events/executed inst)
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu.iq.int_inst_queue_reads 15538 # Number of integer instruction queue reads
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.iq.int_inst_queue_writes 7472 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 3658 # Number of integer instruction queue wakeup accesses
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.iq.int_alu_accesses 4104 # Number of integer alu accesses
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.iew.lsq.thread0.forwLoads 36 # Number of loads that had data forwarded from stores
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.iew.lsq.thread0.squashedLoads 549 # Number of loads squashed
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.iew.lsq.thread0.memOrderViolation 5 # Number of memory ordering violations
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.iew.lsq.thread0.squashedStores 172 # Number of stores squashed
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.iew.lsq.thread0.cacheBlocked 10 # Number of times an access to memory failed due to the cache being blocked
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.iew.iewSquashCycles 500 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 100 # Number of cycles IEW is blocking
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.iew.iewUnblockCycles 4 # Number of cycles IEW is unblocking
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.iew.iewDispatchedInsts 5355 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 129 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 964 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 466 # Number of dispatched store instructions
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.iew.memOrderViolationEvents 5 # Number of memory order violations
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.iew.predictedTakenIncorrect 56 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 159 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 215 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 3852 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 737 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 213 # Number of squashed instructions skipped in execute
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.iew.exec_nop 339 # number of nop insts executed
system.cpu.iew.exec_refs 1114 # number of memory reference insts executed
system.cpu.iew.exec_branches 649 # Number of branches executed
system.cpu.iew.exec_stores 377 # Number of stores executed
system.cpu.iew.exec_rate 0.205978 # Inst execution rate
system.cpu.iew.wb_sent 3743 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 3664 # cumulative count of insts written-back
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu.iew.wb_producers 1729 # num instructions producing a value
system.cpu.iew.wb_consumers 2228 # num instructions consuming a value
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.iew.wb_rate 0.195925 # insts written-back per cycle
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu.iew.wb_fanout 0.776032 # average fanout of values written-back
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.commit.commitSquashedInsts 2758 # The number of squashed insts skipped by commit
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.commit.branchMispredicts 180 # The number of times a branch was mispredicted
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu.commit.committed_per_cycle::samples 6822 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.377602 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.238659 # Number of insts commited each cycle
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu.commit.committed_per_cycle::0 5958 87.34% 87.34% # Number of insts commited each cycle
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.commit.committed_per_cycle::1 201 2.95% 90.28% # Number of insts commited each cycle
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu.commit.committed_per_cycle::2 310 4.54% 94.83% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 116 1.70% 96.53% # Number of insts commited each cycle
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.commit.committed_per_cycle::4 63 0.92% 97.45% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 50 0.73% 98.18% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 32 0.47% 98.65% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 23 0.34% 98.99% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 69 1.01% 100.00% # Number of insts commited each cycle
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu.commit.committed_per_cycle::total 6822 # Number of insts commited each cycle
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.commit.committedInsts 2576 # Number of instructions committed
system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 709 # Number of memory references committed
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu.commit.loads 415 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.commit.branches 396 # Number of branches committed
system.cpu.commit.fp_insts 6 # Number of committed floating point instructions.
system.cpu.commit.int_insts 2367 # Number of committed integer instructions.
system.cpu.commit.function_calls 71 # Number of function calls committed.
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.commit.bw_lim_events 69 # number cycles where commit BW limit reached
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu.rob.rob_reads 11840 # The number of ROB reads
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.rob.rob_writes 11181 # The number of ROB writes
system.cpu.timesIdled 163 # Number of times that the entire CPU went into an idle state and unscheduled itself
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu.idleCycles 11379 # Total number of cycles that the CPU has spent unscheduled due to idling
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
system.cpu.committedInsts 2387 # Number of Instructions Simulated
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
system.cpu.committedInsts_total 2387 # Number of Instructions Simulated
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.cpi 7.834520 # CPI: Cycles Per Instruction
system.cpu.cpi_total 7.834520 # CPI: Total CPI of All Threads
system.cpu.ipc 0.127640 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.127640 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 4649 # number of integer regfile reads
system.cpu.int_regfile_writes 2842 # number of integer regfile writes
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.fp_regfile_reads 6 # number of floating regfile reads
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
system.cpu.icache.replacements 0 # number of replacements
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.icache.tagsinuse 90.926534 # Cycle average of tags in use
system.cpu.icache.total_refs 794 # Total number of references to valid blocks.
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.icache.sampled_refs 187 # Sample count of references to valid blocks.
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.icache.avg_refs 4.245989 # Average number of references to valid blocks.
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.icache.occ_blocks::cpu.inst 90.926534 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.044398 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.044398 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 794 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 794 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 794 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 794 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 794 # number of overall hits
system.cpu.icache.overall_hits::total 794 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 249 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 249 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 249 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 249 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 249 # number of overall misses
system.cpu.icache.overall_misses::total 249 # number of overall misses
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu.icache.ReadReq_miss_latency::cpu.inst 12418499 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 12418499 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 12418499 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 12418499 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 12418499 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 12418499 # number of overall miss cycles
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.icache.ReadReq_accesses::cpu.inst 1043 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 1043 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 1043 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 1043 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 1043 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 1043 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.238734 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.238734 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.238734 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.238734 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.238734 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.238734 # miss rate for overall accesses
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49873.489960 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 49873.489960 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 49873.489960 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 49873.489960 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 49873.489960 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 49873.489960 # average overall miss latency
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.icache.blocked_cycles::no_mshrs 160 # number of cycles access was blocked
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.icache.avg_blocked_cycles::no_mshrs 53.333333 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 62 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 62 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 62 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 62 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 62 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 62 # number of overall MSHR hits
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 187 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 187 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 187 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 187 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 187 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 187 # number of overall MSHR misses
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9624999 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 9624999 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9624999 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 9624999 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9624999 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 9624999 # number of overall MSHR miss cycles
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.179291 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.179291 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.179291 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.179291 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.179291 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.179291 # mshr miss rate for overall accesses
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51470.582888 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51470.582888 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51470.582888 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 51470.582888 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51470.582888 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 51470.582888 # average overall mshr miss latency
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.l2cache.tagsinuse 119.099647 # Cycle average of tags in use
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.l2cache.sampled_refs 248 # Sample count of references to valid blocks.
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.l2cache.occ_blocks::cpu.inst 91.174754 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 27.924893 # Average occupied blocks per requestor
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.l2cache.occ_percent::cpu.inst 0.002782 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.000852 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.003635 # Average percentage of cache occupancy
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.l2cache.ReadReq_misses::cpu.inst 187 # number of ReadReq misses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.ReadReq_misses::cpu.data 61 # number of ReadReq misses
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.l2cache.ReadReq_misses::total 248 # number of ReadReq misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadExReq_misses::cpu.data 24 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 24 # number of ReadExReq misses
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.l2cache.demand_misses::cpu.inst 187 # number of demand (read+write) misses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.demand_misses::cpu.data 85 # number of demand (read+write) misses
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.l2cache.demand_misses::total 272 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 187 # number of overall misses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.l2cache.overall_misses::total 272 # number of overall misses
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 9437000 # number of ReadReq miss cycles
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3587500 # number of ReadReq miss cycles
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu.l2cache.ReadReq_miss_latency::total 13024500 # number of ReadReq miss cycles
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1408000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 1408000 # number of ReadExReq miss cycles
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu.l2cache.demand_miss_latency::cpu.inst 9437000 # number of demand (read+write) miss cycles
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.l2cache.demand_miss_latency::cpu.data 4995500 # number of demand (read+write) miss cycles
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu.l2cache.demand_miss_latency::total 14432500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 9437000 # number of overall miss cycles
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.l2cache.overall_miss_latency::cpu.data 4995500 # number of overall miss cycles
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu.l2cache.overall_miss_latency::total 14432500 # number of overall miss cycles
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.l2cache.ReadReq_accesses::cpu.inst 187 # number of ReadReq accesses(hits+misses)
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.ReadReq_accesses::cpu.data 61 # number of ReadReq accesses(hits+misses)
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.l2cache.ReadReq_accesses::total 248 # number of ReadReq accesses(hits+misses)
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadExReq_accesses::cpu.data 24 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 24 # number of ReadExReq accesses(hits+misses)
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.l2cache.demand_accesses::cpu.inst 187 # number of demand (read+write) accesses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.demand_accesses::cpu.data 85 # number of demand (read+write) accesses
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.l2cache.demand_accesses::total 272 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 187 # number of overall (read+write) accesses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.overall_accesses::cpu.data 85 # number of overall (read+write) accesses
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.l2cache.overall_accesses::total 272 # number of overall (read+write) accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.demand_miss_rate::total 1 # miss rate for demand accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50465.240642 # average ReadReq miss latency
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58811.475410 # average ReadReq miss latency
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52518.145161 # average ReadReq miss latency
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 58666.666667 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 58666.666667 # average ReadExReq miss latency
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50465.240642 # average overall miss latency
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 58770.588235 # average overall miss latency
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu.l2cache.demand_avg_miss_latency::total 53060.661765 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50465.240642 # average overall miss latency
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 58770.588235 # average overall miss latency
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu.l2cache.overall_avg_miss_latency::total 53060.661765 # average overall miss latency
stats: update reference outputs now that compatibility is gone Because of the initialization bug, it wasn't consistent anyway.
2009-04-22 19:25:17 +02:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 187 # number of ReadReq MSHR misses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.l2cache.ReadReq_mshr_misses::total 248 # number of ReadReq MSHR misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 24 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 24 # number of ReadExReq MSHR misses
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.l2cache.demand_mshr_misses::cpu.inst 187 # number of demand (read+write) MSHR misses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.demand_mshr_misses::cpu.data 85 # number of demand (read+write) MSHR misses
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.l2cache.demand_mshr_misses::total 272 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 187 # number of overall MSHR misses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.l2cache.overall_mshr_misses::total 272 # number of overall MSHR misses
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 7116144 # number of ReadReq MSHR miss cycles
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2838783 # number of ReadReq MSHR miss cycles
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9954927 # number of ReadReq MSHR miss cycles
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1114012 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1114012 # number of ReadExReq MSHR miss cycles
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7116144 # number of demand (read+write) MSHR miss cycles
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3952795 # number of demand (read+write) MSHR miss cycles
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu.l2cache.demand_mshr_miss_latency::total 11068939 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7116144 # number of overall MSHR miss cycles
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3952795 # number of overall MSHR miss cycles
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu.l2cache.overall_mshr_miss_latency::total 11068939 # number of overall MSHR miss cycles
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38054.245989 # average ReadReq mshr miss latency
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46537.426230 # average ReadReq mshr miss latency
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40140.834677 # average ReadReq mshr miss latency
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 46417.166667 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 46417.166667 # average ReadExReq mshr miss latency
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38054.245989 # average overall mshr miss latency
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 46503.470588 # average overall mshr miss latency
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40694.628676 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38054.245989 # average overall mshr miss latency
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 46503.470588 # average overall mshr miss latency
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40694.628676 # average overall mshr miss latency
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.dcache.replacements 0 # number of replacements
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.dcache.tagsinuse 44.507812 # Cycle average of tags in use
system.cpu.dcache.total_refs 763 # Total number of references to valid blocks.
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks.
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.dcache.avg_refs 8.976471 # Average number of references to valid blocks.
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.dcache.occ_blocks::cpu.data 44.507812 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.010866 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.010866 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 550 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 550 # number of ReadReq hits
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.dcache.WriteReq_hits::cpu.data 213 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 213 # number of WriteReq hits
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.dcache.demand_hits::cpu.data 763 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 763 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 763 # number of overall hits
system.cpu.dcache.overall_hits::total 763 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 112 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 112 # number of ReadReq misses
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.dcache.demand_misses::cpu.data 193 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 193 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 193 # number of overall misses
system.cpu.dcache.overall_misses::total 193 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5526500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 5526500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4429500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 4429500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 9956000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 9956000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 9956000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 9956000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 662 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 662 # number of ReadReq accesses(hits+misses)
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses)
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.dcache.demand_accesses::cpu.data 956 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 956 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 956 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 956 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.169184 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.169184 # miss rate for ReadReq accesses
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.275510 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.275510 # miss rate for WriteReq accesses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.dcache.demand_miss_rate::cpu.data 0.201883 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.201883 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.201883 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.201883 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49343.750000 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 49343.750000 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54685.185185 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 54685.185185 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 51585.492228 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 51585.492228 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 51585.492228 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 51585.492228 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 88 # number of cycles access was blocked
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.dcache.avg_blocked_cycles::no_mshrs 29.333333 # average number of cycles each access was blocked
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 51 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 51 # number of ReadReq MSHR hits
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 57 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 57 # number of WriteReq MSHR hits
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.dcache.demand_mshr_hits::cpu.data 108 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 108 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 108 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 108 # number of overall MSHR hits
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 61 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 24 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 24 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 85 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3648500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3648500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1433500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1433500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5082000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 5082000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5082000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 5082000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.092145 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.092145 # mshr miss rate for ReadReq accesses
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081633 # mshr miss rate for WriteReq accesses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.088912 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.088912 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.088912 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.088912 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59811.475410 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59811.475410 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59729.166667 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59729.166667 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 59788.235294 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 59788.235294 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 59788.235294 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 59788.235294 # average overall mshr miss latency
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink