2006-09-01 23:59:36 +02:00
---------- Begin Simulation Statistics ----------
2016-10-14 00:21:40 +02:00
sim_seconds 0.000024 # Number of seconds simulated
sim_ticks 23776000 # Number of ticks simulated
final_tick 23776000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
2011-06-21 00:57:14 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
2016-11-30 23:12:59 +01:00
host_inst_rate 4743 # Simulator instruction rate (inst/s)
host_op_rate 4743 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 17659718 # Simulator tick rate (ticks/s)
host_mem_usage 236044 # Number of bytes of host memory used
host_seconds 1.35 # Real time elapsed on the host
2016-03-17 18:32:53 +01:00
sim_insts 6385 # Number of instructions simulated
sim_ops 6385 # Number of ops (including micro ops) simulated
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
2016-10-14 00:21:40 +02:00
system.physmem.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states
2016-04-08 18:01:45 +02:00
system.physmem.bytes_read::cpu.inst 19968 # Number of bytes read from this memory
2016-03-17 18:32:53 +01:00
system.physmem.bytes_read::cpu.data 11072 # Number of bytes read from this memory
2016-04-08 18:01:45 +02:00
system.physmem.bytes_read::total 31040 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 19968 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 19968 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 312 # Number of read requests responded to by this memory
2016-03-17 18:32:53 +01:00
system.physmem.num_reads::cpu.data 173 # Number of read requests responded to by this memory
2016-04-08 18:01:45 +02:00
system.physmem.num_reads::total 485 # Number of read requests responded to by this memory
2016-10-14 00:21:40 +02:00
system.physmem.bw_read::cpu.inst 839838493 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 465679677 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1305518170 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 839838493 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 839838493 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 839838493 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 465679677 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1305518170 # Total bandwidth to/from this memory (bytes/s)
2016-04-08 18:01:45 +02:00
system.physmem.readReqs 485 # Number of read requests accepted
2013-11-01 16:56:34 +01:00
system.physmem.writeReqs 0 # Number of write requests accepted
2016-04-08 18:01:45 +02:00
system.physmem.readBursts 485 # Number of DRAM read bursts, including those serviced by the write queue
2013-11-01 16:56:34 +01:00
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
2016-04-08 18:01:45 +02:00
system.physmem.bytesReadDRAM 31040 # Total number of bytes read from DRAM
2013-11-01 16:56:34 +01:00
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
2016-04-08 18:01:45 +02:00
system.physmem.bytesReadSys 31040 # Total read bytes from the system interface side
2013-11-01 16:56:34 +01:00
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
2016-04-08 18:01:45 +02:00
system.physmem.perBankRdBursts::0 69 # Per bank write bursts
2015-09-15 15:14:09 +02:00
system.physmem.perBankRdBursts::1 32 # Per bank write bursts
2016-04-08 18:01:45 +02:00
system.physmem.perBankRdBursts::2 33 # Per bank write bursts
2013-11-01 16:56:34 +01:00
system.physmem.perBankRdBursts::3 47 # Per bank write bursts
2016-03-17 18:32:53 +01:00
system.physmem.perBankRdBursts::4 42 # Per bank write bursts
2014-09-03 13:42:59 +02:00
system.physmem.perBankRdBursts::5 20 # Per bank write bursts
2013-11-01 16:56:34 +01:00
system.physmem.perBankRdBursts::6 1 # Per bank write bursts
system.physmem.perBankRdBursts::7 3 # Per bank write bursts
system.physmem.perBankRdBursts::8 0 # Per bank write bursts
system.physmem.perBankRdBursts::9 1 # Per bank write bursts
2015-03-02 11:04:20 +01:00
system.physmem.perBankRdBursts::10 22 # Per bank write bursts
2014-09-03 13:42:59 +02:00
system.physmem.perBankRdBursts::11 25 # Per bank write bursts
2013-11-01 16:56:34 +01:00
system.physmem.perBankRdBursts::12 14 # Per bank write bursts
2015-09-15 15:14:09 +02:00
system.physmem.perBankRdBursts::13 118 # Per bank write bursts
2013-11-01 16:56:34 +01:00
system.physmem.perBankRdBursts::14 45 # Per bank write bursts
2016-03-17 18:32:53 +01:00
system.physmem.perBankRdBursts::15 13 # Per bank write bursts
2013-11-01 16:56:34 +01:00
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
system.physmem.perBankWrBursts::4 0 # Per bank write bursts
system.physmem.perBankWrBursts::5 0 # Per bank write bursts
system.physmem.perBankWrBursts::6 0 # Per bank write bursts
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
system.physmem.perBankWrBursts::10 0 # Per bank write bursts
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
2016-10-14 00:21:40 +02:00
system.physmem.totGap 23381000 # Total gap between requests
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
2016-04-08 18:01:45 +02:00
system.physmem.readPktSize::6 485 # Read request sizes (log2)
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
2016-10-14 00:21:40 +02:00
system.physmem.rdQLenPdf::0 260 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 141 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 52 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 21 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see
2012-10-30 14:35:32 +01:00
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
2016-10-14 00:21:40 +02:00
system.physmem.bytesPerActivate::samples 89 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 348.044944 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 230.274346 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 313.082327 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 21 23.60% 23.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 22 24.72% 48.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 15 16.85% 65.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 9 10.11% 75.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 6 6.74% 82.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 3 3.37% 85.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 2 2.25% 87.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1 1.12% 88.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 10 11.24% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 89 # Bytes accessed per row activation
2016-11-30 23:12:59 +01:00
system.physmem.totQLat 8008750 # Total ticks spent queuing
system.physmem.totMemAccLat 17102500 # Total ticks spent from burst creation until serviced by the DRAM
2016-04-08 18:01:45 +02:00
system.physmem.totBusLat 2425000 # Total ticks spent in databus transfers
2016-11-30 23:12:59 +01:00
system.physmem.avgQLat 16512.89 # Average queueing delay per DRAM burst
2013-11-01 16:56:34 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
2016-11-30 23:12:59 +01:00
system.physmem.avgMemAccLat 35262.89 # Average memory access latency per DRAM burst
2016-10-14 00:21:40 +02:00
system.physmem.avgRdBW 1305.52 # Average DRAM read bandwidth in MiByte/s
2013-11-01 16:56:34 +01:00
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
2016-10-14 00:21:40 +02:00
system.physmem.avgRdBWSys 1305.52 # Average system read bandwidth in MiByte/s
2013-11-01 16:56:34 +01:00
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
2016-10-14 00:21:40 +02:00
system.physmem.busUtil 10.20 # Data bus utilization in percentage
system.physmem.busUtilRead 10.20 # Data bus utilization in percentage for reads
2013-11-01 16:56:34 +01:00
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
2016-10-14 00:21:40 +02:00
system.physmem.avgRdQLen 1.82 # Average read queue length when enqueuing
2013-11-01 16:56:34 +01:00
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
2016-10-14 00:21:40 +02:00
system.physmem.readRowHits 395 # Number of row buffer hits during reads
2012-10-25 19:14:42 +02:00
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
2016-10-14 00:21:40 +02:00
system.physmem.readRowHitRate 81.44 # Row buffer hit rate for reads
2012-10-25 19:14:42 +02:00
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
2016-10-14 00:21:40 +02:00
system.physmem.avgGap 48208.25 # Average gap between requests
system.physmem.pageHitRate 81.44 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 242760 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 125235 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 1763580 # Energy for read commands per rank (pJ)
2014-12-23 15:31:20 +01:00
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
2016-10-14 00:21:40 +02:00
system.physmem_0.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ)
2016-11-30 23:12:59 +01:00
system.physmem_0.actBackEnergy 3004470 # Energy for active background per rank (pJ)
2016-10-14 00:21:40 +02:00
system.physmem_0.preBackEnergy 47520 # Energy for precharge background per rank (pJ)
2016-11-30 23:12:59 +01:00
system.physmem_0.actPowerDownEnergy 7623750 # Energy for active power-down per rank (pJ)
2016-10-14 00:21:40 +02:00
system.physmem_0.prePowerDownEnergy 132480 # Energy for precharge power-down per rank (pJ)
system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
system.physmem_0.totalEnergy 14783715 # Total energy per rank (pJ)
system.physmem_0.averagePower 621.784975 # Core power per rank (mW)
2016-11-30 23:12:59 +01:00
system.physmem_0.totalIdleTime 16958250 # Total Idle time Per DRAM Rank
2016-10-14 00:21:40 +02:00
system.physmem_0.memoryStateTime::IDLE 40500 # Time in different power states
system.physmem_0.memoryStateTime::REF 780000 # Time in different power states
system.physmem_0.memoryStateTime::SREF 0 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 344500 # Time in different power states
2016-11-30 23:12:59 +01:00
system.physmem_0.memoryStateTime::ACT 5899500 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 16711500 # Time in different power states
2016-10-14 00:21:40 +02:00
system.physmem_1.actEnergy 399840 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 212520 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 1699320 # Energy for read commands per rank (pJ)
2014-12-23 15:31:20 +01:00
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
2016-10-14 00:21:40 +02:00
system.physmem_1.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 2978250 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 130080 # Energy for precharge background per rank (pJ)
system.physmem_1.actPowerDownEnergy 7628310 # Energy for active power-down per rank (pJ)
system.physmem_1.prePowerDownEnergy 68160 # Energy for precharge power-down per rank (pJ)
system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
system.physmem_1.totalEnergy 14960400 # Total energy per rank (pJ)
system.physmem_1.averagePower 629.216130 # Core power per rank (mW)
system.physmem_1.totalIdleTime 16769000 # Total Idle time Per DRAM Rank
system.physmem_1.memoryStateTime::IDLE 214000 # Time in different power states
system.physmem_1.memoryStateTime::REF 780000 # Time in different power states
system.physmem_1.memoryStateTime::SREF 0 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 178500 # Time in different power states
system.physmem_1.memoryStateTime::ACT 5875500 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 16728000 # Time in different power states
system.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 2854 # Number of BP lookups
system.cpu.branchPred.condPredicted 1681 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 482 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 2203 # Number of BTB lookups
2016-04-08 18:01:45 +02:00
system.cpu.branchPred.BTBHits 713 # Number of BTB hits
2013-01-24 19:29:00 +01:00
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
2016-10-14 00:21:40 +02:00
system.cpu.branchPred.BTBHitPct 32.364957 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 441 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 42 # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups 462 # Number of indirect predictor lookups.
2016-04-08 18:01:45 +02:00
system.cpu.branchPred.indirectHits 25 # Number of indirect target hits.
2016-10-14 00:21:40 +02:00
system.cpu.branchPred.indirectMisses 437 # Number of indirect misses.
2016-04-08 18:01:45 +02:00
system.cpu.branchPredindirectMispredicted 123 # Number of mispredicted indirect branches.
2014-12-23 15:31:20 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
2009-04-09 07:21:30 +02:00
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
2011-06-21 00:57:14 +02:00
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
2016-10-14 00:21:40 +02:00
system.cpu.dtb.read_hits 2252 # DTB read hits
2016-04-08 18:01:45 +02:00
system.cpu.dtb.read_misses 48 # DTB read misses
2011-06-21 00:57:14 +02:00
system.cpu.dtb.read_acv 0 # DTB read access violations
2016-10-14 00:21:40 +02:00
system.cpu.dtb.read_accesses 2300 # DTB read accesses
system.cpu.dtb.write_hits 1038 # DTB write hits
2015-09-15 15:14:09 +02:00
system.cpu.dtb.write_misses 28 # DTB write misses
2011-06-21 00:57:14 +02:00
system.cpu.dtb.write_acv 0 # DTB write access violations
2016-10-14 00:21:40 +02:00
system.cpu.dtb.write_accesses 1066 # DTB write accesses
system.cpu.dtb.data_hits 3290 # DTB hits
2016-04-08 18:01:45 +02:00
system.cpu.dtb.data_misses 76 # DTB misses
2011-06-21 00:57:14 +02:00
system.cpu.dtb.data_acv 0 # DTB access violations
2016-10-14 00:21:40 +02:00
system.cpu.dtb.data_accesses 3366 # DTB accesses
system.cpu.itb.fetch_hits 2295 # ITB hits
2016-04-08 18:01:45 +02:00
system.cpu.itb.fetch_misses 27 # ITB misses
2011-06-21 00:57:14 +02:00
system.cpu.itb.fetch_acv 0 # ITB acv
2016-10-14 00:21:40 +02:00
system.cpu.itb.fetch_accesses 2322 # ITB accesses
2011-06-21 00:57:14 +02:00
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
2016-10-14 00:21:40 +02:00
system.cpu.pwrStateResidencyTicks::ON 23776000 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 47553 # number of cpu cycles simulated
2011-06-21 00:57:14 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
2016-11-30 23:12:59 +01:00
system.cpu.fetch.icacheStallCycles 8498 # Number of cycles fetch is stalled on an Icache miss
2016-10-14 00:21:40 +02:00
system.cpu.fetch.Insts 16559 # Number of instructions fetch has processed
system.cpu.fetch.Branches 2854 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 1179 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 5759 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 1046 # Number of cycles fetch has spent squashing
2016-04-08 18:01:45 +02:00
system.cpu.fetch.MiscStallCycles 22 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
2016-08-12 15:12:59 +02:00
system.cpu.fetch.PendingTrapStallCycles 656 # Number of stall cycles due to pending traps
2016-10-14 00:21:40 +02:00
system.cpu.fetch.CacheLines 2295 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 335 # Number of outstanding Icache misses that were squashed
2016-11-30 23:12:59 +01:00
system.cpu.fetch.rateDist::samples 15458 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.071225 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.458645 # Number of instructions fetched each cycle (Total)
2009-07-07 00:49:48 +02:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
2016-11-30 23:12:59 +01:00
system.cpu.fetch.rateDist::0 12472 80.68% 80.68% # Number of instructions fetched each cycle (Total)
2016-10-14 00:21:40 +02:00
system.cpu.fetch.rateDist::1 297 1.92% 82.60% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 230 1.49% 84.09% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 258 1.67% 85.76% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 292 1.89% 87.65% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 234 1.51% 89.16% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 282 1.82% 90.99% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 146 0.94% 91.93% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 1247 8.07% 100.00% # Number of instructions fetched each cycle (Total)
2009-07-07 00:49:48 +02:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
2016-11-30 23:12:59 +01:00
system.cpu.fetch.rateDist::total 15458 # Number of instructions fetched each cycle (Total)
2016-10-14 00:21:40 +02:00
system.cpu.fetch.branchRate 0.060017 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.348222 # Number of inst fetches per cycle
2016-11-30 23:12:59 +01:00
system.cpu.decode.IdleCycles 8341 # Number of cycles decode is idle
2016-10-14 00:21:40 +02:00
system.cpu.decode.BlockedCycles 4008 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 2446 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 214 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 449 # Number of cycles decode is squashing
2016-04-08 18:01:45 +02:00
system.cpu.decode.BranchResolved 226 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 75 # Number of times decode detected a branch misprediction
2016-10-14 00:21:40 +02:00
system.cpu.decode.DecodedInsts 15004 # Number of instructions handled by decode
2016-04-08 18:01:45 +02:00
system.cpu.decode.SquashedInsts 221 # Number of squashed instructions handled by decode
2016-10-14 00:21:40 +02:00
system.cpu.rename.SquashCycles 449 # Number of cycles rename is squashing
2016-11-30 23:12:59 +01:00
system.cpu.rename.IdleCycles 8500 # Number of cycles rename is idle
2016-10-14 00:21:40 +02:00
system.cpu.rename.BlockCycles 1841 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 655 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 2476 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 1537 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 14448 # Number of instructions processed by rename
2016-04-08 18:01:45 +02:00
system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 21 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 10 # Number of times rename has blocked due to LQ full
2016-10-14 00:21:40 +02:00
system.cpu.rename.SQFullEvents 1471 # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands 10929 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 17896 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 17887 # Number of integer rename lookups
2013-10-16 16:44:12 +02:00
system.cpu.rename.fp_rename_lookups 8 # Number of floating rename lookups
2016-03-17 18:32:53 +01:00
system.cpu.rename.CommittedMaps 4577 # Number of HB maps that are committed
2016-10-14 00:21:40 +02:00
system.cpu.rename.UndoneMaps 6352 # Number of HB maps that are undone due to squashing
2016-04-08 18:01:45 +02:00
system.cpu.rename.serializingInsts 28 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 22 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 585 # count of insts added to the skid buffer
2016-10-14 00:21:40 +02:00
system.cpu.memDep0.insertedLoads 2834 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 1292 # Number of stores inserted to the mem dependence unit.
2016-04-08 18:01:45 +02:00
system.cpu.memDep0.conflictingLoads 18 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 6 # Number of conflicting stores.
2016-10-14 00:21:40 +02:00
system.cpu.iq.iqInstsAdded 13054 # Number of instructions added to the IQ (excludes non-spec)
2016-04-08 18:01:45 +02:00
system.cpu.iq.iqNonSpecInstsAdded 27 # Number of non-speculative instructions added to the IQ
2016-10-14 00:21:40 +02:00
system.cpu.iq.iqInstsIssued 10776 # Number of instructions issued
2016-04-08 18:01:45 +02:00
system.cpu.iq.iqSquashedInstsIssued 17 # Number of squashed instructions issued
2016-10-14 00:21:40 +02:00
system.cpu.iq.iqSquashedInstsExamined 6695 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 3669 # Number of squashed operands that are examined and possibly removed from graph
2016-04-08 18:01:45 +02:00
system.cpu.iq.iqSquashedNonSpecRemoved 10 # Number of squashed non-spec instructions that were removed
2016-11-30 23:12:59 +01:00
system.cpu.iq.issued_per_cycle::samples 15458 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.697115 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.442161 # Number of insts issued each cycle
2011-06-21 00:57:14 +02:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
2016-11-30 23:12:59 +01:00
system.cpu.iq.issued_per_cycle::0 11418 73.86% 73.86% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 1297 8.39% 82.26% # Number of insts issued each cycle
2016-10-14 00:21:40 +02:00
system.cpu.iq.issued_per_cycle::2 916 5.93% 88.18% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 681 4.41% 92.59% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 517 3.34% 95.93% # Number of insts issued each cycle
2016-11-30 23:12:59 +01:00
system.cpu.iq.issued_per_cycle::5 347 2.24% 98.18% # Number of insts issued each cycle
2016-10-14 00:21:40 +02:00
system.cpu.iq.issued_per_cycle::6 200 1.29% 99.47% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 55 0.36% 99.83% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 27 0.17% 100.00% # Number of insts issued each cycle
2011-06-21 00:57:14 +02:00
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
2016-11-30 23:12:59 +01:00
system.cpu.iq.issued_per_cycle::total 15458 # Number of insts issued each cycle
2011-06-21 00:57:14 +02:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
2016-10-14 00:21:40 +02:00
system.cpu.iq.fu_full::IntAlu 21 14.89% 14.89% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 14.89% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 14.89% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 14.89% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 14.89% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 14.89% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 14.89% # attempts to use FU when none available
2016-10-19 12:20:04 +02:00
system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 14.89% # attempts to use FU when none available
2016-10-14 00:21:40 +02:00
system.cpu.iq.fu_full::FloatDiv 0 0.00% 14.89% # attempts to use FU when none available
2016-10-19 12:20:04 +02:00
system.cpu.iq.fu_full::FloatMisc 0 0.00% 14.89% # attempts to use FU when none available
2016-10-14 00:21:40 +02:00
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 14.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 14.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 14.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 14.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 14.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 14.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 14.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 14.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 14.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 14.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 14.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 14.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 14.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 14.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 14.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 14.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 14.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 14.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 14.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 14.89% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 83 58.87% 73.76% # attempts to use FU when none available
2016-10-19 12:20:04 +02:00
system.cpu.iq.fu_full::MemWrite 36 25.53% 99.29% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMemRead 0 0.00% 99.29% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMemWrite 1 0.71% 100.00% # attempts to use FU when none available
2011-06-21 00:57:14 +02:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
2011-04-20 03:45:23 +02:00
system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued
2016-10-14 00:21:40 +02:00
system.cpu.iq.FU_type_0::IntAlu 7185 66.68% 66.69% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 1 0.01% 66.70% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.70% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 66.72% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.72% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.72% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.72% # Type of FU issued
2016-10-19 12:20:04 +02:00
system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 66.72% # Type of FU issued
2016-10-14 00:21:40 +02:00
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.72% # Type of FU issued
2016-10-19 12:20:04 +02:00
system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 66.72% # Type of FU issued
2016-10-14 00:21:40 +02:00
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.72% # Type of FU issued
2016-10-19 12:20:04 +02:00
system.cpu.iq.FU_type_0::MemRead 2474 22.96% 89.68% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 1104 10.24% 99.93% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMemRead 1 0.01% 99.94% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMemWrite 7 0.06% 100.00% # Type of FU issued
2011-04-20 03:45:23 +02:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
2016-10-14 00:21:40 +02:00
system.cpu.iq.FU_type_0::total 10776 # Type of FU issued
system.cpu.iq.rate 0.226610 # Inst issue rate
system.cpu.iq.fu_busy_cnt 141 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.013085 # FU busy rate (busy events/executed inst)
2016-11-30 23:12:59 +01:00
system.cpu.iq.int_inst_queue_reads 37147 # Number of integer instruction queue reads
2016-10-14 00:21:40 +02:00
system.cpu.iq.int_inst_queue_writes 19787 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 9745 # Number of integer instruction queue wakeup accesses
2011-06-21 00:57:14 +02:00
system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses
2016-10-14 00:21:40 +02:00
system.cpu.iq.int_alu_accesses 10904 # Number of integer alu accesses
2011-06-21 00:57:14 +02:00
system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses
2016-04-08 18:01:45 +02:00
system.cpu.iew.lsq.thread0.forwLoads 119 # Number of loads that had data forwarded from stores
2011-06-21 00:57:14 +02:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
2016-10-14 00:21:40 +02:00
system.cpu.iew.lsq.thread0.squashedLoads 1649 # Number of loads squashed
2016-04-08 18:01:45 +02:00
system.cpu.iew.lsq.thread0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 23 # Number of memory ordering violations
2016-10-14 00:21:40 +02:00
system.cpu.iew.lsq.thread0.squashedStores 427 # Number of stores squashed
2011-06-21 00:57:14 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
2016-10-14 00:21:40 +02:00
system.cpu.iew.lsq.thread0.cacheBlocked 78 # Number of times an access to memory failed due to the cache being blocked
2011-06-21 00:57:14 +02:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
2016-10-14 00:21:40 +02:00
system.cpu.iew.iewSquashCycles 449 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 1429 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 338 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 13165 # Number of instructions dispatched to IQ
2016-04-08 18:01:45 +02:00
system.cpu.iew.iewDispSquashedInsts 125 # Number of squashed instructions skipped by dispatch
2016-10-14 00:21:40 +02:00
system.cpu.iew.iewDispLoadInsts 2834 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 1292 # Number of dispatched store instructions
2016-04-08 18:01:45 +02:00
system.cpu.iew.iewDispNonSpecInsts 27 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall
2016-10-14 00:21:40 +02:00
system.cpu.iew.iewLSQFullEvents 331 # Number of times the LSQ has become full, causing a stall
2016-04-08 18:01:45 +02:00
system.cpu.iew.memOrderViolationEvents 23 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 107 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 390 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 497 # Number of branch mispredicts detected at execute
2016-10-14 00:21:40 +02:00
system.cpu.iew.iewExecutedInsts 10290 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 2300 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 486 # Number of squashed instructions skipped in execute
2011-06-21 00:57:14 +02:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
2016-04-08 18:01:45 +02:00
system.cpu.iew.exec_nop 84 # number of nop insts executed
2016-10-14 00:21:40 +02:00
system.cpu.iew.exec_refs 3376 # number of memory reference insts executed
system.cpu.iew.exec_branches 1642 # Number of branches executed
system.cpu.iew.exec_stores 1076 # Number of stores executed
system.cpu.iew.exec_rate 0.216390 # Inst execution rate
system.cpu.iew.wb_sent 9948 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 9755 # cumulative count of insts written-back
system.cpu.iew.wb_producers 5155 # num instructions producing a value
system.cpu.iew.wb_consumers 7025 # num instructions consuming a value
system.cpu.iew.wb_rate 0.205140 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.733808 # average fanout of values written-back
system.cpu.commit.commitSquashedInsts 6712 # The number of squashed insts skipped by commit
2011-06-21 00:57:14 +02:00
system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
2016-10-14 00:21:40 +02:00
system.cpu.commit.branchMispredicts 408 # The number of times a branch was mispredicted
2016-11-30 23:12:59 +01:00
system.cpu.commit.committed_per_cycle::samples 14221 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.450179 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.361050 # Number of insts commited each cycle
2011-06-21 00:57:14 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
2016-11-30 23:12:59 +01:00
system.cpu.commit.committed_per_cycle::0 11794 82.93% 82.93% # Number of insts commited each cycle
2016-10-14 00:21:40 +02:00
system.cpu.commit.committed_per_cycle::1 1158 8.14% 91.08% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 469 3.30% 94.37% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 205 1.44% 95.82% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 133 0.94% 96.75% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 85 0.60% 97.35% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 97 0.68% 98.03% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 88 0.62% 98.65% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 192 1.35% 100.00% # Number of insts commited each cycle
2011-06-21 00:57:14 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
2016-11-30 23:12:59 +01:00
system.cpu.commit.committed_per_cycle::total 14221 # Number of insts commited each cycle
2016-03-17 18:32:53 +01:00
system.cpu.commit.committedInsts 6402 # Number of instructions committed
system.cpu.commit.committedOps 6402 # Number of ops (including micro ops) committed
2011-06-21 00:57:14 +02:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
2016-03-17 18:32:53 +01:00
system.cpu.commit.refs 2050 # Number of memory references committed
system.cpu.commit.loads 1185 # Number of loads committed
2011-06-21 00:57:14 +02:00
system.cpu.commit.membars 0 # Number of memory barriers committed
2016-03-17 18:32:53 +01:00
system.cpu.commit.branches 1056 # Number of branches committed
2011-06-21 00:57:14 +02:00
system.cpu.commit.fp_insts 10 # Number of committed floating point instructions.
2016-03-17 18:32:53 +01:00
system.cpu.commit.int_insts 6319 # Number of committed integer instructions.
2011-06-21 00:57:14 +02:00
system.cpu.commit.function_calls 127 # Number of function calls committed.
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_0::No_OpClass 19 0.30% 0.30% # Class of committed instruction
2016-03-17 18:32:53 +01:00
system.cpu.commit.op_class_0::IntAlu 4330 67.64% 67.93% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 1 0.02% 67.95% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 0 0.00% 67.95% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 2 0.03% 67.98% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 67.98% # Class of committed instruction
2016-10-19 12:20:04 +02:00
system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 67.98% # Class of committed instruction
2016-03-17 18:32:53 +01:00
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 67.98% # Class of committed instruction
2016-10-19 12:20:04 +02:00
system.cpu.commit.op_class_0::FloatMisc 0 0.00% 67.98% # Class of committed instruction
2016-03-17 18:32:53 +01:00
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.98% # Class of committed instruction
2016-10-19 12:20:04 +02:00
system.cpu.commit.op_class_0::MemRead 1184 18.49% 86.47% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 858 13.40% 99.88% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMemRead 1 0.02% 99.89% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMemWrite 7 0.11% 100.00% # Class of committed instruction
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
2016-03-17 18:32:53 +01:00
system.cpu.commit.op_class_0::total 6402 # Class of committed instruction
2016-04-08 18:01:45 +02:00
system.cpu.commit.bw_lim_events 192 # number cycles where commit BW limit reached
2016-11-30 23:12:59 +01:00
system.cpu.rob.rob_reads 26792 # The number of ROB reads
2016-10-14 00:21:40 +02:00
system.cpu.rob.rob_writes 27482 # The number of ROB writes
2016-08-12 15:12:59 +02:00
system.cpu.timesIdled 250 # Number of times that the entire CPU went into an idle state and unscheduled itself
2016-11-30 23:12:59 +01:00
system.cpu.idleCycles 32095 # Total number of cycles that the CPU has spent unscheduled due to idling
2016-03-17 18:32:53 +01:00
system.cpu.committedInsts 6385 # Number of Instructions Simulated
system.cpu.committedOps 6385 # Number of Ops (including micro ops) Simulated
2016-10-14 00:21:40 +02:00
system.cpu.cpi 7.447612 # CPI: Cycles Per Instruction
system.cpu.cpi_total 7.447612 # CPI: Total CPI of All Threads
system.cpu.ipc 0.134271 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.134271 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 12923 # number of integer regfile reads
system.cpu.int_regfile_writes 7437 # number of integer regfile writes
2011-06-21 00:57:14 +02:00
system.cpu.fp_regfile_reads 8 # number of floating regfile reads
system.cpu.fp_regfile_writes 2 # number of floating regfile writes
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
2016-10-14 00:21:40 +02:00
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states
2014-12-23 15:31:20 +01:00
system.cpu.dcache.tags.replacements 0 # number of replacements
2016-10-14 00:21:40 +02:00
system.cpu.dcache.tags.tagsinuse 110.182603 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 2402 # Total number of references to valid blocks.
2016-03-17 18:32:53 +01:00
system.cpu.dcache.tags.sampled_refs 173 # Sample count of references to valid blocks.
2016-10-14 00:21:40 +02:00
system.cpu.dcache.tags.avg_refs 13.884393 # Average number of references to valid blocks.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2016-10-14 00:21:40 +02:00
system.cpu.dcache.tags.occ_blocks::cpu.data 110.182603 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.026900 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.026900 # Average percentage of cache occupancy
2016-03-17 18:32:53 +01:00
system.cpu.dcache.tags.occ_task_id_blocks::1024 173 # Occupied blocks per task id
2016-10-14 00:21:40 +02:00
system.cpu.dcache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id
2016-03-17 18:32:53 +01:00
system.cpu.dcache.tags.occ_task_id_percent::1024 0.042236 # Percentage of cache occupancy per task id
2016-10-14 00:21:40 +02:00
system.cpu.dcache.tags.tag_accesses 6051 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 6051 # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 1894 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1894 # number of ReadReq hits
2016-08-12 15:12:59 +02:00
system.cpu.dcache.WriteReq_hits::cpu.data 508 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 508 # number of WriteReq hits
2016-10-14 00:21:40 +02:00
system.cpu.dcache.demand_hits::cpu.data 2402 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 2402 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 2402 # number of overall hits
system.cpu.dcache.overall_hits::total 2402 # number of overall hits
2016-04-08 18:01:45 +02:00
system.cpu.dcache.ReadReq_misses::cpu.data 180 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 180 # number of ReadReq misses
2016-08-12 15:12:59 +02:00
system.cpu.dcache.WriteReq_misses::cpu.data 357 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 357 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 537 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 537 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 537 # number of overall misses
system.cpu.dcache.overall_misses::total 537 # number of overall misses
2016-10-14 00:21:40 +02:00
system.cpu.dcache.ReadReq_miss_latency::cpu.data 13953000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 13953000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 31158482 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 31158482 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 45111482 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 45111482 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 45111482 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 45111482 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 2074 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 2074 # number of ReadReq accesses(hits+misses)
2014-12-23 15:31:20 +01:00
system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses)
2016-10-14 00:21:40 +02:00
system.cpu.dcache.demand_accesses::cpu.data 2939 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 2939 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 2939 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 2939 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.086789 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.086789 # miss rate for ReadReq accesses
2016-08-12 15:12:59 +02:00
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.412717 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.412717 # miss rate for WriteReq accesses
2016-10-14 00:21:40 +02:00
system.cpu.dcache.demand_miss_rate::cpu.data 0.182715 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.182715 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.182715 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.182715 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77516.666667 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 77516.666667 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 87278.661064 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 87278.661064 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 84006.484171 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 84006.484171 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 84006.484171 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 84006.484171 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 3098 # number of cycles access was blocked
2014-12-23 15:31:20 +01:00
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2016-10-14 00:21:40 +02:00
system.cpu.dcache.blocked::no_mshrs 37 # number of cycles access was blocked
2014-12-23 15:31:20 +01:00
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
2016-10-14 00:21:40 +02:00
system.cpu.dcache.avg_blocked_cycles::no_mshrs 83.729730 # average number of cycles each access was blocked
2014-12-23 15:31:20 +01:00
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-04-08 18:01:45 +02:00
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 79 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 79 # number of ReadReq MSHR hits
2016-08-12 15:12:59 +02:00
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 285 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 285 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 364 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 364 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 364 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 364 # number of overall MSHR hits
2016-03-17 18:32:53 +01:00
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 101 # number of ReadReq MSHR misses
2014-12-23 15:31:20 +01:00
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 72 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 72 # number of WriteReq MSHR misses
2016-03-17 18:32:53 +01:00
system.cpu.dcache.demand_mshr_misses::cpu.data 173 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 173 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 173 # number of overall MSHR misses
2016-10-14 00:21:40 +02:00
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9401500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 9401500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7013500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 7013500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16415000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 16415000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16415000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 16415000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.048698 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.048698 # mshr miss rate for ReadReq accesses
2014-12-23 15:31:20 +01:00
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses
2016-10-14 00:21:40 +02:00
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.058864 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.058864 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.058864 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.058864 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 93084.158416 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 93084.158416 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 97409.722222 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 97409.722222 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 94884.393064 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 94884.393064 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 94884.393064 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 94884.393064 # average overall mshr miss latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states
2013-08-19 09:52:36 +02:00
system.cpu.icache.tags.replacements 0 # number of replacements
2016-10-14 00:21:40 +02:00
system.cpu.icache.tags.tagsinuse 160.538154 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 1837 # Total number of references to valid blocks.
2016-04-08 18:01:45 +02:00
system.cpu.icache.tags.sampled_refs 313 # Sample count of references to valid blocks.
2016-10-14 00:21:40 +02:00
system.cpu.icache.tags.avg_refs 5.869010 # Average number of references to valid blocks.
2013-08-19 09:52:36 +02:00
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2016-10-14 00:21:40 +02:00
system.cpu.icache.tags.occ_blocks::cpu.inst 160.538154 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.078388 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.078388 # Average percentage of cache occupancy
2016-04-08 18:01:45 +02:00
system.cpu.icache.tags.occ_task_id_blocks::1024 313 # Occupied blocks per task id
2016-10-14 00:21:40 +02:00
system.cpu.icache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 187 # Occupied blocks per task id
2016-04-08 18:01:45 +02:00
system.cpu.icache.tags.occ_task_id_percent::1024 0.152832 # Percentage of cache occupancy per task id
2016-10-14 00:21:40 +02:00
system.cpu.icache.tags.tag_accesses 4903 # Number of tag accesses
system.cpu.icache.tags.data_accesses 4903 # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 1837 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1837 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1837 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 1837 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 1837 # number of overall hits
system.cpu.icache.overall_hits::total 1837 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 458 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 458 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 458 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 458 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 458 # number of overall misses
system.cpu.icache.overall_misses::total 458 # number of overall misses
2016-11-30 23:12:59 +01:00
system.cpu.icache.ReadReq_miss_latency::cpu.inst 35506500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 35506500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 35506500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 35506500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 35506500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 35506500 # number of overall miss cycles
2016-10-14 00:21:40 +02:00
system.cpu.icache.ReadReq_accesses::cpu.inst 2295 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 2295 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 2295 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 2295 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 2295 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 2295 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.199564 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.199564 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.199564 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.199564 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.199564 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.199564 # miss rate for overall accesses
2016-11-30 23:12:59 +01:00
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77525.109170 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 77525.109170 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 77525.109170 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 77525.109170 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 77525.109170 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 77525.109170 # average overall miss latency
2016-10-14 00:21:40 +02:00
system.cpu.icache.blocked_cycles::no_mshrs 67 # number of cycles access was blocked
2011-06-21 00:57:14 +02:00
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2016-04-08 18:01:45 +02:00
system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked
2011-06-21 00:57:14 +02:00
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
2016-10-14 00:21:40 +02:00
system.cpu.icache.avg_blocked_cycles::no_mshrs 67 # average number of cycles each access was blocked
2012-05-09 20:52:14 +02:00
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-10-14 00:21:40 +02:00
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 145 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 145 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 145 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 145 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 145 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 145 # number of overall MSHR hits
2016-04-08 18:01:45 +02:00
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 313 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 313 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 313 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 313 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 313 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 313 # number of overall MSHR misses
2016-11-30 23:12:59 +01:00
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26274500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 26274500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26274500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 26274500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26274500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 26274500 # number of overall MSHR miss cycles
2016-10-14 00:21:40 +02:00
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.136383 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.136383 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.136383 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.136383 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.136383 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.136383 # mshr miss rate for overall accesses
2016-11-30 23:12:59 +01:00
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83944.089457 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83944.089457 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83944.089457 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 83944.089457 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83944.089457 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 83944.089457 # average overall mshr miss latency
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.replacements 0 # number of replacements
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.tags.tagsinuse 270.818986 # Cycle average of tags in use
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
2016-08-12 15:12:59 +02:00
system.cpu.l2cache.tags.sampled_refs 485 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.002062 # Average number of references to valid blocks.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.tags.occ_blocks::cpu.inst 160.559983 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 110.259003 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004900 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.003365 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.008265 # Average percentage of cache occupancy
2016-08-12 15:12:59 +02:00
system.cpu.l2cache.tags.occ_task_id_blocks::1024 485 # Occupied blocks per task id
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 167 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 318 # Occupied blocks per task id
2016-08-12 15:12:59 +02:00
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.014801 # Percentage of cache occupancy per task id
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.tags.tag_accesses 4373 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 4373 # Number of data accesses
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits
system.cpu.l2cache.overall_hits::total 1 # number of overall hits
2014-06-22 23:33:09 +02:00
system.cpu.l2cache.ReadExReq_misses::cpu.data 72 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 72 # number of ReadExReq misses
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 312 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 312 # number of ReadCleanReq misses
2016-03-17 18:32:53 +01:00
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 101 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 101 # number of ReadSharedReq misses
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.demand_misses::cpu.inst 312 # number of demand (read+write) misses
2016-03-17 18:32:53 +01:00
system.cpu.l2cache.demand_misses::cpu.data 173 # number of demand (read+write) misses
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.demand_misses::total 485 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 312 # number of overall misses
2016-03-17 18:32:53 +01:00
system.cpu.l2cache.overall_misses::cpu.data 173 # number of overall misses
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.overall_misses::total 485 # number of overall misses
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6902500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 6902500 # number of ReadExReq miss cycles
2016-11-30 23:12:59 +01:00
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25791500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 25791500 # number of ReadCleanReq miss cycles
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 9241500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 9241500 # number of ReadSharedReq miss cycles
2016-11-30 23:12:59 +01:00
system.cpu.l2cache.demand_miss_latency::cpu.inst 25791500 # number of demand (read+write) miss cycles
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.demand_miss_latency::cpu.data 16144000 # number of demand (read+write) miss cycles
2016-11-30 23:12:59 +01:00
system.cpu.l2cache.demand_miss_latency::total 41935500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 25791500 # number of overall miss cycles
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.overall_miss_latency::cpu.data 16144000 # number of overall miss cycles
2016-11-30 23:12:59 +01:00
system.cpu.l2cache.overall_miss_latency::total 41935500 # number of overall miss cycles
2014-06-22 23:33:09 +02:00
system.cpu.l2cache.ReadExReq_accesses::cpu.data 72 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 72 # number of ReadExReq accesses(hits+misses)
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 313 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 313 # number of ReadCleanReq accesses(hits+misses)
2016-03-17 18:32:53 +01:00
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 101 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 101 # number of ReadSharedReq accesses(hits+misses)
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.demand_accesses::cpu.inst 313 # number of demand (read+write) accesses
2016-03-17 18:32:53 +01:00
system.cpu.l2cache.demand_accesses::cpu.data 173 # number of demand (read+write) accesses
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.demand_accesses::total 486 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 313 # number of overall (read+write) accesses
2016-03-17 18:32:53 +01:00
system.cpu.l2cache.overall_accesses::cpu.data 173 # number of overall (read+write) accesses
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.overall_accesses::total 486 # number of overall (read+write) accesses
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.996805 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.996805 # miss rate for ReadCleanReq accesses
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996805 # miss rate for demand accesses
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.demand_miss_rate::total 0.997942 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996805 # miss rate for overall accesses
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.overall_miss_rate::total 0.997942 # miss rate for overall accesses
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 95868.055556 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 95868.055556 # average ReadExReq miss latency
2016-11-30 23:12:59 +01:00
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82665.064103 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82665.064103 # average ReadCleanReq miss latency
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 91500 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 91500 # average ReadSharedReq miss latency
2016-11-30 23:12:59 +01:00
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82665.064103 # average overall miss latency
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93317.919075 # average overall miss latency
2016-11-30 23:12:59 +01:00
system.cpu.l2cache.demand_avg_miss_latency::total 86464.948454 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82665.064103 # average overall miss latency
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93317.919075 # average overall miss latency
2016-11-30 23:12:59 +01:00
system.cpu.l2cache.overall_avg_miss_latency::total 86464.948454 # average overall miss latency
2011-06-21 00:57:14 +02:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
2012-05-09 20:52:14 +02:00
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2014-06-22 23:33:09 +02:00
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 72 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 72 # number of ReadExReq MSHR misses
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 312 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 312 # number of ReadCleanReq MSHR misses
2016-03-17 18:32:53 +01:00
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 101 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 101 # number of ReadSharedReq MSHR misses
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.demand_mshr_misses::cpu.inst 312 # number of demand (read+write) MSHR misses
2016-03-17 18:32:53 +01:00
system.cpu.l2cache.demand_mshr_misses::cpu.data 173 # number of demand (read+write) MSHR misses
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.demand_mshr_misses::total 485 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 312 # number of overall MSHR misses
2016-03-17 18:32:53 +01:00
system.cpu.l2cache.overall_mshr_misses::cpu.data 173 # number of overall MSHR misses
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.overall_mshr_misses::total 485 # number of overall MSHR misses
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6182500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6182500 # number of ReadExReq MSHR miss cycles
2016-11-30 23:12:59 +01:00
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22671500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22671500 # number of ReadCleanReq MSHR miss cycles
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 8231500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 8231500 # number of ReadSharedReq MSHR miss cycles
2016-11-30 23:12:59 +01:00
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22671500 # number of demand (read+write) MSHR miss cycles
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14414000 # number of demand (read+write) MSHR miss cycles
2016-11-30 23:12:59 +01:00
system.cpu.l2cache.demand_mshr_miss_latency::total 37085500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22671500 # number of overall MSHR miss cycles
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14414000 # number of overall MSHR miss cycles
2016-11-30 23:12:59 +01:00
system.cpu.l2cache.overall_mshr_miss_latency::total 37085500 # number of overall MSHR miss cycles
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996805 # mshr miss rate for ReadCleanReq accesses
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for demand accesses
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.demand_mshr_miss_rate::total 0.997942 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for overall accesses
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.overall_mshr_miss_rate::total 0.997942 # mshr miss rate for overall accesses
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 85868.055556 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 85868.055556 # average ReadExReq mshr miss latency
2016-11-30 23:12:59 +01:00
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72665.064103 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72665.064103 # average ReadCleanReq mshr miss latency
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 81500 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 81500 # average ReadSharedReq mshr miss latency
2016-11-30 23:12:59 +01:00
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72665.064103 # average overall mshr miss latency
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83317.919075 # average overall mshr miss latency
2016-11-30 23:12:59 +01:00
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76464.948454 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72665.064103 # average overall mshr miss latency
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83317.919075 # average overall mshr miss latency
2016-11-30 23:12:59 +01:00
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76464.948454 # average overall mshr miss latency
2016-04-08 18:01:45 +02:00
system.cpu.toL2Bus.snoop_filter.tot_requests 486 # Total number of requests made to the snoop filter.
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2016-10-14 00:21:40 +02:00
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states
2016-04-08 18:01:45 +02:00
system.cpu.toL2Bus.trans_dist::ReadResp 414 # Transaction distribution
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.trans_dist::ReadExReq 72 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 72 # Transaction distribution
2016-04-08 18:01:45 +02:00
system.cpu.toL2Bus.trans_dist::ReadCleanReq 313 # Transaction distribution
2016-03-17 18:32:53 +01:00
system.cpu.toL2Bus.trans_dist::ReadSharedReq 101 # Transaction distribution
2016-04-08 18:01:45 +02:00
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 626 # Packet count per connected master and slave (bytes)
2016-03-17 18:32:53 +01:00
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 346 # Packet count per connected master and slave (bytes)
2016-04-08 18:01:45 +02:00
system.cpu.toL2Bus.pkt_count::total 972 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20032 # Cumulative packet size per connected master and slave (bytes)
2016-03-17 18:32:53 +01:00
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 11072 # Cumulative packet size per connected master and slave (bytes)
2016-04-08 18:01:45 +02:00
system.cpu.toL2Bus.pkt_size::total 31104 # Cumulative packet size per connected master and slave (bytes)
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
2016-07-21 18:19:18 +02:00
system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes)
2016-04-08 18:01:45 +02:00
system.cpu.toL2Bus.snoop_fanout::samples 486 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.002058 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.045361 # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-04-08 18:01:45 +02:00
system.cpu.toL2Bus.snoop_fanout::0 485 99.79% 99.79% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::1 1 0.21% 100.00% # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
2016-04-08 18:01:45 +02:00
system.cpu.toL2Bus.snoop_fanout::total 486 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 243000 # Layer occupancy (ticks)
2016-10-14 00:21:40 +02:00
system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%)
2016-04-08 18:01:45 +02:00
system.cpu.toL2Bus.respLayer0.occupancy 469500 # Layer occupancy (ticks)
2016-10-14 00:21:40 +02:00
system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%)
2016-03-17 18:32:53 +01:00
system.cpu.toL2Bus.respLayer1.occupancy 259500 # Layer occupancy (ticks)
2016-10-14 00:21:40 +02:00
system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.membus.snoop_filter.tot_requests 485 # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2016-10-14 00:21:40 +02:00
system.membus.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states
2016-04-08 18:01:45 +02:00
system.membus.trans_dist::ReadResp 413 # Transaction distribution
2014-12-23 15:31:20 +01:00
system.membus.trans_dist::ReadExReq 72 # Transaction distribution
system.membus.trans_dist::ReadExResp 72 # Transaction distribution
2016-04-08 18:01:45 +02:00
system.membus.trans_dist::ReadSharedReq 413 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 970 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 970 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31040 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 31040 # Cumulative packet size per connected master and slave (bytes)
2014-12-23 15:31:20 +01:00
system.membus.snoops 0 # Total snoops (count)
2016-07-21 18:19:18 +02:00
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
2016-04-08 18:01:45 +02:00
system.membus.snoop_fanout::samples 485 # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-04-08 18:01:45 +02:00
system.membus.snoop_fanout::0 485 100.00% 100.00% # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
2016-04-08 18:01:45 +02:00
system.membus.snoop_fanout::total 485 # Request fanout histogram
2016-10-14 00:21:40 +02:00
system.membus.reqLayer0.occupancy 595000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 2.5 # Layer utilization (%)
system.membus.respLayer1.occupancy 2572250 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 10.8 # Layer utilization (%)
2006-09-01 23:59:36 +02:00
---------- End Simulation Statistics ----------
