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tests: Regression stats updated for recent patches

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This commit is contained in:
Jason Lowe-Power 2016-11-30 17:12:59 -05:00
parent 33683bd087
commit 7520331402
172 changed files with 71405 additions and 7796 deletions
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58
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
View file

@ -12,12 +12,12 @@ time_sync_spin_threshold=100000000
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
atags_addr=134217728
boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm
boot_loader=/dist/m5/system/binaries/boot_emm.arm
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
cache_line_size=64
clk_domain=system.clk_domain
default_p_state=UNDEFINED
dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
dtb_filename=/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
@ -30,7 +30,7 @@ have_security=false
have_virtualization=false
highest_el_is_64=false
init_param=0
kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel=/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
@ -49,7 +49,7 @@ panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
power_model=Null
readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh
readfile=/z/powerjg/gem5-upstream/tests/testing/../halt.sh
reset_addr_64=0
symbolfile=
thermal_components=
@ -99,7 +99,7 @@ table_size=65536
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
image_file=/arm/projectscratch/randd/systems/dist/disks/linux-aarch32-ael.img
image_file=/dist/m5/system/disks/linux-aarch32-ael.img
read_only=true
[system.clk_domain]
@ -157,10 +157,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=6
@ -174,6 +174,7 @@ response_latency=2
sequential_access=false
size=32768
system=system
tag_latency=2
tags=system.cpu0.dcache.tags
tgts_per_mshr=8
write_buffers=16
@ -186,15 +187,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768
tag_latency=2
[system.cpu0.dstage2_mmu]
type=ArmStage2MMU
@ -254,10 +256,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=1
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=1
is_read_only=true
max_miss_count=0
mshrs=2
@ -271,6 +273,7 @@ response_latency=1
sequential_access=false
size=32768
system=system
tag_latency=1
tags=system.cpu0.icache.tags
tgts_per_mshr=8
write_buffers=8
@ -283,15 +286,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=1
default_p_state=UNDEFINED
eventq_index=0
hit_latency=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768
tag_latency=1
[system.cpu0.interrupts]
type=ArmInterrupts
@ -386,10 +390,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=16
clk_domain=system.cpu_clk_domain
clusivity=mostly_excl
data_latency=12
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=12
is_read_only=false
max_miss_count=0
mshrs=16
@ -403,6 +407,7 @@ response_latency=12
sequential_access=false
size=1048576
system=system
tag_latency=12
tags=system.cpu0.l2cache.tags
tgts_per_mshr=8
write_buffers=8
@ -445,15 +450,16 @@ type=RandomRepl
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=12
default_p_state=UNDEFINED
eventq_index=0
hit_latency=12
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=1048576
tag_latency=12
[system.cpu0.toL2Bus]
type=CoherentXBar
@ -535,10 +541,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=6
@ -552,6 +558,7 @@ response_latency=2
sequential_access=false
size=32768
system=system
tag_latency=2
tags=system.cpu1.dcache.tags
tgts_per_mshr=8
write_buffers=16
@ -564,15 +571,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768
tag_latency=2
[system.cpu1.dstage2_mmu]
type=ArmStage2MMU
@ -632,10 +640,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=1
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=1
is_read_only=true
max_miss_count=0
mshrs=2
@ -649,6 +657,7 @@ response_latency=1
sequential_access=false
size=32768
system=system
tag_latency=1
tags=system.cpu1.icache.tags
tgts_per_mshr=8
write_buffers=8
@ -661,15 +670,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=1
default_p_state=UNDEFINED
eventq_index=0
hit_latency=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768
tag_latency=1
[system.cpu1.interrupts]
type=ArmInterrupts
@ -764,10 +774,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=16
clk_domain=system.cpu_clk_domain
clusivity=mostly_excl
data_latency=12
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=12
is_read_only=false
max_miss_count=0
mshrs=16
@ -781,6 +791,7 @@ response_latency=12
sequential_access=false
size=1048576
system=system
tag_latency=12
tags=system.cpu1.l2cache.tags
tgts_per_mshr=8
write_buffers=8
@ -823,15 +834,16 @@ type=RandomRepl
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=12
default_p_state=UNDEFINED
eventq_index=0
hit_latency=12
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=1048576
tag_latency=12
[system.cpu1.toL2Bus]
type=CoherentXBar
@ -911,10 +923,10 @@ addr_ranges=2147483648:2415919103:0:0:0:0
assoc=8
clk_domain=system.clk_domain
clusivity=mostly_incl
data_latency=50
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=50
is_read_only=false
max_miss_count=0
mshrs=20
@ -928,6 +940,7 @@ response_latency=50
sequential_access=false
size=1024
system=system
tag_latency=50
tags=system.iocache.tags
tgts_per_mshr=12
write_buffers=8
@ -940,15 +953,16 @@ type=LRU
assoc=8
block_size=64
clk_domain=system.clk_domain
data_latency=50
default_p_state=UNDEFINED
eventq_index=0
hit_latency=50
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=1024
tag_latency=50
[system.l2c]
type=Cache
@ -957,10 +971,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=20
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=20
is_read_only=false
max_miss_count=0
mshrs=20
@ -974,6 +988,7 @@ response_latency=20
sequential_access=false
size=4194304
system=system
tag_latency=20
tags=system.l2c.tags
tgts_per_mshr=12
write_buffers=8
@ -986,15 +1001,16 @@ type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=20
default_p_state=UNDEFINED
eventq_index=0
hit_latency=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=4194304
tag_latency=20
[system.membus]
type=CoherentXBar

14
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout
View file

@ -3,16 +3,16 @@ Redirecting stderr to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realv
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Oct 11 2016 00:00:58
gem5 started Oct 13 2016 20:54:49
gem5 executing on e108600-lin, pid 17501
command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual
gem5 compiled Nov 29 2016 19:03:48
gem5 started Nov 29 2016 19:04:20
gem5 executing on zizzer, pid 5756
command line: /z/powerjg/gem5-upstream/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
info: kernel located at: /dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x80008000
info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000
info: Loading DTB file: /dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000
info: Entering event queue @ 0. Starting simulation...
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
@ -29,4 +29,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
Exiting @ tick 2870822663000 because m5_exit instruction encountered
Exiting @ tick 2870988926500 because m5_exit instruction encountered

4845
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
View file

File diff suppressed because it is too large Load diff

2
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminal
View file

@ -159,9 +159,9 @@ ata1.00: configured for UDMA/33
scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
sd 0:0:0:0: [sda] 1048320 512-byte logical blocks: (536 MB/511 MiB)
sd 0:0:0:0: [sda] Write Protect is off
sd 0:0:0:0: Attached scsi generic sg0 type 0
sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
sd 0:0:0:0: Attached scsi generic sg0 type 0
sda: sda1
sd 0:0:0:0: [sda] Attached SCSI disk
e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01

34
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
View file

@ -12,12 +12,12 @@ time_sync_spin_threshold=100000000
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
atags_addr=134217728
boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm
boot_loader=/dist/m5/system/binaries/boot_emm.arm
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
cache_line_size=64
clk_domain=system.clk_domain
default_p_state=UNDEFINED
dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
dtb_filename=/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
@ -30,7 +30,7 @@ have_security=false
have_virtualization=false
highest_el_is_64=false
init_param=0
kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel=/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
@ -49,7 +49,7 @@ panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
power_model=Null
readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh
readfile=/z/powerjg/gem5-upstream/tests/testing/../halt.sh
reset_addr_64=0
symbolfile=
thermal_components=
@ -99,7 +99,7 @@ table_size=65536
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
image_file=/arm/projectscratch/randd/systems/dist/disks/linux-aarch32-ael.img
image_file=/dist/m5/system/disks/linux-aarch32-ael.img
read_only=true
[system.clk_domain]
@ -157,10 +157,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=4
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=4
@ -174,6 +174,7 @@ response_latency=2
sequential_access=false
size=32768
system=system
tag_latency=2
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
@ -186,15 +187,16 @@ type=LRU
assoc=4
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768
tag_latency=2
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
@ -254,10 +256,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=1
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=true
max_miss_count=0
mshrs=4
@ -271,6 +273,7 @@ response_latency=2
sequential_access=false
size=32768
system=system
tag_latency=2
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
@ -283,15 +286,16 @@ type=LRU
assoc=1
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768
tag_latency=2
[system.cpu.interrupts]
type=ArmInterrupts
@ -386,10 +390,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=20
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=20
is_read_only=false
max_miss_count=0
mshrs=20
@ -403,6 +407,7 @@ response_latency=20
sequential_access=false
size=4194304
system=system
tag_latency=20
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
@ -415,15 +420,16 @@ type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=20
default_p_state=UNDEFINED
eventq_index=0
hit_latency=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=4194304
tag_latency=20
[system.cpu.toL2Bus]
type=CoherentXBar
@ -503,10 +509,10 @@ addr_ranges=2147483648:2415919103:0:0:0:0
assoc=8
clk_domain=system.clk_domain
clusivity=mostly_incl
data_latency=50
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=50
is_read_only=false
max_miss_count=0
mshrs=20
@ -520,6 +526,7 @@ response_latency=50
sequential_access=false
size=1024
system=system
tag_latency=50
tags=system.iocache.tags
tgts_per_mshr=12
write_buffers=8
@ -532,15 +539,16 @@ type=LRU
assoc=8
block_size=64
clk_domain=system.clk_domain
data_latency=50
default_p_state=UNDEFINED
eventq_index=0
hit_latency=50
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=1024
tag_latency=50
[system.membus]
type=CoherentXBar

14
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
View file

@ -3,16 +3,16 @@ Redirecting stderr to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realv
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Oct 11 2016 00:00:58
gem5 started Oct 13 2016 21:01:25
gem5 executing on e108600-lin, pid 17555
command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/fs/10.linux-boot/arm/linux/realview-simple-timing
gem5 compiled Nov 29 2016 19:03:48
gem5 started Nov 29 2016 19:06:57
gem5 executing on zizzer, pid 5768
command line: /z/powerjg/gem5-upstream/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/fs/10.linux-boot/arm/linux/realview-simple-timing
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
info: kernel located at: /dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x80008000
info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000
info: Loading DTB file: /dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000
info: Entering event queue @ 0. Starting simulation...
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
@ -29,4 +29,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
Exiting @ tick 2905297782500 because m5_exit instruction encountered
Exiting @ tick 2905317504500 because m5_exit instruction encountered

1843
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

84
tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini
View file

@ -177,10 +177,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=4
@ -194,6 +194,7 @@ response_latency=2
sequential_access=false
size=262144
system=system
tag_latency=2
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
@ -206,15 +207,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=262144
tag_latency=2
[system.cpu.dtb]
type=AlphaTLB
@ -292,10 +294,10 @@ pipelined=true
[system.cpu.fuPool.FUList3]
type=FUDesc
children=opList0 opList1 opList2
children=opList0 opList1 opList2 opList3 opList4
count=2
eventq_index=0
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4
[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
@ -307,11 +309,25 @@ pipelined=true
[system.cpu.fuPool.FUList3.opList1]
type=OpDesc
eventq_index=0
opClass=FloatMultAcc
opLat=5
pipelined=true
[system.cpu.fuPool.FUList3.opList2]
type=OpDesc
eventq_index=0
opClass=FloatMisc
opLat=3
pipelined=true
[system.cpu.fuPool.FUList3.opList3]
type=OpDesc
eventq_index=0
opClass=FloatDiv
opLat=12
pipelined=false
[system.cpu.fuPool.FUList3.opList2]
[system.cpu.fuPool.FUList3.opList4]
type=OpDesc
eventq_index=0
opClass=FloatSqrt
@ -320,18 +336,25 @@ pipelined=false
[system.cpu.fuPool.FUList4]
type=FUDesc
children=opList
children=opList0 opList1
count=0
eventq_index=0
opList=system.cpu.fuPool.FUList4.opList
opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1
[system.cpu.fuPool.FUList4.opList]
[system.cpu.fuPool.FUList4.opList0]
type=OpDesc
eventq_index=0
opClass=MemRead
opLat=1
pipelined=true
[system.cpu.fuPool.FUList4.opList1]
type=OpDesc
eventq_index=0
opClass=FloatMemRead
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5]
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
@ -481,24 +504,31 @@ pipelined=true
[system.cpu.fuPool.FUList6]
type=FUDesc
children=opList
children=opList0 opList1
count=0
eventq_index=0
opList=system.cpu.fuPool.FUList6.opList
opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
[system.cpu.fuPool.FUList6.opList]
[system.cpu.fuPool.FUList6.opList0]
type=OpDesc
eventq_index=0
opClass=MemWrite
opLat=1
pipelined=true
[system.cpu.fuPool.FUList6.opList1]
type=OpDesc
eventq_index=0
opClass=FloatMemWrite
opLat=1
pipelined=true
[system.cpu.fuPool.FUList7]
type=FUDesc
children=opList0 opList1
children=opList0 opList1 opList2 opList3
count=4
eventq_index=0
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 system.cpu.fuPool.FUList7.opList2 system.cpu.fuPool.FUList7.opList3
[system.cpu.fuPool.FUList7.opList0]
type=OpDesc
@ -514,6 +544,20 @@ opClass=MemWrite
opLat=1
pipelined=true
[system.cpu.fuPool.FUList7.opList2]
type=OpDesc
eventq_index=0
opClass=FloatMemRead
opLat=1
pipelined=true
[system.cpu.fuPool.FUList7.opList3]
type=OpDesc
eventq_index=0
opClass=FloatMemWrite
opLat=1
pipelined=true
[system.cpu.fuPool.FUList8]
type=FUDesc
children=opList
@ -535,10 +579,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=true
max_miss_count=0
mshrs=4
@ -552,6 +596,7 @@ response_latency=2
sequential_access=false
size=131072
system=system
tag_latency=2
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
@ -564,15 +609,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=131072
tag_latency=2
[system.cpu.interrupts]
type=AlphaInterrupts
@ -595,10 +641,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=20
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=20
is_read_only=false
max_miss_count=0
mshrs=20
@ -612,6 +658,7 @@ response_latency=20
sequential_access=false
size=2097152
system=system
tag_latency=20
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
@ -624,15 +671,16 @@ type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=20
default_p_state=UNDEFINED
eventq_index=0
hit_latency=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=2097152
tag_latency=20
[system.cpu.toL2Bus]
type=CoherentXBar
@ -677,7 +725,7 @@ env=
errout=cerr
euid=100
eventq_index=0
executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/linux/hello
executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
kvmInSE=false

8
tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout
View file

@ -3,10 +3,10 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-tim
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Oct 11 2016 00:00:58
gem5 started Oct 13 2016 20:19:49
gem5 executing on e108600-lin, pid 28099
command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/linux/o3-timing
gem5 compiled Nov 29 2016 18:06:09
gem5 started Nov 29 2016 18:06:29
gem5 executing on zizzer, pid 27582
command line: /z/powerjg/gem5-upstream/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/00.hello/alpha/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

170
tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.000024 # Nu
sim_ticks 23776000 # Number of ticks simulated
final_tick 23776000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 139405 # Simulator instruction rate (inst/s)
host_op_rate 139373 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 518883929 # Simulator tick rate (ticks/s)
host_mem_usage 254032 # Number of bytes of host memory used
host_seconds 0.05 # Real time elapsed on the host
host_inst_rate 4743 # Simulator instruction rate (inst/s)
host_op_rate 4743 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 17659718 # Simulator tick rate (ticks/s)
host_mem_usage 236044 # Number of bytes of host memory used
host_seconds 1.35 # Real time elapsed on the host
sim_insts 6385 # Number of instructions simulated
sim_ops 6385 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@ -201,12 +201,12 @@ system.physmem.bytesPerActivate::768-895 2 2.25% 87.64% # By
system.physmem.bytesPerActivate::896-1023 1 1.12% 88.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 10 11.24% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 89 # Bytes accessed per row activation
system.physmem.totQLat 8009750 # Total ticks spent queuing
system.physmem.totMemAccLat 17103500 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totQLat 8008750 # Total ticks spent queuing
system.physmem.totMemAccLat 17102500 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2425000 # Total ticks spent in databus transfers
system.physmem.avgQLat 16514.95 # Average queueing delay per DRAM burst
system.physmem.avgQLat 16512.89 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 35264.95 # Average memory access latency per DRAM burst
system.physmem.avgMemAccLat 35262.89 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 1305.52 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 1305.52 # Average system read bandwidth in MiByte/s
@ -228,20 +228,20 @@ system.physmem_0.preEnergy 125235 # En
system.physmem_0.readEnergy 1763580 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 3005040 # Energy for active background per rank (pJ)
system.physmem_0.actBackEnergy 3004470 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 47520 # Energy for precharge background per rank (pJ)
system.physmem_0.actPowerDownEnergy 7623180 # Energy for active power-down per rank (pJ)
system.physmem_0.actPowerDownEnergy 7623750 # Energy for active power-down per rank (pJ)
system.physmem_0.prePowerDownEnergy 132480 # Energy for precharge power-down per rank (pJ)
system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
system.physmem_0.totalEnergy 14783715 # Total energy per rank (pJ)
system.physmem_0.averagePower 621.784975 # Core power per rank (mW)
system.physmem_0.totalIdleTime 16957250 # Total Idle time Per DRAM Rank
system.physmem_0.totalIdleTime 16958250 # Total Idle time Per DRAM Rank
system.physmem_0.memoryStateTime::IDLE 40500 # Time in different power states
system.physmem_0.memoryStateTime::REF 780000 # Time in different power states
system.physmem_0.memoryStateTime::SREF 0 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 344500 # Time in different power states
system.physmem_0.memoryStateTime::ACT 5900500 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 16710500 # Time in different power states
system.physmem_0.memoryStateTime::ACT 5899500 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 16711500 # Time in different power states
system.physmem_1.actEnergy 399840 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 212520 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 1699320 # Energy for read commands per rank (pJ)
@ -313,7 +313,7 @@ system.cpu.pwrStateResidencyTicks::ON 23776000 # Cu
system.cpu.numCycles 47553 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles 8496 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.icacheStallCycles 8498 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 16559 # Number of instructions fetch has processed
system.cpu.fetch.Branches 2854 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 1179 # Number of branches that fetch has predicted taken
@ -323,11 +323,11 @@ system.cpu.fetch.MiscStallCycles 22 # Nu
system.cpu.fetch.PendingTrapStallCycles 656 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 2295 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 335 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 15456 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.071364 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.458774 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::samples 15458 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.071225 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.458645 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 12470 80.68% 80.68% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 12472 80.68% 80.68% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 297 1.92% 82.60% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 230 1.49% 84.09% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 258 1.67% 85.76% # Number of instructions fetched each cycle (Total)
@ -339,10 +339,10 @@ system.cpu.fetch.rateDist::8 1247 8.07% 100.00% # Nu
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 15456 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 15458 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.060017 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.348222 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 8339 # Number of cycles decode is idle
system.cpu.decode.IdleCycles 8341 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 4008 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 2446 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 214 # Number of cycles decode is unblocking
@ -352,7 +352,7 @@ system.cpu.decode.BranchMispred 75 # Nu
system.cpu.decode.DecodedInsts 15004 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 221 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 449 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 8498 # Number of cycles rename is idle
system.cpu.rename.IdleCycles 8500 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 1841 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 655 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 2476 # Number of cycles rename is running
@ -382,23 +382,23 @@ system.cpu.iq.iqSquashedInstsIssued 17 # Nu
system.cpu.iq.iqSquashedInstsExamined 6695 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 3669 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 10 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 15456 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.697205 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.442232 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::samples 15458 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.697115 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.442161 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 11416 73.86% 73.86% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 1297 8.39% 82.25% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 11418 73.86% 73.86% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 1297 8.39% 82.26% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 916 5.93% 88.18% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 681 4.41% 92.59% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 517 3.34% 95.93% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 347 2.25% 98.18% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 347 2.24% 98.18% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 200 1.29% 99.47% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 55 0.36% 99.83% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 27 0.17% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 15456 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 15458 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 21 14.89% 14.89% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 14.89% # attempts to use FU when none available
@ -479,7 +479,7 @@ system.cpu.iq.FU_type_0::total 10776 # Ty
system.cpu.iq.rate 0.226610 # Inst issue rate
system.cpu.iq.fu_busy_cnt 141 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.013085 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 37145 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_reads 37147 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 19787 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 9745 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads
@ -530,11 +530,11 @@ system.cpu.iew.wb_fanout 0.733808 # av
system.cpu.commit.commitSquashedInsts 6712 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 408 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 14219 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.450243 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.361136 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::samples 14221 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.450179 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.361050 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 11792 82.93% 82.93% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 11794 82.93% 82.93% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 1158 8.14% 91.08% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 469 3.30% 94.37% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 205 1.44% 95.82% # Number of insts commited each cycle
@ -546,7 +546,7 @@ system.cpu.commit.committed_per_cycle::8 192 1.35% 100.00% # Nu
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 14219 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 14221 # Number of insts commited each cycle
system.cpu.commit.committedInsts 6402 # Number of instructions committed
system.cpu.commit.committedOps 6402 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
@ -597,10 +597,10 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 6402 # Class of committed instruction
system.cpu.commit.bw_lim_events 192 # number cycles where commit BW limit reached
system.cpu.rob.rob_reads 26790 # The number of ROB reads
system.cpu.rob.rob_reads 26792 # The number of ROB reads
system.cpu.rob.rob_writes 27482 # The number of ROB writes
system.cpu.timesIdled 250 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 32097 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.idleCycles 32095 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 6385 # Number of Instructions Simulated
system.cpu.committedOps 6385 # Number of Ops (including micro ops) Simulated
system.cpu.cpi 7.447612 # CPI: Cycles Per Instruction
@ -753,12 +753,12 @@ system.cpu.icache.demand_misses::cpu.inst 458 # n
system.cpu.icache.demand_misses::total 458 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 458 # number of overall misses
system.cpu.icache.overall_misses::total 458 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 35507500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 35507500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 35507500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 35507500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 35507500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 35507500 # number of overall miss cycles
system.cpu.icache.ReadReq_miss_latency::cpu.inst 35506500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 35506500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 35506500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 35506500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 35506500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 35506500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 2295 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 2295 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 2295 # number of demand (read+write) accesses
@ -771,12 +771,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.199564
system.cpu.icache.demand_miss_rate::total 0.199564 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.199564 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.199564 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77527.292576 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 77527.292576 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 77527.292576 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 77527.292576 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 77527.292576 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 77527.292576 # average overall miss latency
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77525.109170 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 77525.109170 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 77525.109170 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 77525.109170 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 77525.109170 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 77525.109170 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 67 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked
@ -795,24 +795,24 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 313
system.cpu.icache.demand_mshr_misses::total 313 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 313 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 313 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26275500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 26275500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26275500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 26275500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26275500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 26275500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26274500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 26274500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26274500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 26274500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26274500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 26274500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.136383 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.136383 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.136383 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.136383 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.136383 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.136383 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83947.284345 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83947.284345 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83947.284345 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 83947.284345 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83947.284345 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 83947.284345 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83944.089457 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83944.089457 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83944.089457 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 83944.089457 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83944.089457 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 83944.089457 # average overall mshr miss latency
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 270.818986 # Cycle average of tags in use
@ -852,16 +852,16 @@ system.cpu.l2cache.overall_misses::cpu.data 173 #
system.cpu.l2cache.overall_misses::total 485 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6902500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 6902500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25792500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 25792500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25791500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 25791500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 9241500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 9241500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 25792500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 25791500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 16144000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 41936500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 25792500 # number of overall miss cycles
system.cpu.l2cache.demand_miss_latency::total 41935500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 25791500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 16144000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 41936500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 41935500 # number of overall miss cycles
system.cpu.l2cache.ReadExReq_accesses::cpu.data 72 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 72 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 313 # number of ReadCleanReq accesses(hits+misses)
@ -888,16 +888,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 1
system.cpu.l2cache.overall_miss_rate::total 0.997942 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 95868.055556 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 95868.055556 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82668.269231 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82668.269231 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82665.064103 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82665.064103 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 91500 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 91500 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82668.269231 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82665.064103 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93317.919075 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 86467.010309 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82668.269231 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 86464.948454 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82665.064103 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93317.919075 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 86467.010309 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 86464.948454 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -918,16 +918,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data 173
system.cpu.l2cache.overall_mshr_misses::total 485 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6182500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6182500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22672500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22672500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22671500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22671500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 8231500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 8231500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22672500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22671500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14414000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 37086500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22672500 # number of overall MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 37085500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22671500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14414000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 37086500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 37085500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for ReadCleanReq accesses
@ -942,16 +942,16 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1
system.cpu.l2cache.overall_mshr_miss_rate::total 0.997942 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 85868.055556 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 85868.055556 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72668.269231 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72668.269231 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72665.064103 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72665.064103 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 81500 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 81500 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72668.269231 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72665.064103 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83317.919075 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76467.010309 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72668.269231 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76464.948454 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72665.064103 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83317.919075 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76467.010309 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76464.948454 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 486 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.

66
tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
View file

@ -176,10 +176,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=6
@ -193,6 +193,7 @@ response_latency=2
sequential_access=false
size=32768
system=system
tag_latency=2
tags=system.cpu.dcache.tags
tgts_per_mshr=8
write_buffers=16
@ -205,15 +206,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768
tag_latency=2
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
@ -316,38 +318,52 @@ pipelined=true
[system.cpu.fuPool.FUList2]
type=FUDesc
children=opList
children=opList0 opList1
count=1
eventq_index=0
opList=system.cpu.fuPool.FUList2.opList
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1
[system.cpu.fuPool.FUList2.opList]
[system.cpu.fuPool.FUList2.opList0]
type=OpDesc
eventq_index=0
opClass=MemRead
opLat=2
pipelined=true
[system.cpu.fuPool.FUList2.opList1]
type=OpDesc
eventq_index=0
opClass=FloatMemRead
opLat=2
pipelined=true
[system.cpu.fuPool.FUList3]
type=FUDesc
children=opList
children=opList0 opList1
count=1
eventq_index=0
opList=system.cpu.fuPool.FUList3.opList
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1
[system.cpu.fuPool.FUList3.opList]
[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
eventq_index=0
opClass=MemWrite
opLat=2
pipelined=true
[system.cpu.fuPool.FUList3.opList1]
type=OpDesc
eventq_index=0
opClass=FloatMemWrite
opLat=2
pipelined=true
[system.cpu.fuPool.FUList4]
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 opList26 opList27
count=2
eventq_index=0
opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25
opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 system.cpu.fuPool.FUList4.opList26 system.cpu.fuPool.FUList4.opList27
[system.cpu.fuPool.FUList4.opList00]
type=OpDesc
@ -479,7 +495,7 @@ pipelined=true
type=OpDesc
eventq_index=0
opClass=SimdFloatMultAcc
opLat=1
opLat=5
pipelined=true
[system.cpu.fuPool.FUList4.opList19]
@ -531,6 +547,20 @@ opClass=FloatMult
opLat=4
pipelined=true
[system.cpu.fuPool.FUList4.opList26]
type=OpDesc
eventq_index=0
opClass=FloatMultAcc
opLat=5
pipelined=true
[system.cpu.fuPool.FUList4.opList27]
type=OpDesc
eventq_index=0
opClass=FloatMisc
opLat=3
pipelined=true
[system.cpu.icache]
type=Cache
children=tags
@ -538,10 +568,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=1
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=1
is_read_only=true
max_miss_count=0
mshrs=2
@ -555,6 +585,7 @@ response_latency=1
sequential_access=false
size=32768
system=system
tag_latency=1
tags=system.cpu.icache.tags
tgts_per_mshr=8
write_buffers=8
@ -567,15 +598,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=1
default_p_state=UNDEFINED
eventq_index=0
hit_latency=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768
tag_latency=1
[system.cpu.interrupts]
type=ArmInterrupts
@ -670,10 +702,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=16
clk_domain=system.cpu_clk_domain
clusivity=mostly_excl
data_latency=12
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=12
is_read_only=false
max_miss_count=0
mshrs=16
@ -687,6 +719,7 @@ response_latency=12
sequential_access=false
size=1048576
system=system
tag_latency=12
tags=system.cpu.l2cache.tags
tgts_per_mshr=8
write_buffers=8
@ -729,15 +762,16 @@ type=RandomRepl
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=12
default_p_state=UNDEFINED
eventq_index=0
hit_latency=12
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=1048576
tag_latency=12
[system.cpu.toL2Bus]
type=CoherentXBar
@ -782,7 +816,7 @@ env=
errout=cerr
euid=100
eventq_index=0
executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/arm/linux/hello
executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello
gid=100
input=cin
kvmInSE=false

10
tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout
View file

@ -3,12 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing/
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Oct 11 2016 00:00:58
gem5 started Oct 13 2016 20:52:56
gem5 executing on e108600-lin, pid 17478
command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/arm/linux/o3-timing
gem5 compiled Nov 29 2016 19:03:48
gem5 started Nov 29 2016 19:06:55
gem5 executing on zizzer, pid 5766
command line: /z/powerjg/gem5-upstream/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/00.hello/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
Exiting @ tick 20299000 because target called exit()
Exiting @ tick 20302000 because target called exit()

826
tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

84
tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini
View file

@ -177,10 +177,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=4
@ -194,6 +194,7 @@ response_latency=2
sequential_access=false
size=262144
system=system
tag_latency=2
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
@ -206,15 +207,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=262144
tag_latency=2
[system.cpu.dtb]
type=MipsTLB
@ -292,10 +294,10 @@ pipelined=true
[system.cpu.fuPool.FUList3]
type=FUDesc
children=opList0 opList1 opList2
children=opList0 opList1 opList2 opList3 opList4
count=2
eventq_index=0
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4
[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
@ -307,11 +309,25 @@ pipelined=true
[system.cpu.fuPool.FUList3.opList1]
type=OpDesc
eventq_index=0
opClass=FloatMultAcc
opLat=5
pipelined=true
[system.cpu.fuPool.FUList3.opList2]
type=OpDesc
eventq_index=0
opClass=FloatMisc
opLat=3
pipelined=true
[system.cpu.fuPool.FUList3.opList3]
type=OpDesc
eventq_index=0
opClass=FloatDiv
opLat=12
pipelined=false
[system.cpu.fuPool.FUList3.opList2]
[system.cpu.fuPool.FUList3.opList4]
type=OpDesc
eventq_index=0
opClass=FloatSqrt
@ -320,18 +336,25 @@ pipelined=false
[system.cpu.fuPool.FUList4]
type=FUDesc
children=opList
children=opList0 opList1
count=0
eventq_index=0
opList=system.cpu.fuPool.FUList4.opList
opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1
[system.cpu.fuPool.FUList4.opList]
[system.cpu.fuPool.FUList4.opList0]
type=OpDesc
eventq_index=0
opClass=MemRead
opLat=1
pipelined=true
[system.cpu.fuPool.FUList4.opList1]
type=OpDesc
eventq_index=0
opClass=FloatMemRead
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5]
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
@ -481,24 +504,31 @@ pipelined=true
[system.cpu.fuPool.FUList6]
type=FUDesc
children=opList
children=opList0 opList1
count=0
eventq_index=0
opList=system.cpu.fuPool.FUList6.opList
opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
[system.cpu.fuPool.FUList6.opList]
[system.cpu.fuPool.FUList6.opList0]
type=OpDesc
eventq_index=0
opClass=MemWrite
opLat=1
pipelined=true
[system.cpu.fuPool.FUList6.opList1]
type=OpDesc
eventq_index=0
opClass=FloatMemWrite
opLat=1
pipelined=true
[system.cpu.fuPool.FUList7]
type=FUDesc
children=opList0 opList1
children=opList0 opList1 opList2 opList3
count=4
eventq_index=0
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 system.cpu.fuPool.FUList7.opList2 system.cpu.fuPool.FUList7.opList3
[system.cpu.fuPool.FUList7.opList0]
type=OpDesc
@ -514,6 +544,20 @@ opClass=MemWrite
opLat=1
pipelined=true
[system.cpu.fuPool.FUList7.opList2]
type=OpDesc
eventq_index=0
opClass=FloatMemRead
opLat=1
pipelined=true
[system.cpu.fuPool.FUList7.opList3]
type=OpDesc
eventq_index=0
opClass=FloatMemWrite
opLat=1
pipelined=true
[system.cpu.fuPool.FUList8]
type=FUDesc
children=opList
@ -535,10 +579,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=true
max_miss_count=0
mshrs=4
@ -552,6 +596,7 @@ response_latency=2
sequential_access=false
size=131072
system=system
tag_latency=2
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
@ -564,15 +609,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=131072
tag_latency=2
[system.cpu.interrupts]
type=MipsInterrupts
@ -597,10 +643,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=20
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=20
is_read_only=false
max_miss_count=0
mshrs=20
@ -614,6 +660,7 @@ response_latency=20
sequential_access=false
size=2097152
system=system
tag_latency=20
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
@ -626,15 +673,16 @@ type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=20
default_p_state=UNDEFINED
eventq_index=0
hit_latency=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=2097152
tag_latency=20
[system.cpu.toL2Bus]
type=CoherentXBar
@ -679,7 +727,7 @@ env=
errout=cerr
euid=100
eventq_index=0
executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/mips/linux/hello
executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello
gid=100
input=cin
kvmInSE=false

8
tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout
View file

@ -3,10 +3,10 @@ Redirecting stderr to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timin
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Oct 13 2016 20:36:34
gem5 started Oct 13 2016 20:36:59
gem5 executing on e108600-lin, pid 36840
command line: /work/curdun01/gem5-external.hg/build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/mips/linux/o3-timing
gem5 compiled Nov 29 2016 18:13:44
gem5 started Nov 29 2016 18:14:01
gem5 executing on zizzer, pid 32698
command line: /z/powerjg/gem5-upstream/build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/00.hello/mips/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

412
tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.000024 # Nu
sim_ticks 24405000 # Number of ticks simulated
final_tick 24405000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 123007 # Simulator instruction rate (inst/s)
host_op_rate 122970 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 600170719 # Simulator tick rate (ticks/s)
host_mem_usage 251144 # Number of bytes of host memory used
host_seconds 0.04 # Real time elapsed on the host
host_inst_rate 38911 # Simulator instruction rate (inst/s)
host_op_rate 38904 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 189891987 # Simulator tick rate (ticks/s)
host_mem_usage 234100 # Number of bytes of host memory used
host_seconds 0.13 # Real time elapsed on the host
sim_insts 4999 # Number of instructions simulated
sim_ops 4999 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@ -201,12 +201,12 @@ system.physmem.bytesPerActivate::768-895 4 3.51% 93.86% # By
system.physmem.bytesPerActivate::896-1023 3 2.63% 96.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 4 3.51% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 114 # Bytes accessed per row activation
system.physmem.totQLat 7578250 # Total ticks spent queuing
system.physmem.totMemAccLat 16372000 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totQLat 7577250 # Total ticks spent queuing
system.physmem.totMemAccLat 16371000 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2345000 # Total ticks spent in databus transfers
system.physmem.avgQLat 16158.32 # Average queueing delay per DRAM burst
system.physmem.avgQLat 16156.18 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 34908.32 # Average memory access latency per DRAM burst
system.physmem.avgMemAccLat 34906.18 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 1229.91 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 1229.91 # Average system read bandwidth in MiByte/s
@ -229,9 +229,9 @@ system.physmem_0.readEnergy 756840 # En
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 1602840 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 46080 # Energy for precharge background per rank (pJ)
system.physmem_0.preBackEnergy 46560 # Energy for precharge background per rank (pJ)
system.physmem_0.actPowerDownEnergy 8339100 # Energy for active power-down per rank (pJ)
system.physmem_0.prePowerDownEnergy 953280 # Energy for precharge power-down per rank (pJ)
system.physmem_0.prePowerDownEnergy 952800 # Energy for precharge power-down per rank (pJ)
system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
system.physmem_0.totalEnergy 13833510 # Total energy per rank (pJ)
system.physmem_0.averagePower 566.830977 # Core power per rank (mW)
@ -239,9 +239,9 @@ system.physmem_0.totalIdleTime 20709000 # To
system.physmem_0.memoryStateTime::IDLE 23500 # Time in different power states
system.physmem_0.memoryStateTime::REF 780000 # Time in different power states
system.physmem_0.memoryStateTime::SREF 0 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 2481750 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 2481250 # Time in different power states
system.physmem_0.memoryStateTime::ACT 2828750 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 18291000 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 18291500 # Time in different power states
system.physmem_1.actEnergy 642600 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 333960 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 2591820 # Energy for read commands per rank (pJ)
@ -299,7 +299,7 @@ system.cpu.pwrStateResidencyTicks::ON 24405000 # Cu
system.cpu.numCycles 48811 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles 9089 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.icacheStallCycles 9088 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 13001 # Number of instructions fetch has processed
system.cpu.fetch.Branches 2188 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 841 # Number of branches that fetch has predicted taken
@ -308,11 +308,11 @@ system.cpu.fetch.SquashCycles 868 # Nu
system.cpu.fetch.PendingTrapStallCycles 205 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 2050 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 263 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 15175 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 0.856738 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.144886 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::samples 15174 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 0.856795 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.144946 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 11815 77.86% 77.86% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 11814 77.86% 77.86% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 1507 9.93% 87.79% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 111 0.73% 88.52% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 162 1.07% 89.59% # Number of instructions fetched each cycle (Total)
@ -324,11 +324,11 @@ system.cpu.fetch.rateDist::8 903 5.95% 100.00% # Nu
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 15175 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 15174 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.044826 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.266354 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 8420 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 3451 # Number of cycles decode is blocked
system.cpu.decode.BlockedCycles 3450 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 2768 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 142 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 394 # Number of cycles decode is squashing
@ -338,7 +338,7 @@ system.cpu.decode.DecodedInsts 12000 # Nu
system.cpu.decode.SquashedInsts 160 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 394 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 8571 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 621 # Number of cycles rename is blocking
system.cpu.rename.BlockCycles 620 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 1023 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 2740 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 1826 # Number of cycles rename is unblocking
@ -356,25 +356,25 @@ system.cpu.rename.UndoneMaps 3635 # Nu
system.cpu.rename.serializingInsts 13 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 9 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 323 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 2470 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 1160 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.insertedLoads 2468 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 1158 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 6 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 9019 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsAdded 9014 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 11 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 8119 # Number of instructions issued
system.cpu.iq.iqInstsIssued 8118 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 19 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 4030 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 2019 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedInstsExamined 4025 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 2012 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 15175 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.535025 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.265920 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::samples 15174 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.534994 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.265800 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 11852 78.10% 78.10% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 1334 8.79% 86.89% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 728 4.80% 91.69% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 454 2.99% 94.68% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 11850 78.09% 78.09% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 1336 8.80% 86.90% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 728 4.80% 91.70% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 453 2.99% 94.68% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 341 2.25% 96.93% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 284 1.87% 98.80% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 110 0.72% 99.53% # Number of insts issued each cycle
@ -383,7 +383,7 @@ system.cpu.iq.issued_per_cycle::8 19 0.13% 100.00% # Nu
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 15175 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 15174 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 6 3.33% 3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 3.33% # attempts to use FU when none available
@ -423,73 +423,73 @@ system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # at
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 4775 58.81% 58.81% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.86% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 1 0.01% 58.87% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 58.90% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.90% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.90% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.90% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 58.90% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.90% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 58.90% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.90% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 2274 28.01% 86.91% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 4775 58.82% 58.82% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.87% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 1 0.01% 58.88% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 58.91% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.91% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.91% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.91% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 58.91% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.91% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 58.91% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.91% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 2273 28.00% 86.91% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 1063 13.09% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 8119 # Type of FU issued
system.cpu.iq.rate 0.166335 # Inst issue rate
system.cpu.iq.FU_type_0::total 8118 # Type of FU issued
system.cpu.iq.rate 0.166315 # Inst issue rate
system.cpu.iq.fu_busy_cnt 180 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.022170 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 31608 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 13067 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 7338 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fu_busy_rate 0.022173 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 31605 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 13057 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 7337 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 8297 # Number of integer alu accesses
system.cpu.iq.int_alu_accesses 8296 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 78 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 1335 # Number of loads squashed
system.cpu.iew.lsq.thread0.squashedLoads 1333 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 10 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 259 # Number of stores squashed
system.cpu.iew.lsq.thread0.squashedStores 257 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 25 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 394 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 491 # Number of cycles IEW is blocking
system.cpu.iew.iewBlockCycles 490 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 74 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 10629 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispatchedInsts 10621 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 154 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 2470 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 1160 # Number of dispatched store instructions
system.cpu.iew.iewDispLoadInsts 2468 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 1158 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 11 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 75 # Number of times the LSQ has become full, causing a stall
@ -497,22 +497,22 @@ system.cpu.iew.memOrderViolationEvents 10 # Nu
system.cpu.iew.predictedTakenIncorrect 101 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 338 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 439 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 7792 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 2130 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 327 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 7790 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 2129 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 328 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 1599 # number of nop insts executed
system.cpu.iew.exec_refs 3179 # number of memory reference insts executed
system.cpu.iew.exec_branches 1364 # Number of branches executed
system.cpu.iew.exec_nop 1596 # number of nop insts executed
system.cpu.iew.exec_refs 3178 # number of memory reference insts executed
system.cpu.iew.exec_branches 1363 # Number of branches executed
system.cpu.iew.exec_stores 1049 # Number of stores executed
system.cpu.iew.exec_rate 0.159636 # Inst execution rate
system.cpu.iew.wb_sent 7433 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 7340 # cumulative count of insts written-back
system.cpu.iew.exec_rate 0.159595 # Inst execution rate
system.cpu.iew.wb_sent 7432 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 7339 # cumulative count of insts written-back
system.cpu.iew.wb_producers 2867 # num instructions producing a value
system.cpu.iew.wb_consumers 4275 # num instructions consuming a value
system.cpu.iew.wb_rate 0.150376 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.670643 # average fanout of values written-back
system.cpu.commit.commitSquashedInsts 4990 # The number of squashed insts skipped by commit
system.cpu.iew.wb_consumers 4274 # num instructions consuming a value
system.cpu.iew.wb_rate 0.150355 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.670800 # average fanout of values written-back
system.cpu.commit.commitSquashedInsts 4982 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 9 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 384 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 14293 # Number of insts commited each cycle
@ -582,46 +582,46 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 5640 # Class of committed instruction
system.cpu.commit.bw_lim_events 102 # number cycles where commit BW limit reached
system.cpu.rob.rob_reads 24808 # The number of ROB reads
system.cpu.rob.rob_writes 22150 # The number of ROB writes
system.cpu.rob.rob_reads 24800 # The number of ROB reads
system.cpu.rob.rob_writes 22133 # The number of ROB writes
system.cpu.timesIdled 264 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 33636 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.idleCycles 33637 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 4999 # Number of Instructions Simulated
system.cpu.committedOps 4999 # Number of Ops (including micro ops) Simulated
system.cpu.cpi 9.764153 # CPI: Cycles Per Instruction
system.cpu.cpi_total 9.764153 # CPI: Total CPI of All Threads
system.cpu.ipc 0.102415 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.102415 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 10563 # number of integer regfile reads
system.cpu.int_regfile_reads 10560 # number of integer regfile reads
system.cpu.int_regfile_writes 5141 # number of integer regfile writes
system.cpu.fp_regfile_reads 3 # number of floating regfile reads
system.cpu.fp_regfile_writes 1 # number of floating regfile writes
system.cpu.misc_regfile_reads 161 # number of misc regfile reads
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 91.114118 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 2396 # Total number of references to valid blocks.
system.cpu.dcache.tags.tagsinuse 91.114159 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 2395 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 140 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 17.114286 # Average number of references to valid blocks.
system.cpu.dcache.tags.avg_refs 17.107143 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 91.114118 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_blocks::cpu.data 91.114159 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.022245 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.022245 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 140 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 109 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.034180 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 5954 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 5954 # Number of data accesses
system.cpu.dcache.tags.tag_accesses 5952 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 5952 # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 1839 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1839 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::cpu.data 1838 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1838 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 557 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 557 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 2396 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 2396 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 2396 # number of overall hits
system.cpu.dcache.overall_hits::total 2396 # number of overall hits
system.cpu.dcache.demand_hits::cpu.data 2395 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 2395 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 2395 # number of overall hits
system.cpu.dcache.overall_hits::total 2395 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 167 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 167 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 344 # number of WriteReq misses
@ -630,38 +630,38 @@ system.cpu.dcache.demand_misses::cpu.data 511 # n
system.cpu.dcache.demand_misses::total 511 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 511 # number of overall misses
system.cpu.dcache.overall_misses::total 511 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 12711500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 12711500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::cpu.data 12709500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 12709500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 34219499 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 34219499 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 46930999 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 46930999 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 46930999 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 46930999 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 2006 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 2006 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.demand_miss_latency::cpu.data 46928999 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 46928999 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 46928999 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 46928999 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 2005 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 2005 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 2907 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 2907 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 2907 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 2907 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.083250 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.083250 # miss rate for ReadReq accesses
system.cpu.dcache.demand_accesses::cpu.data 2906 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 2906 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 2906 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 2906 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.083292 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.083292 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.381798 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.381798 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.175783 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.175783 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.175783 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.175783 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76116.766467 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 76116.766467 # average ReadReq miss latency
system.cpu.dcache.demand_miss_rate::cpu.data 0.175843 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.175843 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.175843 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.175843 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76104.790419 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 76104.790419 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 99475.287791 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 99475.287791 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 91841.485323 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 91841.485323 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 91841.485323 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 91841.485323 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 91837.571429 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 91837.571429 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 91837.571429 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 91837.571429 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 636 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 10 # number of cycles access was blocked
@ -684,30 +684,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 140
system.cpu.dcache.demand_mshr_misses::total 140 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 140 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 140 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8095000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 8095000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8094500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 8094500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4915999 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4915999 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13010999 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 13010999 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13010999 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 13010999 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.044865 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.044865 # mshr miss rate for ReadReq accesses
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13010499 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 13010499 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13010499 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 13010499 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.044888 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.044888 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048160 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.048160 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048160 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.048160 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 89944.444444 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 89944.444444 # average ReadReq mshr miss latency
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048176 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.048176 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048176 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.048176 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 89938.888889 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 89938.888889 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 98319.980000 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 98319.980000 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 92935.707143 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 92935.707143 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 92935.707143 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 92935.707143 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 92932.135714 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 92932.135714 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 92932.135714 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 92932.135714 # average overall mshr miss latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 17 # number of replacements
system.cpu.icache.tags.tagsinuse 160.115290 # Cycle average of tags in use
@ -781,33 +781,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 332
system.cpu.icache.demand_mshr_misses::total 332 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 332 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 332 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28113000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 28113000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28113000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 28113000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28113000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 28113000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28112000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 28112000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28112000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 28112000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28112000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 28112000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.161951 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.161951 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.161951 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.161951 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.161951 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.161951 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 84677.710843 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 84677.710843 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84677.710843 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 84677.710843 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84677.710843 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 84677.710843 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 84674.698795 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 84674.698795 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84674.698795 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 84674.698795 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84674.698795 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 84674.698795 # average overall mshr miss latency
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 253.317608 # Cycle average of tags in use
system.cpu.l2cache.tags.tagsinuse 253.317649 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 20 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 469 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.042644 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst 162.143256 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 91.174352 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 91.174392 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004948 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.002782 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.007731 # Average percentage of cache occupancy
@ -840,16 +840,16 @@ system.cpu.l2cache.overall_misses::cpu.data 140 #
system.cpu.l2cache.overall_misses::total 469 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4840000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 4840000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 27582000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 27582000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7957000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 7957000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 27582000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 12797000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 40379000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 27582000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 12797000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 40379000 # number of overall miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 27581000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 27581000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7956500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 7956500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 27581000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 12796500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 40377500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 27581000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 12796500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 40377500 # number of overall miss cycles
system.cpu.l2cache.WritebackClean_accesses::writebacks 17 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 17 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 50 # number of ReadExReq accesses(hits+misses)
@ -878,16 +878,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 1
system.cpu.l2cache.overall_miss_rate::total 0.993644 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 96800 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 96800 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83835.866261 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83835.866261 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 88411.111111 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 88411.111111 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83835.866261 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 91407.142857 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 86095.948827 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83835.866261 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 91407.142857 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 86095.948827 # average overall miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83832.826748 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83832.826748 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 88405.555556 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 88405.555556 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83832.826748 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 91403.571429 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 86092.750533 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83832.826748 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 91403.571429 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 86092.750533 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -908,16 +908,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data 140
system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4340000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4340000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 24292000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 24292000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7057000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7057000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24292000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11397000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 35689000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24292000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11397000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 35689000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 24291000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 24291000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7056500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7056500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24291000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11396500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 35687500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24291000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11396500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 35687500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.990964 # mshr miss rate for ReadCleanReq accesses
@ -932,16 +932,16 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1
system.cpu.l2cache.overall_mshr_miss_rate::total 0.993644 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86800 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86800 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73835.866261 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73835.866261 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78411.111111 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78411.111111 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73835.866261 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 81407.142857 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76095.948827 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73835.866261 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 81407.142857 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76095.948827 # average overall mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73832.826748 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73832.826748 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78405.555556 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78405.555556 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73832.826748 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 81403.571429 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76092.750533 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73832.826748 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 81403.571429 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76092.750533 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 489 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 17 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
@ -1007,7 +1007,7 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 469 # Request fanout histogram
system.membus.reqLayer0.occupancy 581500 # Layer occupancy (ticks)
system.membus.reqLayer0.occupancy 581000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 2.4 # Layer utilization (%)
system.membus.respLayer1.occupancy 2488500 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 10.2 # Layer utilization (%)

84
tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini
View file

@ -178,10 +178,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=4
@ -195,6 +195,7 @@ response_latency=2
sequential_access=false
size=262144
system=system
tag_latency=2
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
@ -207,15 +208,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=262144
tag_latency=2
[system.cpu.dtb]
type=PowerTLB
@ -293,10 +295,10 @@ pipelined=true
[system.cpu.fuPool.FUList3]
type=FUDesc
children=opList0 opList1 opList2
children=opList0 opList1 opList2 opList3 opList4
count=2
eventq_index=0
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4
[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
@ -308,11 +310,25 @@ pipelined=true
[system.cpu.fuPool.FUList3.opList1]
type=OpDesc
eventq_index=0
opClass=FloatMultAcc
opLat=5
pipelined=true
[system.cpu.fuPool.FUList3.opList2]
type=OpDesc
eventq_index=0
opClass=FloatMisc
opLat=3
pipelined=true
[system.cpu.fuPool.FUList3.opList3]
type=OpDesc
eventq_index=0
opClass=FloatDiv
opLat=12
pipelined=false
[system.cpu.fuPool.FUList3.opList2]
[system.cpu.fuPool.FUList3.opList4]
type=OpDesc
eventq_index=0
opClass=FloatSqrt
@ -321,18 +337,25 @@ pipelined=false
[system.cpu.fuPool.FUList4]
type=FUDesc
children=opList
children=opList0 opList1
count=0
eventq_index=0
opList=system.cpu.fuPool.FUList4.opList
opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1
[system.cpu.fuPool.FUList4.opList]
[system.cpu.fuPool.FUList4.opList0]
type=OpDesc
eventq_index=0
opClass=MemRead
opLat=1
pipelined=true
[system.cpu.fuPool.FUList4.opList1]
type=OpDesc
eventq_index=0
opClass=FloatMemRead
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5]
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
@ -482,24 +505,31 @@ pipelined=true
[system.cpu.fuPool.FUList6]
type=FUDesc
children=opList
children=opList0 opList1
count=0
eventq_index=0
opList=system.cpu.fuPool.FUList6.opList
opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
[system.cpu.fuPool.FUList6.opList]
[system.cpu.fuPool.FUList6.opList0]
type=OpDesc
eventq_index=0
opClass=MemWrite
opLat=1
pipelined=true
[system.cpu.fuPool.FUList6.opList1]
type=OpDesc
eventq_index=0
opClass=FloatMemWrite
opLat=1
pipelined=true
[system.cpu.fuPool.FUList7]
type=FUDesc
children=opList0 opList1
children=opList0 opList1 opList2 opList3
count=4
eventq_index=0
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 system.cpu.fuPool.FUList7.opList2 system.cpu.fuPool.FUList7.opList3
[system.cpu.fuPool.FUList7.opList0]
type=OpDesc
@ -515,6 +545,20 @@ opClass=MemWrite
opLat=1
pipelined=true
[system.cpu.fuPool.FUList7.opList2]
type=OpDesc
eventq_index=0
opClass=FloatMemRead
opLat=1
pipelined=true
[system.cpu.fuPool.FUList7.opList3]
type=OpDesc
eventq_index=0
opClass=FloatMemWrite
opLat=1
pipelined=true
[system.cpu.fuPool.FUList8]
type=FUDesc
children=opList
@ -536,10 +580,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=true
max_miss_count=0
mshrs=4
@ -553,6 +597,7 @@ response_latency=2
sequential_access=false
size=131072
system=system
tag_latency=2
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
@ -565,15 +610,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=131072
tag_latency=2
[system.cpu.interrupts]
type=PowerInterrupts
@ -595,10 +641,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=20
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=20
is_read_only=false
max_miss_count=0
mshrs=20
@ -612,6 +658,7 @@ response_latency=20
sequential_access=false
size=2097152
system=system
tag_latency=20
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
@ -624,15 +671,16 @@ type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=20
default_p_state=UNDEFINED
eventq_index=0
hit_latency=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=2097152
tag_latency=20
[system.cpu.toL2Bus]
type=CoherentXBar
@ -677,7 +725,7 @@ env=
errout=cerr
euid=100
eventq_index=0
executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/power/linux/hello
executable=/dist/m5/regression/test-progs/hello/bin/power/linux/hello
gid=100
input=cin
kvmInSE=false

8
tests/quick/se/00.hello/ref/power/linux/o3-timing/simout
View file

@ -3,10 +3,10 @@ Redirecting stderr to build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-tim
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Oct 13 2016 20:40:28
gem5 started Oct 13 2016 20:40:51
gem5 executing on e108600-lin, pid 9917
command line: /work/curdun01/gem5-external.hg/build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/power/linux/o3-timing
gem5 compiled Nov 29 2016 18:37:43
gem5 started Nov 29 2016 18:37:59
gem5 executing on zizzer, pid 53433
command line: /z/powerjg/gem5-upstream/build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/00.hello/power/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

64
tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.000021 # Nu
sim_ticks 21268000 # Number of ticks simulated
final_tick 21268000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 133148 # Simulator instruction rate (inst/s)
host_op_rate 133114 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 488684971 # Simulator tick rate (ticks/s)
host_mem_usage 249832 # Number of bytes of host memory used
host_seconds 0.04 # Real time elapsed on the host
host_inst_rate 49400 # Simulator instruction rate (inst/s)
host_op_rate 49392 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 181337178 # Simulator tick rate (ticks/s)
host_mem_usage 231948 # Number of bytes of host memory used
host_seconds 0.12 # Real time elapsed on the host
sim_insts 5792 # Number of instructions simulated
sim_ops 5792 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@ -299,7 +299,7 @@ system.cpu.pwrStateResidencyTicks::ON 21268000 # Cu
system.cpu.numCycles 42537 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles 7672 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.icacheStallCycles 7674 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 13369 # Number of instructions fetch has processed
system.cpu.fetch.Branches 2411 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 939 # Number of branches that fetch has predicted taken
@ -310,26 +310,26 @@ system.cpu.fetch.PendingTrapStallCycles 146 # Nu
system.cpu.fetch.IcacheWaitRetryStallCycles 22 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 1861 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 290 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 12418 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.076582 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.475981 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::samples 12420 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.076409 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.475819 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 10084 81.20% 81.20% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 10086 81.21% 81.21% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 166 1.34% 82.54% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 214 1.72% 84.26% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 214 1.72% 84.27% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 147 1.18% 85.45% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 241 1.94% 87.39% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 150 1.21% 88.60% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 280 2.25% 90.85% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 148 1.19% 92.04% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 988 7.96% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 148 1.19% 92.05% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 988 7.95% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 12418 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 12420 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.056680 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.314291 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 7245 # Number of cycles decode is idle
system.cpu.decode.IdleCycles 7247 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 2821 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 1946 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 130 # Number of cycles decode is unblocking
@ -339,7 +339,7 @@ system.cpu.decode.BranchMispred 149 # Nu
system.cpu.decode.DecodedInsts 11479 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 451 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 276 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 7413 # Number of cycles rename is idle
system.cpu.rename.IdleCycles 7415 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 800 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 463 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 1897 # Number of cycles rename is running
@ -368,11 +368,11 @@ system.cpu.iq.iqSquashedInstsIssued 53 # Nu
system.cpu.iq.iqSquashedInstsExamined 4442 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 3474 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 47 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 12418 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.709293 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.511827 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::samples 12420 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.709179 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.511732 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 9303 74.92% 74.92% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 9305 74.92% 74.92% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 969 7.80% 82.72% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 656 5.28% 88.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 462 3.72% 91.72% # Number of insts issued each cycle
@ -384,7 +384,7 @@ system.cpu.iq.issued_per_cycle::8 30 0.24% 100.00% # Nu
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 12418 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 12420 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 12 6.06% 6.06% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 6.06% # attempts to use FU when none available
@ -465,7 +465,7 @@ system.cpu.iq.FU_type_0::total 8808 # Ty
system.cpu.iq.rate 0.207067 # Inst issue rate
system.cpu.iq.fu_busy_cnt 198 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.022480 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 30218 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_reads 30220 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 14647 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 8115 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 67 # Number of floating instruction queue reads
@ -516,14 +516,14 @@ system.cpu.iew.wb_fanout 0.621403 # av
system.cpu.commit.commitSquashedInsts 4444 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 270 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 11716 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.494367 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.358573 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::samples 11718 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.494282 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.358473 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 9551 81.52% 81.52% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 850 7.26% 88.78% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 527 4.50% 93.27% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 215 1.84% 95.11% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 9553 81.52% 81.52% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 850 7.25% 88.78% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 527 4.50% 93.28% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 215 1.83% 95.11% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 176 1.50% 96.61% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 112 0.96% 97.57% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 126 1.08% 98.64% # Number of insts commited each cycle
@ -532,7 +532,7 @@ system.cpu.commit.committed_per_cycle::8 110 0.94% 100.00% # Nu
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 11716 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 11718 # Number of insts commited each cycle
system.cpu.commit.committedInsts 5792 # Number of instructions committed
system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
@ -583,10 +583,10 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 5792 # Class of committed instruction
system.cpu.commit.bw_lim_events 110 # number cycles where commit BW limit reached
system.cpu.rob.rob_reads 21842 # The number of ROB reads
system.cpu.rob.rob_reads 21844 # The number of ROB reads
system.cpu.rob.rob_writes 21175 # The number of ROB writes
system.cpu.timesIdled 228 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 30119 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.idleCycles 30117 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 5792 # Number of Instructions Simulated
system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated
system.cpu.cpi 7.344095 # CPI: Cycles Per Instruction

902
tests/quick/se/00.hello/ref/riscv/linux/minor-timing/config.ini Normal file
View file

@ -0,0 +1,902 @@
[root]
type=Root
children=system
eventq_index=0
full_system=false
sim_quantum=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.clk_domain]
type=SrcClockDomain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.cpu]
type=MinorCPU
children=branchPred dcache dtb executeFuncUnits icache interrupts isa itb l2cache toL2Bus tracer workload
branchPred=system.cpu.branchPred
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
decodeCycleInput=true
decodeInputBufferSize=3
decodeInputWidth=2
decodeToExecuteForwardDelay=1
default_p_state=UNDEFINED
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
enableIdling=true
eventq_index=0
executeAllowEarlyMemoryIssue=true
executeBranchDelay=1
executeCommitLimit=2
executeCycleInput=true
executeFuncUnits=system.cpu.executeFuncUnits
executeInputBufferSize=7
executeInputWidth=2
executeIssueLimit=2
executeLSQMaxStoreBufferStoresPerCycle=2
executeLSQRequestsQueueSize=1
executeLSQStoreBufferSize=5
executeLSQTransfersQueueSize=2
executeMaxAccessesInMemory=2
executeMemoryCommitLimit=1
executeMemoryIssueLimit=1
executeMemoryWidth=0
executeSetTraceTimeOnCommit=true
executeSetTraceTimeOnIssue=false
fetch1FetchLimit=1
fetch1LineSnapWidth=0
fetch1LineWidth=0
fetch1ToFetch2BackwardDelay=1
fetch1ToFetch2ForwardDelay=1
fetch2CycleInput=true
fetch2InputBufferSize=2
fetch2ToDecodeForwardDelay=1
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
profile=0
progress_interval=0
simpoint_start_insts=
socket_id=0
switched_out=false
system=system
threadPolicy=RoundRobin
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
type=TournamentBP
BTBEntries=4096
BTBTagSize=16
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
indirectHashGHR=true
indirectHashTargets=true
indirectPathLength=3
indirectSets=256
indirectTagSize=16
indirectWays=2
instShiftAmt=2
localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
useIndirect=true
[system.cpu.dcache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
is_read_only=false
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=262144
system=system
tag_latency=2
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dcache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=262144
tag_latency=2
[system.cpu.dtb]
type=RiscvTLB
eventq_index=0
size=64
[system.cpu.executeFuncUnits]
type=MinorFUPool
children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6
eventq_index=0
funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6
[system.cpu.executeFuncUnits.funcUnits0]
type=MinorFU
children=opClasses timings
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses
opLat=3
timings=system.cpu.executeFuncUnits.funcUnits0.timings
[system.cpu.executeFuncUnits.funcUnits0.opClasses]
type=MinorOpClassSet
children=opClasses
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses
[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses]
type=MinorOpClass
eventq_index=0
opClass=IntAlu
[system.cpu.executeFuncUnits.funcUnits0.timings]
type=MinorFUTiming
children=opClasses
description=Int
eventq_index=0
extraAssumedLat=0
extraCommitLat=0
extraCommitLatExpr=Null
mask=0
match=0
opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses
srcRegsRelativeLats=2
suppress=false
[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses]
type=MinorOpClassSet
eventq_index=0
opClasses=
[system.cpu.executeFuncUnits.funcUnits1]
type=MinorFU
children=opClasses timings
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses
opLat=3
timings=system.cpu.executeFuncUnits.funcUnits1.timings
[system.cpu.executeFuncUnits.funcUnits1.opClasses]
type=MinorOpClassSet
children=opClasses
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses
[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses]
type=MinorOpClass
eventq_index=0
opClass=IntAlu
[system.cpu.executeFuncUnits.funcUnits1.timings]
type=MinorFUTiming
children=opClasses
description=Int
eventq_index=0
extraAssumedLat=0
extraCommitLat=0
extraCommitLatExpr=Null
mask=0
match=0
opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses
srcRegsRelativeLats=2
suppress=false
[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses]
type=MinorOpClassSet
eventq_index=0
opClasses=
[system.cpu.executeFuncUnits.funcUnits2]
type=MinorFU
children=opClasses timings
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses
opLat=3
timings=system.cpu.executeFuncUnits.funcUnits2.timings
[system.cpu.executeFuncUnits.funcUnits2.opClasses]
type=MinorOpClassSet
children=opClasses
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses
[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses]
type=MinorOpClass
eventq_index=0
opClass=IntMult
[system.cpu.executeFuncUnits.funcUnits2.timings]
type=MinorFUTiming
children=opClasses
description=Mul
eventq_index=0
extraAssumedLat=0
extraCommitLat=0
extraCommitLatExpr=Null
mask=0
match=0
opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses
srcRegsRelativeLats=0
suppress=false
[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses]
type=MinorOpClassSet
eventq_index=0
opClasses=
[system.cpu.executeFuncUnits.funcUnits3]
type=MinorFU
children=opClasses
cantForwardFromFUIndices=
eventq_index=0
issueLat=9
opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses
opLat=9
timings=
[system.cpu.executeFuncUnits.funcUnits3.opClasses]
type=MinorOpClassSet
children=opClasses
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses
[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses]
type=MinorOpClass
eventq_index=0
opClass=IntDiv
[system.cpu.executeFuncUnits.funcUnits4]
type=MinorFU
children=opClasses timings
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses
opLat=6
timings=system.cpu.executeFuncUnits.funcUnits4.timings
[system.cpu.executeFuncUnits.funcUnits4.opClasses]
type=MinorOpClassSet
children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 opClasses26 opClasses27
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses26 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses27
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00]
type=MinorOpClass
eventq_index=0
opClass=FloatAdd
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01]
type=MinorOpClass
eventq_index=0
opClass=FloatCmp
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02]
type=MinorOpClass
eventq_index=0
opClass=FloatCvt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03]
type=MinorOpClass
eventq_index=0
opClass=FloatMisc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04]
type=MinorOpClass
eventq_index=0
opClass=FloatMult
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05]
type=MinorOpClass
eventq_index=0
opClass=FloatMultAcc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06]
type=MinorOpClass
eventq_index=0
opClass=FloatDiv
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07]
type=MinorOpClass
eventq_index=0
opClass=FloatSqrt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08]
type=MinorOpClass
eventq_index=0
opClass=SimdAdd
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09]
type=MinorOpClass
eventq_index=0
opClass=SimdAddAcc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10]
type=MinorOpClass
eventq_index=0
opClass=SimdAlu
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11]
type=MinorOpClass
eventq_index=0
opClass=SimdCmp
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12]
type=MinorOpClass
eventq_index=0
opClass=SimdCvt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13]
type=MinorOpClass
eventq_index=0
opClass=SimdMisc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14]
type=MinorOpClass
eventq_index=0
opClass=SimdMult
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15]
type=MinorOpClass
eventq_index=0
opClass=SimdMultAcc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16]
type=MinorOpClass
eventq_index=0
opClass=SimdShift
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17]
type=MinorOpClass
eventq_index=0
opClass=SimdShiftAcc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18]
type=MinorOpClass
eventq_index=0
opClass=SimdSqrt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatAdd
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatAlu
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatCmp
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatCvt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatDiv
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatMisc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatMult
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses26]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatMultAcc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses27]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatSqrt
[system.cpu.executeFuncUnits.funcUnits4.timings]
type=MinorFUTiming
children=opClasses
description=FloatSimd
eventq_index=0
extraAssumedLat=0
extraCommitLat=0
extraCommitLatExpr=Null
mask=0
match=0
opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses
srcRegsRelativeLats=2
suppress=false
[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses]
type=MinorOpClassSet
eventq_index=0
opClasses=
[system.cpu.executeFuncUnits.funcUnits5]
type=MinorFU
children=opClasses timings
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses
opLat=1
timings=system.cpu.executeFuncUnits.funcUnits5.timings
[system.cpu.executeFuncUnits.funcUnits5.opClasses]
type=MinorOpClassSet
children=opClasses0 opClasses1 opClasses2 opClasses3
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses2 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses3
[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0]
type=MinorOpClass
eventq_index=0
opClass=MemRead
[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1]
type=MinorOpClass
eventq_index=0
opClass=MemWrite
[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses2]
type=MinorOpClass
eventq_index=0
opClass=FloatMemRead
[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses3]
type=MinorOpClass
eventq_index=0
opClass=FloatMemWrite
[system.cpu.executeFuncUnits.funcUnits5.timings]
type=MinorFUTiming
children=opClasses
description=Mem
eventq_index=0
extraAssumedLat=2
extraCommitLat=0
extraCommitLatExpr=Null
mask=0
match=0
opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses
srcRegsRelativeLats=1
suppress=false
[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses]
type=MinorOpClassSet
eventq_index=0
opClasses=
[system.cpu.executeFuncUnits.funcUnits6]
type=MinorFU
children=opClasses
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses
opLat=1
timings=
[system.cpu.executeFuncUnits.funcUnits6.opClasses]
type=MinorOpClassSet
children=opClasses0 opClasses1
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1
[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0]
type=MinorOpClass
eventq_index=0
opClass=IprAccess
[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1]
type=MinorOpClass
eventq_index=0
opClass=InstPrefetch
[system.cpu.icache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
is_read_only=true
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=131072
system=system
tag_latency=2
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=true
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.icache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=131072
tag_latency=2
[system.cpu.interrupts]
type=RiscvInterrupts
eventq_index=0
[system.cpu.isa]
type=RiscvISA
eventq_index=0
[system.cpu.itb]
type=RiscvTLB
eventq_index=0
size=64
[system.cpu.l2cache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=20
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
is_read_only=false
max_miss_count=0
mshrs=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=20
sequential_access=false
size=2097152
system=system
tag_latency=20
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.l2cache.tags]
type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=20
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=2097152
tag_latency=20
[system.cpu.toL2Bus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=0
frontend_latency=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=false
power_model=Null
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.toL2Bus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=0
max_capacity=8388608
system=system
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=LiveProcess
cmd=hello
cwd=
drivers=
egid=100
env=
errout=cerr
euid=100
eventq_index=0
executable=/z/powerjg/gem5-upstream/tests/test-progs/hello/bin/riscv/linux/hello
gid=100
input=cin
kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.dvfs_handler]
type=DVFSHandler
domains=
enable=false
eventq_index=0
sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=4
frontend_latency=3
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem]
type=DRAMCtrl
IDD0=0.055000
IDD02=0.000000
IDD2N=0.032000
IDD2N2=0.000000
IDD2P0=0.000000
IDD2P02=0.000000
IDD2P1=0.032000
IDD2P12=0.000000
IDD3N=0.038000
IDD3N2=0.000000
IDD3P0=0.000000
IDD3P02=0.000000
IDD3P1=0.038000
IDD3P12=0.000000
IDD4R=0.157000
IDD4R2=0.000000
IDD4W=0.125000
IDD4W2=0.000000
IDD5=0.235000
IDD52=0.000000
IDD6=0.020000
IDD62=0.000000
VDD=1.500000
VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
clk_domain=system.clk_domain
conf_table_reported=true
default_p_state=UNDEFINED
device_bus_width=8
device_rowbuffer_size=1024
device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
in_addr_map=true
kvm_map=true
max_accesses_per_row=16
mem_sched_policy=frfcfs
min_writes_per_switch=16
null=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
page_policy=open_adaptive
power_model=Null
range=0:134217727:0:0:0:0
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
tCCD_L=0
tCK=1250
tCL=13750
tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
tXP=6000
tXPDLL=0
tXS=270000
tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
port=system.membus.master[0]
[system.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.000000

1211
tests/quick/se/00.hello/ref/riscv/linux/minor-timing/config.json Normal file
View file

File diff suppressed because it is too large Load diff

4
tests/quick/se/00.hello/ref/riscv/linux/minor-timing/simerr Executable file
View file

@ -0,0 +1,4 @@
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Unknown operating system; assuming Linux.
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick

15
tests/quick/se/00.hello/ref/riscv/linux/minor-timing/simout Executable file
View file

@ -0,0 +1,15 @@
Redirecting stdout to build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/minor-timing/simout
Redirecting stderr to build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/minor-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Nov 30 2016 14:33:35
gem5 started Nov 30 2016 16:18:28
gem5 executing on zizzer, pid 34056
command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/minor-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/00.hello/riscv/linux/minor-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
Exiting @ tick 14435000 because target called exit()

749
tests/quick/se/00.hello/ref/riscv/linux/minor-timing/stats.txt Normal file
View file

@ -0,0 +1,749 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000014 # Number of seconds simulated
sim_ticks 14435000 # Number of ticks simulated
final_tick 14435000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 13240 # Simulator instruction rate (inst/s)
host_op_rate 13237 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 119615611 # Simulator tick rate (ticks/s)
host_mem_usage 232036 # Number of bytes of host memory used
host_seconds 0.12 # Real time elapsed on the host
sim_insts 1597 # Number of instructions simulated
sim_ops 1597 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 14435000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 9984 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 2048 # Number of bytes read from this memory
system.physmem.bytes_read::total 12032 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 9984 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 9984 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 156 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 32 # Number of read requests responded to by this memory
system.physmem.num_reads::total 188 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 691652234 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 141877381 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 833529616 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 691652234 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 691652234 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 691652234 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 141877381 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 833529616 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 188 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 188 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 12032 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 12032 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 97 # Per bank write bursts
system.physmem.perBankRdBursts::1 64 # Per bank write bursts
system.physmem.perBankRdBursts::2 18 # Per bank write bursts
system.physmem.perBankRdBursts::3 9 # Per bank write bursts
system.physmem.perBankRdBursts::4 0 # Per bank write bursts
system.physmem.perBankRdBursts::5 0 # Per bank write bursts
system.physmem.perBankRdBursts::6 0 # Per bank write bursts
system.physmem.perBankRdBursts::7 0 # Per bank write bursts
system.physmem.perBankRdBursts::8 0 # Per bank write bursts
system.physmem.perBankRdBursts::9 0 # Per bank write bursts
system.physmem.perBankRdBursts::10 0 # Per bank write bursts
system.physmem.perBankRdBursts::11 0 # Per bank write bursts
system.physmem.perBankRdBursts::12 0 # Per bank write bursts
system.physmem.perBankRdBursts::13 0 # Per bank write bursts
system.physmem.perBankRdBursts::14 0 # Per bank write bursts
system.physmem.perBankRdBursts::15 0 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
system.physmem.perBankWrBursts::4 0 # Per bank write bursts
system.physmem.perBankWrBursts::5 0 # Per bank write bursts
system.physmem.perBankWrBursts::6 0 # Per bank write bursts
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
system.physmem.perBankWrBursts::10 0 # Per bank write bursts
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 14206000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 188 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 161 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 25 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 13 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 817.230769 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 665.111831 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 349.717542 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 1 7.69% 7.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 1 7.69% 15.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 1 7.69% 23.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1 7.69% 30.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 9 69.23% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 13 # Bytes accessed per row activation
system.physmem.totQLat 1580250 # Total ticks spent queuing
system.physmem.totMemAccLat 5105250 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 940000 # Total ticks spent in databus transfers
system.physmem.avgQLat 8405.59 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 27155.59 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 833.53 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 833.53 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 6.51 # Data bus utilization in percentage
system.physmem.busUtilRead 6.51 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.14 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 171 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 90.96 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 75563.83 # Average gap between requests
system.physmem.pageHitRate 90.96 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 121380 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 49335 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 1342320 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 614640.000000 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 2281140 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 17760 # Energy for precharge background per rank (pJ)
system.physmem_0.actPowerDownEnergy 4279560 # Energy for active power-down per rank (pJ)
system.physmem_0.prePowerDownEnergy 480 # Energy for precharge power-down per rank (pJ)
system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
system.physmem_0.totalEnergy 8706615 # Total energy per rank (pJ)
system.physmem_0.averagePower 603.160028 # Core power per rank (mW)
system.physmem_0.totalIdleTime 9188750 # Total Idle time Per DRAM Rank
system.physmem_0.memoryStateTime::IDLE 18000 # Time in different power states
system.physmem_0.memoryStateTime::REF 260000 # Time in different power states
system.physmem_0.memoryStateTime::SREF 0 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 1250 # Time in different power states
system.physmem_0.memoryStateTime::ACT 4776000 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 9379750 # Time in different power states
system.physmem_1.actEnergy 0 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 0 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 0 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 614640.000000 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 112290 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 2995200 # Energy for precharge background per rank (pJ)
system.physmem_1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ)
system.physmem_1.prePowerDownEnergy 2453280 # Energy for precharge power-down per rank (pJ)
system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
system.physmem_1.totalEnergy 6175410 # Total energy per rank (pJ)
system.physmem_1.averagePower 427.808105 # Core power per rank (mW)
system.physmem_1.totalIdleTime 0 # Total Idle time Per DRAM Rank
system.physmem_1.memoryStateTime::IDLE 7786250 # Time in different power states
system.physmem_1.memoryStateTime::REF 260000 # Time in different power states
system.physmem_1.memoryStateTime::SREF 0 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 6388750 # Time in different power states
system.physmem_1.memoryStateTime::ACT 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.pwrStateResidencyTicks::UNDEFINED 14435000 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 995 # Number of BP lookups
system.cpu.branchPred.condPredicted 543 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 229 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 945 # Number of BTB lookups
system.cpu.branchPred.BTBHits 100 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 10.582011 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups 204 # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits 11 # Number of indirect target hits.
system.cpu.branchPred.indirectMisses 193 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 64 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 9 # Number of system calls
system.cpu.pwrStateResidencyTicks::ON 14435000 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 28870 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 1597 # Number of instructions committed
system.cpu.committedOps 1597 # Number of ops (including micro ops) committed
system.cpu.discardedOps 744 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 18.077646 # CPI: cycles per instruction
system.cpu.ipc 0.055317 # IPC: instructions per cycle
system.cpu.op_class_0::No_OpClass 9 0.56% 0.56% # Class of committed instruction
system.cpu.op_class_0::IntAlu 1019 63.81% 64.37% # Class of committed instruction
system.cpu.op_class_0::IntMult 0 0.00% 64.37% # Class of committed instruction
system.cpu.op_class_0::IntDiv 0 0.00% 64.37% # Class of committed instruction
system.cpu.op_class_0::FloatAdd 0 0.00% 64.37% # Class of committed instruction
system.cpu.op_class_0::FloatCmp 0 0.00% 64.37% # Class of committed instruction
system.cpu.op_class_0::FloatCvt 0 0.00% 64.37% # Class of committed instruction
system.cpu.op_class_0::FloatMult 0 0.00% 64.37% # Class of committed instruction
system.cpu.op_class_0::FloatMultAcc 0 0.00% 64.37% # Class of committed instruction
system.cpu.op_class_0::FloatDiv 0 0.00% 64.37% # Class of committed instruction
system.cpu.op_class_0::FloatMisc 0 0.00% 64.37% # Class of committed instruction
system.cpu.op_class_0::FloatSqrt 0 0.00% 64.37% # Class of committed instruction
system.cpu.op_class_0::SimdAdd 0 0.00% 64.37% # Class of committed instruction
system.cpu.op_class_0::SimdAddAcc 0 0.00% 64.37% # Class of committed instruction
system.cpu.op_class_0::SimdAlu 0 0.00% 64.37% # Class of committed instruction
system.cpu.op_class_0::SimdCmp 0 0.00% 64.37% # Class of committed instruction
system.cpu.op_class_0::SimdCvt 0 0.00% 64.37% # Class of committed instruction
system.cpu.op_class_0::SimdMisc 0 0.00% 64.37% # Class of committed instruction
system.cpu.op_class_0::SimdMult 0 0.00% 64.37% # Class of committed instruction
system.cpu.op_class_0::SimdMultAcc 0 0.00% 64.37% # Class of committed instruction
system.cpu.op_class_0::SimdShift 0 0.00% 64.37% # Class of committed instruction
system.cpu.op_class_0::SimdShiftAcc 0 0.00% 64.37% # Class of committed instruction
system.cpu.op_class_0::SimdSqrt 0 0.00% 64.37% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAdd 0 0.00% 64.37% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAlu 0 0.00% 64.37% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCmp 0 0.00% 64.37% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCvt 0 0.00% 64.37% # Class of committed instruction
system.cpu.op_class_0::SimdFloatDiv 0 0.00% 64.37% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMisc 0 0.00% 64.37% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMult 0 0.00% 64.37% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 64.37% # Class of committed instruction
system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 64.37% # Class of committed instruction
system.cpu.op_class_0::MemRead 289 18.10% 82.47% # Class of committed instruction
system.cpu.op_class_0::MemWrite 280 17.53% 100.00% # Class of committed instruction
system.cpu.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::total 1597 # Class of committed instruction
system.cpu.tickCycles 4106 # Number of cycles that the object actually ticked
system.cpu.idleCycles 24764 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 14435000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 24.135470 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 645 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 33 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 19.545455 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 24.135470 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.005892 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.005892 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 33 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.008057 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 1411 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 1411 # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 14435000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 394 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 394 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 251 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 251 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 645 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 645 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 645 # number of overall hits
system.cpu.dcache.overall_hits::total 645 # number of overall hits
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system.cpu.dcache.ReadReq_misses::total 16 # number of ReadReq misses
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system.cpu.dcache.WriteReq_misses::total 28 # number of WriteReq misses
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system.cpu.dcache.demand_misses::total 44 # number of demand (read+write) misses
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system.cpu.dcache.overall_misses::total 44 # number of overall misses
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system.cpu.dcache.ReadReq_miss_latency::total 1268000 # number of ReadReq miss cycles
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system.cpu.dcache.WriteReq_miss_latency::total 2223500 # number of WriteReq miss cycles
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system.cpu.dcache.demand_miss_latency::total 3491500 # number of demand (read+write) miss cycles
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system.cpu.dcache.overall_miss_latency::total 3491500 # number of overall miss cycles
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system.cpu.dcache.WriteReq_accesses::total 279 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.demand_accesses::total 689 # number of demand (read+write) accesses
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system.cpu.dcache.overall_accesses::total 689 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.039024 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.039024 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.100358 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.100358 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.063861 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.063861 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.063861 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.063861 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 79250 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 79250 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 79410.714286 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 79410.714286 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 79352.272727 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 79352.272727 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 79352.272727 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 79352.272727 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 11 # number of WriteReq MSHR hits
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system.cpu.dcache.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits
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system.cpu.dcache.overall_mshr_hits::total 11 # number of overall MSHR hits
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system.cpu.dcache.WriteReq_mshr_misses::total 17 # number of WriteReq MSHR misses
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system.cpu.dcache.demand_mshr_misses::total 33 # number of demand (read+write) MSHR misses
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system.cpu.dcache.overall_mshr_misses::total 33 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1252000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 1252000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1342000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1342000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 2594000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 2594000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 2594000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 2594000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.039024 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.039024 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.060932 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.060932 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.demand_mshr_miss_rate::total 0.047896 # mshr miss rate for demand accesses
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system.cpu.dcache.overall_mshr_miss_rate::total 0.047896 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78250 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78250 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78941.176471 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78941.176471 # average WriteReq mshr miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency::total 78606.060606 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78606.060606 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 78606.060606 # average overall mshr miss latency
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system.cpu.icache.tags.total_refs 709 # Total number of references to valid blocks.
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system.cpu.icache.tags.avg_refs 4.515924 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.tags.occ_task_id_blocks::1024 157 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 49 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.076660 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 1889 # Number of tag accesses
system.cpu.icache.tags.data_accesses 1889 # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 14435000 # Cumulative time (in ticks) in various power states
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system.cpu.icache.overall_hits::total 709 # number of overall hits
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system.cpu.icache.ReadReq_misses::total 157 # number of ReadReq misses
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system.cpu.icache.overall_misses::total 157 # number of overall misses
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system.cpu.icache.ReadReq_miss_latency::total 12560500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 12560500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 12560500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 12560500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 12560500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 866 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 866 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_accesses::total 866 # number of demand (read+write) accesses
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system.cpu.icache.overall_accesses::total 866 # number of overall (read+write) accesses
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system.cpu.icache.ReadReq_avg_miss_latency::total 80003.184713 # average ReadReq miss latency
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system.cpu.icache.demand_avg_miss_latency::total 80003.184713 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 80003.184713 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 80003.184713 # average overall miss latency
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system.cpu.icache.ReadReq_mshr_misses::total 157 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 157 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 157 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 157 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 157 # number of overall MSHR misses
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system.cpu.icache.ReadReq_mshr_miss_latency::total 12403500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12403500 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12403500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 12403500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.181293 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.181293 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.181293 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.181293 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.181293 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.181293 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 79003.184713 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79003.184713 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 79003.184713 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 79003.184713 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 79003.184713 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 79003.184713 # average overall mshr miss latency
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 14435000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 102.489649 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 188 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.010638 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst 79.179084 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 23.310565 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002416 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000711 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.003128 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 188 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.005737 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 1708 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 1708 # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 14435000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits
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system.cpu.l2cache.ReadSharedReq_hits::total 1 # number of ReadSharedReq hits
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system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits
system.cpu.l2cache.overall_hits::total 2 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 17 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 17 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 156 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 156 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 15 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 15 # number of ReadSharedReq misses
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system.cpu.l2cache.demand_misses::cpu.data 32 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 188 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 156 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 32 # number of overall misses
system.cpu.l2cache.overall_misses::total 188 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1316500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 1316500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 12156500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 12156500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1215500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 1215500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 12156500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 2532000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 14688500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 12156500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 2532000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 14688500 # number of overall miss cycles
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system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 157 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 157 # number of ReadCleanReq accesses(hits+misses)
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system.cpu.l2cache.ReadSharedReq_accesses::total 16 # number of ReadSharedReq accesses(hits+misses)
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system.cpu.l2cache.demand_accesses::cpu.data 33 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 190 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 157 # number of overall (read+write) accesses
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system.cpu.l2cache.overall_accesses::total 190 # number of overall (read+write) accesses
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system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
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system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.993631 # miss rate for ReadCleanReq accesses
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system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.937500 # miss rate for ReadSharedReq accesses
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system.cpu.l2cache.overall_miss_rate::total 0.989474 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77441.176471 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77441.176471 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77926.282051 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77926.282051 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81033.333333 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81033.333333 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77926.282051 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79125 # average overall miss latency
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system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77926.282051 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79125 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 78130.319149 # average overall miss latency
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system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 17 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 17 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 156 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 156 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 15 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 15 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 156 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 32 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 188 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 156 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 32 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 188 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1146500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1146500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 10596500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 10596500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1065500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1065500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10596500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2212000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 12808500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10596500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2212000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 12808500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.993631 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.993631 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.937500 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.937500 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993631 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.969697 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.989474 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993631 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.969697 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.989474 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67441.176471 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67441.176471 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67926.282051 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67926.282051 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71033.333333 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71033.333333 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67926.282051 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69125 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68130.319149 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67926.282051 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69125 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68130.319149 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 190 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 14435000 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 173 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 17 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 17 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 157 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 16 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 314 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 66 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 380 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10048 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2112 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 12160 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples 190 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.010526 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.102326 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 188 98.95% 98.95% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 2 1.05% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 190 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 95000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 235500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 1.6 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 49500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%)
system.membus.snoop_filter.tot_requests 188 # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 14435000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 171 # Transaction distribution
system.membus.trans_dist::ReadExReq 17 # Transaction distribution
system.membus.trans_dist::ReadExResp 17 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 171 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 376 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 376 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 12032 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 12032 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples 188 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 188 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 188 # Request fanout histogram
system.membus.reqLayer0.occupancy 217500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 1.5 # Layer utilization (%)
system.membus.respLayer1.occupancy 991750 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 6.9 # Layer utilization (%)
---------- End Simulation Statistics ----------

872
tests/quick/se/00.hello/ref/riscv/linux/o3-timing/config.ini Normal file
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@ -0,0 +1,872 @@
[root]
type=Root
children=system
eventq_index=0
full_system=false
sim_quantum=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.clk_domain]
type=SrcClockDomain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.cpu]
type=DerivO3CPU
children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
branchPred=system.cpu.branchPred
cachePorts=200
checker=Null
clk_domain=system.cpu_clk_domain
commitToDecodeDelay=1
commitToFetchDelay=1
commitToIEWDelay=1
commitToRenameDelay=1
commitWidth=8
cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
default_p_state=UNDEFINED
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
eventq_index=0
fetchBufferSize=64
fetchQueueSize=32
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
numIQEntries=64
numPhysCCRegs=0
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
renameToIEWDelay=2
renameToROBDelay=1
renameWidth=8
simpoint_start_insts=
smtCommitPolicy=RoundRobin
smtFetchPolicy=SingleThread
smtIQPolicy=Partitioned
smtIQThreshold=100
smtLSQPolicy=Partitioned
smtLSQThreshold=100
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
type=TournamentBP
BTBEntries=4096
BTBTagSize=16
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
indirectHashGHR=true
indirectHashTargets=true
indirectPathLength=3
indirectSets=256
indirectTagSize=16
indirectWays=2
instShiftAmt=2
localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
useIndirect=true
[system.cpu.dcache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
is_read_only=false
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=262144
system=system
tag_latency=2
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dcache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=262144
tag_latency=2
[system.cpu.dtb]
type=RiscvTLB
eventq_index=0
size=64
[system.cpu.fuPool]
type=FUPool
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
eventq_index=0
[system.cpu.fuPool.FUList0]
type=FUDesc
children=opList
count=6
eventq_index=0
opList=system.cpu.fuPool.FUList0.opList
[system.cpu.fuPool.FUList0.opList]
type=OpDesc
eventq_index=0
opClass=IntAlu
opLat=1
pipelined=true
[system.cpu.fuPool.FUList1]
type=FUDesc
children=opList0 opList1
count=2
eventq_index=0
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
[system.cpu.fuPool.FUList1.opList0]
type=OpDesc
eventq_index=0
opClass=IntMult
opLat=3
pipelined=true
[system.cpu.fuPool.FUList1.opList1]
type=OpDesc
eventq_index=0
opClass=IntDiv
opLat=20
pipelined=false
[system.cpu.fuPool.FUList2]
type=FUDesc
children=opList0 opList1 opList2
count=4
eventq_index=0
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
[system.cpu.fuPool.FUList2.opList0]
type=OpDesc
eventq_index=0
opClass=FloatAdd
opLat=2
pipelined=true
[system.cpu.fuPool.FUList2.opList1]
type=OpDesc
eventq_index=0
opClass=FloatCmp
opLat=2
pipelined=true
[system.cpu.fuPool.FUList2.opList2]
type=OpDesc
eventq_index=0
opClass=FloatCvt
opLat=2
pipelined=true
[system.cpu.fuPool.FUList3]
type=FUDesc
children=opList0 opList1 opList2 opList3 opList4
count=2
eventq_index=0
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4
[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
eventq_index=0
opClass=FloatMult
opLat=4
pipelined=true
[system.cpu.fuPool.FUList3.opList1]
type=OpDesc
eventq_index=0
opClass=FloatMultAcc
opLat=5
pipelined=true
[system.cpu.fuPool.FUList3.opList2]
type=OpDesc
eventq_index=0
opClass=FloatMisc
opLat=3
pipelined=true
[system.cpu.fuPool.FUList3.opList3]
type=OpDesc
eventq_index=0
opClass=FloatDiv
opLat=12
pipelined=false
[system.cpu.fuPool.FUList3.opList4]
type=OpDesc
eventq_index=0
opClass=FloatSqrt
opLat=24
pipelined=false
[system.cpu.fuPool.FUList4]
type=FUDesc
children=opList0 opList1
count=0
eventq_index=0
opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1
[system.cpu.fuPool.FUList4.opList0]
type=OpDesc
eventq_index=0
opClass=MemRead
opLat=1
pipelined=true
[system.cpu.fuPool.FUList4.opList1]
type=OpDesc
eventq_index=0
opClass=FloatMemRead
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5]
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
count=4
eventq_index=0
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
[system.cpu.fuPool.FUList5.opList00]
type=OpDesc
eventq_index=0
opClass=SimdAdd
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList01]
type=OpDesc
eventq_index=0
opClass=SimdAddAcc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList02]
type=OpDesc
eventq_index=0
opClass=SimdAlu
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList03]
type=OpDesc
eventq_index=0
opClass=SimdCmp
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList04]
type=OpDesc
eventq_index=0
opClass=SimdCvt
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList05]
type=OpDesc
eventq_index=0
opClass=SimdMisc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList06]
type=OpDesc
eventq_index=0
opClass=SimdMult
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList07]
type=OpDesc
eventq_index=0
opClass=SimdMultAcc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList08]
type=OpDesc
eventq_index=0
opClass=SimdShift
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList09]
type=OpDesc
eventq_index=0
opClass=SimdShiftAcc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList10]
type=OpDesc
eventq_index=0
opClass=SimdSqrt
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList11]
type=OpDesc
eventq_index=0
opClass=SimdFloatAdd
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList12]
type=OpDesc
eventq_index=0
opClass=SimdFloatAlu
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList13]
type=OpDesc
eventq_index=0
opClass=SimdFloatCmp
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList14]
type=OpDesc
eventq_index=0
opClass=SimdFloatCvt
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList15]
type=OpDesc
eventq_index=0
opClass=SimdFloatDiv
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList16]
type=OpDesc
eventq_index=0
opClass=SimdFloatMisc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList17]
type=OpDesc
eventq_index=0
opClass=SimdFloatMult
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList18]
type=OpDesc
eventq_index=0
opClass=SimdFloatMultAcc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList19]
type=OpDesc
eventq_index=0
opClass=SimdFloatSqrt
opLat=1
pipelined=true
[system.cpu.fuPool.FUList6]
type=FUDesc
children=opList0 opList1
count=0
eventq_index=0
opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
[system.cpu.fuPool.FUList6.opList0]
type=OpDesc
eventq_index=0
opClass=MemWrite
opLat=1
pipelined=true
[system.cpu.fuPool.FUList6.opList1]
type=OpDesc
eventq_index=0
opClass=FloatMemWrite
opLat=1
pipelined=true
[system.cpu.fuPool.FUList7]
type=FUDesc
children=opList0 opList1 opList2 opList3
count=4
eventq_index=0
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 system.cpu.fuPool.FUList7.opList2 system.cpu.fuPool.FUList7.opList3
[system.cpu.fuPool.FUList7.opList0]
type=OpDesc
eventq_index=0
opClass=MemRead
opLat=1
pipelined=true
[system.cpu.fuPool.FUList7.opList1]
type=OpDesc
eventq_index=0
opClass=MemWrite
opLat=1
pipelined=true
[system.cpu.fuPool.FUList7.opList2]
type=OpDesc
eventq_index=0
opClass=FloatMemRead
opLat=1
pipelined=true
[system.cpu.fuPool.FUList7.opList3]
type=OpDesc
eventq_index=0
opClass=FloatMemWrite
opLat=1
pipelined=true
[system.cpu.fuPool.FUList8]
type=FUDesc
children=opList
count=1
eventq_index=0
opList=system.cpu.fuPool.FUList8.opList
[system.cpu.fuPool.FUList8.opList]
type=OpDesc
eventq_index=0
opClass=IprAccess
opLat=3
pipelined=false
[system.cpu.icache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
is_read_only=true
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=131072
system=system
tag_latency=2
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=true
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.icache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=131072
tag_latency=2
[system.cpu.interrupts]
type=RiscvInterrupts
eventq_index=0
[system.cpu.isa]
type=RiscvISA
eventq_index=0
[system.cpu.itb]
type=RiscvTLB
eventq_index=0
size=64
[system.cpu.l2cache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=20
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
is_read_only=false
max_miss_count=0
mshrs=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=20
sequential_access=false
size=2097152
system=system
tag_latency=20
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.l2cache.tags]
type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=20
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=2097152
tag_latency=20
[system.cpu.toL2Bus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=0
frontend_latency=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=false
power_model=Null
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.toL2Bus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=0
max_capacity=8388608
system=system
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=LiveProcess
cmd=hello
cwd=
drivers=
egid=100
env=
errout=cerr
euid=100
eventq_index=0
executable=/z/powerjg/gem5-upstream/tests/test-progs/hello/bin/riscv/linux/hello
gid=100
input=cin
kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.dvfs_handler]
type=DVFSHandler
domains=
enable=false
eventq_index=0
sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=4
frontend_latency=3
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem]
type=DRAMCtrl
IDD0=0.055000
IDD02=0.000000
IDD2N=0.032000
IDD2N2=0.000000
IDD2P0=0.000000
IDD2P02=0.000000
IDD2P1=0.032000
IDD2P12=0.000000
IDD3N=0.038000
IDD3N2=0.000000
IDD3P0=0.000000
IDD3P02=0.000000
IDD3P1=0.038000
IDD3P12=0.000000
IDD4R=0.157000
IDD4R2=0.000000
IDD4W=0.125000
IDD4W2=0.000000
IDD5=0.235000
IDD52=0.000000
IDD6=0.020000
IDD62=0.000000
VDD=1.500000
VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
clk_domain=system.clk_domain
conf_table_reported=true
default_p_state=UNDEFINED
device_bus_width=8
device_rowbuffer_size=1024
device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
in_addr_map=true
kvm_map=true
max_accesses_per_row=16
mem_sched_policy=frfcfs
min_writes_per_switch=16
null=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
page_policy=open_adaptive
power_model=Null
range=0:134217727:0:0:0:0
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
tCCD_L=0
tCK=1250
tCL=13750
tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
tXP=6000
tXPDLL=0
tXS=270000
tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
port=system.membus.master[0]
[system.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.000000

1151
tests/quick/se/00.hello/ref/riscv/linux/o3-timing/config.json Normal file
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File diff suppressed because it is too large Load diff

4
tests/quick/se/00.hello/ref/riscv/linux/o3-timing/simerr Executable file
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@ -0,0 +1,4 @@
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Unknown operating system; assuming Linux.
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick

15
tests/quick/se/00.hello/ref/riscv/linux/o3-timing/simout Executable file
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@ -0,0 +1,15 @@
Redirecting stdout to build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/o3-timing/simout
Redirecting stderr to build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Nov 30 2016 14:33:35
gem5 started Nov 30 2016 16:18:28
gem5 executing on zizzer, pid 34057
command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/o3-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/00.hello/riscv/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
Exiting @ tick 7939500 because target called exit()

1000
tests/quick/se/00.hello/ref/riscv/linux/o3-timing/stats.txt Normal file
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File diff suppressed because it is too large Load diff

211
tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/config.ini Normal file
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@ -0,0 +1,211 @@
[root]
type=Root
children=system
eventq_index=0
full_system=false
sim_quantum=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mem_mode=atomic
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.clk_domain]
type=SrcClockDomain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.cpu]
type=AtomicSimpleCPU
children=dtb interrupts isa itb tracer workload
branchPred=Null
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
default_p_state=UNDEFINED
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
eventq_index=0
fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
profile=0
progress_interval=0
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
socket_id=0
switched_out=false
system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
dcache_port=system.membus.slave[2]
icache_port=system.membus.slave[1]
[system.cpu.dtb]
type=RiscvTLB
eventq_index=0
size=64
[system.cpu.interrupts]
type=RiscvInterrupts
eventq_index=0
[system.cpu.isa]
type=RiscvISA
eventq_index=0
[system.cpu.itb]
type=RiscvTLB
eventq_index=0
size=64
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=LiveProcess
cmd=hello
cwd=
drivers=
egid=100
env=
errout=cerr
euid=100
eventq_index=0
executable=/z/powerjg/gem5-upstream/tests/test-progs/hello/bin/riscv/linux/hello
gid=100
input=cin
kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.dvfs_handler]
type=DVFSHandler
domains=
enable=false
eventq_index=0
sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=4
frontend_latency=3
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
width=16
master=system.physmem.port
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
clk_domain=system.clk_domain
conf_table_reported=true
default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
kvm_map=true
latency=30000
latency_var=0
null=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
range=0:134217727:0:0:0:0
port=system.membus.master[0]
[system.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.000000

289
tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/config.json Normal file
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@ -0,0 +1,289 @@
{
"name": null,
"sim_quantum": 0,
"system": {
"kernel": "",
"mmap_using_noreserve": false,
"kernel_addr_check": true,
"membus": {
"point_of_coherency": true,
"system": "system",
"response_latency": 2,
"cxx_class": "CoherentXBar",
"forward_latency": 4,
"clk_domain": "system.clk_domain",
"width": 16,
"eventq_index": 0,
"default_p_state": "UNDEFINED",
"p_state_clk_gate_max": 1000000000000,
"master": {
"peer": [
"system.physmem.port"
],
"role": "MASTER"
},
"type": "CoherentXBar",
"frontend_latency": 3,
"slave": {
"peer": [
"system.system_port",
"system.cpu.icache_port",
"system.cpu.dcache_port"
],
"role": "SLAVE"
},
"p_state_clk_gate_min": 1000,
"snoop_filter": {
"name": "snoop_filter",
"system": "system",
"max_capacity": 8388608,
"eventq_index": 0,
"cxx_class": "SnoopFilter",
"path": "system.membus.snoop_filter",
"type": "SnoopFilter",
"lookup_latency": 1
},
"power_model": null,
"path": "system.membus",
"snoop_response_latency": 4,
"name": "membus",
"p_state_clk_gate_bins": 20,
"use_default_range": false
},
"symbolfile": "",
"readfile": "",
"thermal_model": null,
"cxx_class": "System",
"work_begin_cpu_id_exit": -1,
"load_offset": 0,
"work_begin_exit_count": 0,
"p_state_clk_gate_min": 1000,
"memories": [
"system.physmem"
],
"work_begin_ckpt_count": 0,
"clk_domain": {
"name": "clk_domain",
"clock": [
1000
],
"init_perf_level": 0,
"voltage_domain": "system.voltage_domain",
"eventq_index": 0,
"cxx_class": "SrcClockDomain",
"path": "system.clk_domain",
"type": "SrcClockDomain",
"domain_id": -1
},
"mem_ranges": [],
"eventq_index": 0,
"default_p_state": "UNDEFINED",
"p_state_clk_gate_max": 1000000000000,
"dvfs_handler": {
"enable": false,
"name": "dvfs_handler",
"sys_clk_domain": "system.clk_domain",
"transition_latency": 100000000,
"eventq_index": 0,
"cxx_class": "DVFSHandler",
"domains": [],
"path": "system.dvfs_handler",
"type": "DVFSHandler"
},
"work_end_exit_count": 0,
"type": "System",
"voltage_domain": {
"name": "voltage_domain",
"eventq_index": 0,
"voltage": [
"1.0"
],
"cxx_class": "VoltageDomain",
"path": "system.voltage_domain",
"type": "VoltageDomain"
},
"cache_line_size": 64,
"boot_osflags": "a",
"system_port": {
"peer": "system.membus.slave[0]",
"role": "MASTER"
},
"physmem": {
"range": "0:134217727:0:0:0:0",
"latency": 30000,
"name": "physmem",
"p_state_clk_gate_min": 1000,
"eventq_index": 0,
"p_state_clk_gate_bins": 20,
"default_p_state": "UNDEFINED",
"kvm_map": true,
"clk_domain": "system.clk_domain",
"power_model": null,
"latency_var": 0,
"bandwidth": "73.000000",
"conf_table_reported": true,
"cxx_class": "SimpleMemory",
"p_state_clk_gate_max": 1000000000000,
"path": "system.physmem",
"null": false,
"type": "SimpleMemory",
"port": {
"peer": "system.membus.master[0]",
"role": "SLAVE"
},
"in_addr_map": true
},
"power_model": null,
"work_cpus_ckpt_count": 0,
"thermal_components": [],
"path": "system",
"cpu_clk_domain": {
"name": "cpu_clk_domain",
"clock": [
500
],
"init_perf_level": 0,
"voltage_domain": "system.voltage_domain",
"eventq_index": 0,
"cxx_class": "SrcClockDomain",
"path": "system.cpu_clk_domain",
"type": "SrcClockDomain",
"domain_id": -1
},
"work_end_ckpt_count": 0,
"mem_mode": "atomic",
"name": "system",
"init_param": 0,
"p_state_clk_gate_bins": 20,
"load_addr_mask": 1099511627775,
"cpu": [
{
"do_statistics_insts": true,
"numThreads": 1,
"itb": {
"name": "itb",
"eventq_index": 0,
"cxx_class": "RiscvISA::TLB",
"path": "system.cpu.itb",
"type": "RiscvTLB",
"size": 64
},
"simulate_data_stalls": false,
"function_trace": false,
"do_checkpoint_insts": true,
"cxx_class": "AtomicSimpleCPU",
"max_loads_all_threads": 0,
"system": "system",
"clk_domain": "system.cpu_clk_domain",
"function_trace_start": 0,
"cpu_id": 0,
"width": 1,
"checker": null,
"eventq_index": 0,
"default_p_state": "UNDEFINED",
"p_state_clk_gate_max": 1000000000000,
"do_quiesce": true,
"type": "AtomicSimpleCPU",
"fastmem": false,
"profile": 0,
"icache_port": {
"peer": "system.membus.slave[1]",
"role": "MASTER"
},
"p_state_clk_gate_bins": 20,
"p_state_clk_gate_min": 1000,
"interrupts": [
{
"eventq_index": 0,
"path": "system.cpu.interrupts",
"type": "RiscvInterrupts",
"name": "interrupts",
"cxx_class": "RiscvISA::Interrupts"
}
],
"dcache_port": {
"peer": "system.membus.slave[2]",
"role": "MASTER"
},
"socket_id": 0,
"power_model": null,
"max_insts_all_threads": 0,
"path": "system.cpu",
"max_loads_any_thread": 0,
"switched_out": false,
"workload": [
{
"uid": 100,
"pid": 100,
"kvmInSE": false,
"cxx_class": "LiveProcess",
"executable": "/z/powerjg/gem5-upstream/tests/test-progs/hello/bin/riscv/linux/hello",
"drivers": [],
"system": "system",
"gid": 100,
"eventq_index": 0,
"env": [],
"input": "cin",
"ppid": 99,
"type": "LiveProcess",
"cwd": "",
"simpoint": 0,
"euid": 100,
"path": "system.cpu.workload",
"max_stack_size": 67108864,
"name": "workload",
"cmd": [
"hello"
],
"errout": "cerr",
"useArchPT": false,
"egid": 100,
"output": "cout"
}
],
"name": "cpu",
"dtb": {
"name": "dtb",
"eventq_index": 0,
"cxx_class": "RiscvISA::TLB",
"path": "system.cpu.dtb",
"type": "RiscvTLB",
"size": 64
},
"simpoint_start_insts": [],
"max_insts_any_thread": 0,
"simulate_inst_stalls": false,
"progress_interval": 0,
"branchPred": null,
"isa": [
{
"eventq_index": 0,
"path": "system.cpu.isa",
"type": "RiscvISA",
"name": "isa",
"cxx_class": "RiscvISA::ISA"
}
],
"tracer": {
"eventq_index": 0,
"path": "system.cpu.tracer",
"type": "ExeTracer",
"name": "tracer",
"cxx_class": "Trace::ExeTracer"
}
}
],
"multi_thread": false,
"exit_on_work_items": false,
"work_item_id": -1,
"num_work_ids": 16
},
"time_sync_period": 100000000000,
"eventq_index": 0,
"time_sync_spin_threshold": 100000000,
"cxx_class": "Root",
"path": "root",
"time_sync_enable": false,
"type": "Root",
"full_system": false
}

3
tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/simerr Executable file
View file

@ -0,0 +1,3 @@
warn: Unknown operating system; assuming Linux.
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick

15
tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/simout Executable file
View file

@ -0,0 +1,15 @@
Redirecting stdout to build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-atomic/simout
Redirecting stderr to build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Nov 30 2016 14:33:35
gem5 started Nov 30 2016 16:18:29
gem5 executing on zizzer, pid 34058
command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-atomic -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/00.hello/riscv/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
Exiting @ tick 798000 because target called exit()

153
tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/stats.txt Normal file
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@ -0,0 +1,153 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000001 # Number of seconds simulated
sim_ticks 798000 # Number of ticks simulated
final_tick 798000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 49942 # Simulator instruction rate (inst/s)
host_op_rate 49911 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 25081647 # Simulator tick rate (ticks/s)
host_mem_usage 221640 # Number of bytes of host memory used
host_seconds 0.03 # Real time elapsed on the host
sim_insts 1587 # Number of instructions simulated
sim_ops 1587 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 798000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 6388 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1816 # Number of bytes read from this memory
system.physmem.bytes_read::total 8204 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 6388 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 6388 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 1750 # Number of bytes written to this memory
system.physmem.bytes_written::total 1750 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 1597 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 289 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1886 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 279 # Number of write requests responded to by this memory
system.physmem.num_writes::total 279 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 8005012531 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2275689223 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 10280701754 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 8005012531 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 8005012531 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 2192982456 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2192982456 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 8005012531 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 4468671679 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 12473684211 # Total bandwidth to/from this memory (bytes/s)
system.pwrStateResidencyTicks::UNDEFINED 798000 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 9 # Number of system calls
system.cpu.pwrStateResidencyTicks::ON 798000 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 1597 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 1587 # Number of instructions committed
system.cpu.committedOps 1587 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1588 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 142 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 231 # number of instructions that are conditional controls
system.cpu.num_int_insts 1588 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_int_register_reads 2062 # number of times the integer registers were read
system.cpu.num_int_register_writes 1077 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 569 # number of memory refs
system.cpu.num_load_insts 289 # Number of load instructions
system.cpu.num_store_insts 280 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 1597 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.Branches 373 # Number of branches fetched
system.cpu.op_class::No_OpClass 9 0.56% 0.56% # Class of executed instruction
system.cpu.op_class::IntAlu 1019 63.81% 64.37% # Class of executed instruction
system.cpu.op_class::IntMult 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::FloatMultAcc 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::FloatMisc 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::MemRead 289 18.10% 82.47% # Class of executed instruction
system.cpu.op_class::MemWrite 280 17.53% 100.00% # Class of executed instruction
system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 1597 # Class of executed instruction
system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 798000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 1886 # Transaction distribution
system.membus.trans_dist::ReadResp 1886 # Transaction distribution
system.membus.trans_dist::WriteReq 279 # Transaction distribution
system.membus.trans_dist::WriteResp 279 # Transaction distribution
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 3194 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1136 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 4330 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 6388 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 3566 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 9954 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples 2165 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 2165 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 2165 # Request fanout histogram
---------- End Simulation Statistics ----------

1265
tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/config.ini Normal file
View file

File diff suppressed because it is too large Load diff

1734
tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/config.json Normal file
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File diff suppressed because it is too large Load diff

11
tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/simerr Executable file
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@ -0,0 +1,11 @@
warn: rounding error > tolerance
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Unknown operating system; assuming Linux.
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!

15
tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/simout Executable file
View file

@ -0,0 +1,15 @@
Redirecting stdout to build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-timing-ruby/simout
Redirecting stderr to build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-timing-ruby/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Nov 30 2016 14:33:35
gem5 started Nov 30 2016 16:18:29
gem5 executing on zizzer, pid 34060
command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-timing-ruby -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/00.hello/riscv/linux/simple-timing-ruby
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
Exiting @ tick 27947 because target called exit()

639
tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/stats.txt Normal file
View file

@ -0,0 +1,639 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000028 # Number of seconds simulated
sim_ticks 27947 # Number of ticks simulated
final_tick 27947 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_inst_rate 19868 # Simulator instruction rate (inst/s)
host_op_rate 19863 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 349695 # Simulator tick rate (ticks/s)
host_mem_usage 390760 # Number of bytes of host memory used
host_seconds 0.08 # Real time elapsed on the host
sim_insts 1587 # Number of instructions simulated
sim_ops 1587 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 27947 # Cumulative time (in ticks) in various power states
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 28032 # Number of bytes read from this memory
system.mem_ctrls.bytes_read::total 28032 # Number of bytes read from this memory
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 27776 # Number of bytes written to this memory
system.mem_ctrls.bytes_written::total 27776 # Number of bytes written to this memory
system.mem_ctrls.num_reads::ruby.dir_cntrl0 438 # Number of read requests responded to by this memory
system.mem_ctrls.num_reads::total 438 # Number of read requests responded to by this memory
system.mem_ctrls.num_writes::ruby.dir_cntrl0 434 # Number of write requests responded to by this memory
system.mem_ctrls.num_writes::total 434 # Number of write requests responded to by this memory
system.mem_ctrls.bw_read::ruby.dir_cntrl0 1003041471 # Total read bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_read::total 1003041471 # Total read bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_write::ruby.dir_cntrl0 993881275 # Write bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_write::total 993881275 # Write bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_total::ruby.dir_cntrl0 1996922747 # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.bw_total::total 1996922747 # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.readReqs 438 # Number of read requests accepted
system.mem_ctrls.writeReqs 434 # Number of write requests accepted
system.mem_ctrls.readBursts 438 # Number of DRAM read bursts, including those serviced by the write queue
system.mem_ctrls.writeBursts 434 # Number of DRAM write bursts, including those merged in the write queue
system.mem_ctrls.bytesReadDRAM 15616 # Total number of bytes read from DRAM
system.mem_ctrls.bytesReadWrQ 12416 # Total number of bytes read from write queue
system.mem_ctrls.bytesWritten 14912 # Total number of bytes written to DRAM
system.mem_ctrls.bytesReadSys 28032 # Total read bytes from the system interface side
system.mem_ctrls.bytesWrittenSys 27776 # Total written bytes from the system interface side
system.mem_ctrls.servicedByWrQ 194 # Number of DRAM read bursts serviced by the write queue
system.mem_ctrls.mergedWrBursts 183 # Number of DRAM write bursts merged with an existing one
system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.mem_ctrls.perBankRdBursts::0 102 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::1 69 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::2 43 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::3 30 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::4 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::5 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::6 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::7 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::9 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::10 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::11 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::12 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::13 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::14 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::15 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::0 100 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::1 62 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::2 41 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::3 30 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
system.mem_ctrls.totGap 27875 # Total gap between requests
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::6 438 # Read request sizes (log2)
system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::6 434 # Write request sizes (log2)
system.mem_ctrls.rdQLenPdf::0 244 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::15 5 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::16 5 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::17 12 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::18 14 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::19 15 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::20 15 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::21 16 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::22 14 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::23 14 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::24 14 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::25 14 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::26 14 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::27 14 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::28 14 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::29 14 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::30 14 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::31 14 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::32 14 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.mem_ctrls.bytesPerActivate::samples 35 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::mean 835.657143 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::gmean 690.201292 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::stdev 331.080756 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::0-127 2 5.71% 5.71% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::128-255 2 5.71% 11.43% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::256-383 1 2.86% 14.29% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::384-511 1 2.86% 17.14% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::512-639 1 2.86% 20.00% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::640-767 3 8.57% 28.57% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::1024-1151 25 71.43% 100.00% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::total 35 # Bytes accessed per row activation
system.mem_ctrls.rdPerTurnAround::samples 14 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::mean 17.285714 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::gmean 16.736288 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::stdev 5.580579 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::12-13 1 7.14% 7.14% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::14-15 4 28.57% 35.71% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::16-17 7 50.00% 85.71% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::18-19 1 7.14% 92.86% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::36-37 1 7.14% 100.00% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::total 14 # Reads before turning the bus around for writes
system.mem_ctrls.wrPerTurnAround::samples 14 # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::mean 16.642857 # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::gmean 16.611629 # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::stdev 1.081818 # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::16 10 71.43% 71.43% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::18 3 21.43% 92.86% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::19 1 7.14% 100.00% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::total 14 # Writes before turning the bus around for reads
system.mem_ctrls.totQLat 2979 # Total ticks spent queuing
system.mem_ctrls.totMemAccLat 7615 # Total ticks spent from burst creation until serviced by the DRAM
system.mem_ctrls.totBusLat 1220 # Total ticks spent in databus transfers
system.mem_ctrls.avgQLat 12.21 # Average queueing delay per DRAM burst
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
system.mem_ctrls.avgMemAccLat 31.21 # Average memory access latency per DRAM burst
system.mem_ctrls.avgRdBW 558.77 # Average DRAM read bandwidth in MiByte/s
system.mem_ctrls.avgWrBW 533.58 # Average achieved write bandwidth in MiByte/s
system.mem_ctrls.avgRdBWSys 1003.04 # Average system read bandwidth in MiByte/s
system.mem_ctrls.avgWrBWSys 993.88 # Average system write bandwidth in MiByte/s
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.mem_ctrls.busUtil 8.53 # Data bus utilization in percentage
system.mem_ctrls.busUtilRead 4.37 # Data bus utilization in percentage for reads
system.mem_ctrls.busUtilWrite 4.17 # Data bus utilization in percentage for writes
system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing
system.mem_ctrls.avgWrQLen 24.44 # Average write queue length when enqueuing
system.mem_ctrls.readRowHits 212 # Number of row buffer hits during reads
system.mem_ctrls.writeRowHits 228 # Number of row buffer hits during writes
system.mem_ctrls.readRowHitRate 86.89 # Row buffer hit rate for reads
system.mem_ctrls.writeRowHitRate 90.84 # Row buffer hit rate for writes
system.mem_ctrls.avgGap 31.97 # Average gap between requests
system.mem_ctrls.pageHitRate 88.89 # Row buffer hit rate, read and write combined
system.mem_ctrls_0.actEnergy 264180 # Energy for activate commands per rank (pJ)
system.mem_ctrls_0.preEnergy 135240 # Energy for precharge commands per rank (pJ)
system.mem_ctrls_0.readEnergy 2787456 # Energy for read commands per rank (pJ)
system.mem_ctrls_0.writeEnergy 1946016 # Energy for write commands per rank (pJ)
system.mem_ctrls_0.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ)
system.mem_ctrls_0.actBackEnergy 4405872 # Energy for active background per rank (pJ)
system.mem_ctrls_0.preBackEnergy 40704 # Energy for precharge background per rank (pJ)
system.mem_ctrls_0.actPowerDownEnergy 8149176 # Energy for active power-down per rank (pJ)
system.mem_ctrls_0.prePowerDownEnergy 118272 # Energy for precharge power-down per rank (pJ)
system.mem_ctrls_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
system.mem_ctrls_0.totalEnergy 19690836 # Total energy per rank (pJ)
system.mem_ctrls_0.averagePower 704.577808 # Core power per rank (mW)
system.mem_ctrls_0.totalIdleTime 18179 # Total Idle time Per DRAM Rank
system.mem_ctrls_0.memoryStateTime::IDLE 22 # Time in different power states
system.mem_ctrls_0.memoryStateTime::REF 780 # Time in different power states
system.mem_ctrls_0.memoryStateTime::SREF 0 # Time in different power states
system.mem_ctrls_0.memoryStateTime::PRE_PDN 308 # Time in different power states
system.mem_ctrls_0.memoryStateTime::ACT 8966 # Time in different power states
system.mem_ctrls_0.memoryStateTime::ACT_PDN 17871 # Time in different power states
system.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ)
system.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ)
system.mem_ctrls_1.readEnergy 0 # Energy for read commands per rank (pJ)
system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.mem_ctrls_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ)
system.mem_ctrls_1.actBackEnergy 224352 # Energy for active background per rank (pJ)
system.mem_ctrls_1.preBackEnergy 3002880 # Energy for precharge background per rank (pJ)
system.mem_ctrls_1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ)
system.mem_ctrls_1.prePowerDownEnergy 2889984 # Energy for precharge power-down per rank (pJ)
system.mem_ctrls_1.selfRefreshEnergy 2906160 # Energy for self refresh per rank (pJ)
system.mem_ctrls_1.totalEnergy 10252656 # Total energy per rank (pJ)
system.mem_ctrls_1.averagePower 366.860701 # Core power per rank (mW)
system.mem_ctrls_1.totalIdleTime 7526 # Total Idle time Per DRAM Rank
system.mem_ctrls_1.memoryStateTime::IDLE 7786 # Time in different power states
system.mem_ctrls_1.memoryStateTime::REF 526 # Time in different power states
system.mem_ctrls_1.memoryStateTime::SREF 12109 # Time in different power states
system.mem_ctrls_1.memoryStateTime::PRE_PDN 7526 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.pwrStateResidencyTicks::UNDEFINED 27947 # Cumulative time (in ticks) in various power states
system.cpu.clk_domain.clock 1 # Clock period in ticks
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 9 # Number of system calls
system.cpu.pwrStateResidencyTicks::ON 27947 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 27947 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 1587 # Number of instructions committed
system.cpu.committedOps 1587 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1588 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 142 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 231 # number of instructions that are conditional controls
system.cpu.num_int_insts 1588 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_int_register_reads 2062 # number of times the integer registers were read
system.cpu.num_int_register_writes 1077 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 569 # number of memory refs
system.cpu.num_load_insts 289 # Number of load instructions
system.cpu.num_store_insts 280 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 27947 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.Branches 373 # Number of branches fetched
system.cpu.op_class::No_OpClass 9 0.56% 0.56% # Class of executed instruction
system.cpu.op_class::IntAlu 1019 63.81% 64.37% # Class of executed instruction
system.cpu.op_class::IntMult 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::FloatMultAcc 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::FloatMisc 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::MemRead 289 18.10% 82.47% # Class of executed instruction
system.cpu.op_class::MemWrite 280 17.53% 100.00% # Class of executed instruction
system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 1597 # Class of executed instruction
system.ruby.clk_domain.clock 1 # Clock period in ticks
system.ruby.pwrStateResidencyTicks::UNDEFINED 27947 # Cumulative time (in ticks) in various power states
system.ruby.delayHist::bucket_size 1 # delay histogram for all message
system.ruby.delayHist::max_bucket 9 # delay histogram for all message
system.ruby.delayHist::samples 872 # delay histogram for all message
system.ruby.delayHist | 872 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message
system.ruby.delayHist::total 872 # delay histogram for all message
system.ruby.outstanding_req_hist_seqr::bucket_size 1
system.ruby.outstanding_req_hist_seqr::max_bucket 9
system.ruby.outstanding_req_hist_seqr::samples 2166
system.ruby.outstanding_req_hist_seqr::mean 1
system.ruby.outstanding_req_hist_seqr::gmean 1
system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 2166 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.outstanding_req_hist_seqr::total 2166
system.ruby.latency_hist_seqr::bucket_size 32
system.ruby.latency_hist_seqr::max_bucket 319
system.ruby.latency_hist_seqr::samples 2165
system.ruby.latency_hist_seqr::mean 11.908545
system.ruby.latency_hist_seqr::gmean 2.205817
system.ruby.latency_hist_seqr::stdev 24.908130
system.ruby.latency_hist_seqr | 1727 79.77% 79.77% | 202 9.33% 89.10% | 224 10.35% 99.45% | 2 0.09% 99.54% | 2 0.09% 99.63% | 7 0.32% 99.95% | 0 0.00% 99.95% | 0 0.00% 99.95% | 0 0.00% 99.95% | 1 0.05% 100.00%
system.ruby.latency_hist_seqr::total 2165
system.ruby.hit_latency_hist_seqr::bucket_size 1
system.ruby.hit_latency_hist_seqr::max_bucket 9
system.ruby.hit_latency_hist_seqr::samples 1727
system.ruby.hit_latency_hist_seqr::mean 1
system.ruby.hit_latency_hist_seqr::gmean 1
system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 1727 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.hit_latency_hist_seqr::total 1727
system.ruby.miss_latency_hist_seqr::bucket_size 32
system.ruby.miss_latency_hist_seqr::max_bucket 319
system.ruby.miss_latency_hist_seqr::samples 438
system.ruby.miss_latency_hist_seqr::mean 54.920091
system.ruby.miss_latency_hist_seqr::gmean 49.915756
system.ruby.miss_latency_hist_seqr::stdev 27.345330
system.ruby.miss_latency_hist_seqr | 0 0.00% 0.00% | 202 46.12% 46.12% | 224 51.14% 97.26% | 2 0.46% 97.72% | 2 0.46% 98.17% | 7 1.60% 99.77% | 0 0.00% 99.77% | 0 0.00% 99.77% | 0 0.00% 99.77% | 1 0.23% 100.00%
system.ruby.miss_latency_hist_seqr::total 438
system.ruby.Directory.incomplete_times_seqr 437
system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 27947 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl0.cacheMemory.demand_hits 1727 # Number of cache demand hits
system.ruby.l1_cntrl0.cacheMemory.demand_misses 438 # Number of cache demand misses
system.ruby.l1_cntrl0.cacheMemory.demand_accesses 2165 # Number of cache demand accesses
system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 27947 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 27947 # Cumulative time (in ticks) in various power states
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 27947 # Cumulative time (in ticks) in various power states
system.ruby.network.routers0.percent_links_utilized 7.800479
system.ruby.network.routers0.msg_count.Control::2 438
system.ruby.network.routers0.msg_count.Data::2 434
system.ruby.network.routers0.msg_count.Response_Data::4 438
system.ruby.network.routers0.msg_count.Writeback_Control::3 434
system.ruby.network.routers0.msg_bytes.Control::2 3504
system.ruby.network.routers0.msg_bytes.Data::2 31248
system.ruby.network.routers0.msg_bytes.Response_Data::4 31536
system.ruby.network.routers0.msg_bytes.Writeback_Control::3 3472
system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 27947 # Cumulative time (in ticks) in various power states
system.ruby.network.routers1.percent_links_utilized 7.800479
system.ruby.network.routers1.msg_count.Control::2 438
system.ruby.network.routers1.msg_count.Data::2 434
system.ruby.network.routers1.msg_count.Response_Data::4 438
system.ruby.network.routers1.msg_count.Writeback_Control::3 434
system.ruby.network.routers1.msg_bytes.Control::2 3504
system.ruby.network.routers1.msg_bytes.Data::2 31248
system.ruby.network.routers1.msg_bytes.Response_Data::4 31536
system.ruby.network.routers1.msg_bytes.Writeback_Control::3 3472
system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 27947 # Cumulative time (in ticks) in various power states
system.ruby.network.routers2.percent_links_utilized 7.800479
system.ruby.network.routers2.msg_count.Control::2 438
system.ruby.network.routers2.msg_count.Data::2 434
system.ruby.network.routers2.msg_count.Response_Data::4 438
system.ruby.network.routers2.msg_count.Writeback_Control::3 434
system.ruby.network.routers2.msg_bytes.Control::2 3504
system.ruby.network.routers2.msg_bytes.Data::2 31248
system.ruby.network.routers2.msg_bytes.Response_Data::4 31536
system.ruby.network.routers2.msg_bytes.Writeback_Control::3 3472
system.ruby.network.pwrStateResidencyTicks::UNDEFINED 27947 # Cumulative time (in ticks) in various power states
system.ruby.network.msg_count.Control 1314
system.ruby.network.msg_count.Data 1302
system.ruby.network.msg_count.Response_Data 1314
system.ruby.network.msg_count.Writeback_Control 1302
system.ruby.network.msg_byte.Control 10512
system.ruby.network.msg_byte.Data 93744
system.ruby.network.msg_byte.Response_Data 94608
system.ruby.network.msg_byte.Writeback_Control 10416
system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 27947 # Cumulative time (in ticks) in various power states
system.ruby.network.routers0.throttle0.link_utilization 7.829105
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 438
system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 434
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 31536
system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 3472
system.ruby.network.routers0.throttle1.link_utilization 7.771854
system.ruby.network.routers0.throttle1.msg_count.Control::2 438
system.ruby.network.routers0.throttle1.msg_count.Data::2 434
system.ruby.network.routers0.throttle1.msg_bytes.Control::2 3504
system.ruby.network.routers0.throttle1.msg_bytes.Data::2 31248
system.ruby.network.routers1.throttle0.link_utilization 7.771854
system.ruby.network.routers1.throttle0.msg_count.Control::2 438
system.ruby.network.routers1.throttle0.msg_count.Data::2 434
system.ruby.network.routers1.throttle0.msg_bytes.Control::2 3504
system.ruby.network.routers1.throttle0.msg_bytes.Data::2 31248
system.ruby.network.routers1.throttle1.link_utilization 7.829105
system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 438
system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 434
system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 31536
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 3472
system.ruby.network.routers2.throttle0.link_utilization 7.829105
system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 438
system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 434
system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 31536
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 3472
system.ruby.network.routers2.throttle1.link_utilization 7.771854
system.ruby.network.routers2.throttle1.msg_count.Control::2 438
system.ruby.network.routers2.throttle1.msg_count.Data::2 434
system.ruby.network.routers2.throttle1.msg_bytes.Control::2 3504
system.ruby.network.routers2.throttle1.msg_bytes.Data::2 31248
system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1::samples 438 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1 | 438 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1::total 438 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2::samples 434 # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2 | 434 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2::total 434 # delay histogram for vnet_2
system.ruby.LD.latency_hist_seqr::bucket_size 32
system.ruby.LD.latency_hist_seqr::max_bucket 319
system.ruby.LD.latency_hist_seqr::samples 289
system.ruby.LD.latency_hist_seqr::mean 23.332180
system.ruby.LD.latency_hist_seqr::gmean 5.457216
system.ruby.LD.latency_hist_seqr::stdev 32.553168
system.ruby.LD.latency_hist_seqr | 161 55.71% 55.71% | 72 24.91% 80.62% | 54 18.69% 99.31% | 0 0.00% 99.31% | 0 0.00% 99.31% | 1 0.35% 99.65% | 0 0.00% 99.65% | 0 0.00% 99.65% | 0 0.00% 99.65% | 1 0.35% 100.00%
system.ruby.LD.latency_hist_seqr::total 289
system.ruby.LD.hit_latency_hist_seqr::bucket_size 1
system.ruby.LD.hit_latency_hist_seqr::max_bucket 9
system.ruby.LD.hit_latency_hist_seqr::samples 161
system.ruby.LD.hit_latency_hist_seqr::mean 1
system.ruby.LD.hit_latency_hist_seqr::gmean 1
system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 161 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.hit_latency_hist_seqr::total 161
system.ruby.LD.miss_latency_hist_seqr::bucket_size 32
system.ruby.LD.miss_latency_hist_seqr::max_bucket 319
system.ruby.LD.miss_latency_hist_seqr::samples 128
system.ruby.LD.miss_latency_hist_seqr::mean 51.421875
system.ruby.LD.miss_latency_hist_seqr::gmean 46.125665
system.ruby.LD.miss_latency_hist_seqr::stdev 31.235103
system.ruby.LD.miss_latency_hist_seqr | 0 0.00% 0.00% | 72 56.25% 56.25% | 54 42.19% 98.44% | 0 0.00% 98.44% | 0 0.00% 98.44% | 1 0.78% 99.22% | 0 0.00% 99.22% | 0 0.00% 99.22% | 0 0.00% 99.22% | 1 0.78% 100.00%
system.ruby.LD.miss_latency_hist_seqr::total 128
system.ruby.ST.latency_hist_seqr::bucket_size 16
system.ruby.ST.latency_hist_seqr::max_bucket 159
system.ruby.ST.latency_hist_seqr::samples 279
system.ruby.ST.latency_hist_seqr::mean 13.150538
system.ruby.ST.latency_hist_seqr::gmean 2.682693
system.ruby.ST.latency_hist_seqr::stdev 23.311750
system.ruby.ST.latency_hist_seqr | 206 73.84% 73.84% | 0 0.00% 73.84% | 45 16.13% 89.96% | 2 0.72% 90.68% | 22 7.89% 98.57% | 2 0.72% 99.28% | 0 0.00% 99.28% | 1 0.36% 99.64% | 1 0.36% 100.00% | 0 0.00% 100.00%
system.ruby.ST.latency_hist_seqr::total 279
system.ruby.ST.hit_latency_hist_seqr::bucket_size 1
system.ruby.ST.hit_latency_hist_seqr::max_bucket 9
system.ruby.ST.hit_latency_hist_seqr::samples 206
system.ruby.ST.hit_latency_hist_seqr::mean 1
system.ruby.ST.hit_latency_hist_seqr::gmean 1
system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 206 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.hit_latency_hist_seqr::total 206
system.ruby.ST.miss_latency_hist_seqr::bucket_size 16
system.ruby.ST.miss_latency_hist_seqr::max_bucket 159
system.ruby.ST.miss_latency_hist_seqr::samples 73
system.ruby.ST.miss_latency_hist_seqr::mean 47.438356
system.ruby.ST.miss_latency_hist_seqr::gmean 43.447321
system.ruby.ST.miss_latency_hist_seqr::stdev 21.997466
system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 45 61.64% 61.64% | 2 2.74% 64.38% | 22 30.14% 94.52% | 2 2.74% 97.26% | 0 0.00% 97.26% | 1 1.37% 98.63% | 1 1.37% 100.00% | 0 0.00% 100.00%
system.ruby.ST.miss_latency_hist_seqr::total 73
system.ruby.IFETCH.latency_hist_seqr::bucket_size 32
system.ruby.IFETCH.latency_hist_seqr::max_bucket 319
system.ruby.IFETCH.latency_hist_seqr::samples 1597
system.ruby.IFETCH.latency_hist_seqr::mean 9.624296
system.ruby.IFETCH.latency_hist_seqr::gmean 1.809372
system.ruby.IFETCH.latency_hist_seqr::stdev 22.939232
system.ruby.IFETCH.latency_hist_seqr | 1360 85.16% 85.16% | 83 5.20% 90.36% | 146 9.14% 99.50% | 1 0.06% 99.56% | 1 0.06% 99.62% | 6 0.38% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.latency_hist_seqr::total 1597
system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1
system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9
system.ruby.IFETCH.hit_latency_hist_seqr::samples 1360
system.ruby.IFETCH.hit_latency_hist_seqr::mean 1
system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1
system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 1360 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.hit_latency_hist_seqr::total 1360
system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 32
system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 319
system.ruby.IFETCH.miss_latency_hist_seqr::samples 237
system.ruby.IFETCH.miss_latency_hist_seqr::mean 59.113924
system.ruby.IFETCH.miss_latency_hist_seqr::gmean 54.365760
system.ruby.IFETCH.miss_latency_hist_seqr::stdev 25.891554
system.ruby.IFETCH.miss_latency_hist_seqr | 0 0.00% 0.00% | 83 35.02% 35.02% | 146 61.60% 96.62% | 1 0.42% 97.05% | 1 0.42% 97.47% | 6 2.53% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.miss_latency_hist_seqr::total 237
system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 32
system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 319
system.ruby.Directory.miss_mach_latency_hist_seqr::samples 438
system.ruby.Directory.miss_mach_latency_hist_seqr::mean 54.920091
system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 49.915756
system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 27.345330
system.ruby.Directory.miss_mach_latency_hist_seqr | 0 0.00% 0.00% | 202 46.12% 46.12% | 224 51.14% 97.26% | 2 0.46% 97.72% | 2 0.46% 98.17% | 7 1.60% 99.77% | 0 0.00% 99.77% | 0 0.00% 99.77% | 0 0.00% 99.77% | 1 0.23% 100.00%
system.ruby.Directory.miss_mach_latency_hist_seqr::total 438
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 1
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::stdev nan
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::total 1
system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::bucket_size 1
system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::max_bucket 9
system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::samples 1
system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::stdev nan
system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::total 1
system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::bucket_size 1
system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::max_bucket 9
system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::samples 1
system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::stdev nan
system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::total 1
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::bucket_size 8
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::max_bucket 79
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::samples 1
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::mean 75
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::gmean 75.000000
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::stdev nan
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00%
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 128
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 51.421875
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 46.125665
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 31.235103
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 72 56.25% 56.25% | 54 42.19% 98.44% | 0 0.00% 98.44% | 0 0.00% 98.44% | 1 0.78% 99.22% | 0 0.00% 99.22% | 0 0.00% 99.22% | 0 0.00% 99.22% | 1 0.78% 100.00%
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 128
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 16
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 159
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 73
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 47.438356
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 43.447321
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 21.997466
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 45 61.64% 61.64% | 2 2.74% 64.38% | 22 30.14% 94.52% | 2 2.74% 97.26% | 0 0.00% 97.26% | 1 1.37% 98.63% | 1 1.37% 100.00% | 0 0.00% 100.00%
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 73
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 237
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 59.113924
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 54.365760
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 25.891554
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 83 35.02% 35.02% | 146 61.60% 96.62% | 1 0.42% 97.05% | 1 0.42% 97.47% | 6 2.53% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 237
system.ruby.Directory_Controller.GETX 438 0.00% 0.00%
system.ruby.Directory_Controller.PUTX 434 0.00% 0.00%
system.ruby.Directory_Controller.Memory_Data 438 0.00% 0.00%
system.ruby.Directory_Controller.Memory_Ack 434 0.00% 0.00%
system.ruby.Directory_Controller.I.GETX 438 0.00% 0.00%
system.ruby.Directory_Controller.M.PUTX 434 0.00% 0.00%
system.ruby.Directory_Controller.IM.Memory_Data 438 0.00% 0.00%
system.ruby.Directory_Controller.MI.Memory_Ack 434 0.00% 0.00%
system.ruby.L1Cache_Controller.Load 289 0.00% 0.00%
system.ruby.L1Cache_Controller.Ifetch 1597 0.00% 0.00%
system.ruby.L1Cache_Controller.Store 279 0.00% 0.00%
system.ruby.L1Cache_Controller.Data 438 0.00% 0.00%
system.ruby.L1Cache_Controller.Replacement 434 0.00% 0.00%
system.ruby.L1Cache_Controller.Writeback_Ack 434 0.00% 0.00%
system.ruby.L1Cache_Controller.I.Load 128 0.00% 0.00%
system.ruby.L1Cache_Controller.I.Ifetch 237 0.00% 0.00%
system.ruby.L1Cache_Controller.I.Store 73 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Load 161 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Ifetch 1360 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Store 206 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Replacement 434 0.00% 0.00%
system.ruby.L1Cache_Controller.MI.Writeback_Ack 434 0.00% 0.00%
system.ruby.L1Cache_Controller.IS.Data 365 0.00% 0.00%
system.ruby.L1Cache_Controller.IM.Data 73 0.00% 0.00%
---------- End Simulation Statistics ----------

380
tests/quick/se/00.hello/ref/riscv/linux/simple-timing/config.ini Normal file
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@ -0,0 +1,380 @@
[root]
type=Root
children=system
eventq_index=0
full_system=false
sim_quantum=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.clk_domain]
type=SrcClockDomain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.cpu]
type=TimingSimpleCPU
children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
branchPred=Null
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
default_p_state=UNDEFINED
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
eventq_index=0
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
profile=0
progress_interval=0
simpoint_start_insts=
socket_id=0
switched_out=false
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
is_read_only=false
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=262144
system=system
tag_latency=2
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dcache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=262144
tag_latency=2
[system.cpu.dtb]
type=RiscvTLB
eventq_index=0
size=64
[system.cpu.icache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
is_read_only=true
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=131072
system=system
tag_latency=2
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=true
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.icache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=131072
tag_latency=2
[system.cpu.interrupts]
type=RiscvInterrupts
eventq_index=0
[system.cpu.isa]
type=RiscvISA
eventq_index=0
[system.cpu.itb]
type=RiscvTLB
eventq_index=0
size=64
[system.cpu.l2cache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=20
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
is_read_only=false
max_miss_count=0
mshrs=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=20
sequential_access=false
size=2097152
system=system
tag_latency=20
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.l2cache.tags]
type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=20
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=2097152
tag_latency=20
[system.cpu.toL2Bus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=0
frontend_latency=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=false
power_model=Null
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.toL2Bus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=0
max_capacity=8388608
system=system
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=LiveProcess
cmd=hello
cwd=
drivers=
egid=100
env=
errout=cerr
euid=100
eventq_index=0
executable=/z/powerjg/gem5-upstream/tests/test-progs/hello/bin/riscv/linux/hello
gid=100
input=cin
kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.dvfs_handler]
type=DVFSHandler
domains=
enable=false
eventq_index=0
sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=4
frontend_latency=3
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
clk_domain=system.clk_domain
conf_table_reported=true
default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
kvm_map=true
latency=30000
latency_var=0
null=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
range=0:134217727:0:0:0:0
port=system.membus.master[0]
[system.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.000000

508
tests/quick/se/00.hello/ref/riscv/linux/simple-timing/config.json Normal file
View file

@ -0,0 +1,508 @@
{
"name": null,
"sim_quantum": 0,
"system": {
"kernel": "",
"mmap_using_noreserve": false,
"kernel_addr_check": true,
"membus": {
"point_of_coherency": true,
"system": "system",
"response_latency": 2,
"cxx_class": "CoherentXBar",
"forward_latency": 4,
"clk_domain": "system.clk_domain",
"width": 16,
"eventq_index": 0,
"default_p_state": "UNDEFINED",
"p_state_clk_gate_max": 1000000000000,
"master": {
"peer": [
"system.physmem.port"
],
"role": "MASTER"
},
"type": "CoherentXBar",
"frontend_latency": 3,
"slave": {
"peer": [
"system.system_port",
"system.cpu.l2cache.mem_side"
],
"role": "SLAVE"
},
"p_state_clk_gate_min": 1000,
"snoop_filter": {
"name": "snoop_filter",
"system": "system",
"max_capacity": 8388608,
"eventq_index": 0,
"cxx_class": "SnoopFilter",
"path": "system.membus.snoop_filter",
"type": "SnoopFilter",
"lookup_latency": 1
},
"power_model": null,
"path": "system.membus",
"snoop_response_latency": 4,
"name": "membus",
"p_state_clk_gate_bins": 20,
"use_default_range": false
},
"symbolfile": "",
"readfile": "",
"thermal_model": null,
"cxx_class": "System",
"work_begin_cpu_id_exit": -1,
"load_offset": 0,
"work_begin_exit_count": 0,
"p_state_clk_gate_min": 1000,
"memories": [
"system.physmem"
],
"work_begin_ckpt_count": 0,
"clk_domain": {
"name": "clk_domain",
"clock": [
1000
],
"init_perf_level": 0,
"voltage_domain": "system.voltage_domain",
"eventq_index": 0,
"cxx_class": "SrcClockDomain",
"path": "system.clk_domain",
"type": "SrcClockDomain",
"domain_id": -1
},
"mem_ranges": [],
"eventq_index": 0,
"default_p_state": "UNDEFINED",
"p_state_clk_gate_max": 1000000000000,
"dvfs_handler": {
"enable": false,
"name": "dvfs_handler",
"sys_clk_domain": "system.clk_domain",
"transition_latency": 100000000,
"eventq_index": 0,
"cxx_class": "DVFSHandler",
"domains": [],
"path": "system.dvfs_handler",
"type": "DVFSHandler"
},
"work_end_exit_count": 0,
"type": "System",
"voltage_domain": {
"name": "voltage_domain",
"eventq_index": 0,
"voltage": [
"1.0"
],
"cxx_class": "VoltageDomain",
"path": "system.voltage_domain",
"type": "VoltageDomain"
},
"cache_line_size": 64,
"boot_osflags": "a",
"system_port": {
"peer": "system.membus.slave[0]",
"role": "MASTER"
},
"physmem": {
"range": "0:134217727:0:0:0:0",
"latency": 30000,
"name": "physmem",
"p_state_clk_gate_min": 1000,
"eventq_index": 0,
"p_state_clk_gate_bins": 20,
"default_p_state": "UNDEFINED",
"kvm_map": true,
"clk_domain": "system.clk_domain",
"power_model": null,
"latency_var": 0,
"bandwidth": "73.000000",
"conf_table_reported": true,
"cxx_class": "SimpleMemory",
"p_state_clk_gate_max": 1000000000000,
"path": "system.physmem",
"null": false,
"type": "SimpleMemory",
"port": {
"peer": "system.membus.master[0]",
"role": "SLAVE"
},
"in_addr_map": true
},
"power_model": null,
"work_cpus_ckpt_count": 0,
"thermal_components": [],
"path": "system",
"cpu_clk_domain": {
"name": "cpu_clk_domain",
"clock": [
500
],
"init_perf_level": 0,
"voltage_domain": "system.voltage_domain",
"eventq_index": 0,
"cxx_class": "SrcClockDomain",
"path": "system.cpu_clk_domain",
"type": "SrcClockDomain",
"domain_id": -1
},
"work_end_ckpt_count": 0,
"mem_mode": "timing",
"name": "system",
"init_param": 0,
"p_state_clk_gate_bins": 20,
"load_addr_mask": 1099511627775,
"cpu": [
{
"do_statistics_insts": true,
"numThreads": 1,
"itb": {
"name": "itb",
"eventq_index": 0,
"cxx_class": "RiscvISA::TLB",
"path": "system.cpu.itb",
"type": "RiscvTLB",
"size": 64
},
"system": "system",
"icache": {
"cpu_side": {
"peer": "system.cpu.icache_port",
"role": "SLAVE"
},
"clusivity": "mostly_incl",
"prefetcher": null,
"system": "system",
"write_buffers": 8,
"response_latency": 2,
"cxx_class": "Cache",
"size": 131072,
"type": "Cache",
"clk_domain": "system.cpu_clk_domain",
"max_miss_count": 0,
"eventq_index": 0,
"default_p_state": "UNDEFINED",
"p_state_clk_gate_max": 1000000000000,
"mem_side": {
"peer": "system.cpu.toL2Bus.slave[0]",
"role": "MASTER"
},
"mshrs": 4,
"writeback_clean": true,
"p_state_clk_gate_min": 1000,
"tags": {
"size": 131072,
"tag_latency": 2,
"name": "tags",
"p_state_clk_gate_min": 1000,
"eventq_index": 0,
"p_state_clk_gate_bins": 20,
"default_p_state": "UNDEFINED",
"clk_domain": "system.cpu_clk_domain",
"power_model": null,
"sequential_access": false,
"assoc": 2,
"cxx_class": "LRU",
"p_state_clk_gate_max": 1000000000000,
"path": "system.cpu.icache.tags",
"block_size": 64,
"type": "LRU",
"data_latency": 2
},
"tgts_per_mshr": 20,
"demand_mshr_reserve": 1,
"power_model": null,
"addr_ranges": [
"0:18446744073709551615:0:0:0:0"
],
"is_read_only": true,
"prefetch_on_access": false,
"path": "system.cpu.icache",
"data_latency": 2,
"tag_latency": 2,
"name": "icache",
"p_state_clk_gate_bins": 20,
"sequential_access": false,
"assoc": 2
},
"function_trace": false,
"do_checkpoint_insts": true,
"cxx_class": "TimingSimpleCPU",
"max_loads_all_threads": 0,
"clk_domain": "system.cpu_clk_domain",
"function_trace_start": 0,
"cpu_id": 0,
"checker": null,
"eventq_index": 0,
"default_p_state": "UNDEFINED",
"p_state_clk_gate_max": 1000000000000,
"toL2Bus": {
"point_of_coherency": false,
"system": "system",
"response_latency": 1,
"cxx_class": "CoherentXBar",
"forward_latency": 0,
"clk_domain": "system.cpu_clk_domain",
"width": 32,
"eventq_index": 0,
"default_p_state": "UNDEFINED",
"p_state_clk_gate_max": 1000000000000,
"master": {
"peer": [
"system.cpu.l2cache.cpu_side"
],
"role": "MASTER"
},
"type": "CoherentXBar",
"frontend_latency": 1,
"slave": {
"peer": [
"system.cpu.icache.mem_side",
"system.cpu.dcache.mem_side"
],
"role": "SLAVE"
},
"p_state_clk_gate_min": 1000,
"snoop_filter": {
"name": "snoop_filter",
"system": "system",
"max_capacity": 8388608,
"eventq_index": 0,
"cxx_class": "SnoopFilter",
"path": "system.cpu.toL2Bus.snoop_filter",
"type": "SnoopFilter",
"lookup_latency": 0
},
"power_model": null,
"path": "system.cpu.toL2Bus",
"snoop_response_latency": 1,
"name": "toL2Bus",
"p_state_clk_gate_bins": 20,
"use_default_range": false
},
"do_quiesce": true,
"type": "TimingSimpleCPU",
"profile": 0,
"icache_port": {
"peer": "system.cpu.icache.cpu_side",
"role": "MASTER"
},
"p_state_clk_gate_bins": 20,
"p_state_clk_gate_min": 1000,
"interrupts": [
{
"eventq_index": 0,
"path": "system.cpu.interrupts",
"type": "RiscvInterrupts",
"name": "interrupts",
"cxx_class": "RiscvISA::Interrupts"
}
],
"dcache_port": {
"peer": "system.cpu.dcache.cpu_side",
"role": "MASTER"
},
"socket_id": 0,
"power_model": null,
"max_insts_all_threads": 0,
"l2cache": {
"cpu_side": {
"peer": "system.cpu.toL2Bus.master[0]",
"role": "SLAVE"
},
"clusivity": "mostly_incl",
"prefetcher": null,
"system": "system",
"write_buffers": 8,
"response_latency": 20,
"cxx_class": "Cache",
"size": 2097152,
"type": "Cache",
"clk_domain": "system.cpu_clk_domain",
"max_miss_count": 0,
"eventq_index": 0,
"default_p_state": "UNDEFINED",
"p_state_clk_gate_max": 1000000000000,
"mem_side": {
"peer": "system.membus.slave[1]",
"role": "MASTER"
},
"mshrs": 20,
"writeback_clean": false,
"p_state_clk_gate_min": 1000,
"tags": {
"size": 2097152,
"tag_latency": 20,
"name": "tags",
"p_state_clk_gate_min": 1000,
"eventq_index": 0,
"p_state_clk_gate_bins": 20,
"default_p_state": "UNDEFINED",
"clk_domain": "system.cpu_clk_domain",
"power_model": null,
"sequential_access": false,
"assoc": 8,
"cxx_class": "LRU",
"p_state_clk_gate_max": 1000000000000,
"path": "system.cpu.l2cache.tags",
"block_size": 64,
"type": "LRU",
"data_latency": 20
},
"tgts_per_mshr": 12,
"demand_mshr_reserve": 1,
"power_model": null,
"addr_ranges": [
"0:18446744073709551615:0:0:0:0"
],
"is_read_only": false,
"prefetch_on_access": false,
"path": "system.cpu.l2cache",
"data_latency": 20,
"tag_latency": 20,
"name": "l2cache",
"p_state_clk_gate_bins": 20,
"sequential_access": false,
"assoc": 8
},
"path": "system.cpu",
"max_loads_any_thread": 0,
"switched_out": false,
"workload": [
{
"uid": 100,
"pid": 100,
"kvmInSE": false,
"cxx_class": "LiveProcess",
"executable": "/z/powerjg/gem5-upstream/tests/test-progs/hello/bin/riscv/linux/hello",
"drivers": [],
"system": "system",
"gid": 100,
"eventq_index": 0,
"env": [],
"input": "cin",
"ppid": 99,
"type": "LiveProcess",
"cwd": "",
"simpoint": 0,
"euid": 100,
"path": "system.cpu.workload",
"max_stack_size": 67108864,
"name": "workload",
"cmd": [
"hello"
],
"errout": "cerr",
"useArchPT": false,
"egid": 100,
"output": "cout"
}
],
"name": "cpu",
"dtb": {
"name": "dtb",
"eventq_index": 0,
"cxx_class": "RiscvISA::TLB",
"path": "system.cpu.dtb",
"type": "RiscvTLB",
"size": 64
},
"simpoint_start_insts": [],
"max_insts_any_thread": 0,
"progress_interval": 0,
"branchPred": null,
"dcache": {
"cpu_side": {
"peer": "system.cpu.dcache_port",
"role": "SLAVE"
},
"clusivity": "mostly_incl",
"prefetcher": null,
"system": "system",
"write_buffers": 8,
"response_latency": 2,
"cxx_class": "Cache",
"size": 262144,
"type": "Cache",
"clk_domain": "system.cpu_clk_domain",
"max_miss_count": 0,
"eventq_index": 0,
"default_p_state": "UNDEFINED",
"p_state_clk_gate_max": 1000000000000,
"mem_side": {
"peer": "system.cpu.toL2Bus.slave[1]",
"role": "MASTER"
},
"mshrs": 4,
"writeback_clean": false,
"p_state_clk_gate_min": 1000,
"tags": {
"size": 262144,
"tag_latency": 2,
"name": "tags",
"p_state_clk_gate_min": 1000,
"eventq_index": 0,
"p_state_clk_gate_bins": 20,
"default_p_state": "UNDEFINED",
"clk_domain": "system.cpu_clk_domain",
"power_model": null,
"sequential_access": false,
"assoc": 2,
"cxx_class": "LRU",
"p_state_clk_gate_max": 1000000000000,
"path": "system.cpu.dcache.tags",
"block_size": 64,
"type": "LRU",
"data_latency": 2
},
"tgts_per_mshr": 20,
"demand_mshr_reserve": 1,
"power_model": null,
"addr_ranges": [
"0:18446744073709551615:0:0:0:0"
],
"is_read_only": false,
"prefetch_on_access": false,
"path": "system.cpu.dcache",
"data_latency": 2,
"tag_latency": 2,
"name": "dcache",
"p_state_clk_gate_bins": 20,
"sequential_access": false,
"assoc": 2
},
"isa": [
{
"eventq_index": 0,
"path": "system.cpu.isa",
"type": "RiscvISA",
"name": "isa",
"cxx_class": "RiscvISA::ISA"
}
],
"tracer": {
"eventq_index": 0,
"path": "system.cpu.tracer",
"type": "ExeTracer",
"name": "tracer",
"cxx_class": "Trace::ExeTracer"
}
}
],
"multi_thread": false,
"exit_on_work_items": false,
"work_item_id": -1,
"num_work_ids": 16
},
"time_sync_period": 100000000000,
"eventq_index": 0,
"time_sync_spin_threshold": 100000000,
"cxx_class": "Root",
"path": "root",
"time_sync_enable": false,
"type": "Root",
"full_system": false
}

3
tests/quick/se/00.hello/ref/riscv/linux/simple-timing/simerr Executable file
View file

@ -0,0 +1,3 @@
warn: Unknown operating system; assuming Linux.
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick

15
tests/quick/se/00.hello/ref/riscv/linux/simple-timing/simout Executable file
View file

@ -0,0 +1,15 @@
Redirecting stdout to build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-timing/simout
Redirecting stderr to build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Nov 30 2016 14:33:35
gem5 started Nov 30 2016 16:18:29
gem5 executing on zizzer, pid 34059
command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/00.hello/riscv/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
Exiting @ tick 11602500 because target called exit()

511
tests/quick/se/00.hello/ref/riscv/linux/simple-timing/stats.txt Normal file
View file

@ -0,0 +1,511 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000012 # Number of seconds simulated
sim_ticks 11602500 # Number of ticks simulated
final_tick 11602500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 36172 # Simulator instruction rate (inst/s)
host_op_rate 36155 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 264212858 # Simulator tick rate (ticks/s)
host_mem_usage 230876 # Number of bytes of host memory used
host_seconds 0.04 # Real time elapsed on the host
sim_insts 1587 # Number of instructions simulated
sim_ops 1587 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 11602500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 7808 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1920 # Number of bytes read from this memory
system.physmem.bytes_read::total 9728 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 7808 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 7808 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 122 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 30 # Number of read requests responded to by this memory
system.physmem.num_reads::total 152 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 672958414 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 165481577 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 838439991 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 672958414 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 672958414 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 672958414 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 165481577 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 838439991 # Total bandwidth to/from this memory (bytes/s)
system.pwrStateResidencyTicks::UNDEFINED 11602500 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 9 # Number of system calls
system.cpu.pwrStateResidencyTicks::ON 11602500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 23205 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 1587 # Number of instructions committed
system.cpu.committedOps 1587 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1588 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 142 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 231 # number of instructions that are conditional controls
system.cpu.num_int_insts 1588 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_int_register_reads 2062 # number of times the integer registers were read
system.cpu.num_int_register_writes 1077 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 569 # number of memory refs
system.cpu.num_load_insts 289 # Number of load instructions
system.cpu.num_store_insts 280 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 23205 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.Branches 373 # Number of branches fetched
system.cpu.op_class::No_OpClass 9 0.56% 0.56% # Class of executed instruction
system.cpu.op_class::IntAlu 1019 63.81% 64.37% # Class of executed instruction
system.cpu.op_class::IntMult 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::FloatMultAcc 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::FloatMisc 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.37% # Class of executed instruction
system.cpu.op_class::MemRead 289 18.10% 82.47% # Class of executed instruction
system.cpu.op_class::MemWrite 280 17.53% 100.00% # Class of executed instruction
system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 1597 # Class of executed instruction
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 11602500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 22.779229 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 537 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 31 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 17.322581 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 22.779229 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.005561 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.005561 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 31 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.007568 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 1167 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 1167 # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 11602500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 276 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 276 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 261 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 261 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 537 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 537 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 537 # number of overall hits
system.cpu.dcache.overall_hits::total 537 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 13 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 13 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 18 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 18 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 31 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 31 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 31 # number of overall misses
system.cpu.dcache.overall_misses::total 31 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 770000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 770000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 1134000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 1134000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 1904000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 1904000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 1904000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 1904000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 289 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 289 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 279 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 279 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 568 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 568 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 568 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 568 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.044983 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.044983 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.064516 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.064516 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.054577 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.054577 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.054577 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.054577 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59230.769231 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 59230.769231 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 61419.354839 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 61419.354839 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 61419.354839 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 61419.354839 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 13 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 13 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 18 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 18 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 31 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 31 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 31 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 31 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 757000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 757000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1116000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1116000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 1873000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 1873000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 1873000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 1873000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.044983 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.044983 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.064516 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.064516 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.054577 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.054577 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.054577 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.054577 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 58230.769231 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58230.769231 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60419.354839 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 60419.354839 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60419.354839 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 60419.354839 # average overall mshr miss latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 11602500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 0 # number of replacements
system.cpu.icache.tags.tagsinuse 56.912998 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 1476 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 122 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 12.098361 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 56.912998 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.027790 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.027790 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 122 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 13 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.059570 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 3318 # Number of tag accesses
system.cpu.icache.tags.data_accesses 3318 # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 11602500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 1476 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1476 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1476 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 1476 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 1476 # number of overall hits
system.cpu.icache.overall_hits::total 1476 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 122 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 122 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 122 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 122 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 122 # number of overall misses
system.cpu.icache.overall_misses::total 122 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 7686500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 7686500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 7686500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 7686500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 7686500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 7686500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 1598 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 1598 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 1598 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 1598 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 1598 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 1598 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.076345 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.076345 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.076345 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.076345 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.076345 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.076345 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63004.098361 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 63004.098361 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 63004.098361 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 63004.098361 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 63004.098361 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 63004.098361 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 122 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 122 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 122 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 122 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 122 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 122 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 7564500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 7564500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 7564500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 7564500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 7564500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 7564500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.076345 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.076345 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.076345 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.076345 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.076345 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.076345 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62004.098361 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62004.098361 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62004.098361 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 62004.098361 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62004.098361 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 62004.098361 # average overall mshr miss latency
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 11602500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 78.991344 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 152 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.006579 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst 57.023406 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 21.967939 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001740 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000670 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.002411 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 152 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.004639 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 1376 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 1376 # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 11602500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 1 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits
system.cpu.l2cache.overall_hits::total 1 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 18 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 18 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 122 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 122 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 12 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 12 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 122 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 30 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 152 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 122 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 30 # number of overall misses
system.cpu.l2cache.overall_misses::total 152 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1089000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 1089000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 7381500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 7381500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 726000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 726000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 7381500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 1815000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 9196500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 7381500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 1815000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 9196500 # number of overall miss cycles
system.cpu.l2cache.ReadExReq_accesses::cpu.data 18 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 18 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 122 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 122 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 13 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 13 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 122 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 31 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 153 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 122 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 31 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 153 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.923077 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.923077 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.967742 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.993464 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.967742 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.993464 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60504.098361 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60504.098361 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60504.098361 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 60503.289474 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60504.098361 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 60503.289474 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 18 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 18 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 122 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 122 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 12 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 12 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 122 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 30 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 152 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 122 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 30 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 152 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 909000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 909000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 6161500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 6161500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 606000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 606000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 6161500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1515000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 7676500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 6161500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1515000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 7676500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.923077 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.923077 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.967742 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.993464 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.967742 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.993464 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50504.098361 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50504.098361 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50504.098361 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50503.289474 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50504.098361 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50503.289474 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 153 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 11602500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 135 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 18 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 18 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 122 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 13 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 244 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 62 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 306 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 7808 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1984 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 9792 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples 153 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.006536 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.080845 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 152 99.35% 99.35% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 1 0.65% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 153 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 76500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 183000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 1.6 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 46500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%)
system.membus.snoop_filter.tot_requests 152 # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 11602500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 134 # Transaction distribution
system.membus.trans_dist::ReadExReq 18 # Transaction distribution
system.membus.trans_dist::ReadExResp 18 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 134 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 304 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 304 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 9728 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 9728 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples 152 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 152 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 152 # Request fanout histogram
system.membus.reqLayer0.occupancy 152500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 1.3 # Layer utilization (%)
system.membus.respLayer1.occupancy 760000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 6.6 # Layer utilization (%)
---------- End Simulation Statistics ----------

84
tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini
View file

@ -183,10 +183,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=4
@ -200,6 +200,7 @@ response_latency=2
sequential_access=false
size=262144
system=system
tag_latency=2
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
@ -212,15 +213,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=262144
tag_latency=2
[system.cpu.dtb]
type=X86TLB
@ -313,10 +315,10 @@ pipelined=true
[system.cpu.fuPool.FUList3]
type=FUDesc
children=opList0 opList1 opList2
children=opList0 opList1 opList2 opList3 opList4
count=2
eventq_index=0
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4
[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
@ -328,11 +330,25 @@ pipelined=true
[system.cpu.fuPool.FUList3.opList1]
type=OpDesc
eventq_index=0
opClass=FloatMultAcc
opLat=5
pipelined=true
[system.cpu.fuPool.FUList3.opList2]
type=OpDesc
eventq_index=0
opClass=FloatMisc
opLat=3
pipelined=true
[system.cpu.fuPool.FUList3.opList3]
type=OpDesc
eventq_index=0
opClass=FloatDiv
opLat=12
pipelined=false
[system.cpu.fuPool.FUList3.opList2]
[system.cpu.fuPool.FUList3.opList4]
type=OpDesc
eventq_index=0
opClass=FloatSqrt
@ -341,18 +357,25 @@ pipelined=false
[system.cpu.fuPool.FUList4]
type=FUDesc
children=opList
children=opList0 opList1
count=0
eventq_index=0
opList=system.cpu.fuPool.FUList4.opList
opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1
[system.cpu.fuPool.FUList4.opList]
[system.cpu.fuPool.FUList4.opList0]
type=OpDesc
eventq_index=0
opClass=MemRead
opLat=1
pipelined=true
[system.cpu.fuPool.FUList4.opList1]
type=OpDesc
eventq_index=0
opClass=FloatMemRead
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5]
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
@ -502,24 +525,31 @@ pipelined=true
[system.cpu.fuPool.FUList6]
type=FUDesc
children=opList
children=opList0 opList1
count=0
eventq_index=0
opList=system.cpu.fuPool.FUList6.opList
opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
[system.cpu.fuPool.FUList6.opList]
[system.cpu.fuPool.FUList6.opList0]
type=OpDesc
eventq_index=0
opClass=MemWrite
opLat=1
pipelined=true
[system.cpu.fuPool.FUList6.opList1]
type=OpDesc
eventq_index=0
opClass=FloatMemWrite
opLat=1
pipelined=true
[system.cpu.fuPool.FUList7]
type=FUDesc
children=opList0 opList1
children=opList0 opList1 opList2 opList3
count=4
eventq_index=0
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 system.cpu.fuPool.FUList7.opList2 system.cpu.fuPool.FUList7.opList3
[system.cpu.fuPool.FUList7.opList0]
type=OpDesc
@ -535,6 +565,20 @@ opClass=MemWrite
opLat=1
pipelined=true
[system.cpu.fuPool.FUList7.opList2]
type=OpDesc
eventq_index=0
opClass=FloatMemRead
opLat=1
pipelined=true
[system.cpu.fuPool.FUList7.opList3]
type=OpDesc
eventq_index=0
opClass=FloatMemWrite
opLat=1
pipelined=true
[system.cpu.fuPool.FUList8]
type=FUDesc
children=opList
@ -556,10 +600,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=true
max_miss_count=0
mshrs=4
@ -573,6 +617,7 @@ response_latency=2
sequential_access=false
size=131072
system=system
tag_latency=2
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
@ -585,15 +630,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=131072
tag_latency=2
[system.cpu.interrupts]
type=X86LocalApic
@ -643,10 +689,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=20
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=20
is_read_only=false
max_miss_count=0
mshrs=20
@ -660,6 +706,7 @@ response_latency=20
sequential_access=false
size=2097152
system=system
tag_latency=20
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
@ -672,15 +719,16 @@ type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=20
default_p_state=UNDEFINED
eventq_index=0
hit_latency=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=2097152
tag_latency=20
[system.cpu.toL2Bus]
type=CoherentXBar
@ -725,7 +773,7 @@ env=
errout=cerr
euid=100
eventq_index=0
executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/x86/linux/hello
executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello
gid=100
input=cin
kvmInSE=false

8
tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout
View file

@ -3,10 +3,10 @@ Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing/
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Oct 11 2016 00:00:58
gem5 started Oct 13 2016 21:09:20
gem5 executing on e108600-lin, pid 17644
command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/x86/linux/o3-timing
gem5 compiled Nov 29 2016 18:55:59
gem5 started Nov 29 2016 18:56:21
gem5 executing on zizzer, pid 719
command line: /z/powerjg/gem5-upstream/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/00.hello/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

272
tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.000022 # Nu
sim_ticks 22466500 # Number of ticks simulated
final_tick 22466500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 70304 # Simulator instruction rate (inst/s)
host_op_rate 127350 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 293494415 # Simulator tick rate (ticks/s)
host_mem_usage 271256 # Number of bytes of host memory used
host_seconds 0.08 # Real time elapsed on the host
host_inst_rate 24766 # Simulator instruction rate (inst/s)
host_op_rate 44863 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 103395613 # Simulator tick rate (ticks/s)
host_mem_usage 253532 # Number of bytes of host memory used
host_seconds 0.22 # Real time elapsed on the host
sim_insts 5380 # Number of instructions simulated
sim_ops 9747 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@ -201,12 +201,12 @@ system.physmem.bytesPerActivate::768-895 2 2.11% 93.68% # By
system.physmem.bytesPerActivate::896-1023 2 2.11% 95.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 4 4.21% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 95 # Bytes accessed per row activation
system.physmem.totQLat 6803250 # Total ticks spent queuing
system.physmem.totMemAccLat 14640750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totQLat 6799250 # Total ticks spent queuing
system.physmem.totMemAccLat 14636750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2090000 # Total ticks spent in databus transfers
system.physmem.avgQLat 16275.72 # Average queueing delay per DRAM burst
system.physmem.avgQLat 16266.15 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 35025.72 # Average memory access latency per DRAM burst
system.physmem.avgMemAccLat 35016.15 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 1190.75 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 1190.75 # Average system read bandwidth in MiByte/s
@ -247,9 +247,9 @@ system.physmem_1.preEnergy 235290 # En
system.physmem_1.readEnergy 1570800 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 2963430 # Energy for active background per rank (pJ)
system.physmem_1.actBackEnergy 2962290 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 82560 # Energy for precharge background per rank (pJ)
system.physmem_1.actPowerDownEnergy 7182000 # Energy for active power-down per rank (pJ)
system.physmem_1.actPowerDownEnergy 7183140 # Energy for active power-down per rank (pJ)
system.physmem_1.prePowerDownEnergy 1440 # Energy for precharge power-down per rank (pJ)
system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
system.physmem_1.totalEnergy 13750320 # Total energy per rank (pJ)
@ -354,13 +354,13 @@ system.cpu.iq.iqSquashedOperandsExamined 16553 # Nu
system.cpu.iq.iqSquashedNonSpecRemoved 11 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 24836 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.729264 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.710819 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.710701 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 19691 79.28% 79.28% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 1200 4.83% 84.12% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 866 3.49% 87.60% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 19689 79.28% 79.28% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 1202 4.84% 84.12% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 867 3.49% 87.61% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 575 2.32% 89.92% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 815 3.28% 93.20% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 814 3.28% 93.20% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 575 2.32% 95.51% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 614 2.47% 97.99% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 364 1.47% 99.45% # Number of insts issued each cycle
@ -493,20 +493,20 @@ system.cpu.iew.exec_stores 1259 # Nu
system.cpu.iew.exec_rate 0.379178 # Inst execution rate
system.cpu.iew.wb_sent 16737 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 16422 # cumulative count of insts written-back
system.cpu.iew.wb_producers 11019 # num instructions producing a value
system.cpu.iew.wb_consumers 17148 # num instructions consuming a value
system.cpu.iew.wb_producers 11018 # num instructions producing a value
system.cpu.iew.wb_consumers 17146 # num instructions consuming a value
system.cpu.iew.wb_rate 0.365469 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.642582 # average fanout of values written-back
system.cpu.iew.wb_fanout 0.642599 # average fanout of values written-back
system.cpu.commit.commitSquashedInsts 12050 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 648 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 22793 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.427631 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.307645 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.307612 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 19538 85.72% 85.72% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 1001 4.39% 90.11% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 566 2.48% 92.59% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 19537 85.71% 85.71% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 1003 4.40% 90.12% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 565 2.48% 92.59% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 727 3.19% 95.78% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 384 1.68% 97.47% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 133 0.58% 98.05% # Number of insts commited each cycle
@ -586,12 +586,12 @@ system.cpu.misc_regfile_reads 7640 # nu
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 81.537714 # Cycle average of tags in use
system.cpu.dcache.tags.tagsinuse 81.537314 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 2520 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 17.872340 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 81.537714 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_blocks::cpu.data 81.537314 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.019907 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.019907 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id
@ -617,14 +617,14 @@ system.cpu.dcache.demand_misses::cpu.data 193 # n
system.cpu.dcache.demand_misses::total 193 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 193 # number of overall misses
system.cpu.dcache.overall_misses::total 193 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 10226000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 10226000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 7070500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 7070500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 17296500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 17296500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 17296500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 17296500 # number of overall miss cycles
system.cpu.dcache.ReadReq_miss_latency::cpu.data 10224000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 10224000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 7069500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 7069500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 17293500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 17293500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 17293500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 17293500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 1778 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1778 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses)
@ -641,14 +641,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.071139
system.cpu.dcache.demand_miss_rate::total 0.071139 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.071139 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.071139 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 87401.709402 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 87401.709402 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 93032.894737 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 93032.894737 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 89619.170984 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 89619.170984 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 89619.170984 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 89619.170984 # average overall miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 87384.615385 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 87384.615385 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 93019.736842 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 93019.736842 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 89603.626943 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 89603.626943 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 89603.626943 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 89603.626943 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 132 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked
@ -669,14 +669,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 141
system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6448000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 6448000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6994500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 6994500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13442500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 13442500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13442500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 13442500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6446000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 6446000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6993500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 6993500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13439500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 13439500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13439500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 13439500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036558 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036558 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081283 # mshr miss rate for WriteReq accesses
@ -685,24 +685,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051972
system.cpu.dcache.demand_mshr_miss_rate::total 0.051972 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051972 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.051972 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 99200 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 99200 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 92032.894737 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 92032.894737 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 95336.879433 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 95336.879433 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 95336.879433 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 95336.879433 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 99169.230769 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 99169.230769 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 92019.736842 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 92019.736842 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 95315.602837 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 95315.602837 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 95315.602837 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 95315.602837 # average overall mshr miss latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 0 # number of replacements
system.cpu.icache.tags.tagsinuse 130.260906 # Cycle average of tags in use
system.cpu.icache.tags.tagsinuse 130.259615 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 1641 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 278 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 5.902878 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 130.260906 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.063604 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.063604 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_blocks::cpu.inst 130.259615 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.063603 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.063603 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 278 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 140 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 138 # Occupied blocks per task id
@ -722,12 +722,12 @@ system.cpu.icache.demand_misses::cpu.inst 385 # n
system.cpu.icache.demand_misses::total 385 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 385 # number of overall misses
system.cpu.icache.overall_misses::total 385 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 30146000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 30146000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 30146000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 30146000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 30146000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 30146000 # number of overall miss cycles
system.cpu.icache.ReadReq_miss_latency::cpu.inst 30145000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 30145000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 30145000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 30145000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 30145000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 30145000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 2026 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 2026 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 2026 # number of demand (read+write) accesses
@ -740,12 +740,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.190030
system.cpu.icache.demand_miss_rate::total 0.190030 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.190030 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.190030 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 78301.298701 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 78301.298701 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 78301.298701 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 78301.298701 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 78301.298701 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 78301.298701 # average overall miss latency
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 78298.701299 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 78298.701299 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 78298.701299 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 78298.701299 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 78298.701299 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 78298.701299 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 171 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked
@ -764,33 +764,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 278
system.cpu.icache.demand_mshr_misses::total 278 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 278 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23206500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 23206500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23206500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 23206500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23206500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 23206500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23205500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 23205500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23205500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 23205500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23205500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 23205500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.137216 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.137216 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.137216 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.137216 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.137216 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.137216 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83476.618705 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83476.618705 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83476.618705 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 83476.618705 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83476.618705 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 83476.618705 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83473.021583 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83473.021583 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83473.021583 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 83473.021583 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83473.021583 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 83473.021583 # average overall mshr miss latency
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 211.897546 # Cycle average of tags in use
system.cpu.l2cache.tags.tagsinuse 211.895854 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 418 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.002392 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.293933 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 81.603612 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.292642 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 81.603212 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003976 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.002490 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.006467 # Average percentage of cache occupancy
@ -819,18 +819,18 @@ system.cpu.l2cache.demand_misses::total 418 # nu
system.cpu.l2cache.overall_misses::cpu.inst 277 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 141 # number of overall misses
system.cpu.l2cache.overall_misses::total 418 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6880500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 6880500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22777500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 22777500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6350000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 6350000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 22777500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 13230500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 36008000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 22777500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 13230500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 36008000 # number of overall miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6879500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 6879500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22776500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 22776500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6348000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 6348000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 22776500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 13227500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 36004000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 22776500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 13227500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 36004000 # number of overall miss cycles
system.cpu.l2cache.ReadExReq_accesses::cpu.data 76 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 76 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 278 # number of ReadCleanReq accesses(hits+misses)
@ -855,18 +855,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.997613 #
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996403 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.997613 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90532.894737 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90532.894737 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82229.241877 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82229.241877 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 97692.307692 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 97692.307692 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82229.241877 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93833.333333 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 86143.540670 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82229.241877 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93833.333333 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 86143.540670 # average overall miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90519.736842 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90519.736842 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82225.631769 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82225.631769 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 97661.538462 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 97661.538462 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82225.631769 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93812.056738 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 86133.971292 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82225.631769 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93812.056738 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 86133.971292 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -885,18 +885,18 @@ system.cpu.l2cache.demand_mshr_misses::total 418
system.cpu.l2cache.overall_mshr_misses::cpu.inst 277 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 418 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6120500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6120500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 20007500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 20007500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5700000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5700000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20007500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11820500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 31828000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20007500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11820500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 31828000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6119500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6119500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 20006500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 20006500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5698000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5698000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20006500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11817500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 31824000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20006500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11817500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 31824000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996403 # mshr miss rate for ReadCleanReq accesses
@ -909,18 +909,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997613
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996403 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.997613 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80532.894737 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80532.894737 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72229.241877 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72229.241877 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 87692.307692 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 87692.307692 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72229.241877 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83833.333333 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76143.540670 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72229.241877 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83833.333333 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76143.540670 # average overall mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80519.736842 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80519.736842 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72225.631769 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72225.631769 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 87661.538462 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 87661.538462 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72225.631769 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83812.056738 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76133.971292 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72225.631769 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83812.056738 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76133.971292 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 419 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.

86
tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/config.ini
View file

@ -177,10 +177,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=4
@ -194,6 +194,7 @@ response_latency=2
sequential_access=false
size=262144
system=system
tag_latency=2
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
@ -206,15 +207,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=262144
tag_latency=2
[system.cpu.dtb]
type=AlphaTLB
@ -292,10 +294,10 @@ pipelined=true
[system.cpu.fuPool.FUList3]
type=FUDesc
children=opList0 opList1 opList2
children=opList0 opList1 opList2 opList3 opList4
count=2
eventq_index=0
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4
[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
@ -307,11 +309,25 @@ pipelined=true
[system.cpu.fuPool.FUList3.opList1]
type=OpDesc
eventq_index=0
opClass=FloatMultAcc
opLat=5
pipelined=true
[system.cpu.fuPool.FUList3.opList2]
type=OpDesc
eventq_index=0
opClass=FloatMisc
opLat=3
pipelined=true
[system.cpu.fuPool.FUList3.opList3]
type=OpDesc
eventq_index=0
opClass=FloatDiv
opLat=12
pipelined=false
[system.cpu.fuPool.FUList3.opList2]
[system.cpu.fuPool.FUList3.opList4]
type=OpDesc
eventq_index=0
opClass=FloatSqrt
@ -320,18 +336,25 @@ pipelined=false
[system.cpu.fuPool.FUList4]
type=FUDesc
children=opList
children=opList0 opList1
count=0
eventq_index=0
opList=system.cpu.fuPool.FUList4.opList
opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1
[system.cpu.fuPool.FUList4.opList]
[system.cpu.fuPool.FUList4.opList0]
type=OpDesc
eventq_index=0
opClass=MemRead
opLat=1
pipelined=true
[system.cpu.fuPool.FUList4.opList1]
type=OpDesc
eventq_index=0
opClass=FloatMemRead
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5]
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
@ -481,24 +504,31 @@ pipelined=true
[system.cpu.fuPool.FUList6]
type=FUDesc
children=opList
children=opList0 opList1
count=0
eventq_index=0
opList=system.cpu.fuPool.FUList6.opList
opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
[system.cpu.fuPool.FUList6.opList]
[system.cpu.fuPool.FUList6.opList0]
type=OpDesc
eventq_index=0
opClass=MemWrite
opLat=1
pipelined=true
[system.cpu.fuPool.FUList6.opList1]
type=OpDesc
eventq_index=0
opClass=FloatMemWrite
opLat=1
pipelined=true
[system.cpu.fuPool.FUList7]
type=FUDesc
children=opList0 opList1
children=opList0 opList1 opList2 opList3
count=4
eventq_index=0
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 system.cpu.fuPool.FUList7.opList2 system.cpu.fuPool.FUList7.opList3
[system.cpu.fuPool.FUList7.opList0]
type=OpDesc
@ -514,6 +544,20 @@ opClass=MemWrite
opLat=1
pipelined=true
[system.cpu.fuPool.FUList7.opList2]
type=OpDesc
eventq_index=0
opClass=FloatMemRead
opLat=1
pipelined=true
[system.cpu.fuPool.FUList7.opList3]
type=OpDesc
eventq_index=0
opClass=FloatMemWrite
opLat=1
pipelined=true
[system.cpu.fuPool.FUList8]
type=FUDesc
children=opList
@ -535,10 +579,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=true
max_miss_count=0
mshrs=4
@ -552,6 +596,7 @@ response_latency=2
sequential_access=false
size=131072
system=system
tag_latency=2
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
@ -564,15 +609,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=131072
tag_latency=2
[system.cpu.interrupts0]
type=AlphaInterrupts
@ -604,10 +650,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=20
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=20
is_read_only=false
max_miss_count=0
mshrs=20
@ -621,6 +667,7 @@ response_latency=20
sequential_access=false
size=2097152
system=system
tag_latency=20
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
@ -633,15 +680,16 @@ type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=20
default_p_state=UNDEFINED
eventq_index=0
hit_latency=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=2097152
tag_latency=20
[system.cpu.toL2Bus]
type=CoherentXBar
@ -686,7 +734,7 @@ env=
errout=cerr
euid=100
eventq_index=0
executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/linux/hello
executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
kvmInSE=false
@ -709,7 +757,7 @@ env=
errout=cerr
euid=100
eventq_index=0
executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/linux/hello
executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
kvmInSE=false

8
tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simout
View file

@ -3,10 +3,10 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Oct 11 2016 00:00:58
gem5 started Oct 13 2016 20:19:48
gem5 executing on e108600-lin, pid 28095
command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt
gem5 compiled Nov 29 2016 18:06:09
gem5 started Nov 29 2016 18:06:32
gem5 executing on zizzer, pid 27586
command line: /z/powerjg/gem5-upstream/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

482
tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.000027 # Nu
sim_ticks 26661500 # Number of ticks simulated
final_tick 26661500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 139098 # Simulator instruction rate (inst/s)
host_op_rate 139080 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 290337480 # Simulator tick rate (ticks/s)
host_mem_usage 255644 # Number of bytes of host memory used
host_seconds 0.09 # Real time elapsed on the host
host_inst_rate 29979 # Simulator instruction rate (inst/s)
host_op_rate 29977 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 62584510 # Simulator tick rate (ticks/s)
host_mem_usage 237004 # Number of bytes of host memory used
host_seconds 0.43 # Real time elapsed on the host
sim_insts 12770 # Number of instructions simulated
sim_ops 12770 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@ -201,12 +201,12 @@ system.physmem.bytesPerActivate::768-895 9 4.46% 91.58% # By
system.physmem.bytesPerActivate::896-1023 3 1.49% 93.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 14 6.93% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 202 # Bytes accessed per row activation
system.physmem.totQLat 15942250 # Total ticks spent queuing
system.physmem.totMemAccLat 34092250 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totQLat 15941250 # Total ticks spent queuing
system.physmem.totMemAccLat 34091250 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 4840000 # Total ticks spent in databus transfers
system.physmem.avgQLat 16469.27 # Average queueing delay per DRAM burst
system.physmem.avgQLat 16468.23 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 35219.27 # Average memory access latency per DRAM burst
system.physmem.avgMemAccLat 35218.23 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 2323.65 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 2323.65 # Average system read bandwidth in MiByte/s
@ -228,9 +228,9 @@ system.physmem_0.preEnergy 436425 # En
system.physmem_0.readEnergy 4191180 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 6127500 # Energy for active background per rank (pJ)
system.physmem_0.actBackEnergy 6126930 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 47520 # Energy for precharge background per rank (pJ)
system.physmem_0.actPowerDownEnergy 5972460 # Energy for active power-down per rank (pJ)
system.physmem_0.actPowerDownEnergy 5973030 # Energy for active power-down per rank (pJ)
system.physmem_0.prePowerDownEnergy 1440 # Energy for precharge power-down per rank (pJ)
system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
system.physmem_0.totalEnergy 19470105 # Total energy per rank (pJ)
@ -247,9 +247,9 @@ system.physmem_1.preEnergy 330165 # En
system.physmem_1.readEnergy 2720340 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 4612440 # Energy for active background per rank (pJ)
system.physmem_1.actBackEnergy 4611870 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 162240 # Energy for precharge background per rank (pJ)
system.physmem_1.actPowerDownEnergy 6908970 # Energy for active power-down per rank (pJ)
system.physmem_1.actPowerDownEnergy 6909540 # Energy for active power-down per rank (pJ)
system.physmem_1.prePowerDownEnergy 373920 # Energy for precharge power-down per rank (pJ)
system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
system.physmem_1.totalEnergy 17623155 # Total energy per rank (pJ)
@ -280,18 +280,18 @@ system.cpu.dtb.fetch_hits 0 # IT
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 4130 # DTB read hits
system.cpu.dtb.read_hits 4131 # DTB read hits
system.cpu.dtb.read_misses 76 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 4206 # DTB read accesses
system.cpu.dtb.read_accesses 4207 # DTB read accesses
system.cpu.dtb.write_hits 2011 # DTB write hits
system.cpu.dtb.write_misses 48 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 2059 # DTB write accesses
system.cpu.dtb.data_hits 6141 # DTB hits
system.cpu.dtb.data_hits 6142 # DTB hits
system.cpu.dtb.data_misses 124 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 6265 # DTB accesses
system.cpu.dtb.data_accesses 6266 # DTB accesses
system.cpu.itb.fetch_hits 3836 # ITB hits
system.cpu.itb.fetch_misses 50 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
@ -323,14 +323,14 @@ system.cpu.fetch.SquashCycles 875 # Nu
system.cpu.fetch.MiscStallCycles 344 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.CacheLines 3836 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 566 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 26300 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.059658 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.449516 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::samples 26305 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.059456 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.449327 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 21275 80.89% 80.89% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 21280 80.90% 80.90% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 504 1.92% 82.81% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 391 1.49% 84.30% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 446 1.70% 85.99% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 446 1.70% 86.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 478 1.82% 87.81% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 367 1.40% 89.21% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 469 1.78% 90.99% # Number of instructions fetched each cycle (Total)
@ -339,28 +339,28 @@ system.cpu.fetch.rateDist::8 2094 7.96% 100.00% # Nu
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 26300 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 26305 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.091216 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.522635 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 36528 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 10375 # Number of cycles decode is blocked
system.cpu.decode.IdleCycles 36539 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 10373 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 3958 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 495 # Number of cycles decode is unblocking
system.cpu.decode.UnblockCycles 496 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 725 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 405 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 151 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 24583 # Number of instructions handled by decode
system.cpu.decode.DecodedInsts 24588 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 377 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 725 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 36872 # Number of cycles rename is idle
system.cpu.rename.IdleCycles 36883 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 3499 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 1435 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 4116 # Number of cycles rename is running
system.cpu.rename.RunCycles 4115 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 5434 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 23584 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 36 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 223 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 328 # Number of times rename has blocked due to LQ full
system.cpu.rename.IQFullEvents 222 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 329 # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents 4703 # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands 17574 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 29532 # Number of register rename lookups that rename has made
@ -370,7 +370,7 @@ system.cpu.rename.CommittedMaps 9154 # Nu
system.cpu.rename.UndoneMaps 8420 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 57 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 45 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 1621 # count of insts added to the skid buffer
system.cpu.rename.skidInsts 1617 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 1925 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 1093 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 7 # Number of conflicting loads.
@ -381,105 +381,105 @@ system.cpu.memDep1.conflictingLoads 15 # Nu
system.cpu.memDep1.conflictingStores 4 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 21800 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 51 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 19296 # Number of instructions issued
system.cpu.iq.iqInstsIssued 19298 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 51 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 9080 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 4753 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedOperandsExamined 4750 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 17 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 26300 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.733688 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.450617 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::samples 26305 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.733625 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.450843 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 18970 72.13% 72.13% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 2362 8.98% 81.11% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 1626 6.18% 87.29% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 1294 4.92% 92.21% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 1061 4.03% 96.25% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 563 2.14% 98.39% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 18975 72.13% 72.13% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 2364 8.99% 81.12% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 1624 6.17% 87.30% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 1293 4.92% 92.21% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 1059 4.03% 96.24% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 566 2.15% 98.39% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 282 1.07% 99.46% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 87 0.33% 99.79% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 55 0.21% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 26300 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 26305 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 29 9.67% 9.67% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 9.67% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 9.67% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.67% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.67% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.67% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 9.67% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 9.67% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.67% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMisc 0 0.00% 9.67% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 9.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 9.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.67% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 191 63.67% 73.33% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 77 25.67% 99.00% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMemRead 0 0.00% 99.00% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMemWrite 3 1.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 29 9.60% 9.60% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 9.60% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 9.60% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.60% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.60% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.60% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 9.60% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 9.60% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.60% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMisc 0 0.00% 9.60% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 9.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 9.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.60% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 193 63.91% 73.51% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 77 25.50% 99.01% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMemRead 0 0.00% 99.01% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMemWrite 3 0.99% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 5884 66.04% 66.06% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 1 0.01% 66.07% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.07% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 66.09% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.09% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.09% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.09% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 66.09% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.09% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 66.09% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.09% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 5886 66.05% 66.07% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 1 0.01% 66.08% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.08% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 66.10% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.10% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.10% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.10% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 66.10% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.10% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 66.10% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.10% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 2014 22.60% 88.70% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 999 11.21% 99.91% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMemRead 1 0.01% 99.92% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMemWrite 7 0.08% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 8910 # Type of FU issued
system.cpu.iq.FU_type_0::total 8912 # Type of FU issued
system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued
system.cpu.iq.FU_type_1::IntAlu 6849 65.94% 65.96% # Type of FU issued
system.cpu.iq.FU_type_1::IntMult 1 0.01% 65.97% # Type of FU issued
@ -519,21 +519,21 @@ system.cpu.iq.FU_type_1::FloatMemWrite 7 0.07% 100.00% # Ty
system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_1::total 10386 # Type of FU issued
system.cpu.iq.FU_type::total 19296 0.00% 0.00% # Type of FU issued
system.cpu.iq.rate 0.361863 # Inst issue rate
system.cpu.iq.fu_busy_cnt::0 152 # FU busy when requested
system.cpu.iq.FU_type::total 19298 0.00% 0.00% # Type of FU issued
system.cpu.iq.rate 0.361901 # Inst issue rate
system.cpu.iq.fu_busy_cnt::0 154 # FU busy when requested
system.cpu.iq.fu_busy_cnt::1 148 # FU busy when requested
system.cpu.iq.fu_busy_cnt::total 300 # FU busy when requested
system.cpu.iq.fu_busy_rate::0 0.007877 # FU busy rate (busy events/executed inst)
system.cpu.iq.fu_busy_rate::1 0.007670 # FU busy rate (busy events/executed inst)
system.cpu.iq.fu_busy_rate::total 0.015547 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 65200 # Number of integer instruction queue reads
system.cpu.iq.fu_busy_cnt::total 302 # FU busy when requested
system.cpu.iq.fu_busy_rate::0 0.007980 # FU busy rate (busy events/executed inst)
system.cpu.iq.fu_busy_rate::1 0.007669 # FU busy rate (busy events/executed inst)
system.cpu.iq.fu_busy_rate::total 0.015649 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 65211 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 30942 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 17504 # Number of integer instruction queue wakeup accesses
system.cpu.iq.int_inst_queue_wakeup_accesses 17509 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 43 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 19569 # Number of integer alu accesses
system.cpu.iq.int_alu_accesses 19573 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 23 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 39 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
@ -570,65 +570,65 @@ system.cpu.iew.memOrderViolationEvents 32 # Nu
system.cpu.iew.predictedTakenIncorrect 134 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 638 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 772 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 18585 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts::0 1945 # Number of load instructions executed
system.cpu.iew.iewExecutedInsts 18590 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts::0 1946 # Number of load instructions executed
system.cpu.iew.iewExecLoadInsts::1 2264 # Number of load instructions executed
system.cpu.iew.iewExecLoadInsts::total 4209 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 711 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecLoadInsts::total 4210 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 708 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp::0 0 # number of swp insts executed
system.cpu.iew.exec_swp::1 0 # number of swp insts executed
system.cpu.iew.exec_swp::total 0 # number of swp insts executed
system.cpu.iew.exec_nop::0 63 # number of nop insts executed
system.cpu.iew.exec_nop::1 71 # number of nop insts executed
system.cpu.iew.exec_nop::total 134 # number of nop insts executed
system.cpu.iew.exec_refs::0 2942 # number of memory reference insts executed
system.cpu.iew.exec_refs::0 2943 # number of memory reference insts executed
system.cpu.iew.exec_refs::1 3338 # number of memory reference insts executed
system.cpu.iew.exec_refs::total 6280 # number of memory reference insts executed
system.cpu.iew.exec_refs::total 6281 # number of memory reference insts executed
system.cpu.iew.exec_branches::0 1393 # Number of branches executed
system.cpu.iew.exec_branches::1 1580 # Number of branches executed
system.cpu.iew.exec_branches::total 2973 # Number of branches executed
system.cpu.iew.exec_stores::0 997 # Number of stores executed
system.cpu.iew.exec_stores::1 1074 # Number of stores executed
system.cpu.iew.exec_stores::total 2071 # Number of stores executed
system.cpu.iew.exec_rate 0.348530 # Inst execution rate
system.cpu.iew.wb_sent::0 8281 # cumulative count of insts sent to commit
system.cpu.iew.exec_rate 0.348624 # Inst execution rate
system.cpu.iew.wb_sent::0 8287 # cumulative count of insts sent to commit
system.cpu.iew.wb_sent::1 9496 # cumulative count of insts sent to commit
system.cpu.iew.wb_sent::total 17777 # cumulative count of insts sent to commit
system.cpu.iew.wb_count::0 8197 # cumulative count of insts written-back
system.cpu.iew.wb_sent::total 17783 # cumulative count of insts sent to commit
system.cpu.iew.wb_count::0 8202 # cumulative count of insts written-back
system.cpu.iew.wb_count::1 9327 # cumulative count of insts written-back
system.cpu.iew.wb_count::total 17524 # cumulative count of insts written-back
system.cpu.iew.wb_producers::0 4340 # num instructions producing a value
system.cpu.iew.wb_producers::1 4919 # num instructions producing a value
system.cpu.iew.wb_producers::total 9259 # num instructions producing a value
system.cpu.iew.wb_consumers::0 5879 # num instructions consuming a value
system.cpu.iew.wb_consumers::1 6619 # num instructions consuming a value
system.cpu.iew.wb_consumers::total 12498 # num instructions consuming a value
system.cpu.iew.wb_rate::0 0.153721 # insts written-back per cycle
system.cpu.iew.wb_count::total 17529 # cumulative count of insts written-back
system.cpu.iew.wb_producers::0 4343 # num instructions producing a value
system.cpu.iew.wb_producers::1 4920 # num instructions producing a value
system.cpu.iew.wb_producers::total 9263 # num instructions producing a value
system.cpu.iew.wb_consumers::0 5887 # num instructions consuming a value
system.cpu.iew.wb_consumers::1 6620 # num instructions consuming a value
system.cpu.iew.wb_consumers::total 12507 # num instructions consuming a value
system.cpu.iew.wb_rate::0 0.153814 # insts written-back per cycle
system.cpu.iew.wb_rate::1 0.174912 # insts written-back per cycle
system.cpu.iew.wb_rate::total 0.328633 # insts written-back per cycle
system.cpu.iew.wb_fanout::0 0.738221 # average fanout of values written-back
system.cpu.iew.wb_fanout::1 0.743164 # average fanout of values written-back
system.cpu.iew.wb_fanout::total 0.740839 # average fanout of values written-back
system.cpu.iew.wb_rate::total 0.328726 # insts written-back per cycle
system.cpu.iew.wb_fanout::0 0.737727 # average fanout of values written-back
system.cpu.iew.wb_fanout::1 0.743202 # average fanout of values written-back
system.cpu.iew.wb_fanout::total 0.740625 # average fanout of values written-back
system.cpu.commit.commitSquashedInsts 9130 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 646 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 26282 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.487178 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.404713 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::samples 26287 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.487085 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.404867 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 21298 81.04% 81.04% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 2499 9.51% 90.54% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 21303 81.04% 81.04% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 2500 9.51% 90.55% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 926 3.52% 94.07% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 403 1.53% 95.60% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 402 1.53% 95.60% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 249 0.95% 96.55% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 154 0.59% 97.13% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 215 0.82% 97.95% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 154 0.59% 97.14% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 214 0.81% 97.95% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 116 0.44% 98.39% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 422 1.61% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 423 1.61% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 26282 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 26287 # Number of insts commited each cycle
system.cpu.commit.committedInsts::0 6402 # Number of instructions committed
system.cpu.commit.committedInsts::1 6402 # Number of instructions committed
system.cpu.commit.committedInsts::total 12804 # Number of instructions committed
@ -738,11 +738,11 @@ system.cpu.commit.op_class_1::IprAccess 0 0.00% 100.00% # Cl
system.cpu.commit.op_class_1::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_1::total 6402 # Class of committed instruction
system.cpu.commit.op_class::total 12804 0.00% 0.00% # Class of committed instruction
system.cpu.commit.bw_lim_events 422 # number cycles where commit BW limit reached
system.cpu.rob.rob_reads 113054 # The number of ROB reads
system.cpu.commit.bw_lim_events 423 # number cycles where commit BW limit reached
system.cpu.rob.rob_reads 113065 # The number of ROB reads
system.cpu.rob.rob_writes 45570 # The number of ROB writes
system.cpu.timesIdled 413 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 27024 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.idleCycles 27019 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts::0 6385 # Number of Instructions Simulated
system.cpu.committedInsts::1 6385 # Number of Instructions Simulated
system.cpu.committedInsts::total 12770 # Number of Instructions Simulated
@ -755,8 +755,8 @@ system.cpu.cpi_total 4.175724 # CP
system.cpu.ipc::0 0.119740 # IPC: Instructions Per Cycle
system.cpu.ipc::1 0.119740 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.239479 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 23475 # number of integer regfile reads
system.cpu.int_regfile_writes 13132 # number of integer regfile writes
system.cpu.int_regfile_reads 23483 # number of integer regfile reads
system.cpu.int_regfile_writes 13138 # number of integer regfile writes
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
system.cpu.fp_regfile_writes 4 # number of floating regfile writes
system.cpu.misc_regfile_reads 2 # number of misc regfile reads
@ -765,29 +765,29 @@ system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 26661500
system.cpu.dcache.tags.replacements::0 0 # number of replacements
system.cpu.dcache.tags.replacements::1 0 # number of replacements
system.cpu.dcache.tags.replacements::total 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 216.020971 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 4236 # Total number of references to valid blocks.
system.cpu.dcache.tags.tagsinuse 216.020896 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 4237 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 342 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 12.385965 # Average number of references to valid blocks.
system.cpu.dcache.tags.avg_refs 12.388889 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 216.020971 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_blocks::cpu.data 216.020896 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.052739 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.052739 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 342 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 270 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.083496 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 10868 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 10868 # Number of data accesses
system.cpu.dcache.tags.tag_accesses 10870 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 10870 # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 3224 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 3224 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::cpu.data 3225 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 3225 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 1012 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 1012 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 4236 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 4236 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 4236 # number of overall hits
system.cpu.dcache.overall_hits::total 4236 # number of overall hits
system.cpu.dcache.demand_hits::cpu.data 4237 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 4237 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 4237 # number of overall hits
system.cpu.dcache.overall_hits::total 4237 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 309 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 309 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 718 # number of WriteReq misses
@ -804,22 +804,22 @@ system.cpu.dcache.demand_miss_latency::cpu.data 75346451
system.cpu.dcache.demand_miss_latency::total 75346451 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 75346451 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 75346451 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 3533 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 3533 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::cpu.data 3534 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 3534 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 1730 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 5263 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 5263 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 5263 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 5263 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.087461 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.087461 # miss rate for ReadReq accesses
system.cpu.dcache.demand_accesses::cpu.data 5264 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 5264 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 5264 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 5264 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.087436 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.087436 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.195136 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.195136 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.195136 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.195136 # miss rate for overall accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.195099 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.195099 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.195099 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.195099 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77721.682848 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 77721.682848 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 71490.878830 # average WriteReq miss latency
@ -858,14 +858,14 @@ system.cpu.dcache.demand_mshr_miss_latency::cpu.data 30306487
system.cpu.dcache.demand_mshr_miss_latency::total 30306487 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 30306487 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 30306487 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.056326 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.056326 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.056310 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.056310 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.065172 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.065172 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.065172 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.065172 # mshr miss rate for overall accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.065160 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.065160 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.065160 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.065160 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 89683.417085 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 89683.417085 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 86524.215278 # average WriteReq mshr miss latency
@ -878,12 +878,12 @@ system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 26661500
system.cpu.icache.tags.replacements::0 7 # number of replacements
system.cpu.icache.tags.replacements::1 0 # number of replacements
system.cpu.icache.tags.replacements::total 7 # number of replacements
system.cpu.icache.tags.tagsinuse 318.055053 # Cycle average of tags in use
system.cpu.icache.tags.tagsinuse 318.054191 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 2937 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 628 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 4.676752 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 318.055053 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_blocks::cpu.inst 318.054191 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.155300 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.155300 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 621 # Occupied blocks per task id
@ -905,12 +905,12 @@ system.cpu.icache.demand_misses::cpu.inst 895 # n
system.cpu.icache.demand_misses::total 895 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 895 # number of overall misses
system.cpu.icache.overall_misses::total 895 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 72806995 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 72806995 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 72806995 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 72806995 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 72806995 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 72806995 # number of overall miss cycles
system.cpu.icache.ReadReq_miss_latency::cpu.inst 72804995 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 72804995 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 72804995 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 72804995 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 72804995 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 72804995 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 3832 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 3832 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 3832 # number of demand (read+write) accesses
@ -923,12 +923,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.233559
system.cpu.icache.demand_miss_rate::total 0.233559 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.233559 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.233559 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 81348.597765 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 81348.597765 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 81348.597765 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 81348.597765 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 81348.597765 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 81348.597765 # average overall miss latency
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 81346.363128 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 81346.363128 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 81346.363128 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 81346.363128 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 81346.363128 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 81346.363128 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 3504 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 58 # number of cycles access was blocked
@ -949,35 +949,35 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 628
system.cpu.icache.demand_mshr_misses::total 628 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 628 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 628 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 54757996 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 54757996 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 54757996 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 54757996 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 54757996 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 54757996 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 54756996 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 54756996 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 54756996 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 54756996 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 54756996 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 54756996 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.163883 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.163883 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.163883 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.163883 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.163883 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.163883 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 87194.261146 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 87194.261146 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 87194.261146 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 87194.261146 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 87194.261146 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 87194.261146 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 87192.668790 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 87192.668790 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 87192.668790 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 87192.668790 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 87192.668790 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 87192.668790 # average overall mshr miss latency
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements::0 0 # number of replacements
system.cpu.l2cache.tags.replacements::1 0 # number of replacements
system.cpu.l2cache.tags.replacements::total 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 534.674828 # Cycle average of tags in use
system.cpu.l2cache.tags.tagsinuse 534.673891 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 10 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 967 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.010341 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst 318.519168 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 216.155660 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 318.518306 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 216.155585 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009720 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.006597 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.016317 # Average percentage of cache occupancy
@ -1010,16 +1010,16 @@ system.cpu.l2cache.overall_misses::cpu.data 343 #
system.cpu.l2cache.overall_misses::total 968 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12308500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 12308500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 53778000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 53778000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 53777000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 53777000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 17466000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 17466000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 53778000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 53777000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 29774500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 83552500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 53778000 # number of overall miss cycles
system.cpu.l2cache.demand_miss_latency::total 83551500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 53777000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 29774500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 83552500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 83551500 # number of overall miss cycles
system.cpu.l2cache.WritebackClean_accesses::writebacks 7 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 7 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 145 # number of ReadExReq accesses(hits+misses)
@ -1048,16 +1048,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 1
system.cpu.l2cache.overall_miss_rate::total 0.996910 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 84886.206897 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 84886.206897 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 86044.800000 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 86044.800000 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 86043.200000 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 86043.200000 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 88212.121212 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 88212.121212 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 86044.800000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 86043.200000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86806.122449 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 86314.566116 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 86044.800000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 86313.533058 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 86043.200000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86806.122449 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 86314.566116 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 86313.533058 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -1078,16 +1078,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data 343
system.cpu.l2cache.overall_mshr_misses::total 968 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10858500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10858500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 47528000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 47528000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 47527000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 47527000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15496000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15496000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 47528000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 47527000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26354500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 73882500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 47528000 # number of overall MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 73881500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 47527000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26354500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 73882500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 73881500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.995223 # mshr miss rate for ReadCleanReq accesses
@ -1102,16 +1102,16 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1
system.cpu.l2cache.overall_mshr_miss_rate::total 0.996910 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 74886.206897 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 74886.206897 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 76044.800000 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 76044.800000 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 76043.200000 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 76043.200000 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78262.626263 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78262.626263 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76044.800000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76043.200000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76835.276968 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76324.896694 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76044.800000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76323.863636 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76043.200000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76835.276968 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76324.896694 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76323.863636 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 978 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 9 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.

902
tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/config.ini Normal file
View file

@ -0,0 +1,902 @@
[root]
type=Root
children=system
eventq_index=0
full_system=false
sim_quantum=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.clk_domain]
type=SrcClockDomain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.cpu]
type=MinorCPU
children=branchPred dcache dtb executeFuncUnits icache interrupts isa itb l2cache toL2Bus tracer workload
branchPred=system.cpu.branchPred
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
decodeCycleInput=true
decodeInputBufferSize=3
decodeInputWidth=2
decodeToExecuteForwardDelay=1
default_p_state=UNDEFINED
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
enableIdling=true
eventq_index=0
executeAllowEarlyMemoryIssue=true
executeBranchDelay=1
executeCommitLimit=2
executeCycleInput=true
executeFuncUnits=system.cpu.executeFuncUnits
executeInputBufferSize=7
executeInputWidth=2
executeIssueLimit=2
executeLSQMaxStoreBufferStoresPerCycle=2
executeLSQRequestsQueueSize=1
executeLSQStoreBufferSize=5
executeLSQTransfersQueueSize=2
executeMaxAccessesInMemory=2
executeMemoryCommitLimit=1
executeMemoryIssueLimit=1
executeMemoryWidth=0
executeSetTraceTimeOnCommit=true
executeSetTraceTimeOnIssue=false
fetch1FetchLimit=1
fetch1LineSnapWidth=0
fetch1LineWidth=0
fetch1ToFetch2BackwardDelay=1
fetch1ToFetch2ForwardDelay=1
fetch2CycleInput=true
fetch2InputBufferSize=2
fetch2ToDecodeForwardDelay=1
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
profile=0
progress_interval=0
simpoint_start_insts=
socket_id=0
switched_out=false
system=system
threadPolicy=RoundRobin
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
type=TournamentBP
BTBEntries=4096
BTBTagSize=16
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
indirectHashGHR=true
indirectHashTargets=true
indirectPathLength=3
indirectSets=256
indirectTagSize=16
indirectWays=2
instShiftAmt=2
localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
useIndirect=true
[system.cpu.dcache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
is_read_only=false
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=262144
system=system
tag_latency=2
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dcache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=262144
tag_latency=2
[system.cpu.dtb]
type=RiscvTLB
eventq_index=0
size=64
[system.cpu.executeFuncUnits]
type=MinorFUPool
children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6
eventq_index=0
funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6
[system.cpu.executeFuncUnits.funcUnits0]
type=MinorFU
children=opClasses timings
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses
opLat=3
timings=system.cpu.executeFuncUnits.funcUnits0.timings
[system.cpu.executeFuncUnits.funcUnits0.opClasses]
type=MinorOpClassSet
children=opClasses
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses
[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses]
type=MinorOpClass
eventq_index=0
opClass=IntAlu
[system.cpu.executeFuncUnits.funcUnits0.timings]
type=MinorFUTiming
children=opClasses
description=Int
eventq_index=0
extraAssumedLat=0
extraCommitLat=0
extraCommitLatExpr=Null
mask=0
match=0
opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses
srcRegsRelativeLats=2
suppress=false
[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses]
type=MinorOpClassSet
eventq_index=0
opClasses=
[system.cpu.executeFuncUnits.funcUnits1]
type=MinorFU
children=opClasses timings
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses
opLat=3
timings=system.cpu.executeFuncUnits.funcUnits1.timings
[system.cpu.executeFuncUnits.funcUnits1.opClasses]
type=MinorOpClassSet
children=opClasses
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses
[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses]
type=MinorOpClass
eventq_index=0
opClass=IntAlu
[system.cpu.executeFuncUnits.funcUnits1.timings]
type=MinorFUTiming
children=opClasses
description=Int
eventq_index=0
extraAssumedLat=0
extraCommitLat=0
extraCommitLatExpr=Null
mask=0
match=0
opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses
srcRegsRelativeLats=2
suppress=false
[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses]
type=MinorOpClassSet
eventq_index=0
opClasses=
[system.cpu.executeFuncUnits.funcUnits2]
type=MinorFU
children=opClasses timings
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses
opLat=3
timings=system.cpu.executeFuncUnits.funcUnits2.timings
[system.cpu.executeFuncUnits.funcUnits2.opClasses]
type=MinorOpClassSet
children=opClasses
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses
[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses]
type=MinorOpClass
eventq_index=0
opClass=IntMult
[system.cpu.executeFuncUnits.funcUnits2.timings]
type=MinorFUTiming
children=opClasses
description=Mul
eventq_index=0
extraAssumedLat=0
extraCommitLat=0
extraCommitLatExpr=Null
mask=0
match=0
opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses
srcRegsRelativeLats=0
suppress=false
[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses]
type=MinorOpClassSet
eventq_index=0
opClasses=
[system.cpu.executeFuncUnits.funcUnits3]
type=MinorFU
children=opClasses
cantForwardFromFUIndices=
eventq_index=0
issueLat=9
opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses
opLat=9
timings=
[system.cpu.executeFuncUnits.funcUnits3.opClasses]
type=MinorOpClassSet
children=opClasses
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses
[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses]
type=MinorOpClass
eventq_index=0
opClass=IntDiv
[system.cpu.executeFuncUnits.funcUnits4]
type=MinorFU
children=opClasses timings
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses
opLat=6
timings=system.cpu.executeFuncUnits.funcUnits4.timings
[system.cpu.executeFuncUnits.funcUnits4.opClasses]
type=MinorOpClassSet
children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 opClasses26 opClasses27
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses26 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses27
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00]
type=MinorOpClass
eventq_index=0
opClass=FloatAdd
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01]
type=MinorOpClass
eventq_index=0
opClass=FloatCmp
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02]
type=MinorOpClass
eventq_index=0
opClass=FloatCvt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03]
type=MinorOpClass
eventq_index=0
opClass=FloatMisc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04]
type=MinorOpClass
eventq_index=0
opClass=FloatMult
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05]
type=MinorOpClass
eventq_index=0
opClass=FloatMultAcc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06]
type=MinorOpClass
eventq_index=0
opClass=FloatDiv
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07]
type=MinorOpClass
eventq_index=0
opClass=FloatSqrt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08]
type=MinorOpClass
eventq_index=0
opClass=SimdAdd
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09]
type=MinorOpClass
eventq_index=0
opClass=SimdAddAcc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10]
type=MinorOpClass
eventq_index=0
opClass=SimdAlu
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11]
type=MinorOpClass
eventq_index=0
opClass=SimdCmp
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12]
type=MinorOpClass
eventq_index=0
opClass=SimdCvt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13]
type=MinorOpClass
eventq_index=0
opClass=SimdMisc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14]
type=MinorOpClass
eventq_index=0
opClass=SimdMult
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15]
type=MinorOpClass
eventq_index=0
opClass=SimdMultAcc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16]
type=MinorOpClass
eventq_index=0
opClass=SimdShift
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17]
type=MinorOpClass
eventq_index=0
opClass=SimdShiftAcc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18]
type=MinorOpClass
eventq_index=0
opClass=SimdSqrt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatAdd
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatAlu
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatCmp
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatCvt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatDiv
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatMisc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatMult
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses26]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatMultAcc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses27]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatSqrt
[system.cpu.executeFuncUnits.funcUnits4.timings]
type=MinorFUTiming
children=opClasses
description=FloatSimd
eventq_index=0
extraAssumedLat=0
extraCommitLat=0
extraCommitLatExpr=Null
mask=0
match=0
opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses
srcRegsRelativeLats=2
suppress=false
[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses]
type=MinorOpClassSet
eventq_index=0
opClasses=
[system.cpu.executeFuncUnits.funcUnits5]
type=MinorFU
children=opClasses timings
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses
opLat=1
timings=system.cpu.executeFuncUnits.funcUnits5.timings
[system.cpu.executeFuncUnits.funcUnits5.opClasses]
type=MinorOpClassSet
children=opClasses0 opClasses1 opClasses2 opClasses3
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses2 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses3
[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0]
type=MinorOpClass
eventq_index=0
opClass=MemRead
[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1]
type=MinorOpClass
eventq_index=0
opClass=MemWrite
[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses2]
type=MinorOpClass
eventq_index=0
opClass=FloatMemRead
[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses3]
type=MinorOpClass
eventq_index=0
opClass=FloatMemWrite
[system.cpu.executeFuncUnits.funcUnits5.timings]
type=MinorFUTiming
children=opClasses
description=Mem
eventq_index=0
extraAssumedLat=2
extraCommitLat=0
extraCommitLatExpr=Null
mask=0
match=0
opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses
srcRegsRelativeLats=1
suppress=false
[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses]
type=MinorOpClassSet
eventq_index=0
opClasses=
[system.cpu.executeFuncUnits.funcUnits6]
type=MinorFU
children=opClasses
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses
opLat=1
timings=
[system.cpu.executeFuncUnits.funcUnits6.opClasses]
type=MinorOpClassSet
children=opClasses0 opClasses1
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1
[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0]
type=MinorOpClass
eventq_index=0
opClass=IprAccess
[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1]
type=MinorOpClass
eventq_index=0
opClass=InstPrefetch
[system.cpu.icache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
is_read_only=true
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=131072
system=system
tag_latency=2
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=true
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.icache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=131072
tag_latency=2
[system.cpu.interrupts]
type=RiscvInterrupts
eventq_index=0
[system.cpu.isa]
type=RiscvISA
eventq_index=0
[system.cpu.itb]
type=RiscvTLB
eventq_index=0
size=64
[system.cpu.l2cache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=20
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
is_read_only=false
max_miss_count=0
mshrs=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=20
sequential_access=false
size=2097152
system=system
tag_latency=20
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.l2cache.tags]
type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=20
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=2097152
tag_latency=20
[system.cpu.toL2Bus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=0
frontend_latency=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=false
power_model=Null
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.toL2Bus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=0
max_capacity=8388608
system=system
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=LiveProcess
cmd=insttest
cwd=
drivers=
egid=100
env=
errout=cerr
euid=100
eventq_index=0
executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64a/insttest
gid=100
input=cin
kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.dvfs_handler]
type=DVFSHandler
domains=
enable=false
eventq_index=0
sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=4
frontend_latency=3
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem]
type=DRAMCtrl
IDD0=0.055000
IDD02=0.000000
IDD2N=0.032000
IDD2N2=0.000000
IDD2P0=0.000000
IDD2P02=0.000000
IDD2P1=0.032000
IDD2P12=0.000000
IDD3N=0.038000
IDD3N2=0.000000
IDD3P0=0.000000
IDD3P02=0.000000
IDD3P1=0.038000
IDD3P12=0.000000
IDD4R=0.157000
IDD4R2=0.000000
IDD4W=0.125000
IDD4W2=0.000000
IDD5=0.235000
IDD52=0.000000
IDD6=0.020000
IDD62=0.000000
VDD=1.500000
VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
clk_domain=system.clk_domain
conf_table_reported=true
default_p_state=UNDEFINED
device_bus_width=8
device_rowbuffer_size=1024
device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
in_addr_map=true
kvm_map=true
max_accesses_per_row=16
mem_sched_policy=frfcfs
min_writes_per_switch=16
null=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
page_policy=open_adaptive
power_model=Null
range=0:134217727:0:0:0:0
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
tCCD_L=0
tCK=1250
tCL=13750
tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
tXP=6000
tXPDLL=0
tXS=270000
tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
port=system.membus.master[0]
[system.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.000000

1211
tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/config.json Normal file
View file

File diff suppressed because it is too large Load diff

4
tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/simerr Executable file
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@ -0,0 +1,4 @@
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Unknown operating system; assuming Linux.
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick

49
tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/simout Executable file
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@ -0,0 +1,49 @@
Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/minor-timing/simout
Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/minor-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Nov 30 2016 14:33:35
gem5 started Nov 30 2016 16:18:29
gem5 executing on zizzer, pid 34061
command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/minor-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64a/minor-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
lr.w/sc.w: PASS
sc.w, no preceding lr.d: PASS
amoswap.w: PASS
amoswap.w, sign extend: PASS
amoswap.w, truncate: PASS
amoadd.w: PASS
amoadd.w, truncate/overflow: PASS
amoadd.w, sign extend: PASS
amoxor.w, truncate: PASS
amoxor.w, sign extend: PASS
amoand.w, truncate: PASS
amoand.w, sign extend: PASS
amoor.w, truncate: PASS
amoor.w, sign extend: PASS
amomin.w, truncate: PASS
amomin.w, sign extend: PASS
amomax.w, truncate: PASS
amomax.w, sign extend: PASS
amominu.w, truncate: PASS
amominu.w, sign extend: PASS
amomaxu.w, truncate: PASS
amomaxu.w, sign extend: PASS
lr.d/sc.d: PASS
sc.d, no preceding lr.d: PASS
amoswap.d: PASS
amoadd.d: PASS
amoadd.d, overflow: PASS
amoxor.d (1): PASS
amoxor.d (0): PASS
amoand.d: PASS
amoor.d: PASS
amomin.d: PASS
amomax.d: PASS
amominu.d: PASS
amomaxu.d: PASS
Exiting @ tick 167328500 because target called exit()

769
tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/stats.txt Normal file
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@ -0,0 +1,769 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000167 # Number of seconds simulated
sim_ticks 167328500 # Number of ticks simulated
final_tick 167328500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 54302 # Simulator instruction rate (inst/s)
host_op_rate 54316 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 79708249 # Simulator tick rate (ticks/s)
host_mem_usage 244184 # Number of bytes of host memory used
host_seconds 2.10 # Real time elapsed on the host
sim_insts 113991 # Number of instructions simulated
sim_ops 114022 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 52672 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 17088 # Number of bytes read from this memory
system.physmem.bytes_read::total 69760 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 52672 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 52672 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 823 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 267 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1090 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 314782001 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 102122472 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 416904472 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 314782001 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 314782001 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 314782001 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 102122472 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 416904472 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 1090 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 1090 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 69760 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 69760 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 110 # Per bank write bursts
system.physmem.perBankRdBursts::1 4 # Per bank write bursts
system.physmem.perBankRdBursts::2 9 # Per bank write bursts
system.physmem.perBankRdBursts::3 124 # Per bank write bursts
system.physmem.perBankRdBursts::4 62 # Per bank write bursts
system.physmem.perBankRdBursts::5 92 # Per bank write bursts
system.physmem.perBankRdBursts::6 88 # Per bank write bursts
system.physmem.perBankRdBursts::7 18 # Per bank write bursts
system.physmem.perBankRdBursts::8 55 # Per bank write bursts
system.physmem.perBankRdBursts::9 86 # Per bank write bursts
system.physmem.perBankRdBursts::10 90 # Per bank write bursts
system.physmem.perBankRdBursts::11 38 # Per bank write bursts
system.physmem.perBankRdBursts::12 113 # Per bank write bursts
system.physmem.perBankRdBursts::13 94 # Per bank write bursts
system.physmem.perBankRdBursts::14 101 # Per bank write bursts
system.physmem.perBankRdBursts::15 6 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
system.physmem.perBankWrBursts::4 0 # Per bank write bursts
system.physmem.perBankWrBursts::5 0 # Per bank write bursts
system.physmem.perBankWrBursts::6 0 # Per bank write bursts
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
system.physmem.perBankWrBursts::10 0 # Per bank write bursts
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 166995000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 1090 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 1032 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 53 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 5 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 207 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 327.729469 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 215.587083 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 297.390992 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 56 27.05% 27.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 46 22.22% 49.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 39 18.84% 68.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 16 7.73% 75.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 14 6.76% 82.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 7 3.38% 85.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 10 4.83% 90.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1 0.48% 91.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 18 8.70% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 207 # Bytes accessed per row activation
system.physmem.totQLat 15434500 # Total ticks spent queuing
system.physmem.totMemAccLat 35872000 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 5450000 # Total ticks spent in databus transfers
system.physmem.avgQLat 14160.09 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 32910.09 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 416.90 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 416.90 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 3.26 # Data bus utilization in percentage
system.physmem.busUtilRead 3.26 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 874 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 80.18 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 153206.42 # Average gap between requests
system.physmem.pageHitRate 80.18 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 763980 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 387090 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 3619980 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 13522080.000000 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 9305250 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 493440 # Energy for precharge background per rank (pJ)
system.physmem_0.actPowerDownEnergy 55143510 # Energy for active power-down per rank (pJ)
system.physmem_0.prePowerDownEnergy 7150560 # Energy for precharge power-down per rank (pJ)
system.physmem_0.selfRefreshEnergy 2565480 # Energy for self refresh per rank (pJ)
system.physmem_0.totalEnergy 92951370 # Total energy per rank (pJ)
system.physmem_0.averagePower 555.501490 # Core power per rank (mW)
system.physmem_0.totalIdleTime 145131750 # Total Idle time Per DRAM Rank
system.physmem_0.memoryStateTime::IDLE 654000 # Time in different power states
system.physmem_0.memoryStateTime::REF 5732000 # Time in different power states
system.physmem_0.memoryStateTime::SREF 6087000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 18616750 # Time in different power states
system.physmem_0.memoryStateTime::ACT 15316500 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 120922250 # Time in different power states
system.physmem_1.actEnergy 778260 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 398475 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 4162620 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 12907440.000000 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 9798300 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 485280 # Energy for precharge background per rank (pJ)
system.physmem_1.actPowerDownEnergy 44769510 # Energy for active power-down per rank (pJ)
system.physmem_1.prePowerDownEnergy 12438720 # Energy for precharge power-down per rank (pJ)
system.physmem_1.selfRefreshEnergy 4465980 # Energy for self refresh per rank (pJ)
system.physmem_1.totalEnergy 90204585 # Total energy per rank (pJ)
system.physmem_1.averagePower 539.085991 # Core power per rank (mW)
system.physmem_1.totalIdleTime 144266000 # Total Idle time Per DRAM Rank
system.physmem_1.memoryStateTime::IDLE 729500 # Time in different power states
system.physmem_1.memoryStateTime::REF 5472000 # Time in different power states
system.physmem_1.memoryStateTime::SREF 14006250 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 32390000 # Time in different power states
system.physmem_1.memoryStateTime::ACT 16564250 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 98166500 # Time in different power states
system.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 31621 # Number of BP lookups
system.cpu.branchPred.condPredicted 20020 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 2186 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 28229 # Number of BTB lookups
system.cpu.branchPred.BTBHits 15507 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 54.932870 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups 5663 # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits 3671 # Number of indirect target hits.
system.cpu.branchPred.indirectMisses 1992 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 1067 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 43 # Number of system calls
system.cpu.pwrStateResidencyTicks::ON 167328500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 334657 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 113991 # Number of instructions committed
system.cpu.committedOps 114022 # Number of ops (including micro ops) committed
system.cpu.discardedOps 5904 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 2.935819 # CPI: cycles per instruction
system.cpu.ipc 0.340620 # IPC: instructions per cycle
system.cpu.op_class_0::No_OpClass 43 0.04% 0.04% # Class of committed instruction
system.cpu.op_class_0::IntAlu 70180 61.55% 61.59% # Class of committed instruction
system.cpu.op_class_0::IntMult 105 0.09% 61.68% # Class of committed instruction
system.cpu.op_class_0::IntDiv 0 0.00% 61.68% # Class of committed instruction
system.cpu.op_class_0::FloatAdd 0 0.00% 61.68% # Class of committed instruction
system.cpu.op_class_0::FloatCmp 0 0.00% 61.68% # Class of committed instruction
system.cpu.op_class_0::FloatCvt 0 0.00% 61.68% # Class of committed instruction
system.cpu.op_class_0::FloatMult 0 0.00% 61.68% # Class of committed instruction
system.cpu.op_class_0::FloatMultAcc 0 0.00% 61.68% # Class of committed instruction
system.cpu.op_class_0::FloatDiv 0 0.00% 61.68% # Class of committed instruction
system.cpu.op_class_0::FloatMisc 0 0.00% 61.68% # Class of committed instruction
system.cpu.op_class_0::FloatSqrt 0 0.00% 61.68% # Class of committed instruction
system.cpu.op_class_0::SimdAdd 0 0.00% 61.68% # Class of committed instruction
system.cpu.op_class_0::SimdAddAcc 0 0.00% 61.68% # Class of committed instruction
system.cpu.op_class_0::SimdAlu 0 0.00% 61.68% # Class of committed instruction
system.cpu.op_class_0::SimdCmp 0 0.00% 61.68% # Class of committed instruction
system.cpu.op_class_0::SimdCvt 0 0.00% 61.68% # Class of committed instruction
system.cpu.op_class_0::SimdMisc 0 0.00% 61.68% # Class of committed instruction
system.cpu.op_class_0::SimdMult 0 0.00% 61.68% # Class of committed instruction
system.cpu.op_class_0::SimdMultAcc 0 0.00% 61.68% # Class of committed instruction
system.cpu.op_class_0::SimdShift 0 0.00% 61.68% # Class of committed instruction
system.cpu.op_class_0::SimdShiftAcc 0 0.00% 61.68% # Class of committed instruction
system.cpu.op_class_0::SimdSqrt 0 0.00% 61.68% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAdd 0 0.00% 61.68% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAlu 0 0.00% 61.68% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCmp 0 0.00% 61.68% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCvt 0 0.00% 61.68% # Class of committed instruction
system.cpu.op_class_0::SimdFloatDiv 0 0.00% 61.68% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMisc 0 0.00% 61.68% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMult 0 0.00% 61.68% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 61.68% # Class of committed instruction
system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 61.68% # Class of committed instruction
system.cpu.op_class_0::MemRead 23779 20.85% 82.53% # Class of committed instruction
system.cpu.op_class_0::MemWrite 19915 17.47% 100.00% # Class of committed instruction
system.cpu.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::total 114022 # Class of committed instruction
system.cpu.tickCycles 171660 # Number of cycles that the object actually ticked
system.cpu.idleCycles 162997 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 215.204481 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 44066 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 268 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 164.425373 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 215.204481 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.052540 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.052540 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 268 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 61 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 203 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.065430 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 89318 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 89318 # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 24534 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 24534 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 19526 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 19526 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 2 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 2 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 4 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 4 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 44060 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 44060 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 44060 # number of overall hits
system.cpu.dcache.overall_hits::total 44060 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 75 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 75 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 384 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 384 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 459 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 459 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 459 # number of overall misses
system.cpu.dcache.overall_misses::total 459 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 8632000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 8632000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 30737000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 30737000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 39369000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 39369000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 39369000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 39369000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 24609 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 24609 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 19910 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 19910 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 2 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 2 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 4 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 4 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 44519 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 44519 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 44519 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 44519 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003048 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.003048 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.019287 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.019287 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.010310 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.010310 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.010310 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.010310 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 115093.333333 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 115093.333333 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80044.270833 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 80044.270833 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 85771.241830 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 85771.241830 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 85771.241830 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 85771.241830 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 185 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 185 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 191 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 191 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 191 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 191 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 69 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 69 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 199 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 199 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 268 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 268 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 268 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 268 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7963000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 7963000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 15953500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 15953500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23916500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 23916500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23916500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 23916500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002804 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002804 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009995 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009995 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006020 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.006020 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006020 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.006020 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 115405.797101 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 115405.797101 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80168.341709 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80168.341709 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 89240.671642 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 89240.671642 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 89240.671642 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 89240.671642 # average overall mshr miss latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 18 # number of replacements
system.cpu.icache.tags.tagsinuse 401.761519 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 49677 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 823 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 60.360875 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 401.761519 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.196173 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.196173 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 805 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 518 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 240 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.393066 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 101823 # Number of tag accesses
system.cpu.icache.tags.data_accesses 101823 # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 49677 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 49677 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 49677 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 49677 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 49677 # number of overall hits
system.cpu.icache.overall_hits::total 49677 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 823 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 823 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 823 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 823 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 823 # number of overall misses
system.cpu.icache.overall_misses::total 823 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 69966000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 69966000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 69966000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 69966000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 69966000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 69966000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 50500 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 50500 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 50500 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 50500 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 50500 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 50500 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016297 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.016297 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.016297 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.016297 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.016297 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.016297 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 85013.365735 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 85013.365735 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 85013.365735 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 85013.365735 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 85013.365735 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 85013.365735 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks 18 # number of writebacks
system.cpu.icache.writebacks::total 18 # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 823 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 823 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 823 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 823 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 823 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 823 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 69143000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 69143000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 69143000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 69143000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 69143000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 69143000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016297 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016297 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016297 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.016297 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016297 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.016297 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 84013.365735 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 84013.365735 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84013.365735 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 84013.365735 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84013.365735 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 84013.365735 # average overall mshr miss latency
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 622.728504 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 19 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 1090 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.017431 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst 407.968080 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 214.760424 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.012450 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.006554 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.019004 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 1090 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 585 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 454 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.033264 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 9962 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 9962 # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackClean_hits::writebacks 18 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 18 # number of WritebackClean hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 1 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits
system.cpu.l2cache.overall_hits::total 1 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 199 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 199 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 823 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 823 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 68 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 68 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 823 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 267 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 1090 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 823 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 267 # number of overall misses
system.cpu.l2cache.overall_misses::total 1090 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 15654000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 15654000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 67908500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 67908500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7847000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 7847000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 67908500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 23501000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 91409500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 67908500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 23501000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 91409500 # number of overall miss cycles
system.cpu.l2cache.WritebackClean_accesses::writebacks 18 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 18 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 199 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 199 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 823 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 823 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 69 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 69 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 823 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 268 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 1091 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 823 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 268 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 1091 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.985507 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.985507 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.996269 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.999083 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.996269 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.999083 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78663.316583 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78663.316583 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82513.365735 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82513.365735 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 115397.058824 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 115397.058824 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82513.365735 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88018.726592 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 83861.926606 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82513.365735 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88018.726592 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 83861.926606 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 199 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 199 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 823 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 823 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 68 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 68 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 823 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 267 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 1090 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 823 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 267 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 1090 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13664000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13664000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 59678500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 59678500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7167000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7167000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 59678500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20831000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 80509500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 59678500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20831000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 80509500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.985507 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.985507 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.996269 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.999083 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.996269 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.999083 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68663.316583 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68663.316583 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72513.365735 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72513.365735 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 105397.058824 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 105397.058824 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72513.365735 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78018.726592 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73861.926606 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72513.365735 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78018.726592 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73861.926606 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 1109 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 19 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 892 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 18 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 199 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 199 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 823 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 69 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1664 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 536 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 2200 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 53824 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 17152 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 70976 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples 1091 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.000917 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.030275 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 1090 99.91% 99.91% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 1 0.09% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 1091 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 572500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 1234500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.7 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 402000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
system.membus.snoop_filter.tot_requests 1090 # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 891 # Transaction distribution
system.membus.trans_dist::ReadExReq 199 # Transaction distribution
system.membus.trans_dist::ReadExResp 199 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 891 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2180 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 2180 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 69760 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 69760 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples 1090 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 1090 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 1090 # Request fanout histogram
system.membus.reqLayer0.occupancy 1226500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.7 # Layer utilization (%)
system.membus.respLayer1.occupancy 5789000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 3.5 # Layer utilization (%)
---------- End Simulation Statistics ----------

211
tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/config.ini Normal file
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@ -0,0 +1,211 @@
[root]
type=Root
children=system
eventq_index=0
full_system=false
sim_quantum=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mem_mode=atomic
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.clk_domain]
type=SrcClockDomain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.cpu]
type=AtomicSimpleCPU
children=dtb interrupts isa itb tracer workload
branchPred=Null
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
default_p_state=UNDEFINED
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
eventq_index=0
fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
profile=0
progress_interval=0
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
socket_id=0
switched_out=false
system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
dcache_port=system.membus.slave[2]
icache_port=system.membus.slave[1]
[system.cpu.dtb]
type=RiscvTLB
eventq_index=0
size=64
[system.cpu.interrupts]
type=RiscvInterrupts
eventq_index=0
[system.cpu.isa]
type=RiscvISA
eventq_index=0
[system.cpu.itb]
type=RiscvTLB
eventq_index=0
size=64
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=LiveProcess
cmd=insttest
cwd=
drivers=
egid=100
env=
errout=cerr
euid=100
eventq_index=0
executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64a/insttest
gid=100
input=cin
kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.dvfs_handler]
type=DVFSHandler
domains=
enable=false
eventq_index=0
sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=4
frontend_latency=3
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
width=16
master=system.physmem.port
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
clk_domain=system.clk_domain
conf_table_reported=true
default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
kvm_map=true
latency=30000
latency_var=0
null=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
range=0:134217727:0:0:0:0
port=system.membus.master[0]
[system.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.000000

289
tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/config.json Normal file
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@ -0,0 +1,289 @@
{
"name": null,
"sim_quantum": 0,
"system": {
"kernel": "",
"mmap_using_noreserve": false,
"kernel_addr_check": true,
"membus": {
"point_of_coherency": true,
"system": "system",
"response_latency": 2,
"cxx_class": "CoherentXBar",
"forward_latency": 4,
"clk_domain": "system.clk_domain",
"width": 16,
"eventq_index": 0,
"default_p_state": "UNDEFINED",
"p_state_clk_gate_max": 1000000000000,
"master": {
"peer": [
"system.physmem.port"
],
"role": "MASTER"
},
"type": "CoherentXBar",
"frontend_latency": 3,
"slave": {
"peer": [
"system.system_port",
"system.cpu.icache_port",
"system.cpu.dcache_port"
],
"role": "SLAVE"
},
"p_state_clk_gate_min": 1000,
"snoop_filter": {
"name": "snoop_filter",
"system": "system",
"max_capacity": 8388608,
"eventq_index": 0,
"cxx_class": "SnoopFilter",
"path": "system.membus.snoop_filter",
"type": "SnoopFilter",
"lookup_latency": 1
},
"power_model": null,
"path": "system.membus",
"snoop_response_latency": 4,
"name": "membus",
"p_state_clk_gate_bins": 20,
"use_default_range": false
},
"symbolfile": "",
"readfile": "",
"thermal_model": null,
"cxx_class": "System",
"work_begin_cpu_id_exit": -1,
"load_offset": 0,
"work_begin_exit_count": 0,
"p_state_clk_gate_min": 1000,
"memories": [
"system.physmem"
],
"work_begin_ckpt_count": 0,
"clk_domain": {
"name": "clk_domain",
"clock": [
1000
],
"init_perf_level": 0,
"voltage_domain": "system.voltage_domain",
"eventq_index": 0,
"cxx_class": "SrcClockDomain",
"path": "system.clk_domain",
"type": "SrcClockDomain",
"domain_id": -1
},
"mem_ranges": [],
"eventq_index": 0,
"default_p_state": "UNDEFINED",
"p_state_clk_gate_max": 1000000000000,
"dvfs_handler": {
"enable": false,
"name": "dvfs_handler",
"sys_clk_domain": "system.clk_domain",
"transition_latency": 100000000,
"eventq_index": 0,
"cxx_class": "DVFSHandler",
"domains": [],
"path": "system.dvfs_handler",
"type": "DVFSHandler"
},
"work_end_exit_count": 0,
"type": "System",
"voltage_domain": {
"name": "voltage_domain",
"eventq_index": 0,
"voltage": [
"1.0"
],
"cxx_class": "VoltageDomain",
"path": "system.voltage_domain",
"type": "VoltageDomain"
},
"cache_line_size": 64,
"boot_osflags": "a",
"system_port": {
"peer": "system.membus.slave[0]",
"role": "MASTER"
},
"physmem": {
"range": "0:134217727:0:0:0:0",
"latency": 30000,
"name": "physmem",
"p_state_clk_gate_min": 1000,
"eventq_index": 0,
"p_state_clk_gate_bins": 20,
"default_p_state": "UNDEFINED",
"kvm_map": true,
"clk_domain": "system.clk_domain",
"power_model": null,
"latency_var": 0,
"bandwidth": "73.000000",
"conf_table_reported": true,
"cxx_class": "SimpleMemory",
"p_state_clk_gate_max": 1000000000000,
"path": "system.physmem",
"null": false,
"type": "SimpleMemory",
"port": {
"peer": "system.membus.master[0]",
"role": "SLAVE"
},
"in_addr_map": true
},
"power_model": null,
"work_cpus_ckpt_count": 0,
"thermal_components": [],
"path": "system",
"cpu_clk_domain": {
"name": "cpu_clk_domain",
"clock": [
500
],
"init_perf_level": 0,
"voltage_domain": "system.voltage_domain",
"eventq_index": 0,
"cxx_class": "SrcClockDomain",
"path": "system.cpu_clk_domain",
"type": "SrcClockDomain",
"domain_id": -1
},
"work_end_ckpt_count": 0,
"mem_mode": "atomic",
"name": "system",
"init_param": 0,
"p_state_clk_gate_bins": 20,
"load_addr_mask": 1099511627775,
"cpu": [
{
"do_statistics_insts": true,
"numThreads": 1,
"itb": {
"name": "itb",
"eventq_index": 0,
"cxx_class": "RiscvISA::TLB",
"path": "system.cpu.itb",
"type": "RiscvTLB",
"size": 64
},
"simulate_data_stalls": false,
"function_trace": false,
"do_checkpoint_insts": true,
"cxx_class": "AtomicSimpleCPU",
"max_loads_all_threads": 0,
"system": "system",
"clk_domain": "system.cpu_clk_domain",
"function_trace_start": 0,
"cpu_id": 0,
"width": 1,
"checker": null,
"eventq_index": 0,
"default_p_state": "UNDEFINED",
"p_state_clk_gate_max": 1000000000000,
"do_quiesce": true,
"type": "AtomicSimpleCPU",
"fastmem": false,
"profile": 0,
"icache_port": {
"peer": "system.membus.slave[1]",
"role": "MASTER"
},
"p_state_clk_gate_bins": 20,
"p_state_clk_gate_min": 1000,
"interrupts": [
{
"eventq_index": 0,
"path": "system.cpu.interrupts",
"type": "RiscvInterrupts",
"name": "interrupts",
"cxx_class": "RiscvISA::Interrupts"
}
],
"dcache_port": {
"peer": "system.membus.slave[2]",
"role": "MASTER"
},
"socket_id": 0,
"power_model": null,
"max_insts_all_threads": 0,
"path": "system.cpu",
"max_loads_any_thread": 0,
"switched_out": false,
"workload": [
{
"uid": 100,
"pid": 100,
"kvmInSE": false,
"cxx_class": "LiveProcess",
"executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64a/insttest",
"drivers": [],
"system": "system",
"gid": 100,
"eventq_index": 0,
"env": [],
"input": "cin",
"ppid": 99,
"type": "LiveProcess",
"cwd": "",
"simpoint": 0,
"euid": 100,
"path": "system.cpu.workload",
"max_stack_size": 67108864,
"name": "workload",
"cmd": [
"insttest"
],
"errout": "cerr",
"useArchPT": false,
"egid": 100,
"output": "cout"
}
],
"name": "cpu",
"dtb": {
"name": "dtb",
"eventq_index": 0,
"cxx_class": "RiscvISA::TLB",
"path": "system.cpu.dtb",
"type": "RiscvTLB",
"size": 64
},
"simpoint_start_insts": [],
"max_insts_any_thread": 0,
"simulate_inst_stalls": false,
"progress_interval": 0,
"branchPred": null,
"isa": [
{
"eventq_index": 0,
"path": "system.cpu.isa",
"type": "RiscvISA",
"name": "isa",
"cxx_class": "RiscvISA::ISA"
}
],
"tracer": {
"eventq_index": 0,
"path": "system.cpu.tracer",
"type": "ExeTracer",
"name": "tracer",
"cxx_class": "Trace::ExeTracer"
}
}
],
"multi_thread": false,
"exit_on_work_items": false,
"work_item_id": -1,
"num_work_ids": 16
},
"time_sync_period": 100000000000,
"eventq_index": 0,
"time_sync_spin_threshold": 100000000,
"cxx_class": "Root",
"path": "root",
"time_sync_enable": false,
"type": "Root",
"full_system": false
}

3
tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/simerr Executable file
View file

@ -0,0 +1,3 @@
warn: Unknown operating system; assuming Linux.
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick

49
tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/simout Executable file
View file

@ -0,0 +1,49 @@
Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-atomic/simout
Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Nov 30 2016 14:33:35
gem5 started Nov 30 2016 16:18:29
gem5 executing on zizzer, pid 34062
command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-atomic -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64a/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
lr.w/sc.w: PASS
sc.w, no preceding lr.d: PASS
amoswap.w: PASS
amoswap.w, sign extend: PASS
amoswap.w, truncate: PASS
amoadd.w: PASS
amoadd.w, truncate/overflow: PASS
amoadd.w, sign extend: PASS
amoxor.w, truncate: PASS
amoxor.w, sign extend: PASS
amoand.w, truncate: PASS
amoand.w, sign extend: PASS
amoor.w, truncate: PASS
amoor.w, sign extend: PASS
amomin.w, truncate: PASS
amomin.w, sign extend: PASS
amomax.w, truncate: PASS
amomax.w, sign extend: PASS
amominu.w, truncate: PASS
amominu.w, sign extend: PASS
amomaxu.w, truncate: PASS
amomaxu.w, sign extend: PASS
lr.d/sc.d: PASS
sc.d, no preceding lr.d: PASS
amoswap.d: PASS
amoadd.d: PASS
amoadd.d, overflow: PASS
amoxor.d (1): PASS
amoxor.d (0): PASS
amoand.d: PASS
amoor.d: PASS
amomin.d: PASS
amomax.d: PASS
amominu.d: PASS
amomaxu.d: PASS
Exiting @ tick 57010500 because target called exit()

156
tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/stats.txt Normal file
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@ -0,0 +1,156 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000057 # Number of seconds simulated
sim_ticks 57010500 # Number of ticks simulated
final_tick 57010500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 83371 # Simulator instruction rate (inst/s)
host_op_rate 83392 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 41711101 # Simulator tick rate (ticks/s)
host_mem_usage 233576 # Number of bytes of host memory used
host_seconds 1.37 # Real time elapsed on the host
sim_insts 113947 # Number of instructions simulated
sim_ops 113978 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 57010500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 455964 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 156854 # Number of bytes read from this memory
system.physmem.bytes_read::total 612818 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 455964 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 455964 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 111519 # Number of bytes written to this memory
system.physmem.bytes_written::total 111519 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 113991 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 23779 # Number of read requests responded to by this memory
system.physmem.num_reads::total 137770 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 19912 # Number of write requests responded to by this memory
system.physmem.num_writes::total 19912 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 7997895125 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2751317740 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 10749212864 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7997895125 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7997895125 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1956113348 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1956113348 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7997895125 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 4707431087 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 12705326212 # Total bandwidth to/from this memory (bytes/s)
system.pwrStateResidencyTicks::UNDEFINED 57010500 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 43 # Number of system calls
system.cpu.pwrStateResidencyTicks::ON 57010500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 114022 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 113947 # Number of instructions committed
system.cpu.committedOps 113978 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 113979 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 8601 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 17313 # number of instructions that are conditional controls
system.cpu.num_int_insts 113979 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_int_register_reads 152039 # number of times the integer registers were read
system.cpu.num_int_register_writes 76786 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 43694 # number of memory refs
system.cpu.num_load_insts 23779 # Number of load instructions
system.cpu.num_store_insts 19915 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 114022 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.Branches 25914 # Number of branches fetched
system.cpu.op_class::No_OpClass 43 0.04% 0.04% # Class of executed instruction
system.cpu.op_class::IntAlu 70180 61.55% 61.59% # Class of executed instruction
system.cpu.op_class::IntMult 105 0.09% 61.68% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 61.68% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 61.68% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 61.68% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 61.68% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 61.68% # Class of executed instruction
system.cpu.op_class::FloatMultAcc 0 0.00% 61.68% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 61.68% # Class of executed instruction
system.cpu.op_class::FloatMisc 0 0.00% 61.68% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 61.68% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 61.68% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 61.68% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 61.68% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 61.68% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 61.68% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 61.68% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 61.68% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 61.68% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 61.68% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 61.68% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 61.68% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 61.68% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 61.68% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 61.68% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 61.68% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 61.68% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 61.68% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 61.68% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.68% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.68% # Class of executed instruction
system.cpu.op_class::MemRead 23779 20.85% 82.53% # Class of executed instruction
system.cpu.op_class::MemWrite 19915 17.47% 100.00% # Class of executed instruction
system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 114022 # Class of executed instruction
system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 57010500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 137768 # Transaction distribution
system.membus.trans_dist::ReadResp 137770 # Transaction distribution
system.membus.trans_dist::WriteReq 19910 # Transaction distribution
system.membus.trans_dist::WriteResp 19910 # Transaction distribution
system.membus.trans_dist::LoadLockedReq 2 # Transaction distribution
system.membus.trans_dist::StoreCondReq 4 # Transaction distribution
system.membus.trans_dist::StoreCondResp 4 # Transaction distribution
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 227982 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 87386 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 315368 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 455964 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 268385 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 724349 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples 157684 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 157684 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 157684 # Request fanout histogram
---------- End Simulation Statistics ----------

1265
tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/config.ini Normal file
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File diff suppressed because it is too large Load diff

1734
tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/config.json Normal file
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File diff suppressed because it is too large Load diff

11
tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/simerr Executable file
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@ -0,0 +1,11 @@
warn: rounding error > tolerance
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Unknown operating system; assuming Linux.
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!

15
tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/simout Executable file
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@ -0,0 +1,15 @@
Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-timing-ruby/simout
Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-timing-ruby/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Nov 30 2016 14:33:35
gem5 started Nov 30 2016 16:18:31
gem5 executing on zizzer, pid 34069
command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-timing-ruby -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64a/simple-timing-ruby
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
lr.w/sc.w: FAIL (expected (-1, 0); found (-1, 1))
Exiting @ tick 796036 because target called exit()

659
tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/stats.txt Normal file
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---------- Begin Simulation Statistics ----------
sim_seconds 0.000796 # Number of seconds simulated
sim_ticks 796036 # Number of ticks simulated
final_tick 796036 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_inst_rate 51863 # Simulator instruction rate (inst/s)
host_op_rate 51862 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 623875 # Simulator tick rate (ticks/s)
host_mem_usage 411084 # Number of bytes of host memory used
host_seconds 1.28 # Real time elapsed on the host
sim_insts 66173 # Number of instructions simulated
sim_ops 66173 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 899200 # Number of bytes read from this memory
system.mem_ctrls.bytes_read::total 899200 # Number of bytes read from this memory
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 898944 # Number of bytes written to this memory
system.mem_ctrls.bytes_written::total 898944 # Number of bytes written to this memory
system.mem_ctrls.num_reads::ruby.dir_cntrl0 14050 # Number of read requests responded to by this memory
system.mem_ctrls.num_reads::total 14050 # Number of read requests responded to by this memory
system.mem_ctrls.num_writes::ruby.dir_cntrl0 14046 # Number of write requests responded to by this memory
system.mem_ctrls.num_writes::total 14046 # Number of write requests responded to by this memory
system.mem_ctrls.bw_read::ruby.dir_cntrl0 1129597154 # Total read bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_read::total 1129597154 # Total read bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_write::ruby.dir_cntrl0 1129275560 # Write bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_write::total 1129275560 # Write bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_total::ruby.dir_cntrl0 2258872714 # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.bw_total::total 2258872714 # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.readReqs 14050 # Number of read requests accepted
system.mem_ctrls.writeReqs 14046 # Number of write requests accepted
system.mem_ctrls.readBursts 14050 # Number of DRAM read bursts, including those serviced by the write queue
system.mem_ctrls.writeBursts 14046 # Number of DRAM write bursts, including those merged in the write queue
system.mem_ctrls.bytesReadDRAM 236096 # Total number of bytes read from DRAM
system.mem_ctrls.bytesReadWrQ 663104 # Total number of bytes read from write queue
system.mem_ctrls.bytesWritten 245056 # Total number of bytes written to DRAM
system.mem_ctrls.bytesReadSys 899200 # Total read bytes from the system interface side
system.mem_ctrls.bytesWrittenSys 898944 # Total written bytes from the system interface side
system.mem_ctrls.servicedByWrQ 10361 # Number of DRAM read bursts serviced by the write queue
system.mem_ctrls.mergedWrBursts 10190 # Number of DRAM write bursts merged with an existing one
system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.mem_ctrls.perBankRdBursts::0 171 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::1 11 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::2 5 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::3 94 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::4 190 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::5 318 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::6 159 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::7 59 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::8 94 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::9 356 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::10 241 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::11 240 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::12 629 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::13 494 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::14 606 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::15 22 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::0 175 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::1 12 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::2 4 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::3 95 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::4 197 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::5 332 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::6 163 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::7 63 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::8 96 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::9 353 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::10 243 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::11 245 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::12 639 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::13 514 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::14 676 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::15 22 # Per bank write bursts
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
system.mem_ctrls.totGap 795950 # Total gap between requests
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::6 14050 # Read request sizes (log2)
system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::6 14046 # Write request sizes (log2)
system.mem_ctrls.rdQLenPdf::0 3689 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::15 25 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::16 31 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::17 198 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::18 236 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::19 240 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::20 247 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::21 253 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::22 253 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::23 240 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::24 236 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::25 236 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::26 236 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::27 235 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::28 235 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::29 235 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::30 235 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::31 235 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::32 235 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.mem_ctrls.bytesPerActivate::samples 1249 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::mean 383.846277 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::gmean 248.755949 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::stdev 339.416055 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::0-127 261 20.90% 20.90% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::128-255 321 25.70% 46.60% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::256-383 184 14.73% 61.33% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::384-511 116 9.29% 70.62% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::512-639 64 5.12% 75.74% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::640-767 46 3.68% 79.42% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::768-895 41 3.28% 82.71% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::896-1023 34 2.72% 85.43% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::1024-1151 182 14.57% 100.00% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::total 1249 # Bytes accessed per row activation
system.mem_ctrls.rdPerTurnAround::samples 235 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::mean 15.651064 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::gmean 15.555359 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::stdev 1.947371 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::12-13 16 6.81% 6.81% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::14-15 98 41.70% 48.51% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::16-17 97 41.28% 89.79% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::18-19 21 8.94% 98.72% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::20-21 2 0.85% 99.57% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::36-37 1 0.43% 100.00% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::total 235 # Reads before turning the bus around for writes
system.mem_ctrls.wrPerTurnAround::samples 235 # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::mean 16.293617 # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::gmean 16.273674 # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::stdev 0.844136 # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::16 208 88.51% 88.51% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::18 14 5.96% 94.47% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::19 11 4.68% 99.15% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::20 2 0.85% 100.00% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::total 235 # Writes before turning the bus around for reads
system.mem_ctrls.totQLat 72649 # Total ticks spent queuing
system.mem_ctrls.totMemAccLat 142740 # Total ticks spent from burst creation until serviced by the DRAM
system.mem_ctrls.totBusLat 18445 # Total ticks spent in databus transfers
system.mem_ctrls.avgQLat 19.69 # Average queueing delay per DRAM burst
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
system.mem_ctrls.avgMemAccLat 38.69 # Average memory access latency per DRAM burst
system.mem_ctrls.avgRdBW 296.59 # Average DRAM read bandwidth in MiByte/s
system.mem_ctrls.avgWrBW 307.85 # Average achieved write bandwidth in MiByte/s
system.mem_ctrls.avgRdBWSys 1129.60 # Average system read bandwidth in MiByte/s
system.mem_ctrls.avgWrBWSys 1129.28 # Average system write bandwidth in MiByte/s
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.mem_ctrls.busUtil 4.72 # Data bus utilization in percentage
system.mem_ctrls.busUtilRead 2.32 # Data bus utilization in percentage for reads
system.mem_ctrls.busUtilWrite 2.41 # Data bus utilization in percentage for writes
system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing
system.mem_ctrls.avgWrQLen 25.57 # Average write queue length when enqueuing
system.mem_ctrls.readRowHits 2727 # Number of row buffer hits during reads
system.mem_ctrls.writeRowHits 3536 # Number of row buffer hits during writes
system.mem_ctrls.readRowHitRate 73.92 # Row buffer hit rate for reads
system.mem_ctrls.writeRowHitRate 91.70 # Row buffer hit rate for writes
system.mem_ctrls.avgGap 28.33 # Average gap between requests
system.mem_ctrls.pageHitRate 83.01 # Row buffer hit rate, read and write combined
system.mem_ctrls_0.actEnergy 3048780 # Energy for activate commands per rank (pJ)
system.mem_ctrls_0.preEnergy 1642200 # Energy for precharge commands per rank (pJ)
system.mem_ctrls_0.readEnergy 11503968 # Energy for read commands per rank (pJ)
system.mem_ctrls_0.writeEnergy 8694432 # Energy for write commands per rank (pJ)
system.mem_ctrls_0.refreshEnergy 44868720.000000 # Energy for refresh commands per rank (pJ)
system.mem_ctrls_0.actBackEnergy 54752376 # Energy for active background per rank (pJ)
system.mem_ctrls_0.preBackEnergy 1331712 # Energy for precharge background per rank (pJ)
system.mem_ctrls_0.actPowerDownEnergy 160437216 # Energy for active power-down per rank (pJ)
system.mem_ctrls_0.prePowerDownEnergy 26780160 # Energy for precharge power-down per rank (pJ)
system.mem_ctrls_0.selfRefreshEnergy 62430000 # Energy for self refresh per rank (pJ)
system.mem_ctrls_0.totalEnergy 375489564 # Total energy per rank (pJ)
system.mem_ctrls_0.averagePower 471.699225 # Core power per rank (mW)
system.mem_ctrls_0.totalIdleTime 672460 # Total Idle time Per DRAM Rank
system.mem_ctrls_0.memoryStateTime::IDLE 1456 # Time in different power states
system.mem_ctrls_0.memoryStateTime::REF 19004 # Time in different power states
system.mem_ctrls_0.memoryStateTime::SREF 250921 # Time in different power states
system.mem_ctrls_0.memoryStateTime::PRE_PDN 69740 # Time in different power states
system.mem_ctrls_0.memoryStateTime::ACT 103079 # Time in different power states
system.mem_ctrls_0.memoryStateTime::ACT_PDN 351836 # Time in different power states
system.mem_ctrls_1.actEnergy 5911920 # Energy for activate commands per rank (pJ)
system.mem_ctrls_1.preEnergy 3183936 # Energy for precharge commands per rank (pJ)
system.mem_ctrls_1.readEnergy 30639168 # Energy for read commands per rank (pJ)
system.mem_ctrls_1.writeEnergy 23285376 # Energy for write commands per rank (pJ)
system.mem_ctrls_1.refreshEnergy 61464000.000000 # Energy for refresh commands per rank (pJ)
system.mem_ctrls_1.actBackEnergy 65872392 # Energy for active background per rank (pJ)
system.mem_ctrls_1.preBackEnergy 2049024 # Energy for precharge background per rank (pJ)
system.mem_ctrls_1.actPowerDownEnergy 210691152 # Energy for active power-down per rank (pJ)
system.mem_ctrls_1.prePowerDownEnergy 47203968 # Energy for precharge power-down per rank (pJ)
system.mem_ctrls_1.selfRefreshEnergy 18571440 # Energy for self refresh per rank (pJ)
system.mem_ctrls_1.totalEnergy 468872376 # Total energy per rank (pJ)
system.mem_ctrls_1.averagePower 589.009010 # Core power per rank (mW)
system.mem_ctrls_1.totalIdleTime 646243 # Total Idle time Per DRAM Rank
system.mem_ctrls_1.memoryStateTime::IDLE 2396 # Time in different power states
system.mem_ctrls_1.memoryStateTime::REF 26042 # Time in different power states
system.mem_ctrls_1.memoryStateTime::SREF 61274 # Time in different power states
system.mem_ctrls_1.memoryStateTime::PRE_PDN 122927 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT 121355 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT_PDN 462042 # Time in different power states
system.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states
system.cpu.clk_domain.clock 1 # Clock period in ticks
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 9 # Number of system calls
system.cpu.pwrStateResidencyTicks::ON 796036 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 796036 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 66173 # Number of instructions committed
system.cpu.committedOps 66173 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 66174 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 5169 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 10311 # number of instructions that are conditional controls
system.cpu.num_int_insts 66174 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_int_register_reads 89437 # number of times the integer registers were read
system.cpu.num_int_register_writes 43419 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 24255 # number of memory refs
system.cpu.num_load_insts 11810 # Number of load instructions
system.cpu.num_store_insts 12445 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 796036 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.Branches 15480 # Number of branches fetched
system.cpu.op_class::No_OpClass 9 0.01% 0.01% # Class of executed instruction
system.cpu.op_class::IntAlu 41896 63.30% 63.32% # Class of executed instruction
system.cpu.op_class::IntMult 15 0.02% 63.34% # Class of executed instruction
system.cpu.op_class::IntDiv 8 0.01% 63.35% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 63.35% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 63.35% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 63.35% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 63.35% # Class of executed instruction
system.cpu.op_class::FloatMultAcc 0 0.00% 63.35% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 63.35% # Class of executed instruction
system.cpu.op_class::FloatMisc 0 0.00% 63.35% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 63.35% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 63.35% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 63.35% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 63.35% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 63.35% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 63.35% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 63.35% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 63.35% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 63.35% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 63.35% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 63.35% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 63.35% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 63.35% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 63.35% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 63.35% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 63.35% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 63.35% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 63.35% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 63.35% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.35% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.35% # Class of executed instruction
system.cpu.op_class::MemRead 11810 17.84% 81.20% # Class of executed instruction
system.cpu.op_class::MemWrite 12445 18.80% 100.00% # Class of executed instruction
system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 66183 # Class of executed instruction
system.ruby.clk_domain.clock 1 # Clock period in ticks
system.ruby.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states
system.ruby.delayHist::bucket_size 1 # delay histogram for all message
system.ruby.delayHist::max_bucket 9 # delay histogram for all message
system.ruby.delayHist::samples 28096 # delay histogram for all message
system.ruby.delayHist | 28096 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message
system.ruby.delayHist::total 28096 # delay histogram for all message
system.ruby.outstanding_req_hist_seqr::bucket_size 1
system.ruby.outstanding_req_hist_seqr::max_bucket 9
system.ruby.outstanding_req_hist_seqr::samples 90437
system.ruby.outstanding_req_hist_seqr::mean 1
system.ruby.outstanding_req_hist_seqr::gmean 1
system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 90437 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.outstanding_req_hist_seqr::total 90437
system.ruby.latency_hist_seqr::bucket_size 64
system.ruby.latency_hist_seqr::max_bucket 639
system.ruby.latency_hist_seqr::samples 90436
system.ruby.latency_hist_seqr::mean 7.802203
system.ruby.latency_hist_seqr::gmean 1.774694
system.ruby.latency_hist_seqr::stdev 20.056111
system.ruby.latency_hist_seqr | 86872 96.06% 96.06% | 3313 3.66% 99.72% | 168 0.19% 99.91% | 27 0.03% 99.94% | 26 0.03% 99.97% | 19 0.02% 99.99% | 1 0.00% 99.99% | 1 0.00% 99.99% | 0 0.00% 99.99% | 9 0.01% 100.00%
system.ruby.latency_hist_seqr::total 90436
system.ruby.hit_latency_hist_seqr::bucket_size 1
system.ruby.hit_latency_hist_seqr::max_bucket 9
system.ruby.hit_latency_hist_seqr::samples 76386
system.ruby.hit_latency_hist_seqr::mean 1
system.ruby.hit_latency_hist_seqr::gmean 1
system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 76386 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.hit_latency_hist_seqr::total 76386
system.ruby.miss_latency_hist_seqr::bucket_size 64
system.ruby.miss_latency_hist_seqr::max_bucket 639
system.ruby.miss_latency_hist_seqr::samples 14050
system.ruby.miss_latency_hist_seqr::mean 44.783915
system.ruby.miss_latency_hist_seqr::gmean 40.136483
system.ruby.miss_latency_hist_seqr::stdev 31.144722
system.ruby.miss_latency_hist_seqr | 10486 74.63% 74.63% | 3313 23.58% 98.21% | 168 1.20% 99.41% | 27 0.19% 99.60% | 26 0.19% 99.79% | 19 0.14% 99.92% | 1 0.01% 99.93% | 1 0.01% 99.94% | 0 0.00% 99.94% | 9 0.06% 100.00%
system.ruby.miss_latency_hist_seqr::total 14050
system.ruby.Directory.incomplete_times_seqr 14049
system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl0.cacheMemory.demand_hits 76386 # Number of cache demand hits
system.ruby.l1_cntrl0.cacheMemory.demand_misses 14050 # Number of cache demand misses
system.ruby.l1_cntrl0.cacheMemory.demand_accesses 90436 # Number of cache demand accesses
system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states
system.ruby.network.routers0.percent_links_utilized 8.823722
system.ruby.network.routers0.msg_count.Control::2 14050
system.ruby.network.routers0.msg_count.Data::2 14046
system.ruby.network.routers0.msg_count.Response_Data::4 14050
system.ruby.network.routers0.msg_count.Writeback_Control::3 14046
system.ruby.network.routers0.msg_bytes.Control::2 112400
system.ruby.network.routers0.msg_bytes.Data::2 1011312
system.ruby.network.routers0.msg_bytes.Response_Data::4 1011600
system.ruby.network.routers0.msg_bytes.Writeback_Control::3 112368
system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states
system.ruby.network.routers1.percent_links_utilized 8.823722
system.ruby.network.routers1.msg_count.Control::2 14050
system.ruby.network.routers1.msg_count.Data::2 14046
system.ruby.network.routers1.msg_count.Response_Data::4 14050
system.ruby.network.routers1.msg_count.Writeback_Control::3 14046
system.ruby.network.routers1.msg_bytes.Control::2 112400
system.ruby.network.routers1.msg_bytes.Data::2 1011312
system.ruby.network.routers1.msg_bytes.Response_Data::4 1011600
system.ruby.network.routers1.msg_bytes.Writeback_Control::3 112368
system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states
system.ruby.network.routers2.percent_links_utilized 8.823722
system.ruby.network.routers2.msg_count.Control::2 14050
system.ruby.network.routers2.msg_count.Data::2 14046
system.ruby.network.routers2.msg_count.Response_Data::4 14050
system.ruby.network.routers2.msg_count.Writeback_Control::3 14046
system.ruby.network.routers2.msg_bytes.Control::2 112400
system.ruby.network.routers2.msg_bytes.Data::2 1011312
system.ruby.network.routers2.msg_bytes.Response_Data::4 1011600
system.ruby.network.routers2.msg_bytes.Writeback_Control::3 112368
system.ruby.network.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states
system.ruby.network.msg_count.Control 42150
system.ruby.network.msg_count.Data 42138
system.ruby.network.msg_count.Response_Data 42150
system.ruby.network.msg_count.Writeback_Control 42138
system.ruby.network.msg_byte.Control 337200
system.ruby.network.msg_byte.Data 3033936
system.ruby.network.msg_byte.Response_Data 3034800
system.ruby.network.msg_byte.Writeback_Control 337104
system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states
system.ruby.network.routers0.throttle0.link_utilization 8.824727
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 14050
system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 14046
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 1011600
system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 112368
system.ruby.network.routers0.throttle1.link_utilization 8.822717
system.ruby.network.routers0.throttle1.msg_count.Control::2 14050
system.ruby.network.routers0.throttle1.msg_count.Data::2 14046
system.ruby.network.routers0.throttle1.msg_bytes.Control::2 112400
system.ruby.network.routers0.throttle1.msg_bytes.Data::2 1011312
system.ruby.network.routers1.throttle0.link_utilization 8.822717
system.ruby.network.routers1.throttle0.msg_count.Control::2 14050
system.ruby.network.routers1.throttle0.msg_count.Data::2 14046
system.ruby.network.routers1.throttle0.msg_bytes.Control::2 112400
system.ruby.network.routers1.throttle0.msg_bytes.Data::2 1011312
system.ruby.network.routers1.throttle1.link_utilization 8.824727
system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 14050
system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 14046
system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 1011600
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 112368
system.ruby.network.routers2.throttle0.link_utilization 8.824727
system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 14050
system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 14046
system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 1011600
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 112368
system.ruby.network.routers2.throttle1.link_utilization 8.822717
system.ruby.network.routers2.throttle1.msg_count.Control::2 14050
system.ruby.network.routers2.throttle1.msg_count.Data::2 14046
system.ruby.network.routers2.throttle1.msg_bytes.Control::2 112400
system.ruby.network.routers2.throttle1.msg_bytes.Data::2 1011312
system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1::samples 14050 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1 | 14050 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1::total 14050 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2::samples 14046 # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2 | 14046 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2::total 14046 # delay histogram for vnet_2
system.ruby.LD.latency_hist_seqr::bucket_size 64
system.ruby.LD.latency_hist_seqr::max_bucket 639
system.ruby.LD.latency_hist_seqr::samples 11809
system.ruby.LD.latency_hist_seqr::mean 15.856719
system.ruby.LD.latency_hist_seqr::gmean 3.539899
system.ruby.LD.latency_hist_seqr::stdev 26.045304
system.ruby.LD.latency_hist_seqr | 10771 91.21% 91.21% | 977 8.27% 99.48% | 43 0.36% 99.85% | 9 0.08% 99.92% | 5 0.04% 99.97% | 2 0.02% 99.98% | 0 0.00% 99.98% | 1 0.01% 99.99% | 0 0.00% 99.99% | 1 0.01% 100.00%
system.ruby.LD.latency_hist_seqr::total 11809
system.ruby.LD.hit_latency_hist_seqr::bucket_size 1
system.ruby.LD.hit_latency_hist_seqr::max_bucket 9
system.ruby.LD.hit_latency_hist_seqr::samples 7768
system.ruby.LD.hit_latency_hist_seqr::mean 1
system.ruby.LD.hit_latency_hist_seqr::gmean 1
system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 7768 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.hit_latency_hist_seqr::total 7768
system.ruby.LD.miss_latency_hist_seqr::bucket_size 64
system.ruby.LD.miss_latency_hist_seqr::max_bucket 639
system.ruby.LD.miss_latency_hist_seqr::samples 4041
system.ruby.LD.miss_latency_hist_seqr::mean 44.415739
system.ruby.LD.miss_latency_hist_seqr::gmean 40.208159
system.ruby.LD.miss_latency_hist_seqr::stdev 27.248261
system.ruby.LD.miss_latency_hist_seqr | 3003 74.31% 74.31% | 977 24.18% 98.49% | 43 1.06% 99.55% | 9 0.22% 99.78% | 5 0.12% 99.90% | 2 0.05% 99.95% | 0 0.00% 99.95% | 1 0.02% 99.98% | 0 0.00% 99.98% | 1 0.02% 100.00%
system.ruby.LD.miss_latency_hist_seqr::total 4041
system.ruby.ST.latency_hist_seqr::bucket_size 64
system.ruby.ST.latency_hist_seqr::max_bucket 639
system.ruby.ST.latency_hist_seqr::samples 12443
system.ruby.ST.latency_hist_seqr::mean 11.799164
system.ruby.ST.latency_hist_seqr::gmean 2.546410
system.ruby.ST.latency_hist_seqr::stdev 25.562634
system.ruby.ST.latency_hist_seqr | 11787 94.73% 94.73% | 602 4.84% 99.57% | 31 0.25% 99.82% | 7 0.06% 99.87% | 4 0.03% 99.90% | 7 0.06% 99.96% | 0 0.00% 99.96% | 0 0.00% 99.96% | 0 0.00% 99.96% | 5 0.04% 100.00%
system.ruby.ST.latency_hist_seqr::total 12443
system.ruby.ST.hit_latency_hist_seqr::bucket_size 1
system.ruby.ST.hit_latency_hist_seqr::max_bucket 9
system.ruby.ST.hit_latency_hist_seqr::samples 9259
system.ruby.ST.hit_latency_hist_seqr::mean 1
system.ruby.ST.hit_latency_hist_seqr::gmean 1
system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 9259 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.hit_latency_hist_seqr::total 9259
system.ruby.ST.miss_latency_hist_seqr::bucket_size 64
system.ruby.ST.miss_latency_hist_seqr::max_bucket 639
system.ruby.ST.miss_latency_hist_seqr::samples 3184
system.ruby.ST.miss_latency_hist_seqr::mean 43.202889
system.ruby.ST.miss_latency_hist_seqr::gmean 38.579676
system.ruby.ST.miss_latency_hist_seqr::stdev 35.050159
system.ruby.ST.miss_latency_hist_seqr | 2528 79.40% 79.40% | 602 18.91% 98.30% | 31 0.97% 99.28% | 7 0.22% 99.50% | 4 0.13% 99.62% | 7 0.22% 99.84% | 0 0.00% 99.84% | 0 0.00% 99.84% | 0 0.00% 99.84% | 5 0.16% 100.00%
system.ruby.ST.miss_latency_hist_seqr::total 3184
system.ruby.IFETCH.latency_hist_seqr::bucket_size 64
system.ruby.IFETCH.latency_hist_seqr::max_bucket 639
system.ruby.IFETCH.latency_hist_seqr::samples 66183
system.ruby.IFETCH.latency_hist_seqr::mean 5.613677
system.ruby.IFETCH.latency_hist_seqr::gmean 1.466025
system.ruby.IFETCH.latency_hist_seqr::stdev 16.923600
system.ruby.IFETCH.latency_hist_seqr | 64313 97.17% 97.17% | 1734 2.62% 99.79% | 94 0.14% 99.94% | 11 0.02% 99.95% | 17 0.03% 99.98% | 10 0.02% 99.99% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 3 0.00% 100.00%
system.ruby.IFETCH.latency_hist_seqr::total 66183
system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1
system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9
system.ruby.IFETCH.hit_latency_hist_seqr::samples 59358
system.ruby.IFETCH.hit_latency_hist_seqr::mean 1
system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1
system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 59358 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.hit_latency_hist_seqr::total 59358
system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64
system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639
system.ruby.IFETCH.miss_latency_hist_seqr::samples 6825
system.ruby.IFETCH.miss_latency_hist_seqr::mean 45.739487
system.ruby.IFETCH.miss_latency_hist_seqr::gmean 40.840935
system.ruby.IFETCH.miss_latency_hist_seqr::stdev 31.340636
system.ruby.IFETCH.miss_latency_hist_seqr | 4955 72.60% 72.60% | 1734 25.41% 98.01% | 94 1.38% 99.38% | 11 0.16% 99.55% | 17 0.25% 99.79% | 10 0.15% 99.94% | 1 0.01% 99.96% | 0 0.00% 99.96% | 0 0.00% 99.96% | 3 0.04% 100.00%
system.ruby.IFETCH.miss_latency_hist_seqr::total 6825
system.ruby.Load_Linked.latency_hist_seqr::bucket_size 1
system.ruby.Load_Linked.latency_hist_seqr::max_bucket 9
system.ruby.Load_Linked.latency_hist_seqr::samples 1
system.ruby.Load_Linked.latency_hist_seqr::mean 1
system.ruby.Load_Linked.latency_hist_seqr::gmean 1
system.ruby.Load_Linked.latency_hist_seqr::stdev nan
system.ruby.Load_Linked.latency_hist_seqr | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.Load_Linked.latency_hist_seqr::total 1
system.ruby.Load_Linked.hit_latency_hist_seqr::bucket_size 1
system.ruby.Load_Linked.hit_latency_hist_seqr::max_bucket 9
system.ruby.Load_Linked.hit_latency_hist_seqr::samples 1
system.ruby.Load_Linked.hit_latency_hist_seqr::mean 1
system.ruby.Load_Linked.hit_latency_hist_seqr::gmean 1
system.ruby.Load_Linked.hit_latency_hist_seqr::stdev nan
system.ruby.Load_Linked.hit_latency_hist_seqr | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.Load_Linked.hit_latency_hist_seqr::total 1
system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64
system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639
system.ruby.Directory.miss_mach_latency_hist_seqr::samples 14050
system.ruby.Directory.miss_mach_latency_hist_seqr::mean 44.783915
system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 40.136483
system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 31.144722
system.ruby.Directory.miss_mach_latency_hist_seqr | 10486 74.63% 74.63% | 3313 23.58% 98.21% | 168 1.20% 99.41% | 27 0.19% 99.60% | 26 0.19% 99.79% | 19 0.14% 99.92% | 1 0.01% 99.93% | 1 0.01% 99.94% | 0 0.00% 99.94% | 9 0.06% 100.00%
system.ruby.Directory.miss_mach_latency_hist_seqr::total 14050
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 1
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::stdev nan
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::total 1
system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::bucket_size 1
system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::max_bucket 9
system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::samples 1
system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::stdev nan
system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::total 1
system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::bucket_size 1
system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::max_bucket 9
system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::samples 1
system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::stdev nan
system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::total 1
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::bucket_size 8
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::max_bucket 79
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::samples 1
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::mean 75
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::gmean 75.000000
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::stdev nan
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00%
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 4041
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 44.415739
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 40.208159
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 27.248261
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 3003 74.31% 74.31% | 977 24.18% 98.49% | 43 1.06% 99.55% | 9 0.22% 99.78% | 5 0.12% 99.90% | 2 0.05% 99.95% | 0 0.00% 99.95% | 1 0.02% 99.98% | 0 0.00% 99.98% | 1 0.02% 100.00%
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 4041
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 3184
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 43.202889
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 38.579676
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 35.050159
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 2528 79.40% 79.40% | 602 18.91% 98.30% | 31 0.97% 99.28% | 7 0.22% 99.50% | 4 0.13% 99.62% | 7 0.22% 99.84% | 0 0.00% 99.84% | 0 0.00% 99.84% | 0 0.00% 99.84% | 5 0.16% 100.00%
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 3184
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 6825
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 45.739487
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 40.840935
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 31.340636
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 4955 72.60% 72.60% | 1734 25.41% 98.01% | 94 1.38% 99.38% | 11 0.16% 99.55% | 17 0.25% 99.79% | 10 0.15% 99.94% | 1 0.01% 99.96% | 0 0.00% 99.96% | 0 0.00% 99.96% | 3 0.04% 100.00%
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 6825
system.ruby.Directory_Controller.GETX 14050 0.00% 0.00%
system.ruby.Directory_Controller.PUTX 14046 0.00% 0.00%
system.ruby.Directory_Controller.Memory_Data 14050 0.00% 0.00%
system.ruby.Directory_Controller.Memory_Ack 14046 0.00% 0.00%
system.ruby.Directory_Controller.I.GETX 14050 0.00% 0.00%
system.ruby.Directory_Controller.M.PUTX 14046 0.00% 0.00%
system.ruby.Directory_Controller.IM.Memory_Data 14050 0.00% 0.00%
system.ruby.Directory_Controller.MI.Memory_Ack 14046 0.00% 0.00%
system.ruby.L1Cache_Controller.Load 11809 0.00% 0.00%
system.ruby.L1Cache_Controller.Ifetch 66183 0.00% 0.00%
system.ruby.L1Cache_Controller.Store 12444 0.00% 0.00%
system.ruby.L1Cache_Controller.Data 14050 0.00% 0.00%
system.ruby.L1Cache_Controller.Replacement 14046 0.00% 0.00%
system.ruby.L1Cache_Controller.Writeback_Ack 14046 0.00% 0.00%
system.ruby.L1Cache_Controller.I.Load 4041 0.00% 0.00%
system.ruby.L1Cache_Controller.I.Ifetch 6825 0.00% 0.00%
system.ruby.L1Cache_Controller.I.Store 3184 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Load 7768 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Ifetch 59358 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Store 9260 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Replacement 14046 0.00% 0.00%
system.ruby.L1Cache_Controller.MI.Writeback_Ack 14046 0.00% 0.00%
system.ruby.L1Cache_Controller.IS.Data 10866 0.00% 0.00%
system.ruby.L1Cache_Controller.IM.Data 3184 0.00% 0.00%
---------- End Simulation Statistics ----------

380
tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/config.ini Normal file
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[root]
type=Root
children=system
eventq_index=0
full_system=false
sim_quantum=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.clk_domain]
type=SrcClockDomain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.cpu]
type=TimingSimpleCPU
children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
branchPred=Null
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
default_p_state=UNDEFINED
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
eventq_index=0
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
profile=0
progress_interval=0
simpoint_start_insts=
socket_id=0
switched_out=false
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
is_read_only=false
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=262144
system=system
tag_latency=2
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dcache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=262144
tag_latency=2
[system.cpu.dtb]
type=RiscvTLB
eventq_index=0
size=64
[system.cpu.icache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
is_read_only=true
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=131072
system=system
tag_latency=2
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=true
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.icache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=131072
tag_latency=2
[system.cpu.interrupts]
type=RiscvInterrupts
eventq_index=0
[system.cpu.isa]
type=RiscvISA
eventq_index=0
[system.cpu.itb]
type=RiscvTLB
eventq_index=0
size=64
[system.cpu.l2cache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=20
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
is_read_only=false
max_miss_count=0
mshrs=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=20
sequential_access=false
size=2097152
system=system
tag_latency=20
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.l2cache.tags]
type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=20
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=2097152
tag_latency=20
[system.cpu.toL2Bus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=0
frontend_latency=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=false
power_model=Null
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.toL2Bus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=0
max_capacity=8388608
system=system
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=LiveProcess
cmd=insttest
cwd=
drivers=
egid=100
env=
errout=cerr
euid=100
eventq_index=0
executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64a/insttest
gid=100
input=cin
kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.dvfs_handler]
type=DVFSHandler
domains=
enable=false
eventq_index=0
sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=4
frontend_latency=3
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
clk_domain=system.clk_domain
conf_table_reported=true
default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
kvm_map=true
latency=30000
latency_var=0
null=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
range=0:134217727:0:0:0:0
port=system.membus.master[0]
[system.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.000000

508
tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/config.json Normal file
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@ -0,0 +1,508 @@
{
"name": null,
"sim_quantum": 0,
"system": {
"kernel": "",
"mmap_using_noreserve": false,
"kernel_addr_check": true,
"membus": {
"point_of_coherency": true,
"system": "system",
"response_latency": 2,
"cxx_class": "CoherentXBar",
"forward_latency": 4,
"clk_domain": "system.clk_domain",
"width": 16,
"eventq_index": 0,
"default_p_state": "UNDEFINED",
"p_state_clk_gate_max": 1000000000000,
"master": {
"peer": [
"system.physmem.port"
],
"role": "MASTER"
},
"type": "CoherentXBar",
"frontend_latency": 3,
"slave": {
"peer": [
"system.system_port",
"system.cpu.l2cache.mem_side"
],
"role": "SLAVE"
},
"p_state_clk_gate_min": 1000,
"snoop_filter": {
"name": "snoop_filter",
"system": "system",
"max_capacity": 8388608,
"eventq_index": 0,
"cxx_class": "SnoopFilter",
"path": "system.membus.snoop_filter",
"type": "SnoopFilter",
"lookup_latency": 1
},
"power_model": null,
"path": "system.membus",
"snoop_response_latency": 4,
"name": "membus",
"p_state_clk_gate_bins": 20,
"use_default_range": false
},
"symbolfile": "",
"readfile": "",
"thermal_model": null,
"cxx_class": "System",
"work_begin_cpu_id_exit": -1,
"load_offset": 0,
"work_begin_exit_count": 0,
"p_state_clk_gate_min": 1000,
"memories": [
"system.physmem"
],
"work_begin_ckpt_count": 0,
"clk_domain": {
"name": "clk_domain",
"clock": [
1000
],
"init_perf_level": 0,
"voltage_domain": "system.voltage_domain",
"eventq_index": 0,
"cxx_class": "SrcClockDomain",
"path": "system.clk_domain",
"type": "SrcClockDomain",
"domain_id": -1
},
"mem_ranges": [],
"eventq_index": 0,
"default_p_state": "UNDEFINED",
"p_state_clk_gate_max": 1000000000000,
"dvfs_handler": {
"enable": false,
"name": "dvfs_handler",
"sys_clk_domain": "system.clk_domain",
"transition_latency": 100000000,
"eventq_index": 0,
"cxx_class": "DVFSHandler",
"domains": [],
"path": "system.dvfs_handler",
"type": "DVFSHandler"
},
"work_end_exit_count": 0,
"type": "System",
"voltage_domain": {
"name": "voltage_domain",
"eventq_index": 0,
"voltage": [
"1.0"
],
"cxx_class": "VoltageDomain",
"path": "system.voltage_domain",
"type": "VoltageDomain"
},
"cache_line_size": 64,
"boot_osflags": "a",
"system_port": {
"peer": "system.membus.slave[0]",
"role": "MASTER"
},
"physmem": {
"range": "0:134217727:0:0:0:0",
"latency": 30000,
"name": "physmem",
"p_state_clk_gate_min": 1000,
"eventq_index": 0,
"p_state_clk_gate_bins": 20,
"default_p_state": "UNDEFINED",
"kvm_map": true,
"clk_domain": "system.clk_domain",
"power_model": null,
"latency_var": 0,
"bandwidth": "73.000000",
"conf_table_reported": true,
"cxx_class": "SimpleMemory",
"p_state_clk_gate_max": 1000000000000,
"path": "system.physmem",
"null": false,
"type": "SimpleMemory",
"port": {
"peer": "system.membus.master[0]",
"role": "SLAVE"
},
"in_addr_map": true
},
"power_model": null,
"work_cpus_ckpt_count": 0,
"thermal_components": [],
"path": "system",
"cpu_clk_domain": {
"name": "cpu_clk_domain",
"clock": [
500
],
"init_perf_level": 0,
"voltage_domain": "system.voltage_domain",
"eventq_index": 0,
"cxx_class": "SrcClockDomain",
"path": "system.cpu_clk_domain",
"type": "SrcClockDomain",
"domain_id": -1
},
"work_end_ckpt_count": 0,
"mem_mode": "timing",
"name": "system",
"init_param": 0,
"p_state_clk_gate_bins": 20,
"load_addr_mask": 1099511627775,
"cpu": [
{
"do_statistics_insts": true,
"numThreads": 1,
"itb": {
"name": "itb",
"eventq_index": 0,
"cxx_class": "RiscvISA::TLB",
"path": "system.cpu.itb",
"type": "RiscvTLB",
"size": 64
},
"system": "system",
"icache": {
"cpu_side": {
"peer": "system.cpu.icache_port",
"role": "SLAVE"
},
"clusivity": "mostly_incl",
"prefetcher": null,
"system": "system",
"write_buffers": 8,
"response_latency": 2,
"cxx_class": "Cache",
"size": 131072,
"type": "Cache",
"clk_domain": "system.cpu_clk_domain",
"max_miss_count": 0,
"eventq_index": 0,
"default_p_state": "UNDEFINED",
"p_state_clk_gate_max": 1000000000000,
"mem_side": {
"peer": "system.cpu.toL2Bus.slave[0]",
"role": "MASTER"
},
"mshrs": 4,
"writeback_clean": true,
"p_state_clk_gate_min": 1000,
"tags": {
"size": 131072,
"tag_latency": 2,
"name": "tags",
"p_state_clk_gate_min": 1000,
"eventq_index": 0,
"p_state_clk_gate_bins": 20,
"default_p_state": "UNDEFINED",
"clk_domain": "system.cpu_clk_domain",
"power_model": null,
"sequential_access": false,
"assoc": 2,
"cxx_class": "LRU",
"p_state_clk_gate_max": 1000000000000,
"path": "system.cpu.icache.tags",
"block_size": 64,
"type": "LRU",
"data_latency": 2
},
"tgts_per_mshr": 20,
"demand_mshr_reserve": 1,
"power_model": null,
"addr_ranges": [
"0:18446744073709551615:0:0:0:0"
],
"is_read_only": true,
"prefetch_on_access": false,
"path": "system.cpu.icache",
"data_latency": 2,
"tag_latency": 2,
"name": "icache",
"p_state_clk_gate_bins": 20,
"sequential_access": false,
"assoc": 2
},
"function_trace": false,
"do_checkpoint_insts": true,
"cxx_class": "TimingSimpleCPU",
"max_loads_all_threads": 0,
"clk_domain": "system.cpu_clk_domain",
"function_trace_start": 0,
"cpu_id": 0,
"checker": null,
"eventq_index": 0,
"default_p_state": "UNDEFINED",
"p_state_clk_gate_max": 1000000000000,
"toL2Bus": {
"point_of_coherency": false,
"system": "system",
"response_latency": 1,
"cxx_class": "CoherentXBar",
"forward_latency": 0,
"clk_domain": "system.cpu_clk_domain",
"width": 32,
"eventq_index": 0,
"default_p_state": "UNDEFINED",
"p_state_clk_gate_max": 1000000000000,
"master": {
"peer": [
"system.cpu.l2cache.cpu_side"
],
"role": "MASTER"
},
"type": "CoherentXBar",
"frontend_latency": 1,
"slave": {
"peer": [
"system.cpu.icache.mem_side",
"system.cpu.dcache.mem_side"
],
"role": "SLAVE"
},
"p_state_clk_gate_min": 1000,
"snoop_filter": {
"name": "snoop_filter",
"system": "system",
"max_capacity": 8388608,
"eventq_index": 0,
"cxx_class": "SnoopFilter",
"path": "system.cpu.toL2Bus.snoop_filter",
"type": "SnoopFilter",
"lookup_latency": 0
},
"power_model": null,
"path": "system.cpu.toL2Bus",
"snoop_response_latency": 1,
"name": "toL2Bus",
"p_state_clk_gate_bins": 20,
"use_default_range": false
},
"do_quiesce": true,
"type": "TimingSimpleCPU",
"profile": 0,
"icache_port": {
"peer": "system.cpu.icache.cpu_side",
"role": "MASTER"
},
"p_state_clk_gate_bins": 20,
"p_state_clk_gate_min": 1000,
"interrupts": [
{
"eventq_index": 0,
"path": "system.cpu.interrupts",
"type": "RiscvInterrupts",
"name": "interrupts",
"cxx_class": "RiscvISA::Interrupts"
}
],
"dcache_port": {
"peer": "system.cpu.dcache.cpu_side",
"role": "MASTER"
},
"socket_id": 0,
"power_model": null,
"max_insts_all_threads": 0,
"l2cache": {
"cpu_side": {
"peer": "system.cpu.toL2Bus.master[0]",
"role": "SLAVE"
},
"clusivity": "mostly_incl",
"prefetcher": null,
"system": "system",
"write_buffers": 8,
"response_latency": 20,
"cxx_class": "Cache",
"size": 2097152,
"type": "Cache",
"clk_domain": "system.cpu_clk_domain",
"max_miss_count": 0,
"eventq_index": 0,
"default_p_state": "UNDEFINED",
"p_state_clk_gate_max": 1000000000000,
"mem_side": {
"peer": "system.membus.slave[1]",
"role": "MASTER"
},
"mshrs": 20,
"writeback_clean": false,
"p_state_clk_gate_min": 1000,
"tags": {
"size": 2097152,
"tag_latency": 20,
"name": "tags",
"p_state_clk_gate_min": 1000,
"eventq_index": 0,
"p_state_clk_gate_bins": 20,
"default_p_state": "UNDEFINED",
"clk_domain": "system.cpu_clk_domain",
"power_model": null,
"sequential_access": false,
"assoc": 8,
"cxx_class": "LRU",
"p_state_clk_gate_max": 1000000000000,
"path": "system.cpu.l2cache.tags",
"block_size": 64,
"type": "LRU",
"data_latency": 20
},
"tgts_per_mshr": 12,
"demand_mshr_reserve": 1,
"power_model": null,
"addr_ranges": [
"0:18446744073709551615:0:0:0:0"
],
"is_read_only": false,
"prefetch_on_access": false,
"path": "system.cpu.l2cache",
"data_latency": 20,
"tag_latency": 20,
"name": "l2cache",
"p_state_clk_gate_bins": 20,
"sequential_access": false,
"assoc": 8
},
"path": "system.cpu",
"max_loads_any_thread": 0,
"switched_out": false,
"workload": [
{
"uid": 100,
"pid": 100,
"kvmInSE": false,
"cxx_class": "LiveProcess",
"executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64a/insttest",
"drivers": [],
"system": "system",
"gid": 100,
"eventq_index": 0,
"env": [],
"input": "cin",
"ppid": 99,
"type": "LiveProcess",
"cwd": "",
"simpoint": 0,
"euid": 100,
"path": "system.cpu.workload",
"max_stack_size": 67108864,
"name": "workload",
"cmd": [
"insttest"
],
"errout": "cerr",
"useArchPT": false,
"egid": 100,
"output": "cout"
}
],
"name": "cpu",
"dtb": {
"name": "dtb",
"eventq_index": 0,
"cxx_class": "RiscvISA::TLB",
"path": "system.cpu.dtb",
"type": "RiscvTLB",
"size": 64
},
"simpoint_start_insts": [],
"max_insts_any_thread": 0,
"progress_interval": 0,
"branchPred": null,
"dcache": {
"cpu_side": {
"peer": "system.cpu.dcache_port",
"role": "SLAVE"
},
"clusivity": "mostly_incl",
"prefetcher": null,
"system": "system",
"write_buffers": 8,
"response_latency": 2,
"cxx_class": "Cache",
"size": 262144,
"type": "Cache",
"clk_domain": "system.cpu_clk_domain",
"max_miss_count": 0,
"eventq_index": 0,
"default_p_state": "UNDEFINED",
"p_state_clk_gate_max": 1000000000000,
"mem_side": {
"peer": "system.cpu.toL2Bus.slave[1]",
"role": "MASTER"
},
"mshrs": 4,
"writeback_clean": false,
"p_state_clk_gate_min": 1000,
"tags": {
"size": 262144,
"tag_latency": 2,
"name": "tags",
"p_state_clk_gate_min": 1000,
"eventq_index": 0,
"p_state_clk_gate_bins": 20,
"default_p_state": "UNDEFINED",
"clk_domain": "system.cpu_clk_domain",
"power_model": null,
"sequential_access": false,
"assoc": 2,
"cxx_class": "LRU",
"p_state_clk_gate_max": 1000000000000,
"path": "system.cpu.dcache.tags",
"block_size": 64,
"type": "LRU",
"data_latency": 2
},
"tgts_per_mshr": 20,
"demand_mshr_reserve": 1,
"power_model": null,
"addr_ranges": [
"0:18446744073709551615:0:0:0:0"
],
"is_read_only": false,
"prefetch_on_access": false,
"path": "system.cpu.dcache",
"data_latency": 2,
"tag_latency": 2,
"name": "dcache",
"p_state_clk_gate_bins": 20,
"sequential_access": false,
"assoc": 2
},
"isa": [
{
"eventq_index": 0,
"path": "system.cpu.isa",
"type": "RiscvISA",
"name": "isa",
"cxx_class": "RiscvISA::ISA"
}
],
"tracer": {
"eventq_index": 0,
"path": "system.cpu.tracer",
"type": "ExeTracer",
"name": "tracer",
"cxx_class": "Trace::ExeTracer"
}
}
],
"multi_thread": false,
"exit_on_work_items": false,
"work_item_id": -1,
"num_work_ids": 16
},
"time_sync_period": 100000000000,
"eventq_index": 0,
"time_sync_spin_threshold": 100000000,
"cxx_class": "Root",
"path": "root",
"time_sync_enable": false,
"type": "Root",
"full_system": false
}

3
tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/simerr Executable file
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@ -0,0 +1,3 @@
warn: Unknown operating system; assuming Linux.
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick

15
tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/simout Executable file
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@ -0,0 +1,15 @@
Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-timing/simout
Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Nov 30 2016 14:33:35
gem5 started Nov 30 2016 16:18:30
gem5 executing on zizzer, pid 34063
command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64a/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
lr.w/sc.w: FAIL (expected (-1, 0); found (-1, 1))
Exiting @ tick 138549500 because target called exit()

519
tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/stats.txt Normal file
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@ -0,0 +1,519 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000139 # Number of seconds simulated
sim_ticks 138549500 # Number of ticks simulated
final_tick 138549500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 338688 # Simulator instruction rate (inst/s)
host_op_rate 338651 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 708977788 # Simulator tick rate (ticks/s)
host_mem_usage 242940 # Number of bytes of host memory used
host_seconds 0.20 # Real time elapsed on the host
sim_insts 66173 # Number of instructions simulated
sim_ops 66173 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 138549500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 33600 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 16064 # Number of bytes read from this memory
system.physmem.bytes_read::total 49664 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 33600 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 33600 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 525 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 251 # Number of read requests responded to by this memory
system.physmem.num_reads::total 776 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 242512604 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 115944121 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 358456725 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 242512604 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 242512604 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 242512604 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 115944121 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 358456725 # Total bandwidth to/from this memory (bytes/s)
system.pwrStateResidencyTicks::UNDEFINED 138549500 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 9 # Number of system calls
system.cpu.pwrStateResidencyTicks::ON 138549500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 277099 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 66173 # Number of instructions committed
system.cpu.committedOps 66173 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 66174 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 5169 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 10311 # number of instructions that are conditional controls
system.cpu.num_int_insts 66174 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_int_register_reads 89437 # number of times the integer registers were read
system.cpu.num_int_register_writes 43419 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 24255 # number of memory refs
system.cpu.num_load_insts 11810 # Number of load instructions
system.cpu.num_store_insts 12445 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 277099 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.Branches 15480 # Number of branches fetched
system.cpu.op_class::No_OpClass 9 0.01% 0.01% # Class of executed instruction
system.cpu.op_class::IntAlu 41896 63.30% 63.32% # Class of executed instruction
system.cpu.op_class::IntMult 15 0.02% 63.34% # Class of executed instruction
system.cpu.op_class::IntDiv 8 0.01% 63.35% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 63.35% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 63.35% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 63.35% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 63.35% # Class of executed instruction
system.cpu.op_class::FloatMultAcc 0 0.00% 63.35% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 63.35% # Class of executed instruction
system.cpu.op_class::FloatMisc 0 0.00% 63.35% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 63.35% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 63.35% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 63.35% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 63.35% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 63.35% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 63.35% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 63.35% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 63.35% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 63.35% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 63.35% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 63.35% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 63.35% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 63.35% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 63.35% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 63.35% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 63.35% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 63.35% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 63.35% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 63.35% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.35% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.35% # Class of executed instruction
system.cpu.op_class::MemRead 11810 17.84% 81.20% # Class of executed instruction
system.cpu.op_class::MemWrite 12445 18.80% 100.00% # Class of executed instruction
system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 66183 # Class of executed instruction
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 138549500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 195.060322 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 24002 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 251 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 95.625498 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 195.060322 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.047622 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.047622 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 251 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 52 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 195 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.061279 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 48757 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 48757 # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 138549500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 11758 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 11758 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 12243 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 12243 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 1 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 1 # number of LoadLockedReq hits
system.cpu.dcache.demand_hits::cpu.data 24001 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 24001 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 24001 # number of overall hits
system.cpu.dcache.overall_hits::total 24001 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 51 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 51 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 200 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 200 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 251 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 251 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 251 # number of overall misses
system.cpu.dcache.overall_misses::total 251 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3213000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 3213000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 12600000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 12600000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 15813000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 15813000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 15813000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 15813000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 11809 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 11809 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 12443 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 12443 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 1 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 24252 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 24252 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 24252 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 24252 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004319 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.004319 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.016073 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.016073 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.010350 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.010350 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.010350 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.010350 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 63000 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 63000 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 63000 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 63000 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 63000 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 51 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 51 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 200 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 200 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 251 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 251 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 251 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 251 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3162000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3162000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12400000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 12400000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15562000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 15562000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15562000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 15562000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004319 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004319 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.016073 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.016073 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.010350 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.010350 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.010350 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.010350 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62000 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62000 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 138549500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 10 # number of replacements
system.cpu.icache.tags.tagsinuse 190.684855 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 65659 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 525 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 125.064762 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 190.684855 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.093108 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.093108 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 515 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 346 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 103 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.251465 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 132893 # Number of tag accesses
system.cpu.icache.tags.data_accesses 132893 # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 138549500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 65659 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 65659 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 65659 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 65659 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 65659 # number of overall hits
system.cpu.icache.overall_hits::total 65659 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 525 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 525 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 525 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 525 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 525 # number of overall misses
system.cpu.icache.overall_misses::total 525 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 33076500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 33076500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 33076500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 33076500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 33076500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 33076500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 66184 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 66184 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 66184 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 66184 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 66184 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 66184 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007932 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.007932 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.007932 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.007932 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.007932 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.007932 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63002.857143 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 63002.857143 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 63002.857143 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 63002.857143 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 63002.857143 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 63002.857143 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks 10 # number of writebacks
system.cpu.icache.writebacks::total 10 # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 525 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 525 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 525 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 525 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 525 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 525 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32551500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 32551500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32551500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 32551500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32551500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 32551500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.007932 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.007932 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.007932 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.007932 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.007932 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.007932 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62002.857143 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62002.857143 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62002.857143 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 62002.857143 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62002.857143 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 62002.857143 # average overall mshr miss latency
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 138549500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 386.887852 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 10 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 776 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.012887 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst 191.808508 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 195.079344 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005854 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.005953 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.011807 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 776 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 405 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 301 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.023682 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 7064 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 7064 # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 138549500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackClean_hits::writebacks 10 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 10 # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 200 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 200 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 525 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 525 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 51 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 51 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 525 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 251 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 776 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 525 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 251 # number of overall misses
system.cpu.l2cache.overall_misses::total 776 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12100000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 12100000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 31763500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 31763500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3085500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 3085500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 31763500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 15185500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 46949000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 31763500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 15185500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 46949000 # number of overall miss cycles
system.cpu.l2cache.WritebackClean_accesses::writebacks 10 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 10 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 200 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 200 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 525 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 525 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 51 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 51 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 525 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 251 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 776 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 525 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 251 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 776 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 1 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60501.904762 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60501.904762 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60501.904762 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 60501.288660 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60501.904762 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 60501.288660 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 200 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 200 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 525 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 525 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 51 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 51 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 525 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 251 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 776 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 525 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 251 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 776 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10100000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10100000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 26513500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 26513500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2575500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2575500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 26513500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12675500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 39189000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 26513500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12675500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 39189000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50501.904762 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50501.904762 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50501.904762 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.288660 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50501.904762 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.288660 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 786 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 10 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 138549500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 576 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 10 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 200 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 200 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 525 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 51 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1060 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 502 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 1562 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 34240 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16064 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 50304 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples 776 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 776 100.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 776 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 403000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 787500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.6 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 376500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%)
system.membus.snoop_filter.tot_requests 776 # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 138549500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 576 # Transaction distribution
system.membus.trans_dist::ReadExReq 200 # Transaction distribution
system.membus.trans_dist::ReadExResp 200 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 576 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1552 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1552 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 49664 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 49664 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples 776 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 776 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 776 # Request fanout histogram
system.membus.reqLayer0.occupancy 777000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.6 # Layer utilization (%)
system.membus.respLayer1.occupancy 3880000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 2.8 # Layer utilization (%)
---------- End Simulation Statistics ----------

902
tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/config.ini Normal file
View file

@ -0,0 +1,902 @@
[root]
type=Root
children=system
eventq_index=0
full_system=false
sim_quantum=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.clk_domain]
type=SrcClockDomain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.cpu]
type=MinorCPU
children=branchPred dcache dtb executeFuncUnits icache interrupts isa itb l2cache toL2Bus tracer workload
branchPred=system.cpu.branchPred
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
decodeCycleInput=true
decodeInputBufferSize=3
decodeInputWidth=2
decodeToExecuteForwardDelay=1
default_p_state=UNDEFINED
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
enableIdling=true
eventq_index=0
executeAllowEarlyMemoryIssue=true
executeBranchDelay=1
executeCommitLimit=2
executeCycleInput=true
executeFuncUnits=system.cpu.executeFuncUnits
executeInputBufferSize=7
executeInputWidth=2
executeIssueLimit=2
executeLSQMaxStoreBufferStoresPerCycle=2
executeLSQRequestsQueueSize=1
executeLSQStoreBufferSize=5
executeLSQTransfersQueueSize=2
executeMaxAccessesInMemory=2
executeMemoryCommitLimit=1
executeMemoryIssueLimit=1
executeMemoryWidth=0
executeSetTraceTimeOnCommit=true
executeSetTraceTimeOnIssue=false
fetch1FetchLimit=1
fetch1LineSnapWidth=0
fetch1LineWidth=0
fetch1ToFetch2BackwardDelay=1
fetch1ToFetch2ForwardDelay=1
fetch2CycleInput=true
fetch2InputBufferSize=2
fetch2ToDecodeForwardDelay=1
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
profile=0
progress_interval=0
simpoint_start_insts=
socket_id=0
switched_out=false
system=system
threadPolicy=RoundRobin
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
type=TournamentBP
BTBEntries=4096
BTBTagSize=16
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
indirectHashGHR=true
indirectHashTargets=true
indirectPathLength=3
indirectSets=256
indirectTagSize=16
indirectWays=2
instShiftAmt=2
localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
useIndirect=true
[system.cpu.dcache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
is_read_only=false
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=262144
system=system
tag_latency=2
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dcache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=262144
tag_latency=2
[system.cpu.dtb]
type=RiscvTLB
eventq_index=0
size=64
[system.cpu.executeFuncUnits]
type=MinorFUPool
children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6
eventq_index=0
funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6
[system.cpu.executeFuncUnits.funcUnits0]
type=MinorFU
children=opClasses timings
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses
opLat=3
timings=system.cpu.executeFuncUnits.funcUnits0.timings
[system.cpu.executeFuncUnits.funcUnits0.opClasses]
type=MinorOpClassSet
children=opClasses
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses
[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses]
type=MinorOpClass
eventq_index=0
opClass=IntAlu
[system.cpu.executeFuncUnits.funcUnits0.timings]
type=MinorFUTiming
children=opClasses
description=Int
eventq_index=0
extraAssumedLat=0
extraCommitLat=0
extraCommitLatExpr=Null
mask=0
match=0
opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses
srcRegsRelativeLats=2
suppress=false
[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses]
type=MinorOpClassSet
eventq_index=0
opClasses=
[system.cpu.executeFuncUnits.funcUnits1]
type=MinorFU
children=opClasses timings
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses
opLat=3
timings=system.cpu.executeFuncUnits.funcUnits1.timings
[system.cpu.executeFuncUnits.funcUnits1.opClasses]
type=MinorOpClassSet
children=opClasses
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses
[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses]
type=MinorOpClass
eventq_index=0
opClass=IntAlu
[system.cpu.executeFuncUnits.funcUnits1.timings]
type=MinorFUTiming
children=opClasses
description=Int
eventq_index=0
extraAssumedLat=0
extraCommitLat=0
extraCommitLatExpr=Null
mask=0
match=0
opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses
srcRegsRelativeLats=2
suppress=false
[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses]
type=MinorOpClassSet
eventq_index=0
opClasses=
[system.cpu.executeFuncUnits.funcUnits2]
type=MinorFU
children=opClasses timings
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses
opLat=3
timings=system.cpu.executeFuncUnits.funcUnits2.timings
[system.cpu.executeFuncUnits.funcUnits2.opClasses]
type=MinorOpClassSet
children=opClasses
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses
[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses]
type=MinorOpClass
eventq_index=0
opClass=IntMult
[system.cpu.executeFuncUnits.funcUnits2.timings]
type=MinorFUTiming
children=opClasses
description=Mul
eventq_index=0
extraAssumedLat=0
extraCommitLat=0
extraCommitLatExpr=Null
mask=0
match=0
opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses
srcRegsRelativeLats=0
suppress=false
[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses]
type=MinorOpClassSet
eventq_index=0
opClasses=
[system.cpu.executeFuncUnits.funcUnits3]
type=MinorFU
children=opClasses
cantForwardFromFUIndices=
eventq_index=0
issueLat=9
opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses
opLat=9
timings=
[system.cpu.executeFuncUnits.funcUnits3.opClasses]
type=MinorOpClassSet
children=opClasses
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses
[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses]
type=MinorOpClass
eventq_index=0
opClass=IntDiv
[system.cpu.executeFuncUnits.funcUnits4]
type=MinorFU
children=opClasses timings
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses
opLat=6
timings=system.cpu.executeFuncUnits.funcUnits4.timings
[system.cpu.executeFuncUnits.funcUnits4.opClasses]
type=MinorOpClassSet
children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 opClasses26 opClasses27
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses26 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses27
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00]
type=MinorOpClass
eventq_index=0
opClass=FloatAdd
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01]
type=MinorOpClass
eventq_index=0
opClass=FloatCmp
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02]
type=MinorOpClass
eventq_index=0
opClass=FloatCvt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03]
type=MinorOpClass
eventq_index=0
opClass=FloatMisc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04]
type=MinorOpClass
eventq_index=0
opClass=FloatMult
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05]
type=MinorOpClass
eventq_index=0
opClass=FloatMultAcc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06]
type=MinorOpClass
eventq_index=0
opClass=FloatDiv
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07]
type=MinorOpClass
eventq_index=0
opClass=FloatSqrt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08]
type=MinorOpClass
eventq_index=0
opClass=SimdAdd
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09]
type=MinorOpClass
eventq_index=0
opClass=SimdAddAcc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10]
type=MinorOpClass
eventq_index=0
opClass=SimdAlu
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11]
type=MinorOpClass
eventq_index=0
opClass=SimdCmp
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12]
type=MinorOpClass
eventq_index=0
opClass=SimdCvt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13]
type=MinorOpClass
eventq_index=0
opClass=SimdMisc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14]
type=MinorOpClass
eventq_index=0
opClass=SimdMult
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15]
type=MinorOpClass
eventq_index=0
opClass=SimdMultAcc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16]
type=MinorOpClass
eventq_index=0
opClass=SimdShift
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17]
type=MinorOpClass
eventq_index=0
opClass=SimdShiftAcc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18]
type=MinorOpClass
eventq_index=0
opClass=SimdSqrt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatAdd
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatAlu
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatCmp
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatCvt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatDiv
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatMisc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatMult
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses26]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatMultAcc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses27]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatSqrt
[system.cpu.executeFuncUnits.funcUnits4.timings]
type=MinorFUTiming
children=opClasses
description=FloatSimd
eventq_index=0
extraAssumedLat=0
extraCommitLat=0
extraCommitLatExpr=Null
mask=0
match=0
opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses
srcRegsRelativeLats=2
suppress=false
[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses]
type=MinorOpClassSet
eventq_index=0
opClasses=
[system.cpu.executeFuncUnits.funcUnits5]
type=MinorFU
children=opClasses timings
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses
opLat=1
timings=system.cpu.executeFuncUnits.funcUnits5.timings
[system.cpu.executeFuncUnits.funcUnits5.opClasses]
type=MinorOpClassSet
children=opClasses0 opClasses1 opClasses2 opClasses3
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses2 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses3
[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0]
type=MinorOpClass
eventq_index=0
opClass=MemRead
[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1]
type=MinorOpClass
eventq_index=0
opClass=MemWrite
[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses2]
type=MinorOpClass
eventq_index=0
opClass=FloatMemRead
[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses3]
type=MinorOpClass
eventq_index=0
opClass=FloatMemWrite
[system.cpu.executeFuncUnits.funcUnits5.timings]
type=MinorFUTiming
children=opClasses
description=Mem
eventq_index=0
extraAssumedLat=2
extraCommitLat=0
extraCommitLatExpr=Null
mask=0
match=0
opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses
srcRegsRelativeLats=1
suppress=false
[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses]
type=MinorOpClassSet
eventq_index=0
opClasses=
[system.cpu.executeFuncUnits.funcUnits6]
type=MinorFU
children=opClasses
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses
opLat=1
timings=
[system.cpu.executeFuncUnits.funcUnits6.opClasses]
type=MinorOpClassSet
children=opClasses0 opClasses1
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1
[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0]
type=MinorOpClass
eventq_index=0
opClass=IprAccess
[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1]
type=MinorOpClass
eventq_index=0
opClass=InstPrefetch
[system.cpu.icache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
is_read_only=true
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=131072
system=system
tag_latency=2
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=true
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.icache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=131072
tag_latency=2
[system.cpu.interrupts]
type=RiscvInterrupts
eventq_index=0
[system.cpu.isa]
type=RiscvISA
eventq_index=0
[system.cpu.itb]
type=RiscvTLB
eventq_index=0
size=64
[system.cpu.l2cache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=20
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
is_read_only=false
max_miss_count=0
mshrs=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=20
sequential_access=false
size=2097152
system=system
tag_latency=20
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.l2cache.tags]
type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=20
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=2097152
tag_latency=20
[system.cpu.toL2Bus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=0
frontend_latency=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=false
power_model=Null
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.toL2Bus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=0
max_capacity=8388608
system=system
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=LiveProcess
cmd=insttest
cwd=
drivers=
egid=100
env=
errout=cerr
euid=100
eventq_index=0
executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64d/insttest
gid=100
input=cin
kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.dvfs_handler]
type=DVFSHandler
domains=
enable=false
eventq_index=0
sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=4
frontend_latency=3
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem]
type=DRAMCtrl
IDD0=0.055000
IDD02=0.000000
IDD2N=0.032000
IDD2N2=0.000000
IDD2P0=0.000000
IDD2P02=0.000000
IDD2P1=0.032000
IDD2P12=0.000000
IDD3N=0.038000
IDD3N2=0.000000
IDD3P0=0.000000
IDD3P02=0.000000
IDD3P1=0.038000
IDD3P12=0.000000
IDD4R=0.157000
IDD4R2=0.000000
IDD4W=0.125000
IDD4W2=0.000000
IDD5=0.235000
IDD52=0.000000
IDD6=0.020000
IDD62=0.000000
VDD=1.500000
VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
clk_domain=system.clk_domain
conf_table_reported=true
default_p_state=UNDEFINED
device_bus_width=8
device_rowbuffer_size=1024
device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
in_addr_map=true
kvm_map=true
max_accesses_per_row=16
mem_sched_policy=frfcfs
min_writes_per_switch=16
null=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
page_policy=open_adaptive
power_model=Null
range=0:134217727:0:0:0:0
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
tCCD_L=0
tCK=1250
tCL=13750
tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
tXP=6000
tXPDLL=0
tXS=270000
tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
port=system.membus.master[0]
[system.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.000000

1211
tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/config.json Normal file
View file

File diff suppressed because it is too large Load diff

4
tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/simerr Executable file
View file

@ -0,0 +1,4 @@
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Unknown operating system; assuming Linux.
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick

168
tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/simout Executable file
View file

@ -0,0 +1,168 @@
Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/minor-timing/simout
Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/minor-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Nov 30 2016 14:33:35
gem5 started Nov 30 2016 16:18:31
gem5 executing on zizzer, pid 34070
command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/minor-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64d/minor-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
fld: PASS
fsd: PASS
fmadd.d: PASS
fmadd.d, quiet NaN: PASS
fmadd.d, signaling NaN: PASS
fmadd.d, infinity: PASS
fmadd.d, -infinity: PASS
fmsub.d: PASS
fmsub.d, quiet NaN: PASS
fmsub.d, signaling NaN: PASS
fmsub.d, infinity: PASS
fmsub.d, -infinity: PASS
fmsub.d, subtract infinity: PASS
fnmsub.d: PASS
fnmsub.d, quiet NaN: PASS
fnmsub.d, signaling NaN: PASS
fnmsub.d, infinity: PASS
fnmsub.d, -infinity: PASS
fnmsub.d, subtract infinity: PASS
fnmadd.d: PASS
fnmadd.d, quiet NaN: PASS
fnmadd.d, signaling NaN: PASS
fnmadd.d, infinity: PASS
fnmadd.d, -infinity: PASS
fadd.d: PASS
fadd.d, quiet NaN: PASS
fadd.d, signaling NaN: PASS
fadd.d, infinity: PASS
fadd.d, -infinity: PASS
fsub.d: PASS
fsub.d, quiet NaN: PASS
fsub.d, signaling NaN: PASS
fsub.d, infinity: PASS
fsub.d, -infinity: PASS
fsub.d, subtract infinity: PASS
fmul.d: PASS
fmul.d, quiet NaN: PASS
fmul.d, signaling NaN: PASS
fmul.d, infinity: PASS
fmul.d, -infinity: PASS
fmul.d, 0*infinity: PASS
fmul.d, overflow: PASS
fmul.d, underflow: PASS
fdiv.d: PASS
fdiv.d, quiet NaN: PASS
fdiv.d, signaling NaN: PASS
fdiv.d/0: PASS
fdiv.d/infinity: PASS
fdiv.d, infinity/infinity: PASS
fdiv.d, 0/0: PASS
fdiv.d, infinity/0: PASS
fdiv.d, 0/infinity: PASS
fdiv.d, underflow: PASS
fdiv.d, overflow: PASS
fsqrt.d: PASS
fsqrt.d, NaN: PASS
fsqrt.d, quiet NaN: PASS
fsqrt.d, signaling NaN: PASS
fsqrt.d, infinity: PASS
fsgnj.d, ++: PASS
fsgnj.d, +-: PASS
fsgnj.d, -+: PASS
fsgnj.d, --: PASS
fsgnj.d, quiet NaN: PASS
fsgnj.d, signaling NaN: PASS
fsgnj.d, inject NaN: PASS
fsgnj.d, inject -NaN: PASS
fsgnjn.d, ++: PASS
fsgnjn.d, +-: PASS
fsgnjn.d, -+: PASS
fsgnjn.d, --: PASS
fsgnjn.d, quiet NaN: PASS
fsgnjn.d, signaling NaN: PASS
fsgnjn.d, inject NaN: PASS
fsgnjn.d, inject NaN: PASS
fsgnjx.d, ++: PASS
fsgnjx.d, +-: PASS
fsgnjx.d, -+: PASS
fsgnjx.d, --: PASS
fsgnjx.d, quiet NaN: PASS
fsgnjx.d, signaling NaN: PASS
fsgnjx.d, inject NaN: PASS
fsgnjx.d, inject NaN: PASS
fmin.d: PASS
fmin.d, -infinity: PASS
fmin.d, infinity: PASS
fmin.d, quiet NaN first: PASS
fmin.d, quiet NaN second: PASS
fmin.d, quiet NaN both: PASS
fmin.d, signaling NaN first: PASS
fmin.d, signaling NaN second: PASS
fmin.d, signaling NaN both: PASS
fmax.d: PASS
fmax.d, -infinity: PASS
fmax.d, infinity: PASS
fmax.d, quiet NaN first: PASS
fmax.d, quiet NaN second: PASS
fmax.d, quiet NaN both: PASS
fmax.d, signaling NaN first: PASS
fmax.d, signaling NaN second: PASS
fmax.d, signaling NaN both: PASS
fcvt.s.d: PASS
fcvt.s.d, quiet NaN: PASS
fcvt.s.d, signaling NaN: PASS
fcvt.s.d, infinity: PASS
fcvt.s.d, overflow: PASS
fcvt.s.d, underflow: PASS
fcvt.d.s: PASS
fcvt.d.s, quiet NaN: PASS
fcvt.d.s, signaling NaN: PASS
fcvt.d.s, infinity: PASS
feq.d, equal: PASS
feq.d, not equal: PASS
feq.d, 0 == -0: PASS
feq.d, quiet NaN first: PASS
feq.d, quiet NaN second: PASS
feq.d, quiet NaN both: PASS
feq.d, signaling NaN first: PASS
feq.d, signaling NaN second: PASS
feq.d, signaling NaN both: PASS
flt.d, equal: PASS
flt.d, less: PASS
flt.d, greater: PASS
flt.d, quiet NaN first: PASS
flt.d, quiet NaN second: PASS
flt.d, quiet NaN both: PASS
flt.d, signaling NaN first: PASS
flt.d, signaling NaN second: PASS
flt.d, signaling NaN both: PASS
fle.d, equal: PASS
fle.d, less: PASS
fle.d, greater: PASS
fle.d, 0 == -0: PASS
fle.d, quiet NaN first: PASS
fle.d, quiet NaN second: PASS
fle.d, quiet NaN both: PASS
fle.d, signaling NaN first: PASS
fle.d, signaling NaN second: PASS
fle.d, signaling NaN both: PASS
fclass.d, -infinity: PASS
fclass.d, -normal: PASS
fclass.d, -subnormal: PASS
fclass.d, -0.0: PASS
fclass.d, 0.0: PASS
fclass.d, subnormal: PASS
fclass.d, normal: PASS
fclass.d, infinity: PASS
fclass.d, signaling NaN: PASS
fclass.s, quiet NaN: PASS
fcvt.w.d, truncate positive: PASS
fcvt.w.d, truncate negative: PASS
fcvt.w.d, 0.0: PASS
fcvt.w.d, -0.0: PASS
fcvt.w.d, overflow: FAIL (expected 2147483647; found -2147483648)
Exiting @ tick 339160000 because target called exit()

763
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---------- Begin Simulation Statistics ----------
sim_seconds 0.000339 # Number of seconds simulated
sim_ticks 339160000 # Number of ticks simulated
final_tick 339160000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 25032 # Simulator instruction rate (inst/s)
host_op_rate 25032 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 28360795 # Simulator tick rate (ticks/s)
host_mem_usage 244952 # Number of bytes of host memory used
host_seconds 11.96 # Real time elapsed on the host
sim_insts 299354 # Number of instructions simulated
sim_ops 299354 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 74688 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 20352 # Number of bytes read from this memory
system.physmem.bytes_read::total 95040 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 74688 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 74688 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 1167 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 318 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1485 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 220214648 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 60007076 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 280221724 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 220214648 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 220214648 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 220214648 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 60007076 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 280221724 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 1485 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 1485 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 95040 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 95040 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 175 # Per bank write bursts
system.physmem.perBankRdBursts::1 68 # Per bank write bursts
system.physmem.perBankRdBursts::2 18 # Per bank write bursts
system.physmem.perBankRdBursts::3 72 # Per bank write bursts
system.physmem.perBankRdBursts::4 169 # Per bank write bursts
system.physmem.perBankRdBursts::5 291 # Per bank write bursts
system.physmem.perBankRdBursts::6 95 # Per bank write bursts
system.physmem.perBankRdBursts::7 4 # Per bank write bursts
system.physmem.perBankRdBursts::8 9 # Per bank write bursts
system.physmem.perBankRdBursts::9 115 # Per bank write bursts
system.physmem.perBankRdBursts::10 155 # Per bank write bursts
system.physmem.perBankRdBursts::11 169 # Per bank write bursts
system.physmem.perBankRdBursts::12 48 # Per bank write bursts
system.physmem.perBankRdBursts::13 55 # Per bank write bursts
system.physmem.perBankRdBursts::14 15 # Per bank write bursts
system.physmem.perBankRdBursts::15 27 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
system.physmem.perBankWrBursts::4 0 # Per bank write bursts
system.physmem.perBankWrBursts::5 0 # Per bank write bursts
system.physmem.perBankWrBursts::6 0 # Per bank write bursts
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
system.physmem.perBankWrBursts::10 0 # Per bank write bursts
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 338943500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 1485 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 1419 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 63 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 285 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 327.859649 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 221.469651 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 283.652997 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 67 23.51% 23.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 73 25.61% 49.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 39 13.68% 62.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 33 11.58% 74.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 28 9.82% 84.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 15 5.26% 89.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 7 2.46% 91.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 2 0.70% 92.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 21 7.37% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 285 # Bytes accessed per row activation
system.physmem.totQLat 19805250 # Total ticks spent queuing
system.physmem.totMemAccLat 47649000 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 7425000 # Total ticks spent in databus transfers
system.physmem.avgQLat 13336.87 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 32086.87 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 280.22 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 280.22 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 2.19 # Data bus utilization in percentage
system.physmem.busUtilRead 2.19 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 1195 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 80.47 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 228244.78 # Average gap between requests
system.physmem.pageHitRate 80.47 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 1106700 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 576840 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 6368880 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 27044160.000000 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 16006740 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 700320 # Energy for precharge background per rank (pJ)
system.physmem_0.actPowerDownEnergy 122840700 # Energy for active power-down per rank (pJ)
system.physmem_0.prePowerDownEnergy 12504960 # Energy for precharge power-down per rank (pJ)
system.physmem_0.selfRefreshEnergy 619740.000000 # Energy for self refresh per rank (pJ)
system.physmem_0.totalEnergy 187769040 # Total energy per rank (pJ)
system.physmem_0.averagePower 553.629673 # Core power per rank (mW)
system.physmem_0.totalIdleTime 301401000 # Total Idle time Per DRAM Rank
system.physmem_0.memoryStateTime::IDLE 546000 # Time in different power states
system.physmem_0.memoryStateTime::REF 11446000 # Time in different power states
system.physmem_0.memoryStateTime::SREF 280750 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 32576500 # Time in different power states
system.physmem_0.memoryStateTime::ACT 24926250 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 269384500 # Time in different power states
system.physmem_1.actEnergy 963900 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 504735 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 4234020 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 27044160.000000 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 12901950 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 3644640 # Energy for precharge background per rank (pJ)
system.physmem_1.actPowerDownEnergy 106370550 # Energy for active power-down per rank (pJ)
system.physmem_1.prePowerDownEnergy 25587360 # Energy for precharge power-down per rank (pJ)
system.physmem_1.selfRefreshEnergy 905640.000000 # Energy for self refresh per rank (pJ)
system.physmem_1.totalEnergy 182156955 # Total energy per rank (pJ)
system.physmem_1.averagePower 537.082660 # Core power per rank (mW)
system.physmem_1.totalIdleTime 301148500 # Total Idle time Per DRAM Rank
system.physmem_1.memoryStateTime::IDLE 8278250 # Time in different power states
system.physmem_1.memoryStateTime::REF 11446000 # Time in different power states
system.physmem_1.memoryStateTime::SREF 1471750 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 66617000 # Time in different power states
system.physmem_1.memoryStateTime::ACT 18107500 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 233239500 # Time in different power states
system.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 80709 # Number of BP lookups
system.cpu.branchPred.condPredicted 51944 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 5835 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 64346 # Number of BTB lookups
system.cpu.branchPred.BTBHits 38294 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 59.512635 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups 13164 # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits 7506 # Number of indirect target hits.
system.cpu.branchPred.indirectMisses 5658 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 3210 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 162 # Number of system calls
system.cpu.pwrStateResidencyTicks::ON 339160000 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 678320 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 299354 # Number of instructions committed
system.cpu.committedOps 299354 # Number of ops (including micro ops) committed
system.cpu.discardedOps 13959 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 2.265946 # CPI: cycles per instruction
system.cpu.ipc 0.441317 # IPC: instructions per cycle
system.cpu.op_class_0::No_OpClass 162 0.05% 0.05% # Class of committed instruction
system.cpu.op_class_0::IntAlu 179913 60.10% 60.15% # Class of committed instruction
system.cpu.op_class_0::IntMult 466 0.16% 60.31% # Class of committed instruction
system.cpu.op_class_0::IntDiv 40 0.01% 60.32% # Class of committed instruction
system.cpu.op_class_0::FloatAdd 120 0.04% 60.36% # Class of committed instruction
system.cpu.op_class_0::FloatCmp 157 0.05% 60.42% # Class of committed instruction
system.cpu.op_class_0::FloatCvt 60 0.02% 60.44% # Class of committed instruction
system.cpu.op_class_0::FloatMult 30 0.01% 60.45% # Class of committed instruction
system.cpu.op_class_0::FloatMultAcc 0 0.00% 60.45% # Class of committed instruction
system.cpu.op_class_0::FloatDiv 11 0.00% 60.45% # Class of committed instruction
system.cpu.op_class_0::FloatMisc 0 0.00% 60.45% # Class of committed instruction
system.cpu.op_class_0::FloatSqrt 5 0.00% 60.45% # Class of committed instruction
system.cpu.op_class_0::SimdAdd 0 0.00% 60.45% # Class of committed instruction
system.cpu.op_class_0::SimdAddAcc 0 0.00% 60.45% # Class of committed instruction
system.cpu.op_class_0::SimdAlu 0 0.00% 60.45% # Class of committed instruction
system.cpu.op_class_0::SimdCmp 0 0.00% 60.45% # Class of committed instruction
system.cpu.op_class_0::SimdCvt 0 0.00% 60.45% # Class of committed instruction
system.cpu.op_class_0::SimdMisc 0 0.00% 60.45% # Class of committed instruction
system.cpu.op_class_0::SimdMult 0 0.00% 60.45% # Class of committed instruction
system.cpu.op_class_0::SimdMultAcc 0 0.00% 60.45% # Class of committed instruction
system.cpu.op_class_0::SimdShift 0 0.00% 60.45% # Class of committed instruction
system.cpu.op_class_0::SimdShiftAcc 0 0.00% 60.45% # Class of committed instruction
system.cpu.op_class_0::SimdSqrt 0 0.00% 60.45% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAdd 0 0.00% 60.45% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAlu 0 0.00% 60.45% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCmp 0 0.00% 60.45% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCvt 0 0.00% 60.45% # Class of committed instruction
system.cpu.op_class_0::SimdFloatDiv 0 0.00% 60.45% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMisc 0 0.00% 60.45% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMult 0 0.00% 60.45% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 60.45% # Class of committed instruction
system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 60.45% # Class of committed instruction
system.cpu.op_class_0::MemRead 69348 23.17% 83.62% # Class of committed instruction
system.cpu.op_class_0::MemWrite 48400 16.17% 99.79% # Class of committed instruction
system.cpu.op_class_0::FloatMemRead 495 0.17% 99.95% # Class of committed instruction
system.cpu.op_class_0::FloatMemWrite 147 0.05% 100.00% # Class of committed instruction
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::total 299354 # Class of committed instruction
system.cpu.tickCycles 449536 # Number of cycles that the object actually ticked
system.cpu.idleCycles 228784 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 254.196505 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 119907 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 320 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 374.709375 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 254.196505 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.062060 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.062060 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 320 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 288 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.078125 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 241156 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 241156 # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 71754 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 71754 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 48153 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 48153 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 119907 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 119907 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 119907 # number of overall hits
system.cpu.dcache.overall_hits::total 119907 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 118 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 118 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 393 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 393 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 511 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 511 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 511 # number of overall misses
system.cpu.dcache.overall_misses::total 511 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 10963000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 10963000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 31520500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 31520500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 42483500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 42483500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 42483500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 42483500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 71872 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 71872 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 48546 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 48546 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 120418 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 120418 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 120418 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 120418 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001642 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.001642 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008095 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.008095 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.004244 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.004244 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.004244 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.004244 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 92906.779661 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 92906.779661 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80204.834606 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 80204.834606 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 83137.964775 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 83137.964775 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 83137.964775 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 83137.964775 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 191 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 191 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 191 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 191 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 191 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 191 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 118 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 118 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 202 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 202 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 320 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 320 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 320 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 320 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10845000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 10845000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 16122000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 16122000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26967000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 26967000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26967000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 26967000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001642 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001642 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.004161 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.004161 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002657 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.002657 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002657 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.002657 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 91906.779661 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 91906.779661 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79811.881188 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79811.881188 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84271.875000 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 84271.875000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84271.875000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 84271.875000 # average overall mshr miss latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 80 # number of replacements
system.cpu.icache.tags.tagsinuse 640.869470 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 135081 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 1178 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 114.669779 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 640.869470 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.312925 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.312925 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1098 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 182 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 846 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.536133 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 273696 # Number of tag accesses
system.cpu.icache.tags.data_accesses 273696 # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 135081 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 135081 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 135081 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 135081 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 135081 # number of overall hits
system.cpu.icache.overall_hits::total 135081 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1178 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1178 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1178 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1178 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1178 # number of overall misses
system.cpu.icache.overall_misses::total 1178 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 99945500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 99945500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 99945500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 99945500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 99945500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 99945500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 136259 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 136259 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 136259 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 136259 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 136259 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 136259 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008645 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.008645 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.008645 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.008645 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.008645 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.008645 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 84843.378608 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 84843.378608 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 84843.378608 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 84843.378608 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 84843.378608 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 84843.378608 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks 80 # number of writebacks
system.cpu.icache.writebacks::total 80 # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1178 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 1178 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 1178 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 1178 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 1178 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 1178 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 98767500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 98767500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 98767500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 98767500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 98767500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 98767500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008645 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008645 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008645 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.008645 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008645 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.008645 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83843.378608 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83843.378608 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83843.378608 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 83843.378608 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83843.378608 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 83843.378608 # average overall mshr miss latency
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 923.863116 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 93 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 1485 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.062626 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst 671.109849 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 252.753267 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020481 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.007713 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.028194 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 1485 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1201 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.045319 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 14109 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 14109 # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackClean_hits::writebacks 80 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 80 # number of WritebackClean hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 11 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 11 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 2 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 2 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst 11 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 2 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 13 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 11 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 2 # number of overall hits
system.cpu.l2cache.overall_hits::total 13 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 202 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 202 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1167 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 1167 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 116 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 116 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 1167 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 318 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 1485 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 1167 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 318 # number of overall misses
system.cpu.l2cache.overall_misses::total 1485 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 15818500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 15818500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 96885000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 96885000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 10642000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 10642000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 96885000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 26460500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 123345500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 96885000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 26460500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 123345500 # number of overall miss cycles
system.cpu.l2cache.WritebackClean_accesses::writebacks 80 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 80 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 202 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 202 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1178 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 1178 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 118 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 118 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 1178 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 320 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 1498 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 1178 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 320 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 1498 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.990662 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.990662 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.983051 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.983051 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.990662 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.993750 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.991322 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.990662 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.993750 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.991322 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78309.405941 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78309.405941 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83020.565553 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83020.565553 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 91741.379310 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 91741.379310 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83020.565553 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83209.119497 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 83060.942761 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83020.565553 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83209.119497 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 83060.942761 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 202 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 202 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1167 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1167 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 116 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 116 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 1167 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 318 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 1485 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 1167 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 318 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 1485 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13798500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13798500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 85215000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 85215000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 9482000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 9482000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 85215000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23280500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 108495500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 85215000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23280500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 108495500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.990662 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.990662 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.983051 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.983051 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.990662 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.993750 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.991322 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.990662 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.993750 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.991322 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68309.405941 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68309.405941 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73020.565553 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73020.565553 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 81741.379310 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 81741.379310 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73020.565553 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73209.119497 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73060.942761 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73020.565553 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73209.119497 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73060.942761 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 1578 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 82 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 1296 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 80 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 202 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 202 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 1178 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 118 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2436 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 640 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 3076 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 80512 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 20480 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 100992 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples 1498 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.001335 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.036527 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 1496 99.87% 99.87% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 2 0.13% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 1498 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 869000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 1767000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.5 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 480000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
system.membus.snoop_filter.tot_requests 1485 # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 1283 # Transaction distribution
system.membus.trans_dist::ReadExReq 202 # Transaction distribution
system.membus.trans_dist::ReadExResp 202 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 1283 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2970 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 2970 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 95040 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 95040 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples 1485 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 1485 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 1485 # Request fanout histogram
system.membus.reqLayer0.occupancy 1720000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.5 # Layer utilization (%)
system.membus.respLayer1.occupancy 7877750 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 2.3 # Layer utilization (%)
---------- End Simulation Statistics ----------

211
tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-atomic/config.ini Normal file
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@ -0,0 +1,211 @@
[root]
type=Root
children=system
eventq_index=0
full_system=false
sim_quantum=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mem_mode=atomic
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.clk_domain]
type=SrcClockDomain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.cpu]
type=AtomicSimpleCPU
children=dtb interrupts isa itb tracer workload
branchPred=Null
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
default_p_state=UNDEFINED
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
eventq_index=0
fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
profile=0
progress_interval=0
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
socket_id=0
switched_out=false
system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
dcache_port=system.membus.slave[2]
icache_port=system.membus.slave[1]
[system.cpu.dtb]
type=RiscvTLB
eventq_index=0
size=64
[system.cpu.interrupts]
type=RiscvInterrupts
eventq_index=0
[system.cpu.isa]
type=RiscvISA
eventq_index=0
[system.cpu.itb]
type=RiscvTLB
eventq_index=0
size=64
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=LiveProcess
cmd=insttest
cwd=
drivers=
egid=100
env=
errout=cerr
euid=100
eventq_index=0
executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64d/insttest
gid=100
input=cin
kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.dvfs_handler]
type=DVFSHandler
domains=
enable=false
eventq_index=0
sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=4
frontend_latency=3
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
width=16
master=system.physmem.port
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
clk_domain=system.clk_domain
conf_table_reported=true
default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
kvm_map=true
latency=30000
latency_var=0
null=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
range=0:134217727:0:0:0:0
port=system.membus.master[0]
[system.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.000000

289
tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-atomic/config.json Normal file
View file

@ -0,0 +1,289 @@
{
"name": null,
"sim_quantum": 0,
"system": {
"kernel": "",
"mmap_using_noreserve": false,
"kernel_addr_check": true,
"membus": {
"point_of_coherency": true,
"system": "system",
"response_latency": 2,
"cxx_class": "CoherentXBar",
"forward_latency": 4,
"clk_domain": "system.clk_domain",
"width": 16,
"eventq_index": 0,
"default_p_state": "UNDEFINED",
"p_state_clk_gate_max": 1000000000000,
"master": {
"peer": [
"system.physmem.port"
],
"role": "MASTER"
},
"type": "CoherentXBar",
"frontend_latency": 3,
"slave": {
"peer": [
"system.system_port",
"system.cpu.icache_port",
"system.cpu.dcache_port"
],
"role": "SLAVE"
},
"p_state_clk_gate_min": 1000,
"snoop_filter": {
"name": "snoop_filter",
"system": "system",
"max_capacity": 8388608,
"eventq_index": 0,
"cxx_class": "SnoopFilter",
"path": "system.membus.snoop_filter",
"type": "SnoopFilter",
"lookup_latency": 1
},
"power_model": null,
"path": "system.membus",
"snoop_response_latency": 4,
"name": "membus",
"p_state_clk_gate_bins": 20,
"use_default_range": false
},
"symbolfile": "",
"readfile": "",
"thermal_model": null,
"cxx_class": "System",
"work_begin_cpu_id_exit": -1,
"load_offset": 0,
"work_begin_exit_count": 0,
"p_state_clk_gate_min": 1000,
"memories": [
"system.physmem"
],
"work_begin_ckpt_count": 0,
"clk_domain": {
"name": "clk_domain",
"clock": [
1000
],
"init_perf_level": 0,
"voltage_domain": "system.voltage_domain",
"eventq_index": 0,
"cxx_class": "SrcClockDomain",
"path": "system.clk_domain",
"type": "SrcClockDomain",
"domain_id": -1
},
"mem_ranges": [],
"eventq_index": 0,
"default_p_state": "UNDEFINED",
"p_state_clk_gate_max": 1000000000000,
"dvfs_handler": {
"enable": false,
"name": "dvfs_handler",
"sys_clk_domain": "system.clk_domain",
"transition_latency": 100000000,
"eventq_index": 0,
"cxx_class": "DVFSHandler",
"domains": [],
"path": "system.dvfs_handler",
"type": "DVFSHandler"
},
"work_end_exit_count": 0,
"type": "System",
"voltage_domain": {
"name": "voltage_domain",
"eventq_index": 0,
"voltage": [
"1.0"
],
"cxx_class": "VoltageDomain",
"path": "system.voltage_domain",
"type": "VoltageDomain"
},
"cache_line_size": 64,
"boot_osflags": "a",
"system_port": {
"peer": "system.membus.slave[0]",
"role": "MASTER"
},
"physmem": {
"range": "0:134217727:0:0:0:0",
"latency": 30000,
"name": "physmem",
"p_state_clk_gate_min": 1000,
"eventq_index": 0,
"p_state_clk_gate_bins": 20,
"default_p_state": "UNDEFINED",
"kvm_map": true,
"clk_domain": "system.clk_domain",
"power_model": null,
"latency_var": 0,
"bandwidth": "73.000000",
"conf_table_reported": true,
"cxx_class": "SimpleMemory",
"p_state_clk_gate_max": 1000000000000,
"path": "system.physmem",
"null": false,
"type": "SimpleMemory",
"port": {
"peer": "system.membus.master[0]",
"role": "SLAVE"
},
"in_addr_map": true
},
"power_model": null,
"work_cpus_ckpt_count": 0,
"thermal_components": [],
"path": "system",
"cpu_clk_domain": {
"name": "cpu_clk_domain",
"clock": [
500
],
"init_perf_level": 0,
"voltage_domain": "system.voltage_domain",
"eventq_index": 0,
"cxx_class": "SrcClockDomain",
"path": "system.cpu_clk_domain",
"type": "SrcClockDomain",
"domain_id": -1
},
"work_end_ckpt_count": 0,
"mem_mode": "atomic",
"name": "system",
"init_param": 0,
"p_state_clk_gate_bins": 20,
"load_addr_mask": 1099511627775,
"cpu": [
{
"do_statistics_insts": true,
"numThreads": 1,
"itb": {
"name": "itb",
"eventq_index": 0,
"cxx_class": "RiscvISA::TLB",
"path": "system.cpu.itb",
"type": "RiscvTLB",
"size": 64
},
"simulate_data_stalls": false,
"function_trace": false,
"do_checkpoint_insts": true,
"cxx_class": "AtomicSimpleCPU",
"max_loads_all_threads": 0,
"system": "system",
"clk_domain": "system.cpu_clk_domain",
"function_trace_start": 0,
"cpu_id": 0,
"width": 1,
"checker": null,
"eventq_index": 0,
"default_p_state": "UNDEFINED",
"p_state_clk_gate_max": 1000000000000,
"do_quiesce": true,
"type": "AtomicSimpleCPU",
"fastmem": false,
"profile": 0,
"icache_port": {
"peer": "system.membus.slave[1]",
"role": "MASTER"
},
"p_state_clk_gate_bins": 20,
"p_state_clk_gate_min": 1000,
"interrupts": [
{
"eventq_index": 0,
"path": "system.cpu.interrupts",
"type": "RiscvInterrupts",
"name": "interrupts",
"cxx_class": "RiscvISA::Interrupts"
}
],
"dcache_port": {
"peer": "system.membus.slave[2]",
"role": "MASTER"
},
"socket_id": 0,
"power_model": null,
"max_insts_all_threads": 0,
"path": "system.cpu",
"max_loads_any_thread": 0,
"switched_out": false,
"workload": [
{
"uid": 100,
"pid": 100,
"kvmInSE": false,
"cxx_class": "LiveProcess",
"executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64d/insttest",
"drivers": [],
"system": "system",
"gid": 100,
"eventq_index": 0,
"env": [],
"input": "cin",
"ppid": 99,
"type": "LiveProcess",
"cwd": "",
"simpoint": 0,
"euid": 100,
"path": "system.cpu.workload",
"max_stack_size": 67108864,
"name": "workload",
"cmd": [
"insttest"
],
"errout": "cerr",
"useArchPT": false,
"egid": 100,
"output": "cout"
}
],
"name": "cpu",
"dtb": {
"name": "dtb",
"eventq_index": 0,
"cxx_class": "RiscvISA::TLB",
"path": "system.cpu.dtb",
"type": "RiscvTLB",
"size": 64
},
"simpoint_start_insts": [],
"max_insts_any_thread": 0,
"simulate_inst_stalls": false,
"progress_interval": 0,
"branchPred": null,
"isa": [
{
"eventq_index": 0,
"path": "system.cpu.isa",
"type": "RiscvISA",
"name": "isa",
"cxx_class": "RiscvISA::ISA"
}
],
"tracer": {
"eventq_index": 0,
"path": "system.cpu.tracer",
"type": "ExeTracer",
"name": "tracer",
"cxx_class": "Trace::ExeTracer"
}
}
],
"multi_thread": false,
"exit_on_work_items": false,
"work_item_id": -1,
"num_work_ids": 16
},
"time_sync_period": 100000000000,
"eventq_index": 0,
"time_sync_spin_threshold": 100000000,
"cxx_class": "Root",
"path": "root",
"time_sync_enable": false,
"type": "Root",
"full_system": false
}

3
tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-atomic/simerr Executable file
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@ -0,0 +1,3 @@
warn: Unknown operating system; assuming Linux.
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick

168
tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-atomic/simout Executable file
View file

@ -0,0 +1,168 @@
Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/simple-atomic/simout
Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Nov 30 2016 14:33:35
gem5 started Nov 30 2016 16:18:31
gem5 executing on zizzer, pid 34072
command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/simple-atomic -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64d/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
fld: PASS
fsd: PASS
fmadd.d: PASS
fmadd.d, quiet NaN: PASS
fmadd.d, signaling NaN: PASS
fmadd.d, infinity: PASS
fmadd.d, -infinity: PASS
fmsub.d: PASS
fmsub.d, quiet NaN: PASS
fmsub.d, signaling NaN: PASS
fmsub.d, infinity: PASS
fmsub.d, -infinity: PASS
fmsub.d, subtract infinity: PASS
fnmsub.d: PASS
fnmsub.d, quiet NaN: PASS
fnmsub.d, signaling NaN: PASS
fnmsub.d, infinity: PASS
fnmsub.d, -infinity: PASS
fnmsub.d, subtract infinity: PASS
fnmadd.d: PASS
fnmadd.d, quiet NaN: PASS
fnmadd.d, signaling NaN: PASS
fnmadd.d, infinity: PASS
fnmadd.d, -infinity: PASS
fadd.d: PASS
fadd.d, quiet NaN: PASS
fadd.d, signaling NaN: PASS
fadd.d, infinity: PASS
fadd.d, -infinity: PASS
fsub.d: PASS
fsub.d, quiet NaN: PASS
fsub.d, signaling NaN: PASS
fsub.d, infinity: PASS
fsub.d, -infinity: PASS
fsub.d, subtract infinity: PASS
fmul.d: PASS
fmul.d, quiet NaN: PASS
fmul.d, signaling NaN: PASS
fmul.d, infinity: PASS
fmul.d, -infinity: PASS
fmul.d, 0*infinity: PASS
fmul.d, overflow: PASS
fmul.d, underflow: PASS
fdiv.d: PASS
fdiv.d, quiet NaN: PASS
fdiv.d, signaling NaN: PASS
fdiv.d/0: PASS
fdiv.d/infinity: PASS
fdiv.d, infinity/infinity: PASS
fdiv.d, 0/0: PASS
fdiv.d, infinity/0: PASS
fdiv.d, 0/infinity: PASS
fdiv.d, underflow: PASS
fdiv.d, overflow: PASS
fsqrt.d: PASS
fsqrt.d, NaN: PASS
fsqrt.d, quiet NaN: PASS
fsqrt.d, signaling NaN: PASS
fsqrt.d, infinity: PASS
fsgnj.d, ++: PASS
fsgnj.d, +-: PASS
fsgnj.d, -+: PASS
fsgnj.d, --: PASS
fsgnj.d, quiet NaN: PASS
fsgnj.d, signaling NaN: PASS
fsgnj.d, inject NaN: PASS
fsgnj.d, inject -NaN: PASS
fsgnjn.d, ++: PASS
fsgnjn.d, +-: PASS
fsgnjn.d, -+: PASS
fsgnjn.d, --: PASS
fsgnjn.d, quiet NaN: PASS
fsgnjn.d, signaling NaN: PASS
fsgnjn.d, inject NaN: PASS
fsgnjn.d, inject NaN: PASS
fsgnjx.d, ++: PASS
fsgnjx.d, +-: PASS
fsgnjx.d, -+: PASS
fsgnjx.d, --: PASS
fsgnjx.d, quiet NaN: PASS
fsgnjx.d, signaling NaN: PASS
fsgnjx.d, inject NaN: PASS
fsgnjx.d, inject NaN: PASS
fmin.d: PASS
fmin.d, -infinity: PASS
fmin.d, infinity: PASS
fmin.d, quiet NaN first: PASS
fmin.d, quiet NaN second: PASS
fmin.d, quiet NaN both: PASS
fmin.d, signaling NaN first: PASS
fmin.d, signaling NaN second: PASS
fmin.d, signaling NaN both: PASS
fmax.d: PASS
fmax.d, -infinity: PASS
fmax.d, infinity: PASS
fmax.d, quiet NaN first: PASS
fmax.d, quiet NaN second: PASS
fmax.d, quiet NaN both: PASS
fmax.d, signaling NaN first: PASS
fmax.d, signaling NaN second: PASS
fmax.d, signaling NaN both: PASS
fcvt.s.d: PASS
fcvt.s.d, quiet NaN: PASS
fcvt.s.d, signaling NaN: PASS
fcvt.s.d, infinity: PASS
fcvt.s.d, overflow: PASS
fcvt.s.d, underflow: PASS
fcvt.d.s: PASS
fcvt.d.s, quiet NaN: PASS
fcvt.d.s, signaling NaN: PASS
fcvt.d.s, infinity: PASS
feq.d, equal: PASS
feq.d, not equal: PASS
feq.d, 0 == -0: PASS
feq.d, quiet NaN first: PASS
feq.d, quiet NaN second: PASS
feq.d, quiet NaN both: PASS
feq.d, signaling NaN first: PASS
feq.d, signaling NaN second: PASS
feq.d, signaling NaN both: PASS
flt.d, equal: PASS
flt.d, less: PASS
flt.d, greater: PASS
flt.d, quiet NaN first: PASS
flt.d, quiet NaN second: PASS
flt.d, quiet NaN both: PASS
flt.d, signaling NaN first: PASS
flt.d, signaling NaN second: PASS
flt.d, signaling NaN both: PASS
fle.d, equal: PASS
fle.d, less: PASS
fle.d, greater: PASS
fle.d, 0 == -0: PASS
fle.d, quiet NaN first: PASS
fle.d, quiet NaN second: PASS
fle.d, quiet NaN both: PASS
fle.d, signaling NaN first: PASS
fle.d, signaling NaN second: PASS
fle.d, signaling NaN both: PASS
fclass.d, -infinity: PASS
fclass.d, -normal: PASS
fclass.d, -subnormal: PASS
fclass.d, -0.0: PASS
fclass.d, 0.0: PASS
fclass.d, subnormal: PASS
fclass.d, normal: PASS
fclass.d, infinity: PASS
fclass.d, signaling NaN: PASS
fclass.s, quiet NaN: PASS
fcvt.w.d, truncate positive: PASS
fcvt.w.d, truncate negative: PASS
fcvt.w.d, 0.0: PASS
fcvt.w.d, -0.0: PASS
fcvt.w.d, overflow: FAIL (expected 2147483647; found -2147483648)
Exiting @ tick 149676500 because target called exit()

153
tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-atomic/stats.txt Normal file
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@ -0,0 +1,153 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000150 # Number of seconds simulated
sim_ticks 149676500 # Number of ticks simulated
final_tick 149676500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 28553 # Simulator instruction rate (inst/s)
host_op_rate 28553 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 14284274 # Simulator tick rate (ticks/s)
host_mem_usage 234416 # Number of bytes of host memory used
host_seconds 10.48 # Real time elapsed on the host
sim_insts 299191 # Number of instructions simulated
sim_ops 299191 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 149676500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 1197416 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 459717 # Number of bytes read from this memory
system.physmem.bytes_read::total 1657133 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 1197416 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1197416 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 301409 # Number of bytes written to this memory
system.physmem.bytes_written::total 301409 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 299354 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 69843 # Number of read requests responded to by this memory
system.physmem.num_reads::total 369197 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 48546 # Number of write requests responded to by this memory
system.physmem.num_writes::total 48546 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 8000026724 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 3071403995 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 11071430719 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 8000026724 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 8000026724 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 2013736291 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2013736291 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 8000026724 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 5085140286 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 13085167010 # Total bandwidth to/from this memory (bytes/s)
system.pwrStateResidencyTicks::UNDEFINED 149676500 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 162 # Number of system calls
system.cpu.pwrStateResidencyTicks::ON 149676500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 299354 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 299191 # Number of instructions committed
system.cpu.committedOps 299191 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 299008 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 1025 # Number of float alu accesses
system.cpu.num_func_calls 21816 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 44561 # number of instructions that are conditional controls
system.cpu.num_int_insts 299008 # number of integer instructions
system.cpu.num_fp_insts 1025 # number of float instructions
system.cpu.num_int_register_reads 394163 # number of times the integer registers were read
system.cpu.num_int_register_writes 205779 # number of times the integer registers were written
system.cpu.num_fp_register_reads 851 # number of times the floating registers were read
system.cpu.num_fp_register_writes 688 # number of times the floating registers were written
system.cpu.num_mem_refs 118390 # number of memory refs
system.cpu.num_load_insts 69843 # Number of load instructions
system.cpu.num_store_insts 48547 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 299354 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.Branches 66377 # Number of branches fetched
system.cpu.op_class::No_OpClass 162 0.05% 0.05% # Class of executed instruction
system.cpu.op_class::IntAlu 179913 60.10% 60.15% # Class of executed instruction
system.cpu.op_class::IntMult 466 0.16% 60.31% # Class of executed instruction
system.cpu.op_class::IntDiv 40 0.01% 60.32% # Class of executed instruction
system.cpu.op_class::FloatAdd 120 0.04% 60.36% # Class of executed instruction
system.cpu.op_class::FloatCmp 157 0.05% 60.42% # Class of executed instruction
system.cpu.op_class::FloatCvt 60 0.02% 60.44% # Class of executed instruction
system.cpu.op_class::FloatMult 30 0.01% 60.45% # Class of executed instruction
system.cpu.op_class::FloatMultAcc 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::FloatDiv 11 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::FloatMisc 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::FloatSqrt 5 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::MemRead 69348 23.17% 83.62% # Class of executed instruction
system.cpu.op_class::MemWrite 48400 16.17% 99.79% # Class of executed instruction
system.cpu.op_class::FloatMemRead 495 0.17% 99.95% # Class of executed instruction
system.cpu.op_class::FloatMemWrite 147 0.05% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 299354 # Class of executed instruction
system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 149676500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 369197 # Transaction distribution
system.membus.trans_dist::ReadResp 369197 # Transaction distribution
system.membus.trans_dist::WriteReq 48546 # Transaction distribution
system.membus.trans_dist::WriteResp 48546 # Transaction distribution
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 598708 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 236778 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 835486 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1197416 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 761126 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 1958542 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples 417743 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 417743 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 417743 # Request fanout histogram
---------- End Simulation Statistics ----------

1265
tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/config.ini Normal file
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File diff suppressed because it is too large Load diff

1734
tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/config.json Normal file
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File diff suppressed because it is too large Load diff

11
tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/simerr Executable file
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@ -0,0 +1,11 @@
warn: rounding error > tolerance
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Unknown operating system; assuming Linux.
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!

168
tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/simout Executable file
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@ -0,0 +1,168 @@
Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/simple-timing-ruby/simout
Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/simple-timing-ruby/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Nov 30 2016 14:33:35
gem5 started Nov 30 2016 16:18:32
gem5 executing on zizzer, pid 34074
command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/simple-timing-ruby -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64d/simple-timing-ruby
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
fld: PASS
fsd: PASS
fmadd.d: PASS
fmadd.d, quiet NaN: PASS
fmadd.d, signaling NaN: PASS
fmadd.d, infinity: PASS
fmadd.d, -infinity: PASS
fmsub.d: PASS
fmsub.d, quiet NaN: PASS
fmsub.d, signaling NaN: PASS
fmsub.d, infinity: PASS
fmsub.d, -infinity: PASS
fmsub.d, subtract infinity: PASS
fnmsub.d: PASS
fnmsub.d, quiet NaN: PASS
fnmsub.d, signaling NaN: PASS
fnmsub.d, infinity: PASS
fnmsub.d, -infinity: PASS
fnmsub.d, subtract infinity: PASS
fnmadd.d: PASS
fnmadd.d, quiet NaN: PASS
fnmadd.d, signaling NaN: PASS
fnmadd.d, infinity: PASS
fnmadd.d, -infinity: PASS
fadd.d: PASS
fadd.d, quiet NaN: PASS
fadd.d, signaling NaN: PASS
fadd.d, infinity: PASS
fadd.d, -infinity: PASS
fsub.d: PASS
fsub.d, quiet NaN: PASS
fsub.d, signaling NaN: PASS
fsub.d, infinity: PASS
fsub.d, -infinity: PASS
fsub.d, subtract infinity: PASS
fmul.d: PASS
fmul.d, quiet NaN: PASS
fmul.d, signaling NaN: PASS
fmul.d, infinity: PASS
fmul.d, -infinity: PASS
fmul.d, 0*infinity: PASS
fmul.d, overflow: PASS
fmul.d, underflow: PASS
fdiv.d: PASS
fdiv.d, quiet NaN: PASS
fdiv.d, signaling NaN: PASS
fdiv.d/0: PASS
fdiv.d/infinity: PASS
fdiv.d, infinity/infinity: PASS
fdiv.d, 0/0: PASS
fdiv.d, infinity/0: PASS
fdiv.d, 0/infinity: PASS
fdiv.d, underflow: PASS
fdiv.d, overflow: PASS
fsqrt.d: PASS
fsqrt.d, NaN: PASS
fsqrt.d, quiet NaN: PASS
fsqrt.d, signaling NaN: PASS
fsqrt.d, infinity: PASS
fsgnj.d, ++: PASS
fsgnj.d, +-: PASS
fsgnj.d, -+: PASS
fsgnj.d, --: PASS
fsgnj.d, quiet NaN: PASS
fsgnj.d, signaling NaN: PASS
fsgnj.d, inject NaN: PASS
fsgnj.d, inject -NaN: PASS
fsgnjn.d, ++: PASS
fsgnjn.d, +-: PASS
fsgnjn.d, -+: PASS
fsgnjn.d, --: PASS
fsgnjn.d, quiet NaN: PASS
fsgnjn.d, signaling NaN: PASS
fsgnjn.d, inject NaN: PASS
fsgnjn.d, inject NaN: PASS
fsgnjx.d, ++: PASS
fsgnjx.d, +-: PASS
fsgnjx.d, -+: PASS
fsgnjx.d, --: PASS
fsgnjx.d, quiet NaN: PASS
fsgnjx.d, signaling NaN: PASS
fsgnjx.d, inject NaN: PASS
fsgnjx.d, inject NaN: PASS
fmin.d: PASS
fmin.d, -infinity: PASS
fmin.d, infinity: PASS
fmin.d, quiet NaN first: PASS
fmin.d, quiet NaN second: PASS
fmin.d, quiet NaN both: PASS
fmin.d, signaling NaN first: PASS
fmin.d, signaling NaN second: PASS
fmin.d, signaling NaN both: PASS
fmax.d: PASS
fmax.d, -infinity: PASS
fmax.d, infinity: PASS
fmax.d, quiet NaN first: PASS
fmax.d, quiet NaN second: PASS
fmax.d, quiet NaN both: PASS
fmax.d, signaling NaN first: PASS
fmax.d, signaling NaN second: PASS
fmax.d, signaling NaN both: PASS
fcvt.s.d: PASS
fcvt.s.d, quiet NaN: PASS
fcvt.s.d, signaling NaN: PASS
fcvt.s.d, infinity: PASS
fcvt.s.d, overflow: PASS
fcvt.s.d, underflow: PASS
fcvt.d.s: PASS
fcvt.d.s, quiet NaN: PASS
fcvt.d.s, signaling NaN: PASS
fcvt.d.s, infinity: PASS
feq.d, equal: PASS
feq.d, not equal: PASS
feq.d, 0 == -0: PASS
feq.d, quiet NaN first: PASS
feq.d, quiet NaN second: PASS
feq.d, quiet NaN both: PASS
feq.d, signaling NaN first: PASS
feq.d, signaling NaN second: PASS
feq.d, signaling NaN both: PASS
flt.d, equal: PASS
flt.d, less: PASS
flt.d, greater: PASS
flt.d, quiet NaN first: PASS
flt.d, quiet NaN second: PASS
flt.d, quiet NaN both: PASS
flt.d, signaling NaN first: PASS
flt.d, signaling NaN second: PASS
flt.d, signaling NaN both: PASS
fle.d, equal: PASS
fle.d, less: PASS
fle.d, greater: PASS
fle.d, 0 == -0: PASS
fle.d, quiet NaN first: PASS
fle.d, quiet NaN second: PASS
fle.d, quiet NaN both: PASS
fle.d, signaling NaN first: PASS
fle.d, signaling NaN second: PASS
fle.d, signaling NaN both: PASS
fclass.d, -infinity: PASS
fclass.d, -normal: PASS
fclass.d, -subnormal: PASS
fclass.d, -0.0: PASS
fclass.d, 0.0: PASS
fclass.d, subnormal: PASS
fclass.d, normal: PASS
fclass.d, infinity: PASS
fclass.d, signaling NaN: PASS
fclass.s, quiet NaN: PASS
fcvt.w.d, truncate positive: PASS
fcvt.w.d, truncate negative: PASS
fcvt.w.d, 0.0: PASS
fcvt.w.d, -0.0: PASS
fcvt.w.d, overflow: FAIL (expected 2147483647; found -2147483648)
Exiting @ tick 6393532 because target called exit()

645
tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/stats.txt Normal file
View file

@ -0,0 +1,645 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.006394 # Number of seconds simulated
sim_ticks 6393532 # Number of ticks simulated
final_tick 6393532 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_inst_rate 13428 # Simulator instruction rate (inst/s)
host_op_rate 13428 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 286950 # Simulator tick rate (ticks/s)
host_mem_usage 412476 # Number of bytes of host memory used
host_seconds 22.28 # Real time elapsed on the host
sim_insts 299191 # Number of instructions simulated
sim_ops 299191 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 6256640 # Number of bytes read from this memory
system.mem_ctrls.bytes_read::total 6256640 # Number of bytes read from this memory
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 6256384 # Number of bytes written to this memory
system.mem_ctrls.bytes_written::total 6256384 # Number of bytes written to this memory
system.mem_ctrls.num_reads::ruby.dir_cntrl0 97760 # Number of read requests responded to by this memory
system.mem_ctrls.num_reads::total 97760 # Number of read requests responded to by this memory
system.mem_ctrls.num_writes::ruby.dir_cntrl0 97756 # Number of write requests responded to by this memory
system.mem_ctrls.num_writes::total 97756 # Number of write requests responded to by this memory
system.mem_ctrls.bw_read::ruby.dir_cntrl0 978588986 # Total read bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_read::total 978588986 # Total read bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_write::ruby.dir_cntrl0 978548946 # Write bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_write::total 978548946 # Write bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_total::ruby.dir_cntrl0 1957137933 # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.bw_total::total 1957137933 # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.readReqs 97760 # Number of read requests accepted
system.mem_ctrls.writeReqs 97756 # Number of write requests accepted
system.mem_ctrls.readBursts 97760 # Number of DRAM read bursts, including those serviced by the write queue
system.mem_ctrls.writeBursts 97756 # Number of DRAM write bursts, including those merged in the write queue
system.mem_ctrls.bytesReadDRAM 3295040 # Total number of bytes read from DRAM
system.mem_ctrls.bytesReadWrQ 2961600 # Total number of bytes read from write queue
system.mem_ctrls.bytesWritten 3443712 # Total number of bytes written to DRAM
system.mem_ctrls.bytesReadSys 6256640 # Total read bytes from the system interface side
system.mem_ctrls.bytesWrittenSys 6256384 # Total written bytes from the system interface side
system.mem_ctrls.servicedByWrQ 46275 # Number of DRAM read bursts serviced by the write queue
system.mem_ctrls.mergedWrBursts 43917 # Number of DRAM write bursts merged with an existing one
system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.mem_ctrls.perBankRdBursts::0 352 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::1 1012 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::2 26 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::3 3288 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::4 5256 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::5 9431 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::6 7439 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::7 1368 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::8 225 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::9 1039 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::10 2533 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::11 14031 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::12 3005 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::13 1537 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::14 25 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::15 918 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::0 359 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::1 1066 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::2 34 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::3 3555 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::4 5446 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::5 9633 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::6 8466 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::7 1431 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::8 225 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::9 1069 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::10 2579 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::11 14351 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::12 3053 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::13 1590 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::14 28 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::15 923 # Per bank write bursts
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
system.mem_ctrls.totGap 6393460 # Total gap between requests
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::6 97760 # Read request sizes (log2)
system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::6 97756 # Write request sizes (log2)
system.mem_ctrls.rdQLenPdf::0 51485 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::15 306 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::16 334 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::17 2779 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::18 3333 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::19 3383 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::20 3473 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::21 3559 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::22 3516 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::23 3321 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::24 3315 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::25 3314 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::26 3314 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::27 3314 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::28 3313 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::29 3313 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::30 3313 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::31 3312 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::32 3312 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.mem_ctrls.bytesPerActivate::samples 20661 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::mean 326.074440 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::gmean 208.715959 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::stdev 320.266569 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::0-127 5014 24.27% 24.27% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::128-255 6296 30.47% 54.74% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::256-383 3457 16.73% 71.47% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::384-511 1315 6.36% 77.84% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::512-639 736 3.56% 81.40% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::640-767 594 2.87% 84.27% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::768-895 389 1.88% 86.16% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::896-1023 293 1.42% 87.58% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::1024-1151 2567 12.42% 100.00% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::total 20661 # Bytes accessed per row activation
system.mem_ctrls.rdPerTurnAround::samples 3312 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::mean 15.540459 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::gmean 15.485552 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::stdev 1.332467 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::12-13 139 4.20% 4.20% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::14-15 1517 45.80% 50.00% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::16-17 1421 42.90% 92.90% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::18-19 229 6.91% 99.82% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::20-21 5 0.15% 99.97% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::36-37 1 0.03% 100.00% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::total 3312 # Reads before turning the bus around for writes
system.mem_ctrls.wrPerTurnAround::samples 3312 # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::mean 16.246377 # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::gmean 16.229566 # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::stdev 0.773105 # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::16 2986 90.16% 90.16% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::17 14 0.42% 90.58% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::18 147 4.44% 95.02% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::19 153 4.62% 99.64% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::20 11 0.33% 99.97% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::21 1 0.03% 100.00% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::total 3312 # Writes before turning the bus around for reads
system.mem_ctrls.totQLat 1034437 # Total ticks spent queuing
system.mem_ctrls.totMemAccLat 2012652 # Total ticks spent from burst creation until serviced by the DRAM
system.mem_ctrls.totBusLat 257425 # Total ticks spent in databus transfers
system.mem_ctrls.avgQLat 20.09 # Average queueing delay per DRAM burst
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
system.mem_ctrls.avgMemAccLat 39.09 # Average memory access latency per DRAM burst
system.mem_ctrls.avgRdBW 515.37 # Average DRAM read bandwidth in MiByte/s
system.mem_ctrls.avgWrBW 538.62 # Average achieved write bandwidth in MiByte/s
system.mem_ctrls.avgRdBWSys 978.59 # Average system read bandwidth in MiByte/s
system.mem_ctrls.avgWrBWSys 978.55 # Average system write bandwidth in MiByte/s
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.mem_ctrls.busUtil 8.23 # Data bus utilization in percentage
system.mem_ctrls.busUtilRead 4.03 # Data bus utilization in percentage for reads
system.mem_ctrls.busUtilWrite 4.21 # Data bus utilization in percentage for writes
system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing
system.mem_ctrls.avgWrQLen 25.90 # Average write queue length when enqueuing
system.mem_ctrls.readRowHits 36136 # Number of row buffer hits during reads
system.mem_ctrls.writeRowHits 48490 # Number of row buffer hits during writes
system.mem_ctrls.readRowHitRate 70.19 # Row buffer hit rate for reads
system.mem_ctrls.writeRowHitRate 90.06 # Row buffer hit rate for writes
system.mem_ctrls.avgGap 32.70 # Average gap between requests
system.mem_ctrls.pageHitRate 80.35 # Row buffer hit rate, read and write combined
system.mem_ctrls_0.actEnergy 95226180 # Energy for activate commands per rank (pJ)
system.mem_ctrls_0.preEnergy 51522576 # Energy for precharge commands per rank (pJ)
system.mem_ctrls_0.readEnergy 321836928 # Energy for read commands per rank (pJ)
system.mem_ctrls_0.writeEnergy 250476480 # Energy for write commands per rank (pJ)
system.mem_ctrls_0.refreshEnergy 501546240.000000 # Energy for refresh commands per rank (pJ)
system.mem_ctrls_0.actBackEnergy 829542432 # Energy for active background per rank (pJ)
system.mem_ctrls_0.preBackEnergy 11702016 # Energy for precharge background per rank (pJ)
system.mem_ctrls_0.actPowerDownEnergy 1925180016 # Energy for active power-down per rank (pJ)
system.mem_ctrls_0.prePowerDownEnergy 78745728 # Energy for precharge power-down per rank (pJ)
system.mem_ctrls_0.selfRefreshEnergy 34138560 # Energy for self refresh per rank (pJ)
system.mem_ctrls_0.totalEnergy 4099917156 # Total energy per rank (pJ)
system.mem_ctrls_0.averagePower 641.260129 # Core power per rank (mW)
system.mem_ctrls_0.totalIdleTime 4543849 # Total Idle time Per DRAM Rank
system.mem_ctrls_0.memoryStateTime::IDLE 6758 # Time in different power states
system.mem_ctrls_0.memoryStateTime::REF 212226 # Time in different power states
system.mem_ctrls_0.memoryStateTime::SREF 116933 # Time in different power states
system.mem_ctrls_0.memoryStateTime::PRE_PDN 205067 # Time in different power states
system.mem_ctrls_0.memoryStateTime::ACT 1630662 # Time in different power states
system.mem_ctrls_0.memoryStateTime::ACT_PDN 4221886 # Time in different power states
system.mem_ctrls_1.actEnergy 52336200 # Energy for activate commands per rank (pJ)
system.mem_ctrls_1.preEnergy 28311528 # Energy for precharge commands per rank (pJ)
system.mem_ctrls_1.readEnergy 266327712 # Energy for read commands per rank (pJ)
system.mem_ctrls_1.writeEnergy 198927936 # Energy for write commands per rank (pJ)
system.mem_ctrls_1.refreshEnergy 482492400.000000 # Energy for refresh commands per rank (pJ)
system.mem_ctrls_1.actBackEnergy 818266464 # Energy for active background per rank (pJ)
system.mem_ctrls_1.preBackEnergy 13925376 # Energy for precharge background per rank (pJ)
system.mem_ctrls_1.actPowerDownEnergy 1847919480 # Energy for active power-down per rank (pJ)
system.mem_ctrls_1.prePowerDownEnergy 72638976 # Energy for precharge power-down per rank (pJ)
system.mem_ctrls_1.selfRefreshEnergy 80402640 # Energy for self refresh per rank (pJ)
system.mem_ctrls_1.totalEnergy 3861548712 # Total energy per rank (pJ)
system.mem_ctrls_1.averagePower 603.977381 # Core power per rank (mW)
system.mem_ctrls_1.totalIdleTime 4562502 # Total Idle time Per DRAM Rank
system.mem_ctrls_1.memoryStateTime::IDLE 13661 # Time in different power states
system.mem_ctrls_1.memoryStateTime::REF 204136 # Time in different power states
system.mem_ctrls_1.memoryStateTime::SREF 321205 # Time in different power states
system.mem_ctrls_1.memoryStateTime::PRE_PDN 189164 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT 1612911 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT_PDN 4052455 # Time in different power states
system.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states
system.cpu.clk_domain.clock 1 # Clock period in ticks
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 162 # Number of system calls
system.cpu.pwrStateResidencyTicks::ON 6393532 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 6393532 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 299191 # Number of instructions committed
system.cpu.committedOps 299191 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 299008 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 1025 # Number of float alu accesses
system.cpu.num_func_calls 21816 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 44561 # number of instructions that are conditional controls
system.cpu.num_int_insts 299008 # number of integer instructions
system.cpu.num_fp_insts 1025 # number of float instructions
system.cpu.num_int_register_reads 394163 # number of times the integer registers were read
system.cpu.num_int_register_writes 205779 # number of times the integer registers were written
system.cpu.num_fp_register_reads 851 # number of times the floating registers were read
system.cpu.num_fp_register_writes 688 # number of times the floating registers were written
system.cpu.num_mem_refs 118390 # number of memory refs
system.cpu.num_load_insts 69843 # Number of load instructions
system.cpu.num_store_insts 48547 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 6393532 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.Branches 66377 # Number of branches fetched
system.cpu.op_class::No_OpClass 162 0.05% 0.05% # Class of executed instruction
system.cpu.op_class::IntAlu 179913 60.10% 60.15% # Class of executed instruction
system.cpu.op_class::IntMult 466 0.16% 60.31% # Class of executed instruction
system.cpu.op_class::IntDiv 40 0.01% 60.32% # Class of executed instruction
system.cpu.op_class::FloatAdd 120 0.04% 60.36% # Class of executed instruction
system.cpu.op_class::FloatCmp 157 0.05% 60.42% # Class of executed instruction
system.cpu.op_class::FloatCvt 60 0.02% 60.44% # Class of executed instruction
system.cpu.op_class::FloatMult 30 0.01% 60.45% # Class of executed instruction
system.cpu.op_class::FloatMultAcc 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::FloatDiv 11 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::FloatMisc 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::FloatSqrt 5 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::MemRead 69348 23.17% 83.62% # Class of executed instruction
system.cpu.op_class::MemWrite 48400 16.17% 99.79% # Class of executed instruction
system.cpu.op_class::FloatMemRead 495 0.17% 99.95% # Class of executed instruction
system.cpu.op_class::FloatMemWrite 147 0.05% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 299354 # Class of executed instruction
system.ruby.clk_domain.clock 1 # Clock period in ticks
system.ruby.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states
system.ruby.delayHist::bucket_size 1 # delay histogram for all message
system.ruby.delayHist::max_bucket 9 # delay histogram for all message
system.ruby.delayHist::samples 195516 # delay histogram for all message
system.ruby.delayHist | 195516 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message
system.ruby.delayHist::total 195516 # delay histogram for all message
system.ruby.outstanding_req_hist_seqr::bucket_size 1
system.ruby.outstanding_req_hist_seqr::max_bucket 9
system.ruby.outstanding_req_hist_seqr::samples 417744
system.ruby.outstanding_req_hist_seqr::mean 1
system.ruby.outstanding_req_hist_seqr::gmean 1
system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 417744 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.outstanding_req_hist_seqr::total 417744
system.ruby.latency_hist_seqr::bucket_size 64
system.ruby.latency_hist_seqr::max_bucket 639
system.ruby.latency_hist_seqr::samples 417743
system.ruby.latency_hist_seqr::mean 14.304941
system.ruby.latency_hist_seqr::gmean 2.506373
system.ruby.latency_hist_seqr::stdev 29.993401
system.ruby.latency_hist_seqr | 367877 88.06% 88.06% | 46330 11.09% 99.15% | 2431 0.58% 99.74% | 380 0.09% 99.83% | 382 0.09% 99.92% | 309 0.07% 99.99% | 15 0.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00% | 16 0.00% 100.00%
system.ruby.latency_hist_seqr::total 417743
system.ruby.hit_latency_hist_seqr::bucket_size 1
system.ruby.hit_latency_hist_seqr::max_bucket 9
system.ruby.hit_latency_hist_seqr::samples 319983
system.ruby.hit_latency_hist_seqr::mean 1
system.ruby.hit_latency_hist_seqr::gmean 1
system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 319983 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.hit_latency_hist_seqr::total 319983
system.ruby.miss_latency_hist_seqr::bucket_size 64
system.ruby.miss_latency_hist_seqr::max_bucket 639
system.ruby.miss_latency_hist_seqr::samples 97760
system.ruby.miss_latency_hist_seqr::mean 57.853989
system.ruby.miss_latency_hist_seqr::gmean 50.720255
system.ruby.miss_latency_hist_seqr::stdev 36.989317
system.ruby.miss_latency_hist_seqr | 47894 48.99% 48.99% | 46330 47.39% 96.38% | 2431 2.49% 98.87% | 380 0.39% 99.26% | 382 0.39% 99.65% | 309 0.32% 99.97% | 15 0.02% 99.98% | 3 0.00% 99.98% | 0 0.00% 99.98% | 16 0.02% 100.00%
system.ruby.miss_latency_hist_seqr::total 97760
system.ruby.Directory.incomplete_times_seqr 97759
system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl0.cacheMemory.demand_hits 319983 # Number of cache demand hits
system.ruby.l1_cntrl0.cacheMemory.demand_misses 97760 # Number of cache demand misses
system.ruby.l1_cntrl0.cacheMemory.demand_accesses 417743 # Number of cache demand accesses
system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states
system.ruby.network.routers0.percent_links_utilized 7.645070
system.ruby.network.routers0.msg_count.Control::2 97760
system.ruby.network.routers0.msg_count.Data::2 97756
system.ruby.network.routers0.msg_count.Response_Data::4 97760
system.ruby.network.routers0.msg_count.Writeback_Control::3 97756
system.ruby.network.routers0.msg_bytes.Control::2 782080
system.ruby.network.routers0.msg_bytes.Data::2 7038432
system.ruby.network.routers0.msg_bytes.Response_Data::4 7038720
system.ruby.network.routers0.msg_bytes.Writeback_Control::3 782048
system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states
system.ruby.network.routers1.percent_links_utilized 7.645070
system.ruby.network.routers1.msg_count.Control::2 97760
system.ruby.network.routers1.msg_count.Data::2 97756
system.ruby.network.routers1.msg_count.Response_Data::4 97760
system.ruby.network.routers1.msg_count.Writeback_Control::3 97756
system.ruby.network.routers1.msg_bytes.Control::2 782080
system.ruby.network.routers1.msg_bytes.Data::2 7038432
system.ruby.network.routers1.msg_bytes.Response_Data::4 7038720
system.ruby.network.routers1.msg_bytes.Writeback_Control::3 782048
system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states
system.ruby.network.routers2.percent_links_utilized 7.645070
system.ruby.network.routers2.msg_count.Control::2 97760
system.ruby.network.routers2.msg_count.Data::2 97756
system.ruby.network.routers2.msg_count.Response_Data::4 97760
system.ruby.network.routers2.msg_count.Writeback_Control::3 97756
system.ruby.network.routers2.msg_bytes.Control::2 782080
system.ruby.network.routers2.msg_bytes.Data::2 7038432
system.ruby.network.routers2.msg_bytes.Response_Data::4 7038720
system.ruby.network.routers2.msg_bytes.Writeback_Control::3 782048
system.ruby.network.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states
system.ruby.network.msg_count.Control 293280
system.ruby.network.msg_count.Data 293268
system.ruby.network.msg_count.Response_Data 293280
system.ruby.network.msg_count.Writeback_Control 293268
system.ruby.network.msg_byte.Control 2346240
system.ruby.network.msg_byte.Data 21115296
system.ruby.network.msg_byte.Response_Data 21116160
system.ruby.network.msg_byte.Writeback_Control 2346144
system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states
system.ruby.network.routers0.throttle0.link_utilization 7.645195
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 97760
system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 97756
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 7038720
system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 782048
system.ruby.network.routers0.throttle1.link_utilization 7.644945
system.ruby.network.routers0.throttle1.msg_count.Control::2 97760
system.ruby.network.routers0.throttle1.msg_count.Data::2 97756
system.ruby.network.routers0.throttle1.msg_bytes.Control::2 782080
system.ruby.network.routers0.throttle1.msg_bytes.Data::2 7038432
system.ruby.network.routers1.throttle0.link_utilization 7.644945
system.ruby.network.routers1.throttle0.msg_count.Control::2 97760
system.ruby.network.routers1.throttle0.msg_count.Data::2 97756
system.ruby.network.routers1.throttle0.msg_bytes.Control::2 782080
system.ruby.network.routers1.throttle0.msg_bytes.Data::2 7038432
system.ruby.network.routers1.throttle1.link_utilization 7.645195
system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 97760
system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 97756
system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 7038720
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 782048
system.ruby.network.routers2.throttle0.link_utilization 7.645195
system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 97760
system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 97756
system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 7038720
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 782048
system.ruby.network.routers2.throttle1.link_utilization 7.644945
system.ruby.network.routers2.throttle1.msg_count.Control::2 97760
system.ruby.network.routers2.throttle1.msg_count.Data::2 97756
system.ruby.network.routers2.throttle1.msg_bytes.Control::2 782080
system.ruby.network.routers2.throttle1.msg_bytes.Data::2 7038432
system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1::samples 97760 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1 | 97760 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1::total 97760 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2::samples 97756 # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2 | 97756 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2::total 97756 # delay histogram for vnet_2
system.ruby.LD.latency_hist_seqr::bucket_size 64
system.ruby.LD.latency_hist_seqr::max_bucket 639
system.ruby.LD.latency_hist_seqr::samples 69843
system.ruby.LD.latency_hist_seqr::mean 28.322194
system.ruby.LD.latency_hist_seqr::gmean 7.510857
system.ruby.LD.latency_hist_seqr::stdev 36.108227
system.ruby.LD.latency_hist_seqr | 55897 80.03% 80.03% | 12888 18.45% 98.49% | 741 1.06% 99.55% | 131 0.19% 99.73% | 105 0.15% 99.88% | 76 0.11% 99.99% | 4 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00%
system.ruby.LD.latency_hist_seqr::total 69843
system.ruby.LD.hit_latency_hist_seqr::bucket_size 1
system.ruby.LD.hit_latency_hist_seqr::max_bucket 9
system.ruby.LD.hit_latency_hist_seqr::samples 33083
system.ruby.LD.hit_latency_hist_seqr::mean 1
system.ruby.LD.hit_latency_hist_seqr::gmean 1
system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 33083 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.hit_latency_hist_seqr::total 33083
system.ruby.LD.miss_latency_hist_seqr::bucket_size 64
system.ruby.LD.miss_latency_hist_seqr::max_bucket 639
system.ruby.LD.miss_latency_hist_seqr::samples 36760
system.ruby.LD.miss_latency_hist_seqr::mean 52.911425
system.ruby.LD.miss_latency_hist_seqr::gmean 46.109058
system.ruby.LD.miss_latency_hist_seqr::stdev 34.651513
system.ruby.LD.miss_latency_hist_seqr | 22814 62.06% 62.06% | 12888 35.06% 97.12% | 741 2.02% 99.14% | 131 0.36% 99.49% | 105 0.29% 99.78% | 76 0.21% 99.99% | 4 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00%
system.ruby.LD.miss_latency_hist_seqr::total 36760
system.ruby.ST.latency_hist_seqr::bucket_size 64
system.ruby.ST.latency_hist_seqr::max_bucket 639
system.ruby.ST.latency_hist_seqr::samples 48546
system.ruby.ST.latency_hist_seqr::mean 14.735838
system.ruby.ST.latency_hist_seqr::gmean 3.058930
system.ruby.ST.latency_hist_seqr::stdev 27.657147
system.ruby.ST.latency_hist_seqr | 44298 91.25% 91.25% | 3958 8.15% 99.40% | 180 0.37% 99.77% | 35 0.07% 99.85% | 42 0.09% 99.93% | 23 0.05% 99.98% | 0 0.00% 99.98% | 0 0.00% 99.98% | 0 0.00% 99.98% | 10 0.02% 100.00%
system.ruby.ST.latency_hist_seqr::total 48546
system.ruby.ST.hit_latency_hist_seqr::bucket_size 1
system.ruby.ST.hit_latency_hist_seqr::max_bucket 9
system.ruby.ST.hit_latency_hist_seqr::samples 33996
system.ruby.ST.hit_latency_hist_seqr::mean 1
system.ruby.ST.hit_latency_hist_seqr::gmean 1
system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 33996 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.hit_latency_hist_seqr::total 33996
system.ruby.ST.miss_latency_hist_seqr::bucket_size 64
system.ruby.ST.miss_latency_hist_seqr::max_bucket 639
system.ruby.ST.miss_latency_hist_seqr::samples 14550
system.ruby.ST.miss_latency_hist_seqr::mean 46.829553
system.ruby.ST.miss_latency_hist_seqr::gmean 41.696554
system.ruby.ST.miss_latency_hist_seqr::stdev 32.883513
system.ruby.ST.miss_latency_hist_seqr | 10302 70.80% 70.80% | 3958 27.20% 98.01% | 180 1.24% 99.24% | 35 0.24% 99.48% | 42 0.29% 99.77% | 23 0.16% 99.93% | 0 0.00% 99.93% | 0 0.00% 99.93% | 0 0.00% 99.93% | 10 0.07% 100.00%
system.ruby.ST.miss_latency_hist_seqr::total 14550
system.ruby.IFETCH.latency_hist_seqr::bucket_size 64
system.ruby.IFETCH.latency_hist_seqr::max_bucket 639
system.ruby.IFETCH.latency_hist_seqr::samples 299354
system.ruby.IFETCH.latency_hist_seqr::mean 10.964664
system.ruby.IFETCH.latency_hist_seqr::gmean 1.878483
system.ruby.IFETCH.latency_hist_seqr::stdev 27.751002
system.ruby.IFETCH.latency_hist_seqr | 267682 89.42% 89.42% | 29484 9.85% 99.27% | 1510 0.50% 99.77% | 214 0.07% 99.84% | 235 0.08% 99.92% | 210 0.07% 99.99% | 11 0.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00% | 5 0.00% 100.00%
system.ruby.IFETCH.latency_hist_seqr::total 299354
system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1
system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9
system.ruby.IFETCH.hit_latency_hist_seqr::samples 252904
system.ruby.IFETCH.hit_latency_hist_seqr::mean 1
system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1
system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 252904 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.hit_latency_hist_seqr::total 252904
system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64
system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639
system.ruby.IFETCH.miss_latency_hist_seqr::samples 46450
system.ruby.IFETCH.miss_latency_hist_seqr::mean 65.218773
system.ruby.IFETCH.miss_latency_hist_seqr::gmean 58.155656
system.ruby.IFETCH.miss_latency_hist_seqr::stdev 38.458091
system.ruby.IFETCH.miss_latency_hist_seqr | 14778 31.81% 31.81% | 29484 63.47% 95.29% | 1510 3.25% 98.54% | 214 0.46% 99.00% | 235 0.51% 99.51% | 210 0.45% 99.96% | 11 0.02% 99.98% | 3 0.01% 99.99% | 0 0.00% 99.99% | 5 0.01% 100.00%
system.ruby.IFETCH.miss_latency_hist_seqr::total 46450
system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64
system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639
system.ruby.Directory.miss_mach_latency_hist_seqr::samples 97760
system.ruby.Directory.miss_mach_latency_hist_seqr::mean 57.853989
system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 50.720255
system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 36.989317
system.ruby.Directory.miss_mach_latency_hist_seqr | 47894 48.99% 48.99% | 46330 47.39% 96.38% | 2431 2.49% 98.87% | 380 0.39% 99.26% | 382 0.39% 99.65% | 309 0.32% 99.97% | 15 0.02% 99.98% | 3 0.00% 99.98% | 0 0.00% 99.98% | 16 0.02% 100.00%
system.ruby.Directory.miss_mach_latency_hist_seqr::total 97760
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 1
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::stdev nan
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::total 1
system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::bucket_size 1
system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::max_bucket 9
system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::samples 1
system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::stdev nan
system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::total 1
system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::bucket_size 1
system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::max_bucket 9
system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::samples 1
system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::stdev nan
system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::total 1
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::bucket_size 8
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::max_bucket 79
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::samples 1
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::mean 75
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::gmean 75.000000
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::stdev nan
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00%
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 36760
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 52.911425
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 46.109058
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 34.651513
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 22814 62.06% 62.06% | 12888 35.06% 97.12% | 741 2.02% 99.14% | 131 0.36% 99.49% | 105 0.29% 99.78% | 76 0.21% 99.99% | 4 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00%
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 36760
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 14550
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 46.829553
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 41.696554
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 32.883513
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 10302 70.80% 70.80% | 3958 27.20% 98.01% | 180 1.24% 99.24% | 35 0.24% 99.48% | 42 0.29% 99.77% | 23 0.16% 99.93% | 0 0.00% 99.93% | 0 0.00% 99.93% | 0 0.00% 99.93% | 10 0.07% 100.00%
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 14550
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 46450
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 65.218773
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 58.155656
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 38.458091
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 14778 31.81% 31.81% | 29484 63.47% 95.29% | 1510 3.25% 98.54% | 214 0.46% 99.00% | 235 0.51% 99.51% | 210 0.45% 99.96% | 11 0.02% 99.98% | 3 0.01% 99.99% | 0 0.00% 99.99% | 5 0.01% 100.00%
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 46450
system.ruby.Directory_Controller.GETX 97760 0.00% 0.00%
system.ruby.Directory_Controller.PUTX 97756 0.00% 0.00%
system.ruby.Directory_Controller.Memory_Data 97760 0.00% 0.00%
system.ruby.Directory_Controller.Memory_Ack 97756 0.00% 0.00%
system.ruby.Directory_Controller.I.GETX 97760 0.00% 0.00%
system.ruby.Directory_Controller.M.PUTX 97756 0.00% 0.00%
system.ruby.Directory_Controller.IM.Memory_Data 97760 0.00% 0.00%
system.ruby.Directory_Controller.MI.Memory_Ack 97756 0.00% 0.00%
system.ruby.L1Cache_Controller.Load 69843 0.00% 0.00%
system.ruby.L1Cache_Controller.Ifetch 299354 0.00% 0.00%
system.ruby.L1Cache_Controller.Store 48546 0.00% 0.00%
system.ruby.L1Cache_Controller.Data 97760 0.00% 0.00%
system.ruby.L1Cache_Controller.Replacement 97756 0.00% 0.00%
system.ruby.L1Cache_Controller.Writeback_Ack 97756 0.00% 0.00%
system.ruby.L1Cache_Controller.I.Load 36760 0.00% 0.00%
system.ruby.L1Cache_Controller.I.Ifetch 46450 0.00% 0.00%
system.ruby.L1Cache_Controller.I.Store 14550 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Load 33083 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Ifetch 252904 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Store 33996 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Replacement 97756 0.00% 0.00%
system.ruby.L1Cache_Controller.MI.Writeback_Ack 97756 0.00% 0.00%
system.ruby.L1Cache_Controller.IS.Data 83210 0.00% 0.00%
system.ruby.L1Cache_Controller.IM.Data 14550 0.00% 0.00%
---------- End Simulation Statistics ----------

380
tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing/config.ini Normal file
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[root]
type=Root
children=system
eventq_index=0
full_system=false
sim_quantum=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.clk_domain]
type=SrcClockDomain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.cpu]
type=TimingSimpleCPU
children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
branchPred=Null
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
default_p_state=UNDEFINED
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
eventq_index=0
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
profile=0
progress_interval=0
simpoint_start_insts=
socket_id=0
switched_out=false
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
is_read_only=false
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=262144
system=system
tag_latency=2
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dcache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=262144
tag_latency=2
[system.cpu.dtb]
type=RiscvTLB
eventq_index=0
size=64
[system.cpu.icache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
is_read_only=true
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=131072
system=system
tag_latency=2
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=true
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.icache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=131072
tag_latency=2
[system.cpu.interrupts]
type=RiscvInterrupts
eventq_index=0
[system.cpu.isa]
type=RiscvISA
eventq_index=0
[system.cpu.itb]
type=RiscvTLB
eventq_index=0
size=64
[system.cpu.l2cache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=20
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
is_read_only=false
max_miss_count=0
mshrs=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=20
sequential_access=false
size=2097152
system=system
tag_latency=20
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.l2cache.tags]
type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=20
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=2097152
tag_latency=20
[system.cpu.toL2Bus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=0
frontend_latency=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=false
power_model=Null
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.toL2Bus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=0
max_capacity=8388608
system=system
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=LiveProcess
cmd=insttest
cwd=
drivers=
egid=100
env=
errout=cerr
euid=100
eventq_index=0
executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64d/insttest
gid=100
input=cin
kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.dvfs_handler]
type=DVFSHandler
domains=
enable=false
eventq_index=0
sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=4
frontend_latency=3
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
clk_domain=system.clk_domain
conf_table_reported=true
default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
kvm_map=true
latency=30000
latency_var=0
null=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
range=0:134217727:0:0:0:0
port=system.membus.master[0]
[system.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.000000

508
tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing/config.json Normal file
View file

@ -0,0 +1,508 @@
{
"name": null,
"sim_quantum": 0,
"system": {
"kernel": "",
"mmap_using_noreserve": false,
"kernel_addr_check": true,
"membus": {
"point_of_coherency": true,
"system": "system",
"response_latency": 2,
"cxx_class": "CoherentXBar",
"forward_latency": 4,
"clk_domain": "system.clk_domain",
"width": 16,
"eventq_index": 0,
"default_p_state": "UNDEFINED",
"p_state_clk_gate_max": 1000000000000,
"master": {
"peer": [
"system.physmem.port"
],
"role": "MASTER"
},
"type": "CoherentXBar",
"frontend_latency": 3,
"slave": {
"peer": [
"system.system_port",
"system.cpu.l2cache.mem_side"
],
"role": "SLAVE"
},
"p_state_clk_gate_min": 1000,
"snoop_filter": {
"name": "snoop_filter",
"system": "system",
"max_capacity": 8388608,
"eventq_index": 0,
"cxx_class": "SnoopFilter",
"path": "system.membus.snoop_filter",
"type": "SnoopFilter",
"lookup_latency": 1
},
"power_model": null,
"path": "system.membus",
"snoop_response_latency": 4,
"name": "membus",
"p_state_clk_gate_bins": 20,
"use_default_range": false
},
"symbolfile": "",
"readfile": "",
"thermal_model": null,
"cxx_class": "System",
"work_begin_cpu_id_exit": -1,
"load_offset": 0,
"work_begin_exit_count": 0,
"p_state_clk_gate_min": 1000,
"memories": [
"system.physmem"
],
"work_begin_ckpt_count": 0,
"clk_domain": {
"name": "clk_domain",
"clock": [
1000
],
"init_perf_level": 0,
"voltage_domain": "system.voltage_domain",
"eventq_index": 0,
"cxx_class": "SrcClockDomain",
"path": "system.clk_domain",
"type": "SrcClockDomain",
"domain_id": -1
},
"mem_ranges": [],
"eventq_index": 0,
"default_p_state": "UNDEFINED",
"p_state_clk_gate_max": 1000000000000,
"dvfs_handler": {
"enable": false,
"name": "dvfs_handler",
"sys_clk_domain": "system.clk_domain",
"transition_latency": 100000000,
"eventq_index": 0,
"cxx_class": "DVFSHandler",
"domains": [],
"path": "system.dvfs_handler",
"type": "DVFSHandler"
},
"work_end_exit_count": 0,
"type": "System",
"voltage_domain": {
"name": "voltage_domain",
"eventq_index": 0,
"voltage": [
"1.0"
],
"cxx_class": "VoltageDomain",
"path": "system.voltage_domain",
"type": "VoltageDomain"
},
"cache_line_size": 64,
"boot_osflags": "a",
"system_port": {
"peer": "system.membus.slave[0]",
"role": "MASTER"
},
"physmem": {
"range": "0:134217727:0:0:0:0",
"latency": 30000,
"name": "physmem",
"p_state_clk_gate_min": 1000,
"eventq_index": 0,
"p_state_clk_gate_bins": 20,
"default_p_state": "UNDEFINED",
"kvm_map": true,
"clk_domain": "system.clk_domain",
"power_model": null,
"latency_var": 0,
"bandwidth": "73.000000",
"conf_table_reported": true,
"cxx_class": "SimpleMemory",
"p_state_clk_gate_max": 1000000000000,
"path": "system.physmem",
"null": false,
"type": "SimpleMemory",
"port": {
"peer": "system.membus.master[0]",
"role": "SLAVE"
},
"in_addr_map": true
},
"power_model": null,
"work_cpus_ckpt_count": 0,
"thermal_components": [],
"path": "system",
"cpu_clk_domain": {
"name": "cpu_clk_domain",
"clock": [
500
],
"init_perf_level": 0,
"voltage_domain": "system.voltage_domain",
"eventq_index": 0,
"cxx_class": "SrcClockDomain",
"path": "system.cpu_clk_domain",
"type": "SrcClockDomain",
"domain_id": -1
},
"work_end_ckpt_count": 0,
"mem_mode": "timing",
"name": "system",
"init_param": 0,
"p_state_clk_gate_bins": 20,
"load_addr_mask": 1099511627775,
"cpu": [
{
"do_statistics_insts": true,
"numThreads": 1,
"itb": {
"name": "itb",
"eventq_index": 0,
"cxx_class": "RiscvISA::TLB",
"path": "system.cpu.itb",
"type": "RiscvTLB",
"size": 64
},
"system": "system",
"icache": {
"cpu_side": {
"peer": "system.cpu.icache_port",
"role": "SLAVE"
},
"clusivity": "mostly_incl",
"prefetcher": null,
"system": "system",
"write_buffers": 8,
"response_latency": 2,
"cxx_class": "Cache",
"size": 131072,
"type": "Cache",
"clk_domain": "system.cpu_clk_domain",
"max_miss_count": 0,
"eventq_index": 0,
"default_p_state": "UNDEFINED",
"p_state_clk_gate_max": 1000000000000,
"mem_side": {
"peer": "system.cpu.toL2Bus.slave[0]",
"role": "MASTER"
},
"mshrs": 4,
"writeback_clean": true,
"p_state_clk_gate_min": 1000,
"tags": {
"size": 131072,
"tag_latency": 2,
"name": "tags",
"p_state_clk_gate_min": 1000,
"eventq_index": 0,
"p_state_clk_gate_bins": 20,
"default_p_state": "UNDEFINED",
"clk_domain": "system.cpu_clk_domain",
"power_model": null,
"sequential_access": false,
"assoc": 2,
"cxx_class": "LRU",
"p_state_clk_gate_max": 1000000000000,
"path": "system.cpu.icache.tags",
"block_size": 64,
"type": "LRU",
"data_latency": 2
},
"tgts_per_mshr": 20,
"demand_mshr_reserve": 1,
"power_model": null,
"addr_ranges": [
"0:18446744073709551615:0:0:0:0"
],
"is_read_only": true,
"prefetch_on_access": false,
"path": "system.cpu.icache",
"data_latency": 2,
"tag_latency": 2,
"name": "icache",
"p_state_clk_gate_bins": 20,
"sequential_access": false,
"assoc": 2
},
"function_trace": false,
"do_checkpoint_insts": true,
"cxx_class": "TimingSimpleCPU",
"max_loads_all_threads": 0,
"clk_domain": "system.cpu_clk_domain",
"function_trace_start": 0,
"cpu_id": 0,
"checker": null,
"eventq_index": 0,
"default_p_state": "UNDEFINED",
"p_state_clk_gate_max": 1000000000000,
"toL2Bus": {
"point_of_coherency": false,
"system": "system",
"response_latency": 1,
"cxx_class": "CoherentXBar",
"forward_latency": 0,
"clk_domain": "system.cpu_clk_domain",
"width": 32,
"eventq_index": 0,
"default_p_state": "UNDEFINED",
"p_state_clk_gate_max": 1000000000000,
"master": {
"peer": [
"system.cpu.l2cache.cpu_side"
],
"role": "MASTER"
},
"type": "CoherentXBar",
"frontend_latency": 1,
"slave": {
"peer": [
"system.cpu.icache.mem_side",
"system.cpu.dcache.mem_side"
],
"role": "SLAVE"
},
"p_state_clk_gate_min": 1000,
"snoop_filter": {
"name": "snoop_filter",
"system": "system",
"max_capacity": 8388608,
"eventq_index": 0,
"cxx_class": "SnoopFilter",
"path": "system.cpu.toL2Bus.snoop_filter",
"type": "SnoopFilter",
"lookup_latency": 0
},
"power_model": null,
"path": "system.cpu.toL2Bus",
"snoop_response_latency": 1,
"name": "toL2Bus",
"p_state_clk_gate_bins": 20,
"use_default_range": false
},
"do_quiesce": true,
"type": "TimingSimpleCPU",
"profile": 0,
"icache_port": {
"peer": "system.cpu.icache.cpu_side",
"role": "MASTER"
},
"p_state_clk_gate_bins": 20,
"p_state_clk_gate_min": 1000,
"interrupts": [
{
"eventq_index": 0,
"path": "system.cpu.interrupts",
"type": "RiscvInterrupts",
"name": "interrupts",
"cxx_class": "RiscvISA::Interrupts"
}
],
"dcache_port": {
"peer": "system.cpu.dcache.cpu_side",
"role": "MASTER"
},
"socket_id": 0,
"power_model": null,
"max_insts_all_threads": 0,
"l2cache": {
"cpu_side": {
"peer": "system.cpu.toL2Bus.master[0]",
"role": "SLAVE"
},
"clusivity": "mostly_incl",
"prefetcher": null,
"system": "system",
"write_buffers": 8,
"response_latency": 20,
"cxx_class": "Cache",
"size": 2097152,
"type": "Cache",
"clk_domain": "system.cpu_clk_domain",
"max_miss_count": 0,
"eventq_index": 0,
"default_p_state": "UNDEFINED",
"p_state_clk_gate_max": 1000000000000,
"mem_side": {
"peer": "system.membus.slave[1]",
"role": "MASTER"
},
"mshrs": 20,
"writeback_clean": false,
"p_state_clk_gate_min": 1000,
"tags": {
"size": 2097152,
"tag_latency": 20,
"name": "tags",
"p_state_clk_gate_min": 1000,
"eventq_index": 0,
"p_state_clk_gate_bins": 20,
"default_p_state": "UNDEFINED",
"clk_domain": "system.cpu_clk_domain",
"power_model": null,
"sequential_access": false,
"assoc": 8,
"cxx_class": "LRU",
"p_state_clk_gate_max": 1000000000000,
"path": "system.cpu.l2cache.tags",
"block_size": 64,
"type": "LRU",
"data_latency": 20
},
"tgts_per_mshr": 12,
"demand_mshr_reserve": 1,
"power_model": null,
"addr_ranges": [
"0:18446744073709551615:0:0:0:0"
],
"is_read_only": false,
"prefetch_on_access": false,
"path": "system.cpu.l2cache",
"data_latency": 20,
"tag_latency": 20,
"name": "l2cache",
"p_state_clk_gate_bins": 20,
"sequential_access": false,
"assoc": 8
},
"path": "system.cpu",
"max_loads_any_thread": 0,
"switched_out": false,
"workload": [
{
"uid": 100,
"pid": 100,
"kvmInSE": false,
"cxx_class": "LiveProcess",
"executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64d/insttest",
"drivers": [],
"system": "system",
"gid": 100,
"eventq_index": 0,
"env": [],
"input": "cin",
"ppid": 99,
"type": "LiveProcess",
"cwd": "",
"simpoint": 0,
"euid": 100,
"path": "system.cpu.workload",
"max_stack_size": 67108864,
"name": "workload",
"cmd": [
"insttest"
],
"errout": "cerr",
"useArchPT": false,
"egid": 100,
"output": "cout"
}
],
"name": "cpu",
"dtb": {
"name": "dtb",
"eventq_index": 0,
"cxx_class": "RiscvISA::TLB",
"path": "system.cpu.dtb",
"type": "RiscvTLB",
"size": 64
},
"simpoint_start_insts": [],
"max_insts_any_thread": 0,
"progress_interval": 0,
"branchPred": null,
"dcache": {
"cpu_side": {
"peer": "system.cpu.dcache_port",
"role": "SLAVE"
},
"clusivity": "mostly_incl",
"prefetcher": null,
"system": "system",
"write_buffers": 8,
"response_latency": 2,
"cxx_class": "Cache",
"size": 262144,
"type": "Cache",
"clk_domain": "system.cpu_clk_domain",
"max_miss_count": 0,
"eventq_index": 0,
"default_p_state": "UNDEFINED",
"p_state_clk_gate_max": 1000000000000,
"mem_side": {
"peer": "system.cpu.toL2Bus.slave[1]",
"role": "MASTER"
},
"mshrs": 4,
"writeback_clean": false,
"p_state_clk_gate_min": 1000,
"tags": {
"size": 262144,
"tag_latency": 2,
"name": "tags",
"p_state_clk_gate_min": 1000,
"eventq_index": 0,
"p_state_clk_gate_bins": 20,
"default_p_state": "UNDEFINED",
"clk_domain": "system.cpu_clk_domain",
"power_model": null,
"sequential_access": false,
"assoc": 2,
"cxx_class": "LRU",
"p_state_clk_gate_max": 1000000000000,
"path": "system.cpu.dcache.tags",
"block_size": 64,
"type": "LRU",
"data_latency": 2
},
"tgts_per_mshr": 20,
"demand_mshr_reserve": 1,
"power_model": null,
"addr_ranges": [
"0:18446744073709551615:0:0:0:0"
],
"is_read_only": false,
"prefetch_on_access": false,
"path": "system.cpu.dcache",
"data_latency": 2,
"tag_latency": 2,
"name": "dcache",
"p_state_clk_gate_bins": 20,
"sequential_access": false,
"assoc": 2
},
"isa": [
{
"eventq_index": 0,
"path": "system.cpu.isa",
"type": "RiscvISA",
"name": "isa",
"cxx_class": "RiscvISA::ISA"
}
],
"tracer": {
"eventq_index": 0,
"path": "system.cpu.tracer",
"type": "ExeTracer",
"name": "tracer",
"cxx_class": "Trace::ExeTracer"
}
}
],
"multi_thread": false,
"exit_on_work_items": false,
"work_item_id": -1,
"num_work_ids": 16
},
"time_sync_period": 100000000000,
"eventq_index": 0,
"time_sync_spin_threshold": 100000000,
"cxx_class": "Root",
"path": "root",
"time_sync_enable": false,
"type": "Root",
"full_system": false
}

3
tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing/simerr Executable file
View file

@ -0,0 +1,3 @@
warn: Unknown operating system; assuming Linux.
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick

168
tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing/simout Executable file
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@ -0,0 +1,168 @@
Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/simple-timing/simout
Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Nov 30 2016 14:33:35
gem5 started Nov 30 2016 16:18:31
gem5 executing on zizzer, pid 34073
command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/simple-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64d/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
fld: PASS
fsd: PASS
fmadd.d: PASS
fmadd.d, quiet NaN: PASS
fmadd.d, signaling NaN: PASS
fmadd.d, infinity: PASS
fmadd.d, -infinity: PASS
fmsub.d: PASS
fmsub.d, quiet NaN: PASS
fmsub.d, signaling NaN: PASS
fmsub.d, infinity: PASS
fmsub.d, -infinity: PASS
fmsub.d, subtract infinity: PASS
fnmsub.d: PASS
fnmsub.d, quiet NaN: PASS
fnmsub.d, signaling NaN: PASS
fnmsub.d, infinity: PASS
fnmsub.d, -infinity: PASS
fnmsub.d, subtract infinity: PASS
fnmadd.d: PASS
fnmadd.d, quiet NaN: PASS
fnmadd.d, signaling NaN: PASS
fnmadd.d, infinity: PASS
fnmadd.d, -infinity: PASS
fadd.d: PASS
fadd.d, quiet NaN: PASS
fadd.d, signaling NaN: PASS
fadd.d, infinity: PASS
fadd.d, -infinity: PASS
fsub.d: PASS
fsub.d, quiet NaN: PASS
fsub.d, signaling NaN: PASS
fsub.d, infinity: PASS
fsub.d, -infinity: PASS
fsub.d, subtract infinity: PASS
fmul.d: PASS
fmul.d, quiet NaN: PASS
fmul.d, signaling NaN: PASS
fmul.d, infinity: PASS
fmul.d, -infinity: PASS
fmul.d, 0*infinity: PASS
fmul.d, overflow: PASS
fmul.d, underflow: PASS
fdiv.d: PASS
fdiv.d, quiet NaN: PASS
fdiv.d, signaling NaN: PASS
fdiv.d/0: PASS
fdiv.d/infinity: PASS
fdiv.d, infinity/infinity: PASS
fdiv.d, 0/0: PASS
fdiv.d, infinity/0: PASS
fdiv.d, 0/infinity: PASS
fdiv.d, underflow: PASS
fdiv.d, overflow: PASS
fsqrt.d: PASS
fsqrt.d, NaN: PASS
fsqrt.d, quiet NaN: PASS
fsqrt.d, signaling NaN: PASS
fsqrt.d, infinity: PASS
fsgnj.d, ++: PASS
fsgnj.d, +-: PASS
fsgnj.d, -+: PASS
fsgnj.d, --: PASS
fsgnj.d, quiet NaN: PASS
fsgnj.d, signaling NaN: PASS
fsgnj.d, inject NaN: PASS
fsgnj.d, inject -NaN: PASS
fsgnjn.d, ++: PASS
fsgnjn.d, +-: PASS
fsgnjn.d, -+: PASS
fsgnjn.d, --: PASS
fsgnjn.d, quiet NaN: PASS
fsgnjn.d, signaling NaN: PASS
fsgnjn.d, inject NaN: PASS
fsgnjn.d, inject NaN: PASS
fsgnjx.d, ++: PASS
fsgnjx.d, +-: PASS
fsgnjx.d, -+: PASS
fsgnjx.d, --: PASS
fsgnjx.d, quiet NaN: PASS
fsgnjx.d, signaling NaN: PASS
fsgnjx.d, inject NaN: PASS
fsgnjx.d, inject NaN: PASS
fmin.d: PASS
fmin.d, -infinity: PASS
fmin.d, infinity: PASS
fmin.d, quiet NaN first: PASS
fmin.d, quiet NaN second: PASS
fmin.d, quiet NaN both: PASS
fmin.d, signaling NaN first: PASS
fmin.d, signaling NaN second: PASS
fmin.d, signaling NaN both: PASS
fmax.d: PASS
fmax.d, -infinity: PASS
fmax.d, infinity: PASS
fmax.d, quiet NaN first: PASS
fmax.d, quiet NaN second: PASS
fmax.d, quiet NaN both: PASS
fmax.d, signaling NaN first: PASS
fmax.d, signaling NaN second: PASS
fmax.d, signaling NaN both: PASS
fcvt.s.d: PASS
fcvt.s.d, quiet NaN: PASS
fcvt.s.d, signaling NaN: PASS
fcvt.s.d, infinity: PASS
fcvt.s.d, overflow: PASS
fcvt.s.d, underflow: PASS
fcvt.d.s: PASS
fcvt.d.s, quiet NaN: PASS
fcvt.d.s, signaling NaN: PASS
fcvt.d.s, infinity: PASS
feq.d, equal: PASS
feq.d, not equal: PASS
feq.d, 0 == -0: PASS
feq.d, quiet NaN first: PASS
feq.d, quiet NaN second: PASS
feq.d, quiet NaN both: PASS
feq.d, signaling NaN first: PASS
feq.d, signaling NaN second: PASS
feq.d, signaling NaN both: PASS
flt.d, equal: PASS
flt.d, less: PASS
flt.d, greater: PASS
flt.d, quiet NaN first: PASS
flt.d, quiet NaN second: PASS
flt.d, quiet NaN both: PASS
flt.d, signaling NaN first: PASS
flt.d, signaling NaN second: PASS
flt.d, signaling NaN both: PASS
fle.d, equal: PASS
fle.d, less: PASS
fle.d, greater: PASS
fle.d, 0 == -0: PASS
fle.d, quiet NaN first: PASS
fle.d, quiet NaN second: PASS
fle.d, quiet NaN both: PASS
fle.d, signaling NaN first: PASS
fle.d, signaling NaN second: PASS
fle.d, signaling NaN both: PASS
fclass.d, -infinity: PASS
fclass.d, -normal: PASS
fclass.d, -subnormal: PASS
fclass.d, -0.0: PASS
fclass.d, 0.0: PASS
fclass.d, subnormal: PASS
fclass.d, normal: PASS
fclass.d, infinity: PASS
fclass.d, signaling NaN: PASS
fclass.s, quiet NaN: PASS
fcvt.w.d, truncate positive: PASS
fcvt.w.d, truncate negative: PASS
fcvt.w.d, 0.0: PASS
fcvt.w.d, -0.0: PASS
fcvt.w.d, overflow: FAIL (expected 2147483647; found -2147483648)
Exiting @ tick 497165500 because target called exit()

515
tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing/stats.txt Normal file
View file

@ -0,0 +1,515 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000497 # Number of seconds simulated
sim_ticks 497165500 # Number of ticks simulated
final_tick 497165500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 27513 # Simulator instruction rate (inst/s)
host_op_rate 27513 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 45717681 # Simulator tick rate (ticks/s)
host_mem_usage 243824 # Number of bytes of host memory used
host_seconds 10.87 # Real time elapsed on the host
sim_insts 299191 # Number of instructions simulated
sim_ops 299191 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 497165500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 61760 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 20224 # Number of bytes read from this memory
system.physmem.bytes_read::total 81984 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 61760 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 61760 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 965 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 316 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1281 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 124224227 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 40678607 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 164902834 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 124224227 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 124224227 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 124224227 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 40678607 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 164902834 # Total bandwidth to/from this memory (bytes/s)
system.pwrStateResidencyTicks::UNDEFINED 497165500 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 162 # Number of system calls
system.cpu.pwrStateResidencyTicks::ON 497165500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 994331 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 299191 # Number of instructions committed
system.cpu.committedOps 299191 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 299008 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 1025 # Number of float alu accesses
system.cpu.num_func_calls 21816 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 44561 # number of instructions that are conditional controls
system.cpu.num_int_insts 299008 # number of integer instructions
system.cpu.num_fp_insts 1025 # number of float instructions
system.cpu.num_int_register_reads 394163 # number of times the integer registers were read
system.cpu.num_int_register_writes 205779 # number of times the integer registers were written
system.cpu.num_fp_register_reads 851 # number of times the floating registers were read
system.cpu.num_fp_register_writes 688 # number of times the floating registers were written
system.cpu.num_mem_refs 118390 # number of memory refs
system.cpu.num_load_insts 69843 # Number of load instructions
system.cpu.num_store_insts 48547 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 994331 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.Branches 66377 # Number of branches fetched
system.cpu.op_class::No_OpClass 162 0.05% 0.05% # Class of executed instruction
system.cpu.op_class::IntAlu 179913 60.10% 60.15% # Class of executed instruction
system.cpu.op_class::IntMult 466 0.16% 60.31% # Class of executed instruction
system.cpu.op_class::IntDiv 40 0.01% 60.32% # Class of executed instruction
system.cpu.op_class::FloatAdd 120 0.04% 60.36% # Class of executed instruction
system.cpu.op_class::FloatCmp 157 0.05% 60.42% # Class of executed instruction
system.cpu.op_class::FloatCvt 60 0.02% 60.44% # Class of executed instruction
system.cpu.op_class::FloatMult 30 0.01% 60.45% # Class of executed instruction
system.cpu.op_class::FloatMultAcc 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::FloatDiv 11 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::FloatMisc 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::FloatSqrt 5 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.45% # Class of executed instruction
system.cpu.op_class::MemRead 69348 23.17% 83.62% # Class of executed instruction
system.cpu.op_class::MemWrite 48400 16.17% 99.79% # Class of executed instruction
system.cpu.op_class::FloatMemRead 495 0.17% 99.95% # Class of executed instruction
system.cpu.op_class::FloatMemWrite 147 0.05% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 299354 # Class of executed instruction
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 497165500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 258.453748 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 118073 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 316 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 373.648734 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 258.453748 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.063099 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.063099 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 316 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 296 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.077148 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 237094 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 237094 # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 497165500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 69732 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 69732 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 48341 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 48341 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 118073 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 118073 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 118073 # number of overall hits
system.cpu.dcache.overall_hits::total 118073 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 111 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 111 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 205 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 205 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 316 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 316 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 316 # number of overall misses
system.cpu.dcache.overall_misses::total 316 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 6993000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 6993000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 12915000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 12915000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 19908000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 19908000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 19908000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 19908000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 69843 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 69843 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 48546 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 48546 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 118389 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 118389 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 118389 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 118389 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001589 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.001589 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.004223 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.004223 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.002669 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.002669 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.002669 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.002669 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 63000 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 63000 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 63000 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 63000 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 63000 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 111 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 111 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 205 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 205 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 316 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 316 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 316 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 316 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6882000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 6882000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12710000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 12710000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19592000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 19592000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19592000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 19592000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001589 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001589 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.004223 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.004223 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002669 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.002669 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002669 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.002669 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62000 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62000 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 497165500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 26 # number of replacements
system.cpu.icache.tags.tagsinuse 551.353598 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 298390 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 965 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 309.212435 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 551.353598 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.269216 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.269216 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 939 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 774 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.458496 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 599675 # Number of tag accesses
system.cpu.icache.tags.data_accesses 599675 # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 497165500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 298390 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 298390 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 298390 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 298390 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 298390 # number of overall hits
system.cpu.icache.overall_hits::total 298390 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 965 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 965 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 965 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 965 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 965 # number of overall misses
system.cpu.icache.overall_misses::total 965 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 60795500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 60795500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 60795500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 60795500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 60795500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 60795500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 299355 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 299355 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 299355 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 299355 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 299355 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 299355 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003224 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.003224 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.003224 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.003224 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.003224 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.003224 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63000.518135 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 63000.518135 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 63000.518135 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 63000.518135 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 63000.518135 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 63000.518135 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks 26 # number of writebacks
system.cpu.icache.writebacks::total 26 # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 965 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 965 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 965 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 965 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 965 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 965 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59830500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 59830500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59830500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 59830500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59830500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 59830500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.003224 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.003224 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.003224 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.003224 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.003224 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.003224 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62000.518135 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62000.518135 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62000.518135 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 62000.518135 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62000.518135 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 62000.518135 # average overall mshr miss latency
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 497165500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 821.156872 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 26 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 1281 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.020297 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst 562.696450 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 258.460422 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.017172 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.007888 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.025060 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 1281 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 119 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1096 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.039093 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 11737 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 11737 # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 497165500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackClean_hits::writebacks 26 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 26 # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 205 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 205 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 965 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 965 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 111 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 111 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 965 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 316 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 1281 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 965 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 316 # number of overall misses
system.cpu.l2cache.overall_misses::total 1281 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12402500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 12402500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 58383000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 58383000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6715500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 6715500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 58383000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 19118000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 77501000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 58383000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 19118000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 77501000 # number of overall miss cycles
system.cpu.l2cache.WritebackClean_accesses::writebacks 26 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 26 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 205 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 205 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 965 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 965 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 111 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 111 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 965 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 316 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 1281 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 965 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 316 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 1281 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 1 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60500.518135 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60500.518135 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60500.518135 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 60500.390320 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60500.518135 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 60500.390320 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 205 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 205 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 965 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 965 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 111 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 111 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 965 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 316 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 1281 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 965 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 316 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 1281 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10352500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10352500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 48733000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 48733000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5605500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5605500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 48733000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15958000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 64691000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 48733000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15958000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 64691000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50500.518135 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50500.518135 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50500.518135 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.390320 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50500.518135 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.390320 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 1307 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 26 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 497165500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 1076 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 26 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 205 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 205 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 965 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 111 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1956 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 632 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 2588 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 63424 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 20224 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 83648 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples 1281 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 1281 100.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 1281 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 679500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 1447500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 474000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
system.membus.snoop_filter.tot_requests 1281 # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 497165500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 1076 # Transaction distribution
system.membus.trans_dist::ReadExReq 205 # Transaction distribution
system.membus.trans_dist::ReadExResp 205 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 1076 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2562 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 2562 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 81984 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 81984 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples 1281 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 1281 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 1281 # Request fanout histogram
system.membus.reqLayer0.occupancy 1281500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.3 # Layer utilization (%)
system.membus.respLayer1.occupancy 6405000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 1.3 # Layer utilization (%)
---------- End Simulation Statistics ----------

902
tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/config.ini Normal file
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@ -0,0 +1,902 @@
[root]
type=Root
children=system
eventq_index=0
full_system=false
sim_quantum=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.clk_domain]
type=SrcClockDomain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.cpu]
type=MinorCPU
children=branchPred dcache dtb executeFuncUnits icache interrupts isa itb l2cache toL2Bus tracer workload
branchPred=system.cpu.branchPred
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
decodeCycleInput=true
decodeInputBufferSize=3
decodeInputWidth=2
decodeToExecuteForwardDelay=1
default_p_state=UNDEFINED
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
enableIdling=true
eventq_index=0
executeAllowEarlyMemoryIssue=true
executeBranchDelay=1
executeCommitLimit=2
executeCycleInput=true
executeFuncUnits=system.cpu.executeFuncUnits
executeInputBufferSize=7
executeInputWidth=2
executeIssueLimit=2
executeLSQMaxStoreBufferStoresPerCycle=2
executeLSQRequestsQueueSize=1
executeLSQStoreBufferSize=5
executeLSQTransfersQueueSize=2
executeMaxAccessesInMemory=2
executeMemoryCommitLimit=1
executeMemoryIssueLimit=1
executeMemoryWidth=0
executeSetTraceTimeOnCommit=true
executeSetTraceTimeOnIssue=false
fetch1FetchLimit=1
fetch1LineSnapWidth=0
fetch1LineWidth=0
fetch1ToFetch2BackwardDelay=1
fetch1ToFetch2ForwardDelay=1
fetch2CycleInput=true
fetch2InputBufferSize=2
fetch2ToDecodeForwardDelay=1
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
profile=0
progress_interval=0
simpoint_start_insts=
socket_id=0
switched_out=false
system=system
threadPolicy=RoundRobin
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
type=TournamentBP
BTBEntries=4096
BTBTagSize=16
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
indirectHashGHR=true
indirectHashTargets=true
indirectPathLength=3
indirectSets=256
indirectTagSize=16
indirectWays=2
instShiftAmt=2
localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
useIndirect=true
[system.cpu.dcache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
is_read_only=false
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=262144
system=system
tag_latency=2
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dcache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=262144
tag_latency=2
[system.cpu.dtb]
type=RiscvTLB
eventq_index=0
size=64
[system.cpu.executeFuncUnits]
type=MinorFUPool
children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6
eventq_index=0
funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6
[system.cpu.executeFuncUnits.funcUnits0]
type=MinorFU
children=opClasses timings
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses
opLat=3
timings=system.cpu.executeFuncUnits.funcUnits0.timings
[system.cpu.executeFuncUnits.funcUnits0.opClasses]
type=MinorOpClassSet
children=opClasses
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses
[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses]
type=MinorOpClass
eventq_index=0
opClass=IntAlu
[system.cpu.executeFuncUnits.funcUnits0.timings]
type=MinorFUTiming
children=opClasses
description=Int
eventq_index=0
extraAssumedLat=0
extraCommitLat=0
extraCommitLatExpr=Null
mask=0
match=0
opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses
srcRegsRelativeLats=2
suppress=false
[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses]
type=MinorOpClassSet
eventq_index=0
opClasses=
[system.cpu.executeFuncUnits.funcUnits1]
type=MinorFU
children=opClasses timings
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses
opLat=3
timings=system.cpu.executeFuncUnits.funcUnits1.timings
[system.cpu.executeFuncUnits.funcUnits1.opClasses]
type=MinorOpClassSet
children=opClasses
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses
[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses]
type=MinorOpClass
eventq_index=0
opClass=IntAlu
[system.cpu.executeFuncUnits.funcUnits1.timings]
type=MinorFUTiming
children=opClasses
description=Int
eventq_index=0
extraAssumedLat=0
extraCommitLat=0
extraCommitLatExpr=Null
mask=0
match=0
opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses
srcRegsRelativeLats=2
suppress=false
[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses]
type=MinorOpClassSet
eventq_index=0
opClasses=
[system.cpu.executeFuncUnits.funcUnits2]
type=MinorFU
children=opClasses timings
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses
opLat=3
timings=system.cpu.executeFuncUnits.funcUnits2.timings
[system.cpu.executeFuncUnits.funcUnits2.opClasses]
type=MinorOpClassSet
children=opClasses
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses
[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses]
type=MinorOpClass
eventq_index=0
opClass=IntMult
[system.cpu.executeFuncUnits.funcUnits2.timings]
type=MinorFUTiming
children=opClasses
description=Mul
eventq_index=0
extraAssumedLat=0
extraCommitLat=0
extraCommitLatExpr=Null
mask=0
match=0
opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses
srcRegsRelativeLats=0
suppress=false
[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses]
type=MinorOpClassSet
eventq_index=0
opClasses=
[system.cpu.executeFuncUnits.funcUnits3]
type=MinorFU
children=opClasses
cantForwardFromFUIndices=
eventq_index=0
issueLat=9
opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses
opLat=9
timings=
[system.cpu.executeFuncUnits.funcUnits3.opClasses]
type=MinorOpClassSet
children=opClasses
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses
[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses]
type=MinorOpClass
eventq_index=0
opClass=IntDiv
[system.cpu.executeFuncUnits.funcUnits4]
type=MinorFU
children=opClasses timings
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses
opLat=6
timings=system.cpu.executeFuncUnits.funcUnits4.timings
[system.cpu.executeFuncUnits.funcUnits4.opClasses]
type=MinorOpClassSet
children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 opClasses26 opClasses27
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses26 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses27
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00]
type=MinorOpClass
eventq_index=0
opClass=FloatAdd
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01]
type=MinorOpClass
eventq_index=0
opClass=FloatCmp
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02]
type=MinorOpClass
eventq_index=0
opClass=FloatCvt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03]
type=MinorOpClass
eventq_index=0
opClass=FloatMisc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04]
type=MinorOpClass
eventq_index=0
opClass=FloatMult
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05]
type=MinorOpClass
eventq_index=0
opClass=FloatMultAcc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06]
type=MinorOpClass
eventq_index=0
opClass=FloatDiv
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07]
type=MinorOpClass
eventq_index=0
opClass=FloatSqrt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08]
type=MinorOpClass
eventq_index=0
opClass=SimdAdd
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09]
type=MinorOpClass
eventq_index=0
opClass=SimdAddAcc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10]
type=MinorOpClass
eventq_index=0
opClass=SimdAlu
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11]
type=MinorOpClass
eventq_index=0
opClass=SimdCmp
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12]
type=MinorOpClass
eventq_index=0
opClass=SimdCvt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13]
type=MinorOpClass
eventq_index=0
opClass=SimdMisc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14]
type=MinorOpClass
eventq_index=0
opClass=SimdMult
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15]
type=MinorOpClass
eventq_index=0
opClass=SimdMultAcc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16]
type=MinorOpClass
eventq_index=0
opClass=SimdShift
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17]
type=MinorOpClass
eventq_index=0
opClass=SimdShiftAcc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18]
type=MinorOpClass
eventq_index=0
opClass=SimdSqrt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatAdd
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatAlu
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatCmp
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatCvt
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatDiv
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatMisc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatMult
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses26]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatMultAcc
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses27]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatSqrt
[system.cpu.executeFuncUnits.funcUnits4.timings]
type=MinorFUTiming
children=opClasses
description=FloatSimd
eventq_index=0
extraAssumedLat=0
extraCommitLat=0
extraCommitLatExpr=Null
mask=0
match=0
opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses
srcRegsRelativeLats=2
suppress=false
[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses]
type=MinorOpClassSet
eventq_index=0
opClasses=
[system.cpu.executeFuncUnits.funcUnits5]
type=MinorFU
children=opClasses timings
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses
opLat=1
timings=system.cpu.executeFuncUnits.funcUnits5.timings
[system.cpu.executeFuncUnits.funcUnits5.opClasses]
type=MinorOpClassSet
children=opClasses0 opClasses1 opClasses2 opClasses3
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses2 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses3
[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0]
type=MinorOpClass
eventq_index=0
opClass=MemRead
[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1]
type=MinorOpClass
eventq_index=0
opClass=MemWrite
[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses2]
type=MinorOpClass
eventq_index=0
opClass=FloatMemRead
[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses3]
type=MinorOpClass
eventq_index=0
opClass=FloatMemWrite
[system.cpu.executeFuncUnits.funcUnits5.timings]
type=MinorFUTiming
children=opClasses
description=Mem
eventq_index=0
extraAssumedLat=2
extraCommitLat=0
extraCommitLatExpr=Null
mask=0
match=0
opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses
srcRegsRelativeLats=1
suppress=false
[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses]
type=MinorOpClassSet
eventq_index=0
opClasses=
[system.cpu.executeFuncUnits.funcUnits6]
type=MinorFU
children=opClasses
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses
opLat=1
timings=
[system.cpu.executeFuncUnits.funcUnits6.opClasses]
type=MinorOpClassSet
children=opClasses0 opClasses1
eventq_index=0
opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1
[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0]
type=MinorOpClass
eventq_index=0
opClass=IprAccess
[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1]
type=MinorOpClass
eventq_index=0
opClass=InstPrefetch
[system.cpu.icache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
is_read_only=true
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=131072
system=system
tag_latency=2
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=true
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.icache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=131072
tag_latency=2
[system.cpu.interrupts]
type=RiscvInterrupts
eventq_index=0
[system.cpu.isa]
type=RiscvISA
eventq_index=0
[system.cpu.itb]
type=RiscvTLB
eventq_index=0
size=64
[system.cpu.l2cache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=20
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
is_read_only=false
max_miss_count=0
mshrs=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=20
sequential_access=false
size=2097152
system=system
tag_latency=20
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.l2cache.tags]
type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=20
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=2097152
tag_latency=20
[system.cpu.toL2Bus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=0
frontend_latency=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=false
power_model=Null
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.toL2Bus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=0
max_capacity=8388608
system=system
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=LiveProcess
cmd=insttest
cwd=
drivers=
egid=100
env=
errout=cerr
euid=100
eventq_index=0
executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64f/insttest
gid=100
input=cin
kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.dvfs_handler]
type=DVFSHandler
domains=
enable=false
eventq_index=0
sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=4
frontend_latency=3
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem]
type=DRAMCtrl
IDD0=0.055000
IDD02=0.000000
IDD2N=0.032000
IDD2N2=0.000000
IDD2P0=0.000000
IDD2P02=0.000000
IDD2P1=0.032000
IDD2P12=0.000000
IDD3N=0.038000
IDD3N2=0.000000
IDD3P0=0.000000
IDD3P02=0.000000
IDD3P1=0.038000
IDD3P12=0.000000
IDD4R=0.157000
IDD4R2=0.000000
IDD4W=0.125000
IDD4W2=0.000000
IDD5=0.235000
IDD52=0.000000
IDD6=0.020000
IDD62=0.000000
VDD=1.500000
VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
clk_domain=system.clk_domain
conf_table_reported=true
default_p_state=UNDEFINED
device_bus_width=8
device_rowbuffer_size=1024
device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
in_addr_map=true
kvm_map=true
max_accesses_per_row=16
mem_sched_policy=frfcfs
min_writes_per_switch=16
null=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
page_policy=open_adaptive
power_model=Null
range=0:134217727:0:0:0:0
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
tCCD_L=0
tCK=1250
tCL=13750
tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
tXP=6000
tXPDLL=0
tXS=270000
tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
port=system.membus.master[0]
[system.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.000000

1211
tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/config.json Normal file
View file

File diff suppressed because it is too large Load diff

4
tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/simerr Executable file
View file

@ -0,0 +1,4 @@
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Unknown operating system; assuming Linux.
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick

121
tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/simout Executable file
View file

@ -0,0 +1,121 @@
Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/minor-timing/simout
Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/minor-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Nov 30 2016 14:33:35
gem5 started Nov 30 2016 16:18:32
gem5 executing on zizzer, pid 34076
command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/minor-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64f/minor-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
clear fsflags: PASS
flw: PASS
fsw: PASS
fmadd.s: PASS
fmadd.s, quiet NaN: PASS
fmadd.s, signaling NaN: PASS
fmadd.s, infinity: PASS
fmadd.s, -infinity: PASS
fmsub.s: PASS
fmsub.s, quiet NaN: PASS
fmsub.s, signaling NaN: PASS
fmsub.s, infinity: PASS
fmsub.s, -infinity: PASS
fmsub.s, subtract infinity: PASS
fnmsub.s: PASS
fnmsub.s, quiet NaN: PASS
fnmsub.s, signaling NaN: PASS
fnmsub.s, infinity: PASS
fnmsub.s, -infinity: PASS
fnmsub.s, subtract infinity: PASS
fnmadd.s: PASS
fnmadd.s, quiet NaN: PASS
fnmadd.s, signaling NaN: PASS
fnmadd.s, infinity: PASS
fnmadd.s, -infinity: PASS
fadd.s: PASS
fadd.s, quiet NaN: PASS
fadd.s, signaling NaN: PASS
fadd.s, infinity: PASS
fadd.s, -infinity: PASS
fsub.s: PASS
fsub.s, quiet NaN: PASS
fsub.s, signaling NaN: PASS
fsub.s, infinity: PASS
fsub.s, -infinity: PASS
fsub.s, subtract infinity: PASS
fmul.s: PASS
fmul.s, quiet NaN: PASS
fmul.s, signaling NaN: PASS
fmul.s, infinity: PASS
fmul.s, -infinity: PASS
fmul.s, 0*infinity: PASS
fmul.s, overflow: PASS
fmul.s, underflow: PASS
fdiv.s: PASS
fdiv.s, quiet NaN: PASS
fdiv.s, signaling NaN: PASS
fdiv.s/0: PASS
fdiv.s/infinity: PASS
fdiv.s, infinity/infinity: PASS
fdiv.s, 0/0: PASS
fdiv.s, infinity/0: PASS
fdiv.s, 0/infinity: PASS
fdiv.s, underflow: PASS
fdiv.s, overflow: PASS
fsqrt.s: PASS
fsqrt.s, NaN: PASS
fsqrt.s, quiet NaN: PASS
fsqrt.s, signaling NaN: PASS
fsqrt.s, infinity: PASS
fsgnj.s, ++: PASS
fsgnj.s, +-: PASS
fsgnj.s, -+: PASS
fsgnj.s, --: PASS
fsgnj.s, quiet NaN: PASS
fsgnj.s, signaling NaN: PASS
fsgnj.s, inject NaN: PASS
fsgnj.s, inject -NaN: PASS
fsgnjn.s, ++: PASS
fsgnjn.s, +-: PASS
fsgnjn.s, -+: PASS
fsgnjn.s, --: PASS
fsgnjn.s, quiet NaN: PASS
fsgnjn.s, signaling NaN: PASS
fsgnjn.s, inject NaN: PASS
fsgnjn.s, inject NaN: PASS
fsgnjx.s, ++: PASS
fsgnjx.s, +-: PASS
fsgnjx.s, -+: PASS
fsgnjx.s, --: PASS
fsgnjx.s, quiet NaN: PASS
fsgnjx.s, signaling NaN: PASS
fsgnjx.s, inject NaN: PASS
fsgnjx.s, inject -NaN: PASS
fmin.s: PASS
fmin.s, -infinity: PASS
fmin.s, infinity: PASS
fmin.s, quiet NaN first: PASS
fmin.s, quiet NaN second: PASS
fmin.s, quiet NaN both: PASS
fmin.s, signaling NaN first: PASS
fmin.s, signaling NaN second: PASS
fmin.s, signaling NaN both: PASS
fmax.s: PASS
fmax.s, -infinity: PASS
fmax.s, infinity: PASS
fmax.s, quiet NaN first: PASS
fmax.s, quiet NaN second: PASS
fmax.s, quiet NaN both: PASS
fmax.s, signaling NaN first: PASS
fmax.s, signaling NaN second: PASS
fmax.s, signaling NaN both: PASS
fcvt.w.s, truncate positive: PASS
fcvt.w.s, truncate negative: PASS
fcvt.w.s, 0.0: PASS
fcvt.w.s, -0.0: PASS
fcvt.w.s, overflow: FAIL (expected 2147483647; found -2147483648)
Exiting @ tick 270200000 because target called exit()

765
tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/stats.txt Normal file
View file

@ -0,0 +1,765 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000270 # Number of seconds simulated
sim_ticks 270200000 # Number of ticks simulated
final_tick 270200000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 24805 # Simulator instruction rate (inst/s)
host_op_rate 24804 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 29619482 # Simulator tick rate (ticks/s)
host_mem_usage 244928 # Number of bytes of host memory used
host_seconds 9.12 # Real time elapsed on the host
sim_insts 226275 # Number of instructions simulated
sim_ops 226275 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 67072 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 19264 # Number of bytes read from this memory
system.physmem.bytes_read::total 86336 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 67072 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 67072 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 1048 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 301 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1349 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 248230940 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 71295337 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 319526277 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 248230940 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 248230940 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 248230940 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 71295337 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 319526277 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 1349 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 1349 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 86336 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 86336 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 173 # Per bank write bursts
system.physmem.perBankRdBursts::1 19 # Per bank write bursts
system.physmem.perBankRdBursts::2 18 # Per bank write bursts
system.physmem.perBankRdBursts::3 76 # Per bank write bursts
system.physmem.perBankRdBursts::4 196 # Per bank write bursts
system.physmem.perBankRdBursts::5 259 # Per bank write bursts
system.physmem.perBankRdBursts::6 19 # Per bank write bursts
system.physmem.perBankRdBursts::7 4 # Per bank write bursts
system.physmem.perBankRdBursts::8 26 # Per bank write bursts
system.physmem.perBankRdBursts::9 99 # Per bank write bursts
system.physmem.perBankRdBursts::10 157 # Per bank write bursts
system.physmem.perBankRdBursts::11 158 # Per bank write bursts
system.physmem.perBankRdBursts::12 48 # Per bank write bursts
system.physmem.perBankRdBursts::13 47 # Per bank write bursts
system.physmem.perBankRdBursts::14 17 # Per bank write bursts
system.physmem.perBankRdBursts::15 33 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
system.physmem.perBankWrBursts::4 0 # Per bank write bursts
system.physmem.perBankWrBursts::5 0 # Per bank write bursts
system.physmem.perBankWrBursts::6 0 # Per bank write bursts
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
system.physmem.perBankWrBursts::10 0 # Per bank write bursts
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 269959000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 1349 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 1287 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 59 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 239 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 351.330544 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 238.583723 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 292.748127 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 53 22.18% 22.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 57 23.85% 46.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 30 12.55% 58.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 35 14.64% 73.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 21 8.79% 82.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 16 6.69% 88.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 4 1.67% 90.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 3 1.26% 91.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 20 8.37% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 239 # Bytes accessed per row activation
system.physmem.totQLat 15283750 # Total ticks spent queuing
system.physmem.totMemAccLat 40577500 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 6745000 # Total ticks spent in databus transfers
system.physmem.avgQLat 11329.69 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 30079.69 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 319.53 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 319.53 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 2.50 # Data bus utilization in percentage
system.physmem.busUtilRead 2.50 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 1101 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 81.62 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 200117.87 # Average gap between requests
system.physmem.pageHitRate 81.62 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 899640 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 462990 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 5454960 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 20897760.000000 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 13396710 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 455520 # Energy for precharge background per rank (pJ)
system.physmem_0.actPowerDownEnergy 92913420 # Energy for active power-down per rank (pJ)
system.physmem_0.prePowerDownEnergy 13776960 # Energy for precharge power-down per rank (pJ)
system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
system.physmem_0.totalEnergy 148257960 # Total energy per rank (pJ)
system.physmem_0.averagePower 548.697113 # Core power per rank (mW)
system.physmem_0.totalIdleTime 238953500 # Total Idle time Per DRAM Rank
system.physmem_0.memoryStateTime::IDLE 216000 # Time in different power states
system.physmem_0.memoryStateTime::REF 8840000 # Time in different power states
system.physmem_0.memoryStateTime::SREF 0 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 35871500 # Time in different power states
system.physmem_0.memoryStateTime::ACT 21502750 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 203769750 # Time in different power states
system.physmem_1.actEnergy 871080 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 444015 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 4176900 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 21512400.000000 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 11664480 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 3533280 # Energy for precharge background per rank (pJ)
system.physmem_1.actPowerDownEnergy 82867740 # Energy for active power-down per rank (pJ)
system.physmem_1.prePowerDownEnergy 20352000 # Energy for precharge power-down per rank (pJ)
system.physmem_1.selfRefreshEnergy 718140.000000 # Energy for self refresh per rank (pJ)
system.physmem_1.totalEnergy 146140035 # Total energy per rank (pJ)
system.physmem_1.averagePower 540.858753 # Core power per rank (mW)
system.physmem_1.totalIdleTime 235236750 # Total Idle time Per DRAM Rank
system.physmem_1.memoryStateTime::IDLE 8236250 # Time in different power states
system.physmem_1.memoryStateTime::REF 9106000 # Time in different power states
system.physmem_1.memoryStateTime::SREF 690750 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 53009000 # Time in different power states
system.physmem_1.memoryStateTime::ACT 17416750 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 181741250 # Time in different power states
system.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 61485 # Number of BP lookups
system.cpu.branchPred.condPredicted 39320 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 4384 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 51667 # Number of BTB lookups
system.cpu.branchPred.BTBHits 29457 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 57.013181 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups 10264 # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits 6105 # Number of indirect target hits.
system.cpu.branchPred.indirectMisses 4159 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 2365 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 115 # Number of system calls
system.cpu.pwrStateResidencyTicks::ON 270200000 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 540400 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 226275 # Number of instructions committed
system.cpu.committedOps 226275 # Number of ops (including micro ops) committed
system.cpu.discardedOps 10623 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 2.388244 # CPI: cycles per instruction
system.cpu.ipc 0.418718 # IPC: instructions per cycle
system.cpu.op_class_0::No_OpClass 117 0.05% 0.05% # Class of committed instruction
system.cpu.op_class_0::IntAlu 136540 60.34% 60.39% # Class of committed instruction
system.cpu.op_class_0::IntMult 325 0.14% 60.54% # Class of committed instruction
system.cpu.op_class_0::IntDiv 40 0.02% 60.56% # Class of committed instruction
system.cpu.op_class_0::FloatAdd 104 0.05% 60.60% # Class of committed instruction
system.cpu.op_class_0::FloatCmp 119 0.05% 60.65% # Class of committed instruction
system.cpu.op_class_0::FloatCvt 43 0.02% 60.67% # Class of committed instruction
system.cpu.op_class_0::FloatMult 30 0.01% 60.69% # Class of committed instruction
system.cpu.op_class_0::FloatMultAcc 0 0.00% 60.69% # Class of committed instruction
system.cpu.op_class_0::FloatDiv 11 0.00% 60.69% # Class of committed instruction
system.cpu.op_class_0::FloatMisc 0 0.00% 60.69% # Class of committed instruction
system.cpu.op_class_0::FloatSqrt 5 0.00% 60.69% # Class of committed instruction
system.cpu.op_class_0::SimdAdd 0 0.00% 60.69% # Class of committed instruction
system.cpu.op_class_0::SimdAddAcc 0 0.00% 60.69% # Class of committed instruction
system.cpu.op_class_0::SimdAlu 0 0.00% 60.69% # Class of committed instruction
system.cpu.op_class_0::SimdCmp 0 0.00% 60.69% # Class of committed instruction
system.cpu.op_class_0::SimdCvt 0 0.00% 60.69% # Class of committed instruction
system.cpu.op_class_0::SimdMisc 0 0.00% 60.69% # Class of committed instruction
system.cpu.op_class_0::SimdMult 0 0.00% 60.69% # Class of committed instruction
system.cpu.op_class_0::SimdMultAcc 0 0.00% 60.69% # Class of committed instruction
system.cpu.op_class_0::SimdShift 0 0.00% 60.69% # Class of committed instruction
system.cpu.op_class_0::SimdShiftAcc 0 0.00% 60.69% # Class of committed instruction
system.cpu.op_class_0::SimdSqrt 0 0.00% 60.69% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAdd 0 0.00% 60.69% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAlu 0 0.00% 60.69% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCmp 0 0.00% 60.69% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCvt 0 0.00% 60.69% # Class of committed instruction
system.cpu.op_class_0::SimdFloatDiv 0 0.00% 60.69% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMisc 0 0.00% 60.69% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMult 0 0.00% 60.69% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 60.69% # Class of committed instruction
system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 60.69% # Class of committed instruction
system.cpu.op_class_0::MemRead 51297 22.67% 83.36% # Class of committed instruction
system.cpu.op_class_0::MemWrite 37094 16.39% 99.76% # Class of committed instruction
system.cpu.op_class_0::FloatMemRead 414 0.18% 99.94% # Class of committed instruction
system.cpu.op_class_0::FloatMemWrite 136 0.06% 100.00% # Class of committed instruction
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::total 226275 # Class of committed instruction
system.cpu.tickCycles 340080 # Number of cycles that the object actually ticked
system.cpu.idleCycles 200320 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 242.026814 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 90015 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 302 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 298.062914 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 242.026814 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.059089 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.059089 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 302 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 272 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.073730 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 181330 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 181330 # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 53182 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 53182 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 36833 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 36833 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 90015 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 90015 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 90015 # number of overall hits
system.cpu.dcache.overall_hits::total 90015 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 103 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 103 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 396 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 396 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 499 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 499 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 499 # number of overall misses
system.cpu.dcache.overall_misses::total 499 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 9494000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 9494000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 31678500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 31678500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 41172500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 41172500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 41172500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 41172500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 53285 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 53285 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 37229 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 37229 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 90514 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 90514 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 90514 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 90514 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001933 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.001933 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010637 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.010637 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.005513 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.005513 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.005513 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.005513 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 92174.757282 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 92174.757282 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 79996.212121 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 79996.212121 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 82510.020040 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 82510.020040 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 82510.020040 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 82510.020040 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 191 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 191 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 197 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 197 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 197 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 197 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 97 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 97 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 205 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 205 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 302 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 302 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 302 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 302 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8881000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 8881000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 16356000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 16356000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25237000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 25237000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25237000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 25237000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001820 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001820 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005506 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005506 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003337 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.003337 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003337 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.003337 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 91556.701031 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 91556.701031 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79785.365854 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79785.365854 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 83566.225166 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 83566.225166 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 83566.225166 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 83566.225166 # average overall mshr miss latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 69 # number of replacements
system.cpu.icache.tags.tagsinuse 555.532163 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 101722 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 1051 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 96.785918 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 555.532163 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.271256 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.271256 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 982 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 189 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 724 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.479492 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 206597 # Number of tag accesses
system.cpu.icache.tags.data_accesses 206597 # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 101722 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 101722 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 101722 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 101722 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 101722 # number of overall hits
system.cpu.icache.overall_hits::total 101722 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1051 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1051 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1051 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1051 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1051 # number of overall misses
system.cpu.icache.overall_misses::total 1051 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 87209500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 87209500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 87209500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 87209500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 87209500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 87209500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 102773 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 102773 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 102773 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 102773 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 102773 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 102773 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.010226 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.010226 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.010226 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.010226 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.010226 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.010226 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 82977.640343 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 82977.640343 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 82977.640343 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 82977.640343 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 82977.640343 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 82977.640343 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks 69 # number of writebacks
system.cpu.icache.writebacks::total 69 # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1051 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 1051 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 1051 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 1051 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 1051 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 1051 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 86158500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 86158500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 86158500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 86158500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 86158500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 86158500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.010226 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.010226 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.010226 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.010226 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.010226 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.010226 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 81977.640343 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 81977.640343 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 81977.640343 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 81977.640343 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 81977.640343 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 81977.640343 # average overall mshr miss latency
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 827.037841 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 73 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 1349 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.054114 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst 585.656330 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 241.381510 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.017873 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.007366 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.025239 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 1349 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 215 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1060 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.041168 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 12725 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 12725 # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackClean_hits::writebacks 69 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 69 # number of WritebackClean hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 3 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 1 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 4 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits
system.cpu.l2cache.overall_hits::total 4 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 205 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 205 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1048 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 1048 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 96 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 96 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 1048 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 301 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 1349 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 1048 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 301 # number of overall misses
system.cpu.l2cache.overall_misses::total 1349 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16048500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 16048500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 84550500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 84550500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 8723000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 8723000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 84550500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 24771500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 109322000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 84550500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 24771500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 109322000 # number of overall miss cycles
system.cpu.l2cache.WritebackClean_accesses::writebacks 69 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 69 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 205 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 205 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1051 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 1051 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 97 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 97 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 1051 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 302 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 1353 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 1051 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 302 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 1353 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.997146 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.997146 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.989691 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.989691 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.997146 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.996689 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.997044 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.997146 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.996689 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.997044 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78285.365854 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78285.365854 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80677.958015 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80677.958015 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 90864.583333 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 90864.583333 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80677.958015 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82297.342193 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 81039.288362 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80677.958015 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82297.342193 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 81039.288362 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 205 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 205 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1048 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1048 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 96 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 96 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 1048 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 301 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 1349 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 1048 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 301 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 1349 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13998500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13998500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 74070500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 74070500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7763000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7763000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 74070500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 21761500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 95832000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 74070500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 21761500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 95832000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.997146 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.997146 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.989691 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.989691 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.997146 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.996689 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.997044 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.997146 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.996689 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.997044 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68285.365854 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68285.365854 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70677.958015 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70677.958015 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 80864.583333 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 80864.583333 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70677.958015 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72297.342193 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71039.288362 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70677.958015 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72297.342193 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71039.288362 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 1422 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 70 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 1148 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 69 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 205 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 205 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 1051 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 97 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2171 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 604 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 2775 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 71680 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 19328 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 91008 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples 1353 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.000739 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.027186 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 1352 99.93% 99.93% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 1 0.07% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 1353 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 780000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 1576500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.6 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 453000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
system.membus.snoop_filter.tot_requests 1349 # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 1144 # Transaction distribution
system.membus.trans_dist::ReadExReq 205 # Transaction distribution
system.membus.trans_dist::ReadExResp 205 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 1144 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2698 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 2698 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 86336 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 86336 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples 1349 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 1349 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 1349 # Request fanout histogram
system.membus.reqLayer0.occupancy 1554000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.6 # Layer utilization (%)
system.membus.respLayer1.occupancy 7151000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 2.6 # Layer utilization (%)
---------- End Simulation Statistics ----------

872
tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/config.ini Normal file
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@ -0,0 +1,872 @@
[root]
type=Root
children=system
eventq_index=0
full_system=false
sim_quantum=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.clk_domain]
type=SrcClockDomain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.cpu]
type=DerivO3CPU
children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
branchPred=system.cpu.branchPred
cachePorts=200
checker=Null
clk_domain=system.cpu_clk_domain
commitToDecodeDelay=1
commitToFetchDelay=1
commitToIEWDelay=1
commitToRenameDelay=1
commitWidth=8
cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
default_p_state=UNDEFINED
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
eventq_index=0
fetchBufferSize=64
fetchQueueSize=32
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
numIQEntries=64
numPhysCCRegs=0
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
renameToIEWDelay=2
renameToROBDelay=1
renameWidth=8
simpoint_start_insts=
smtCommitPolicy=RoundRobin
smtFetchPolicy=SingleThread
smtIQPolicy=Partitioned
smtIQThreshold=100
smtLSQPolicy=Partitioned
smtLSQThreshold=100
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
type=TournamentBP
BTBEntries=4096
BTBTagSize=16
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
indirectHashGHR=true
indirectHashTargets=true
indirectPathLength=3
indirectSets=256
indirectTagSize=16
indirectWays=2
instShiftAmt=2
localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
useIndirect=true
[system.cpu.dcache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
is_read_only=false
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=262144
system=system
tag_latency=2
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dcache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=262144
tag_latency=2
[system.cpu.dtb]
type=RiscvTLB
eventq_index=0
size=64
[system.cpu.fuPool]
type=FUPool
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
eventq_index=0
[system.cpu.fuPool.FUList0]
type=FUDesc
children=opList
count=6
eventq_index=0
opList=system.cpu.fuPool.FUList0.opList
[system.cpu.fuPool.FUList0.opList]
type=OpDesc
eventq_index=0
opClass=IntAlu
opLat=1
pipelined=true
[system.cpu.fuPool.FUList1]
type=FUDesc
children=opList0 opList1
count=2
eventq_index=0
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
[system.cpu.fuPool.FUList1.opList0]
type=OpDesc
eventq_index=0
opClass=IntMult
opLat=3
pipelined=true
[system.cpu.fuPool.FUList1.opList1]
type=OpDesc
eventq_index=0
opClass=IntDiv
opLat=20
pipelined=false
[system.cpu.fuPool.FUList2]
type=FUDesc
children=opList0 opList1 opList2
count=4
eventq_index=0
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
[system.cpu.fuPool.FUList2.opList0]
type=OpDesc
eventq_index=0
opClass=FloatAdd
opLat=2
pipelined=true
[system.cpu.fuPool.FUList2.opList1]
type=OpDesc
eventq_index=0
opClass=FloatCmp
opLat=2
pipelined=true
[system.cpu.fuPool.FUList2.opList2]
type=OpDesc
eventq_index=0
opClass=FloatCvt
opLat=2
pipelined=true
[system.cpu.fuPool.FUList3]
type=FUDesc
children=opList0 opList1 opList2 opList3 opList4
count=2
eventq_index=0
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4
[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
eventq_index=0
opClass=FloatMult
opLat=4
pipelined=true
[system.cpu.fuPool.FUList3.opList1]
type=OpDesc
eventq_index=0
opClass=FloatMultAcc
opLat=5
pipelined=true
[system.cpu.fuPool.FUList3.opList2]
type=OpDesc
eventq_index=0
opClass=FloatMisc
opLat=3
pipelined=true
[system.cpu.fuPool.FUList3.opList3]
type=OpDesc
eventq_index=0
opClass=FloatDiv
opLat=12
pipelined=false
[system.cpu.fuPool.FUList3.opList4]
type=OpDesc
eventq_index=0
opClass=FloatSqrt
opLat=24
pipelined=false
[system.cpu.fuPool.FUList4]
type=FUDesc
children=opList0 opList1
count=0
eventq_index=0
opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1
[system.cpu.fuPool.FUList4.opList0]
type=OpDesc
eventq_index=0
opClass=MemRead
opLat=1
pipelined=true
[system.cpu.fuPool.FUList4.opList1]
type=OpDesc
eventq_index=0
opClass=FloatMemRead
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5]
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
count=4
eventq_index=0
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
[system.cpu.fuPool.FUList5.opList00]
type=OpDesc
eventq_index=0
opClass=SimdAdd
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList01]
type=OpDesc
eventq_index=0
opClass=SimdAddAcc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList02]
type=OpDesc
eventq_index=0
opClass=SimdAlu
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList03]
type=OpDesc
eventq_index=0
opClass=SimdCmp
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList04]
type=OpDesc
eventq_index=0
opClass=SimdCvt
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList05]
type=OpDesc
eventq_index=0
opClass=SimdMisc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList06]
type=OpDesc
eventq_index=0
opClass=SimdMult
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList07]
type=OpDesc
eventq_index=0
opClass=SimdMultAcc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList08]
type=OpDesc
eventq_index=0
opClass=SimdShift
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList09]
type=OpDesc
eventq_index=0
opClass=SimdShiftAcc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList10]
type=OpDesc
eventq_index=0
opClass=SimdSqrt
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList11]
type=OpDesc
eventq_index=0
opClass=SimdFloatAdd
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList12]
type=OpDesc
eventq_index=0
opClass=SimdFloatAlu
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList13]
type=OpDesc
eventq_index=0
opClass=SimdFloatCmp
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList14]
type=OpDesc
eventq_index=0
opClass=SimdFloatCvt
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList15]
type=OpDesc
eventq_index=0
opClass=SimdFloatDiv
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList16]
type=OpDesc
eventq_index=0
opClass=SimdFloatMisc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList17]
type=OpDesc
eventq_index=0
opClass=SimdFloatMult
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList18]
type=OpDesc
eventq_index=0
opClass=SimdFloatMultAcc
opLat=1
pipelined=true
[system.cpu.fuPool.FUList5.opList19]
type=OpDesc
eventq_index=0
opClass=SimdFloatSqrt
opLat=1
pipelined=true
[system.cpu.fuPool.FUList6]
type=FUDesc
children=opList0 opList1
count=0
eventq_index=0
opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
[system.cpu.fuPool.FUList6.opList0]
type=OpDesc
eventq_index=0
opClass=MemWrite
opLat=1
pipelined=true
[system.cpu.fuPool.FUList6.opList1]
type=OpDesc
eventq_index=0
opClass=FloatMemWrite
opLat=1
pipelined=true
[system.cpu.fuPool.FUList7]
type=FUDesc
children=opList0 opList1 opList2 opList3
count=4
eventq_index=0
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 system.cpu.fuPool.FUList7.opList2 system.cpu.fuPool.FUList7.opList3
[system.cpu.fuPool.FUList7.opList0]
type=OpDesc
eventq_index=0
opClass=MemRead
opLat=1
pipelined=true
[system.cpu.fuPool.FUList7.opList1]
type=OpDesc
eventq_index=0
opClass=MemWrite
opLat=1
pipelined=true
[system.cpu.fuPool.FUList7.opList2]
type=OpDesc
eventq_index=0
opClass=FloatMemRead
opLat=1
pipelined=true
[system.cpu.fuPool.FUList7.opList3]
type=OpDesc
eventq_index=0
opClass=FloatMemWrite
opLat=1
pipelined=true
[system.cpu.fuPool.FUList8]
type=FUDesc
children=opList
count=1
eventq_index=0
opList=system.cpu.fuPool.FUList8.opList
[system.cpu.fuPool.FUList8.opList]
type=OpDesc
eventq_index=0
opClass=IprAccess
opLat=3
pipelined=false
[system.cpu.icache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
is_read_only=true
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=131072
system=system
tag_latency=2
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=true
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.icache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=131072
tag_latency=2
[system.cpu.interrupts]
type=RiscvInterrupts
eventq_index=0
[system.cpu.isa]
type=RiscvISA
eventq_index=0
[system.cpu.itb]
type=RiscvTLB
eventq_index=0
size=64
[system.cpu.l2cache]
type=Cache
children=tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=20
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
is_read_only=false
max_miss_count=0
mshrs=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=20
sequential_access=false
size=2097152
system=system
tag_latency=20
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.l2cache.tags]
type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=20
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=2097152
tag_latency=20
[system.cpu.toL2Bus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=0
frontend_latency=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=false
power_model=Null
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.toL2Bus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=0
max_capacity=8388608
system=system
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=LiveProcess
cmd=insttest
cwd=
drivers=
egid=100
env=
errout=cerr
euid=100
eventq_index=0
executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64f/insttest
gid=100
input=cin
kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.dvfs_handler]
type=DVFSHandler
domains=
enable=false
eventq_index=0
sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=4
frontend_latency=3
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem]
type=DRAMCtrl
IDD0=0.055000
IDD02=0.000000
IDD2N=0.032000
IDD2N2=0.000000
IDD2P0=0.000000
IDD2P02=0.000000
IDD2P1=0.032000
IDD2P12=0.000000
IDD3N=0.038000
IDD3N2=0.000000
IDD3P0=0.000000
IDD3P02=0.000000
IDD3P1=0.038000
IDD3P12=0.000000
IDD4R=0.157000
IDD4R2=0.000000
IDD4W=0.125000
IDD4W2=0.000000
IDD5=0.235000
IDD52=0.000000
IDD6=0.020000
IDD62=0.000000
VDD=1.500000
VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
clk_domain=system.clk_domain
conf_table_reported=true
default_p_state=UNDEFINED
device_bus_width=8
device_rowbuffer_size=1024
device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
in_addr_map=true
kvm_map=true
max_accesses_per_row=16
mem_sched_policy=frfcfs
min_writes_per_switch=16
null=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
page_policy=open_adaptive
power_model=Null
range=0:134217727:0:0:0:0
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
tCCD_L=0
tCK=1250
tCL=13750
tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
tXP=6000
tXPDLL=0
tXS=270000
tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
port=system.membus.master[0]
[system.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.000000

1151
tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/config.json Normal file
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4
tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/simerr Executable file
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@ -0,0 +1,4 @@
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Unknown operating system; assuming Linux.
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick

121
tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/simout Executable file
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@ -0,0 +1,121 @@
Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/o3-timing/simout
Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Nov 30 2016 14:33:35
gem5 started Nov 30 2016 16:18:32
gem5 executing on zizzer, pid 34077
command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/o3-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64f/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
clear fsflags: PASS
flw: PASS
fsw: PASS
fmadd.s: PASS
fmadd.s, quiet NaN: PASS
fmadd.s, signaling NaN: PASS
fmadd.s, infinity: PASS
fmadd.s, -infinity: PASS
fmsub.s: PASS
fmsub.s, quiet NaN: PASS
fmsub.s, signaling NaN: PASS
fmsub.s, infinity: PASS
fmsub.s, -infinity: PASS
fmsub.s, subtract infinity: PASS
fnmsub.s: PASS
fnmsub.s, quiet NaN: PASS
fnmsub.s, signaling NaN: PASS
fnmsub.s, infinity: PASS
fnmsub.s, -infinity: PASS
fnmsub.s, subtract infinity: PASS
fnmadd.s: PASS
fnmadd.s, quiet NaN: PASS
fnmadd.s, signaling NaN: PASS
fnmadd.s, infinity: PASS
fnmadd.s, -infinity: PASS
fadd.s: PASS
fadd.s, quiet NaN: PASS
fadd.s, signaling NaN: PASS
fadd.s, infinity: PASS
fadd.s, -infinity: PASS
fsub.s: PASS
fsub.s, quiet NaN: PASS
fsub.s, signaling NaN: PASS
fsub.s, infinity: PASS
fsub.s, -infinity: PASS
fsub.s, subtract infinity: PASS
fmul.s: PASS
fmul.s, quiet NaN: PASS
fmul.s, signaling NaN: PASS
fmul.s, infinity: PASS
fmul.s, -infinity: PASS
fmul.s, 0*infinity: PASS
fmul.s, overflow: PASS
fmul.s, underflow: PASS
fdiv.s: PASS
fdiv.s, quiet NaN: PASS
fdiv.s, signaling NaN: PASS
fdiv.s/0: PASS
fdiv.s/infinity: PASS
fdiv.s, infinity/infinity: PASS
fdiv.s, 0/0: PASS
fdiv.s, infinity/0: PASS
fdiv.s, 0/infinity: PASS
fdiv.s, underflow: PASS
fdiv.s, overflow: PASS
fsqrt.s: PASS
fsqrt.s, NaN: PASS
fsqrt.s, quiet NaN: PASS
fsqrt.s, signaling NaN: PASS
fsqrt.s, infinity: PASS
fsgnj.s, ++: PASS
fsgnj.s, +-: PASS
fsgnj.s, -+: PASS
fsgnj.s, --: PASS
fsgnj.s, quiet NaN: PASS
fsgnj.s, signaling NaN: PASS
fsgnj.s, inject NaN: PASS
fsgnj.s, inject -NaN: PASS
fsgnjn.s, ++: PASS
fsgnjn.s, +-: PASS
fsgnjn.s, -+: PASS
fsgnjn.s, --: PASS
fsgnjn.s, quiet NaN: PASS
fsgnjn.s, signaling NaN: PASS
fsgnjn.s, inject NaN: PASS
fsgnjn.s, inject NaN: PASS
fsgnjx.s, ++: PASS
fsgnjx.s, +-: PASS
fsgnjx.s, -+: PASS
fsgnjx.s, --: PASS
fsgnjx.s, quiet NaN: PASS
fsgnjx.s, signaling NaN: PASS
fsgnjx.s, inject NaN: PASS
fsgnjx.s, inject -NaN: PASS
fmin.s: PASS
fmin.s, -infinity: PASS
fmin.s, infinity: PASS
fmin.s, quiet NaN first: PASS
fmin.s, quiet NaN second: PASS
fmin.s, quiet NaN both: PASS
fmin.s, signaling NaN first: PASS
fmin.s, signaling NaN second: PASS
fmin.s, signaling NaN both: PASS
fmax.s: PASS
fmax.s, -infinity: PASS
fmax.s, infinity: PASS
fmax.s, quiet NaN first: PASS
fmax.s, quiet NaN second: PASS
fmax.s, quiet NaN both: PASS
fmax.s, signaling NaN first: PASS
fmax.s, signaling NaN second: PASS
fmax.s, signaling NaN both: PASS
fcvt.w.s, truncate positive: PASS
fcvt.w.s, truncate negative: PASS
fcvt.w.s, 0.0: PASS
fcvt.w.s, -0.0: PASS
fcvt.w.s, overflow: FAIL (expected 2147483647; found -2147483648)
Exiting @ tick 113397000 because target called exit()

1020
tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/stats.txt Normal file
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