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stats: update stats for ld.so support

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Additional auxv entries leads to more instructions in start-up
while walking the list, along with different cache conflicts
wrt stack entries.
This commit is contained in:
Steve Reinhardt 2016-03-17 10:32:53 -07:00
parent 9b4249410e
commit d7c083864c
72 changed files with 9252 additions and 9242 deletions
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8
tests/long/se/20.parser/ref/arm/linux/o3-timing/simout
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@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing/
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Mar 15 2016 19:53:43
gem5 started Mar 15 2016 21:14:27
gem5 executing on dinar2c11, pid 11560
gem5 compiled Mar 16 2016 23:07:21
gem5 started Mar 16 2016 23:48:20
gem5 executing on dinar2c11, pid 25963
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing -re /home/stever/gem5-public/tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
@ -70,4 +70,4 @@ info: Increasing stack size by one page.
about 2 million people attended
the five best costumes got prizes
No errors!
Exiting @ tick 233975583000 because target called exit()
Exiting @ tick 234067145000 because target called exit()

1745
tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
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File diff suppressed because it is too large Load diff

4
tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini
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@ -656,9 +656,9 @@ env=
errout=cerr
euid=100
eventq_index=0
executable=/home/stever/m5/dist/cpu2000/binaries/x86/linux/parser
executable=/dist/m5/cpu2000/binaries/x86/linux/parser
gid=100
input=/home/stever/m5/dist/cpu2000/data/parser/mdred/input/parser.in
input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
kvmInSE=false
max_stack_size=67108864
output=cout

1
tests/long/se/20.parser/ref/x86/linux/o3-timing/simerr
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@ -1,2 +1 @@
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections

46
tests/long/se/20.parser/ref/x86/linux/o3-timing/simout
View file

@ -3,17 +3,29 @@ Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Mar 15 2016 21:27:50
gem5 started Mar 15 2016 21:35:29
gem5 executing on phenom, pid 15976
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing
gem5 compiled Mar 16 2016 22:57:26
gem5 started Mar 16 2016 22:58:58
gem5 executing on dinar2c11, pid 24771
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re /home/stever/gem5-public/tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Reading the dictionary files: **info: Increasing stack size by one page.
*******info: Increasing stack size by one page.
****************************************
******************************info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
**********
58924 words stored in 3784810 bytes
@ -25,28 +37,8 @@ Processing sentences in batch mode
Echoing of input sentence turned on.
* as had expected the party to be a success , it was a success
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
* do you know where John 's
* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
* how fast the program is it
* I am wondering whether to invite to the party
* I gave him for his birthday it
@ -86,9 +78,11 @@ info: Increasing stack size by one page.
the man with whom I play tennis is here
there is a dog in the park
this is not the man we know and love
info: Increasing stack size by one page.
info: Increasing stack size by one page.
we like to eat at restaurants , usually on weekends
what did John say he thought you should do
about 2 million people attended
the five best costumes got prizes
No errors!
Exiting @ tick 403557300500 because target called exit()
Exiting @ tick 404911731500 because target called exit()

1786
tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
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File diff suppressed because it is too large Load diff

8
tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout
View file

@ -3,9 +3,9 @@ Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-ato
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Mar 16 2016 15:38:19
gem5 started Mar 16 2016 15:38:59
gem5 executing on dinar2c11, pid 14361
gem5 compiled Mar 16 2016 22:57:26
gem5 started Mar 16 2016 22:58:08
gem5 executing on dinar2c11, pid 24736
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic -re /home/stever/gem5-public/tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
@ -72,4 +72,4 @@ info: Increasing stack size by one page.
about 2 million people attended
the five best costumes got prizes
No errors!
Exiting @ tick 885256008500 because target called exit()
Exiting @ tick 885772926000 because target called exit()

200
tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt
View file

@ -1,127 +1,127 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.885256 # Number of seconds simulated
sim_ticks 885256008500 # Number of ticks simulated
final_tick 885256008500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_seconds 0.885773 # Number of seconds simulated
sim_ticks 885772926000 # Number of ticks simulated
final_tick 885772926000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 362789 # Simulator instruction rate (inst/s)
host_op_rate 670835 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 388389023 # Simulator tick rate (ticks/s)
host_mem_usage 304128 # Number of bytes of host memory used
host_seconds 2279.30 # Real time elapsed on the host
sim_insts 826906380 # Number of instructions simulated
sim_ops 1529035683 # Number of ops (including micro ops) simulated
host_inst_rate 376226 # Simulator instruction rate (inst/s)
host_op_rate 696207 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 403037674 # Simulator tick rate (ticks/s)
host_mem_usage 304140 # Number of bytes of host memory used
host_seconds 2197.74 # Real time elapsed on the host
sim_insts 826847304 # Number of instructions simulated
sim_ops 1530082521 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 8547061720 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 2285750420 # Number of bytes read from this memory
system.physmem.bytes_read::total 10832812140 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 8547061720 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 8547061720 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 991875282 # Number of bytes written to this memory
system.physmem.bytes_written::total 991875282 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 1068382715 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 384117854 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1452500569 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 149164510 # Number of write requests responded to by this memory
system.physmem.num_writes::total 149164510 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 9654903935 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2582021921 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 12236925856 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 9654903935 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 9654903935 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1120438915 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1120438915 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 9654903935 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3702460837 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 13357364772 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::cpu.inst 8546485088 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 2285527276 # Number of bytes read from this memory
system.physmem.bytes_read::total 10832012364 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 8546485088 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 8546485088 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 991837474 # Number of bytes written to this memory
system.physmem.bytes_written::total 991837474 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 1068310636 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 384083342 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1452393978 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 149158211 # Number of write requests responded to by this memory
system.physmem.num_writes::total 149158211 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 9648618554 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2580263190 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 12228881744 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 9648618554 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 9648618554 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1119742368 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1119742368 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 9648618554 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3700005559 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 13348624112 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
system.cpu.workload.num_syscalls 551 # Number of system calls
system.cpu.numCycles 1770512018 # number of cpu cycles simulated
system.cpu.numCycles 1771545853 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 826906380 # Number of instructions committed
system.cpu.committedOps 1529035683 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1526653037 # Number of integer alu accesses
system.cpu.committedInsts 826847304 # Number of instructions committed
system.cpu.committedOps 1530082521 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1527470226 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 35346287 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 92662756 # number of instructions that are conditional controls
system.cpu.num_int_insts 1526653037 # number of integer instructions
system.cpu.num_conditional_control_insts 92881952 # number of instructions that are conditional controls
system.cpu.num_int_insts 1527470226 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_int_register_reads 3293861747 # number of times the integer registers were read
system.cpu.num_int_register_writes 1237389453 # number of times the integer registers were written
system.cpu.num_int_register_reads 3298246119 # number of times the integer registers were read
system.cpu.num_int_register_writes 1240060586 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_cc_register_reads 561356848 # number of times the CC registers were read
system.cpu.num_cc_register_writes 376698535 # number of times the CC registers were written
system.cpu.num_mem_refs 533282319 # number of memory refs
system.cpu.num_load_insts 384117825 # Number of load instructions
system.cpu.num_store_insts 149164494 # Number of store instructions
system.cpu.num_cc_register_reads 562449682 # number of times the CC registers were read
system.cpu.num_cc_register_writes 376900986 # number of times the CC registers were written
system.cpu.num_mem_refs 533241508 # number of memory refs
system.cpu.num_load_insts 384083313 # Number of load instructions
system.cpu.num_store_insts 149158195 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 1770512017.998000 # Number of busy cycles
system.cpu.num_busy_cycles 1771545852.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 149762544 # Number of branches fetched
system.cpu.op_class::No_OpClass 1818553 0.12% 0.12% # Class of executed instruction
system.cpu.op_class::IntAlu 989751625 64.73% 64.85% # Class of executed instruction
system.cpu.op_class::IntMult 306834 0.02% 64.87% # Class of executed instruction
system.cpu.op_class::IntDiv 3876352 0.25% 65.12% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::MemRead 384117825 25.12% 90.24% # Class of executed instruction
system.cpu.op_class::MemWrite 149164494 9.76% 100.00% # Class of executed instruction
system.cpu.Branches 149981740 # Number of branches fetched
system.cpu.op_class::No_OpClass 2048202 0.13% 0.13% # Class of executed instruction
system.cpu.op_class::IntAlu 989691029 64.68% 64.82% # Class of executed instruction
system.cpu.op_class::IntMult 306834 0.02% 64.84% # Class of executed instruction
system.cpu.op_class::IntDiv 4794948 0.31% 65.15% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::MemRead 384083313 25.10% 90.25% # Class of executed instruction
system.cpu.op_class::MemWrite 149158195 9.75% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 1529035683 # Class of executed instruction
system.membus.trans_dist::ReadReq 1452500569 # Transaction distribution
system.membus.trans_dist::ReadResp 1452500569 # Transaction distribution
system.membus.trans_dist::WriteReq 149164510 # Transaction distribution
system.membus.trans_dist::WriteResp 149164510 # Transaction distribution
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 2136765430 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.icache_port::total 2136765430 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1066564728 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::total 1066564728 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 3203330158 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 8547061720 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::total 8547061720 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 3277625702 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::total 3277625702 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 11824687422 # Cumulative packet size per connected master and slave (bytes)
system.cpu.op_class::total 1530082521 # Class of executed instruction
system.membus.trans_dist::ReadReq 1452393978 # Transaction distribution
system.membus.trans_dist::ReadResp 1452393978 # Transaction distribution
system.membus.trans_dist::WriteReq 149158211 # Transaction distribution
system.membus.trans_dist::WriteResp 149158211 # Transaction distribution
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 2136621272 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.icache_port::total 2136621272 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1066483106 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::total 1066483106 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 3203104378 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 8546485088 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::total 8546485088 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 3277364750 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::total 3277364750 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 11823849838 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 1601665079 # Request fanout histogram
system.membus.snoop_fanout::mean 0.667045 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.471271 # Request fanout histogram
system.membus.snoop_fanout::samples 1601552189 # Request fanout histogram
system.membus.snoop_fanout::mean 0.667047 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.471270 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 533282364 33.30% 33.30% # Request fanout histogram
system.membus.snoop_fanout::1 1068382715 66.70% 100.00% # Request fanout histogram
system.membus.snoop_fanout::0 533241553 33.30% 33.30% # Request fanout histogram
system.membus.snoop_fanout::1 1068310636 66.70% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 1601665079 # Request fanout histogram
system.membus.snoop_fanout::total 1601552189 # Request fanout histogram
---------- End Simulation Statistics ----------

8
tests/long/se/20.parser/ref/x86/linux/simple-timing/simout
View file

@ -3,9 +3,9 @@ Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-tim
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Mar 16 2016 15:38:19
gem5 started Mar 16 2016 15:38:49
gem5 executing on dinar2c11, pid 14355
gem5 compiled Mar 16 2016 22:57:26
gem5 started Mar 16 2016 22:57:56
gem5 executing on dinar2c11, pid 24718
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing -re /home/stever/gem5-public/tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
@ -72,4 +72,4 @@ info: Increasing stack size by one page.
about 2 million people attended
the five best costumes got prizes
No errors!
Exiting @ tick 1650600522500 because target called exit()
Exiting @ tick 1650501252500 because target called exit()

690
tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
View file

@ -1,111 +1,111 @@
---------- Begin Simulation Statistics ----------
sim_seconds 1.650601 # Number of seconds simulated
sim_ticks 1650600522500 # Number of ticks simulated
final_tick 1650600522500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_seconds 1.650501 # Number of seconds simulated
sim_ticks 1650501252500 # Number of ticks simulated
final_tick 1650501252500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 236277 # Simulator instruction rate (inst/s)
host_op_rate 436901 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 471636555 # Simulator tick rate (ticks/s)
host_mem_usage 314152 # Number of bytes of host memory used
host_seconds 3499.73 # Real time elapsed on the host
sim_insts 826906380 # Number of instructions simulated
sim_ops 1529035683 # Number of ops (including micro ops) simulated
host_inst_rate 239314 # Simulator instruction rate (inst/s)
host_op_rate 442851 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 477703969 # Simulator tick rate (ticks/s)
host_mem_usage 314168 # Number of bytes of host memory used
host_seconds 3455.07 # Real time elapsed on the host
sim_insts 826847304 # Number of instructions simulated
sim_ops 1530082521 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 115776 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 24258880 # Number of bytes read from this memory
system.physmem.bytes_read::total 24374656 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 24258944 # Number of bytes read from this memory
system.physmem.bytes_read::total 24374720 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 115776 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 115776 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 18765184 # Number of bytes written to this memory
system.physmem.bytes_written::total 18765184 # Number of bytes written to this memory
system.physmem.bytes_written::writebacks 18765248 # Number of bytes written to this memory
system.physmem.bytes_written::total 18765248 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 1809 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 379045 # Number of read requests responded to by this memory
system.physmem.num_reads::total 380854 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 293206 # Number of write requests responded to by this memory
system.physmem.num_writes::total 293206 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 70142 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 14697002 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 14767144 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 70142 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 70142 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 11368701 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 11368701 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 11368701 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 70142 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 14697002 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 26135845 # Total bandwidth to/from this memory (bytes/s)
system.physmem.num_reads::cpu.data 379046 # Number of read requests responded to by this memory
system.physmem.num_reads::total 380855 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 293207 # Number of write requests responded to by this memory
system.physmem.num_writes::total 293207 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 70146 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 14697925 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 14768071 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 70146 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 70146 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 11369424 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 11369424 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 11369424 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 70146 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 14697925 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 26137495 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
system.cpu.workload.num_syscalls 551 # Number of system calls
system.cpu.numCycles 3301201045 # number of cpu cycles simulated
system.cpu.numCycles 3301002505 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 826906380 # Number of instructions committed
system.cpu.committedOps 1529035683 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1526653037 # Number of integer alu accesses
system.cpu.committedInsts 826847304 # Number of instructions committed
system.cpu.committedOps 1530082521 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1527470226 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 35346287 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 92662756 # number of instructions that are conditional controls
system.cpu.num_int_insts 1526653037 # number of integer instructions
system.cpu.num_conditional_control_insts 92881952 # number of instructions that are conditional controls
system.cpu.num_int_insts 1527470226 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_int_register_reads 3293861747 # number of times the integer registers were read
system.cpu.num_int_register_writes 1237389453 # number of times the integer registers were written
system.cpu.num_int_register_reads 3298246119 # number of times the integer registers were read
system.cpu.num_int_register_writes 1240060586 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_cc_register_reads 561356848 # number of times the CC registers were read
system.cpu.num_cc_register_writes 376698535 # number of times the CC registers were written
system.cpu.num_mem_refs 533282319 # number of memory refs
system.cpu.num_load_insts 384117825 # Number of load instructions
system.cpu.num_store_insts 149164494 # Number of store instructions
system.cpu.num_cc_register_reads 562449682 # number of times the CC registers were read
system.cpu.num_cc_register_writes 376900986 # number of times the CC registers were written
system.cpu.num_mem_refs 533241508 # number of memory refs
system.cpu.num_load_insts 384083313 # Number of load instructions
system.cpu.num_store_insts 149158195 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 3301201044.998000 # Number of busy cycles
system.cpu.num_busy_cycles 3301002504.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 149762544 # Number of branches fetched
system.cpu.op_class::No_OpClass 1818553 0.12% 0.12% # Class of executed instruction
system.cpu.op_class::IntAlu 989751625 64.73% 64.85% # Class of executed instruction
system.cpu.op_class::IntMult 306834 0.02% 64.87% # Class of executed instruction
system.cpu.op_class::IntDiv 3876352 0.25% 65.12% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.12% # Class of executed instruction
system.cpu.op_class::MemRead 384117825 25.12% 90.24% # Class of executed instruction
system.cpu.op_class::MemWrite 149164494 9.76% 100.00% # Class of executed instruction
system.cpu.Branches 149981740 # Number of branches fetched
system.cpu.op_class::No_OpClass 2048202 0.13% 0.13% # Class of executed instruction
system.cpu.op_class::IntAlu 989691029 64.68% 64.82% # Class of executed instruction
system.cpu.op_class::IntMult 306834 0.02% 64.84% # Class of executed instruction
system.cpu.op_class::IntDiv 4794948 0.31% 65.15% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.15% # Class of executed instruction
system.cpu.op_class::MemRead 384083313 25.10% 90.25% # Class of executed instruction
system.cpu.op_class::MemWrite 149158195 9.75% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 1529035683 # Class of executed instruction
system.cpu.dcache.tags.replacements 2515885 # number of replacements
system.cpu.dcache.tags.tagsinuse 4086.387052 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 530762383 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 2519981 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 210.621581 # Average number of references to valid blocks.
system.cpu.op_class::total 1530082521 # Class of executed instruction
system.cpu.dcache.tags.replacements 2517016 # number of replacements
system.cpu.dcache.tags.tagsinuse 4086.386474 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 530720441 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 2521112 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 210.510458 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 8246025500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4086.387052 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_blocks::cpu.data 4086.386474 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.997653 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.997653 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
@ -115,56 +115,56 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 29
system.cpu.dcache.tags.age_task_id_blocks_1024::3 4038 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 1069084709 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 1069084709 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 382389020 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 382389020 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 148373363 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 148373363 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 530762383 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 530762383 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 530762383 # number of overall hits
system.cpu.dcache.overall_hits::total 530762383 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1728834 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1728834 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 791147 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 791147 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 2519981 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 2519981 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 2519981 # number of overall misses
system.cpu.dcache.overall_misses::total 2519981 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 30936646500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 30936646500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 20396358500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 20396358500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 51333005000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 51333005000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 51333005000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 51333005000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 384117854 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 384117854 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 149164510 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 149164510 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 533282364 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 533282364 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 533282364 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 533282364 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004501 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.004501 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005304 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.005304 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.004725 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.004725 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.004725 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.004725 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17894.515321 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 17894.515321 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25780.744286 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 25780.744286 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 20370.393666 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 20370.393666 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 20370.393666 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 20370.393666 # average overall miss latency
system.cpu.dcache.tags.tag_accesses 1069004218 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 1069004218 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 382353600 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 382353600 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 148366841 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 148366841 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 530720441 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 530720441 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 530720441 # number of overall hits
system.cpu.dcache.overall_hits::total 530720441 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1729742 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1729742 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 791370 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 791370 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 2521112 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 2521112 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 2521112 # number of overall misses
system.cpu.dcache.overall_misses::total 2521112 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 30948499500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 30948499500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 20399257500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 20399257500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 51347757000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 51347757000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 51347757000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 51347757000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 384083342 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 384083342 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 149158211 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 149158211 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 533241553 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 533241553 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 533241553 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 533241553 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004504 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.004504 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005306 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.005306 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.004728 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.004728 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.004728 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.004728 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17891.974352 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 17891.974352 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25777.142803 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 25777.142803 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 20367.106658 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 20367.106658 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 20367.106658 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 20367.106658 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -173,50 +173,50 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 2324237 # number of writebacks
system.cpu.dcache.writebacks::total 2324237 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1728834 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1728834 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 791147 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 791147 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 2519981 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 2519981 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 2519981 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 2519981 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29207812500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 29207812500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19605211500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 19605211500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 48813024000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 48813024000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 48813024000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 48813024000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004501 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004501 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005304 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005304 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004725 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.004725 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004725 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.004725 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16894.515321 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16894.515321 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24780.744286 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24780.744286 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19370.393666 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 19370.393666 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19370.393666 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 19370.393666 # average overall mshr miss latency
system.cpu.dcache.writebacks::writebacks 2325221 # number of writebacks
system.cpu.dcache.writebacks::total 2325221 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1729742 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1729742 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 791370 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 791370 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 2521112 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 2521112 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 2521112 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 2521112 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29218757500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 29218757500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19607887500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 19607887500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 48826645000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 48826645000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 48826645000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 48826645000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004504 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004504 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005306 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005306 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004728 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.004728 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004728 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.004728 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16891.974352 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16891.974352 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24777.142803 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24777.142803 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19367.106658 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 19367.106658 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19367.106658 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 19367.106658 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 1253 # number of replacements
system.cpu.icache.tags.tagsinuse 881.377882 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 1068379901 # Total number of references to valid blocks.
system.cpu.icache.tags.tagsinuse 881.361687 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 1068307822 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 2814 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 379665.920753 # Average number of references to valid blocks.
system.cpu.icache.tags.avg_refs 379640.306326 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 881.377882 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.430360 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.430360 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_blocks::cpu.inst 881.361687 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.430352 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.430352 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1561 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
@ -224,44 +224,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 7
system.cpu.icache.tags.age_task_id_blocks_1024::3 8 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1507 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.762207 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 2136768244 # Number of tag accesses
system.cpu.icache.tags.data_accesses 2136768244 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 1068379901 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1068379901 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1068379901 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 1068379901 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 1068379901 # number of overall hits
system.cpu.icache.overall_hits::total 1068379901 # number of overall hits
system.cpu.icache.tags.tag_accesses 2136624086 # Number of tag accesses
system.cpu.icache.tags.data_accesses 2136624086 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 1068307822 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1068307822 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1068307822 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 1068307822 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 1068307822 # number of overall hits
system.cpu.icache.overall_hits::total 1068307822 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 2814 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 2814 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 2814 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 2814 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 2814 # number of overall misses
system.cpu.icache.overall_misses::total 2814 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 125256000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 125256000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 125256000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 125256000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 125256000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 125256000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 1068382715 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_accesses::cpu.inst 1068382715 # number of demand (read+write) accesses
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system.cpu.icache.ReadReq_miss_latency::cpu.inst 125255000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 125255000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 125255000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 125255000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 125255000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 125255000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 1068310636 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 1068310636 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.overall_accesses::cpu.inst 1068310636 # number of overall (read+write) accesses
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system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000003 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000003 # miss rate for ReadReq accesses
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system.cpu.icache.overall_miss_rate::total 0.000003 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44511.727079 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 44511.727079 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 44511.727079 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 44511.727079 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 44511.727079 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 44511.727079 # average overall miss latency
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44511.371713 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 44511.371713 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 44511.371713 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 44511.371713 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 44511.371713 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 44511.371713 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -278,126 +278,126 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 2814
system.cpu.icache.demand_mshr_misses::total 2814 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 2814 # number of overall MSHR misses
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system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 122442000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 122442000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 122442000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 122442000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 122442000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 122442000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 122441000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 122441000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 122441000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 122441000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 122441000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 122441000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 43511.727079 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43511.727079 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43511.727079 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 43511.727079 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43511.727079 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 43511.727079 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 43511.371713 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43511.371713 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43511.371713 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 43511.371713 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43511.371713 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 43511.371713 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 348437 # number of replacements
system.cpu.l2cache.tags.tagsinuse 29288.556947 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 3849932 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 380797 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 10.110195 # Average number of references to valid blocks.
system.cpu.l2cache.tags.replacements 348438 # number of replacements
system.cpu.l2cache.tags.tagsinuse 29288.734166 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 3851952 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 380798 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 10.115473 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 756996028500 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 20940.547795 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 131.260188 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 8216.748964 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.639055 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_blocks::writebacks 20940.857984 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 131.259734 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 8216.616448 # Average occupied blocks per requestor
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system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004006 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.250755 # Average percentage of cache occupancy
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system.cpu.l2cache.tags.occ_percent::cpu.data 0.250751 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.893821 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32360 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 8218 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 24062 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 8220 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 24060 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987549 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 41491408 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 41491408 # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks 2324237 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 2324237 # number of WritebackDirty hits
system.cpu.l2cache.tags.tag_accesses 41509728 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 41509728 # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks 2325221 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 2325221 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 1253 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 1253 # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 584791 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 584791 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 585014 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 585014 # number of ReadExReq hits
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system.cpu.l2cache.ReadCleanReq_hits::total 1005 # number of ReadCleanReq hits
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system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59511.885019 # average overall miss latency
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system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59511.332228 # average overall miss latency
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system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -406,125 +406,125 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.016961 # average ReadExReq mshr miss latency
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system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49511.885019 # average ReadCleanReq mshr miss latency
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system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500.234526 # average ReadSharedReq mshr miss latency
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system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49511.332228 # average ReadCleanReq mshr miss latency
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system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500.234524 # average ReadSharedReq mshr miss latency
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system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500.116081 # average overall mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49511.885019 # average overall mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49511.332228 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500.116081 # average overall mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.169356 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.snoop_filter.tot_requests 5039933 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2517138 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_requests 5042195 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2518269 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 1729 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1729 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp 1731648 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 2617444 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 1732556 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 2618429 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 1253 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 246878 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 791147 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 791147 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 247025 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 791370 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 791370 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 2814 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 1728834 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 1729742 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6881 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7555847 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 7562728 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7559240 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 7566121 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 260288 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 310029952 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 310290240 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 348437 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 2871232 # Request fanout histogram
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 310165312 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 310425600 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 348438 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 2872364 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.000602 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.024532 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.024527 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 2869503 99.94% 99.94% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 2870635 99.94% 99.94% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 1729 0.06% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 2871232 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 4845456500 # Layer occupancy (ticks)
system.cpu.toL2Bus.snoop_fanout::total 2872364 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 4847571500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 4221000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 3779971500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.occupancy 3781668000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
system.membus.trans_dist::ReadResp 174498 # Transaction distribution
system.membus.trans_dist::WritebackDirty 293206 # Transaction distribution
system.membus.trans_dist::ReadResp 174499 # Transaction distribution
system.membus.trans_dist::WritebackDirty 293207 # Transaction distribution
system.membus.trans_dist::CleanEvict 53507 # Transaction distribution
system.membus.trans_dist::ReadExReq 206356 # Transaction distribution
system.membus.trans_dist::ReadExResp 206356 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 174498 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1108421 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1108421 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1108421 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43139840 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43139840 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 43139840 # Cumulative packet size per connected master and slave (bytes)
system.membus.trans_dist::ReadSharedReq 174499 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1108424 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1108424 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1108424 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43139968 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43139968 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 43139968 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 727567 # Request fanout histogram
system.membus.snoop_fanout::samples 727569 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 727567 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::0 727569 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 727567 # Request fanout histogram
system.membus.reqLayer0.occupancy 1900421500 # Layer occupancy (ticks)
system.membus.snoop_fanout::total 727569 # Request fanout histogram
system.membus.reqLayer0.occupancy 1900428000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.membus.respLayer1.occupancy 1904270000 # Layer occupancy (ticks)
system.membus.respLayer1.occupancy 1904275000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
---------- End Simulation Statistics ----------

8
tests/long/se/30.eon/ref/arm/linux/simple-timing/simout
View file

@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Mar 16 2016 15:51:04
gem5 started Mar 16 2016 17:19:39
gem5 executing on dinar2c11, pid 17050
gem5 compiled Mar 16 2016 23:07:21
gem5 started Mar 16 2016 23:13:40
gem5 executing on dinar2c11, pid 25474
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing -re /home/stever/gem5-public/tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
@ -16,4 +16,4 @@ info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
OO-style eon Time= 0.510000
Exiting @ tick 517287152500 because target called exit()
Exiting @ tick 517291025500 because target called exit()

702
tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt
View file

@ -1,34 +1,34 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.517287 # Number of seconds simulated
sim_ticks 517287152500 # Number of ticks simulated
final_tick 517287152500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_seconds 0.517291 # Number of seconds simulated
sim_ticks 517291025500 # Number of ticks simulated
final_tick 517291025500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 131506 # Simulator instruction rate (inst/s)
host_op_rate 157879 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 249419657 # Simulator tick rate (ticks/s)
host_mem_usage 307088 # Number of bytes of host memory used
host_seconds 2073.96 # Real time elapsed on the host
sim_insts 272737951 # Number of instructions simulated
sim_ops 327435116 # Number of ops (including micro ops) simulated
host_inst_rate 222408 # Simulator instruction rate (inst/s)
host_op_rate 267009 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 421830266 # Simulator tick rate (ticks/s)
host_mem_usage 307072 # Number of bytes of host memory used
host_seconds 1226.30 # Real time elapsed on the host
sim_insts 272739286 # Number of instructions simulated
sim_ops 327433744 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 166976 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 269696 # Number of bytes read from this memory
system.physmem.bytes_read::total 436672 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 166976 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 166976 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 2609 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 4214 # Number of read requests responded to by this memory
system.physmem.num_reads::total 6823 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 322792 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 521366 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 844158 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 322792 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 322792 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 322792 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 521366 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 844158 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::cpu.inst 166912 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 270336 # Number of bytes read from this memory
system.physmem.bytes_read::total 437248 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 166912 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 166912 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 2608 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 4224 # Number of read requests responded to by this memory
system.physmem.num_reads::total 6832 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 322666 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 522599 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 845265 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 322666 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 322666 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 322666 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 522599 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 845265 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
@ -147,33 +147,33 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 191 # Number of system calls
system.cpu.numCycles 1034574305 # number of cpu cycles simulated
system.cpu.numCycles 1034582051 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 272737951 # Number of instructions committed
system.cpu.committedOps 327435116 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 258332236 # Number of integer alu accesses
system.cpu.committedInsts 272739286 # Number of instructions committed
system.cpu.committedOps 327433744 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 258331537 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses
system.cpu.num_func_calls 12449970 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 15800021 # number of instructions that are conditional controls
system.cpu.num_int_insts 258332236 # number of integer instructions
system.cpu.num_func_calls 12448615 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 15799349 # number of instructions that are conditional controls
system.cpu.num_int_insts 258331537 # number of integer instructions
system.cpu.num_fp_insts 114216705 # number of float instructions
system.cpu.num_int_register_reads 1215886434 # number of times the integer registers were read
system.cpu.num_int_register_writes 162499715 # number of times the integer registers were written
system.cpu.num_int_register_reads 1215888421 # number of times the integer registers were read
system.cpu.num_int_register_writes 162499693 # number of times the integer registers were written
system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read
system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written
system.cpu.num_cc_register_reads 1242911540 # number of times the CC registers were read
system.cpu.num_cc_register_writes 76355719 # number of times the CC registers were written
system.cpu.num_mem_refs 168105830 # number of memory refs
system.cpu.num_load_insts 85730232 # Number of load instructions
system.cpu.num_store_insts 82375598 # Number of store instructions
system.cpu.num_cc_register_reads 1242915503 # number of times the CC registers were read
system.cpu.num_cc_register_writes 76361814 # number of times the CC registers were written
system.cpu.num_mem_refs 168107847 # number of memory refs
system.cpu.num_load_insts 85732248 # Number of load instructions
system.cpu.num_store_insts 82375599 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 1034574304.998000 # Number of busy cycles
system.cpu.num_busy_cycles 1034582050.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 30566209 # Number of branches fetched
system.cpu.Branches 30563503 # Number of branches fetched
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu.op_class::IntAlu 104315933 31.82% 31.82% # Class of executed instruction
system.cpu.op_class::IntAlu 104312544 31.82% 31.82% # Class of executed instruction
system.cpu.op_class::IntMult 2145905 0.65% 32.48% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 32.48% # Class of executed instruction
@ -198,79 +198,79 @@ system.cpu.op_class::SimdFloatAlu 0 0.00% 34.49% # Cl
system.cpu.op_class::SimdFloatCmp 7943502 2.42% 36.91% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 3118180 0.95% 37.86% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 1563217 0.48% 38.34% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 19652356 5.99% 44.33% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 19652356 6.00% 44.33% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 7136937 2.18% 46.51% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 7062098 2.15% 48.67% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 175285 0.05% 48.72% # Class of executed instruction
system.cpu.op_class::MemRead 85730232 26.15% 74.87% # Class of executed instruction
system.cpu.op_class::MemWrite 82375598 25.13% 100.00% # Class of executed instruction
system.cpu.op_class::MemRead 85732248 26.15% 74.87% # Class of executed instruction
system.cpu.op_class::MemWrite 82375599 25.13% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 327813586 # Class of executed instruction
system.cpu.dcache.tags.replacements 1326 # number of replacements
system.cpu.dcache.tags.tagsinuse 3078.339297 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 168357609 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 4469 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 37672.322443 # Average number of references to valid blocks.
system.cpu.op_class::total 327812214 # Class of executed instruction
system.cpu.dcache.tags.replacements 1332 # number of replacements
system.cpu.dcache.tags.tagsinuse 3078.335714 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 168359617 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 4478 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 37597.056052 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 3078.339297 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.751548 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.751548 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 3143 # Occupied blocks per task id
system.cpu.dcache.tags.occ_blocks::cpu.data 3078.335714 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.751547 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.751547 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 3146 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 678 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 2434 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.767334 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 336728627 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 336728627 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 86231946 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 86231946 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 82049814 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 82049814 # number of WriteReq hits
system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 10 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 677 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 2428 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.768066 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 336732670 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 336732670 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 86233963 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 86233963 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 82049805 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 54059 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 54059 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 168281760 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 168281760 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 168335819 # number of overall hits
system.cpu.dcache.overall_hits::total 168335819 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1605 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1605 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 2862 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 2862 # number of WriteReq misses
system.cpu.dcache.demand_hits::cpu.data 168283768 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 168283768 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 168337827 # number of overall hits
system.cpu.dcache.overall_hits::total 168337827 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1604 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1604 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 2872 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 2872 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 3 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data 4467 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 4467 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 4470 # number of overall misses
system.cpu.dcache.overall_misses::total 4470 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 88066000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 88066000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 176802500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 176802500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 264868500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 264868500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 264868500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 264868500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 86233551 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 86233551 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 82052676 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 82052676 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_misses::cpu.data 4476 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 4476 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 4479 # number of overall misses
system.cpu.dcache.overall_misses::total 4479 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 88052000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 88052000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 177422500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 177422500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 265474500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 265474500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 265474500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 265474500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 86235567 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 86235567 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 54062 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 54062 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 168286227 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 168286227 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 168340289 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 168340289 # number of overall (read+write) accesses
system.cpu.dcache.demand_accesses::cpu.data 168288244 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 168288244 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 168342306 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 168342306 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000019 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000019 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000035 # miss rate for WriteReq accesses
@ -281,14 +281,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000027
system.cpu.dcache.demand_miss_rate::total 0.000027 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000027 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000027 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54869.781931 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 54869.781931 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61775.856045 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 61775.856045 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 59294.492948 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 59294.492948 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 59254.697987 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 59254.697987 # average overall miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54895.261845 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 54895.261845 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61776.636490 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 61776.636490 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 59310.656836 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 59310.656836 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 59270.931011 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 59270.931011 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -297,34 +297,34 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 997 # number of writebacks
system.cpu.dcache.writebacks::total 997 # number of writebacks
system.cpu.dcache.writebacks::writebacks 998 # number of writebacks
system.cpu.dcache.writebacks::total 998 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
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system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1604 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1604 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2862 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 2862 # number of WriteReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1603 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1603 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2872 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 2872 # number of WriteReq MSHR misses
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system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses
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system.cpu.dcache.demand_mshr_misses::total 4466 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 4469 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 4469 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 86415000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 86415000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 173940500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 173940500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_misses::cpu.data 4475 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 4475 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 4478 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 4478 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 86402000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 86402000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 174550500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 174550500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 183000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 183000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 260355500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 260355500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 260538500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 260538500 # number of overall MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 260952500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 260952500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 261135500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 261135500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses
@ -335,71 +335,71 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027
system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53874.688279 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53874.688279 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60775.856045 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60775.856045 # average WriteReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53900.187149 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53900.187149 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60776.636490 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60776.636490 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58297.245858 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 58297.245858 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58299.060192 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 58299.060192 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58313.407821 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 58313.407821 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58315.207682 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 58315.207682 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 13798 # number of replacements
system.cpu.icache.tags.tagsinuse 1765.947853 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 348643415 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 15605 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 22341.776033 # Average number of references to valid blocks.
system.cpu.icache.tags.replacements 13796 # number of replacements
system.cpu.icache.tags.tagsinuse 1765.948116 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 348644750 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 15603 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 22344.725373 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1765.947853 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_blocks::cpu.inst 1765.948116 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.862279 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.862279 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1807 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 163 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1522 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 161 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1524 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.882324 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 697333645 # Number of tag accesses
system.cpu.icache.tags.data_accesses 697333645 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 348643415 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 348643415 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 348643415 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 348643415 # number of demand (read+write) hits
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system.cpu.icache.overall_hits::total 348643415 # number of overall hits
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system.cpu.icache.ReadReq_misses::total 15605 # number of ReadReq misses
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system.cpu.icache.demand_misses::total 15605 # number of demand (read+write) misses
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system.cpu.icache.overall_misses::total 15605 # number of overall misses
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system.cpu.icache.ReadReq_miss_latency::total 338522000 # number of ReadReq miss cycles
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system.cpu.icache.demand_miss_latency::total 338522000 # number of demand (read+write) miss cycles
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system.cpu.icache.overall_miss_latency::total 338522000 # number of overall miss cycles
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system.cpu.icache.ReadReq_accesses::total 348659020 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.overall_accesses::total 348659020 # number of overall (read+write) accesses
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system.cpu.icache.tags.data_accesses 697336309 # Number of data accesses
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system.cpu.icache.ReadReq_hits::total 348644750 # number of ReadReq hits
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system.cpu.icache.demand_misses::total 15603 # number of demand (read+write) misses
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system.cpu.icache.overall_misses::total 15603 # number of overall misses
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system.cpu.icache.ReadReq_miss_latency::total 338446000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 338446000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 338446000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 338446000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 338446000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 348660353 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 348660353 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 348660353 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 348660353 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 348660353 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 348660353 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000045 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses
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system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21693.175264 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 21693.175264 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 21693.175264 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 21693.175264 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 21693.175264 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 21693.175264 # average overall miss latency
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21691.085048 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 21691.085048 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 21691.085048 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 21691.085048 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 21691.085048 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 21691.085048 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -408,42 +408,42 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks::writebacks 13798 # number of writebacks
system.cpu.icache.writebacks::total 13798 # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15605 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 15605 # number of ReadReq MSHR misses
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system.cpu.icache.overall_mshr_misses::total 15605 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 322917000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 322917000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 322917000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 322917000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 322917000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 322917000 # number of overall MSHR miss cycles
system.cpu.icache.writebacks::writebacks 13796 # number of writebacks
system.cpu.icache.writebacks::total 13796 # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15603 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 15603 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 15603 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 15603 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 15603 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 322843000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 322843000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 322843000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 322843000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 322843000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 322843000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000045 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20693.175264 # average ReadReq mshr miss latency
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system.cpu.l2cache.tags.tagsinuse 3487.616981 # Cycle average of tags in use
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system.cpu.l2cache.tags.occ_blocks::cpu.inst 2407.328378 # Average occupied blocks per requestor
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@ -451,92 +451,92 @@ system.cpu.l2cache.tags.occ_percent::total 0.106434 #
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system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1233 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
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@ -545,115 +545,115 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
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system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49548.664793 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49548.664793 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49544.461479 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49544.461479 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 129212000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 209421500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 338633500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 129212000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 209421500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 338633500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994429 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994429 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.167147 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.167147 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.851806 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.851806 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.167147 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943278 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.340222 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167147 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943278 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.340222 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49548.494398 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49548.494398 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49544.478528 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49544.478528 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49642.543860 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49642.543860 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49544.461479 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49579.140959 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49565.880111 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49544.461479 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49579.140959 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49565.880111 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49544.478528 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49578.953598 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49565.793326 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49544.478528 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49578.953598 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49565.793326 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.snoop_filter.tot_requests 35198 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 15220 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7664 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_requests 35209 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 15221 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7665 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp 17212 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 997 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 13798 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 329 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 2862 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 2862 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 15605 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 1607 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45008 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10264 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 55272 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1881792 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 349824 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 2231616 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 998 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 13796 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 334 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 2872 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 2872 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 15603 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 1606 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45002 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10288 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 55290 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1881536 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 350464 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 2232000 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 20074 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.386570 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.486976 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::samples 20081 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.386335 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.486921 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 12314 61.34% 61.34% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 7760 38.66% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 12323 61.37% 61.37% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 7758 38.63% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 20074 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 32394000 # Layer occupancy (ticks)
system.cpu.toL2Bus.snoop_fanout::total 20081 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 32398500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 23407500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.occupancy 23404500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 6703500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.occupancy 6717000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.membus.trans_dist::ReadResp 3977 # Transaction distribution
system.membus.trans_dist::ReadExReq 2846 # Transaction distribution
system.membus.trans_dist::ReadExResp 2846 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 3977 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13646 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 13646 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 436672 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 436672 # Cumulative packet size per connected master and slave (bytes)
system.membus.trans_dist::ReadResp 3976 # Transaction distribution
system.membus.trans_dist::ReadExReq 2856 # Transaction distribution
system.membus.trans_dist::ReadExResp 2856 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 3976 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13664 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 13664 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 437248 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 437248 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 6824 # Request fanout histogram
system.membus.snoop_fanout::samples 6833 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 6824 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::0 6833 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 6824 # Request fanout histogram
system.membus.reqLayer0.occupancy 7272500 # Layer occupancy (ticks)
system.membus.snoop_fanout::total 6833 # Request fanout histogram
system.membus.reqLayer0.occupancy 7281500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 34115000 # Layer occupancy (ticks)
system.membus.respLayer1.occupancy 34160000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------

8
tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout
View file

@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing/s
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Mar 15 2016 19:53:43
gem5 started Mar 15 2016 20:34:58
gem5 executing on dinar2c11, pid 10996
gem5 compiled Mar 16 2016 23:07:21
gem5 started Mar 16 2016 23:41:21
gem5 executing on dinar2c11, pid 25849
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing -re /home/stever/gem5-public/tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
@ -27,4 +27,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 767874998000 because target called exit()
Exiting @ tick 767851412000 because target called exit()

1614
tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

6
tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout
View file

@ -3,9 +3,9 @@ Redirecting stderr to build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/s
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Mar 16 2016 15:38:19
gem5 started Mar 16 2016 15:38:50
gem5 executing on dinar2c11, pid 14357
gem5 compiled Mar 16 2016 22:57:26
gem5 started Mar 16 2016 22:58:08
gem5 executing on dinar2c11, pid 24733
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -re /home/stever/gem5-public/tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second

594
tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.079141 # Nu
sim_ticks 79140979500 # Number of ticks simulated
final_tick 79140979500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 48369 # Simulator instruction rate (inst/s)
host_op_rate 81071 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 28984226 # Simulator tick rate (ticks/s)
host_mem_usage 336892 # Number of bytes of host memory used
host_seconds 2730.48 # Real time elapsed on the host
host_inst_rate 47467 # Simulator instruction rate (inst/s)
host_op_rate 79560 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 28443866 # Simulator tick rate (ticks/s)
host_mem_usage 336904 # Number of bytes of host memory used
host_seconds 2782.36 # Real time elapsed on the host
sim_insts 132071192 # Number of instructions simulated
sim_ops 221363384 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@ -231,10 +231,10 @@ system.physmem_0.actBackEnergy 2477527515 # En
system.physmem_0.preBackEnergy 45310553250 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 52987315485 # Total energy per rank (pJ)
system.physmem_0.averagePower 669.541483 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 75375284500 # Time in different power states
system.physmem_0.memoryStateTime::IDLE 75375284000 # Time in different power states
system.physmem_0.memoryStateTime::REF 2642640000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 1122707500 # Time in different power states
system.physmem_0.memoryStateTime::ACT 1122708000 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 3470040 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 1893375 # Energy for precharge commands per rank (pJ)
@ -250,13 +250,13 @@ system.physmem_1.memoryStateTime::REF 2642640000 # Ti
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 884606250 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.branchPred.lookups 20604097 # Number of BP lookups
system.cpu.branchPred.condPredicted 20604097 # Number of conditional branches predicted
system.cpu.branchPred.lookups 20604101 # Number of BP lookups
system.cpu.branchPred.condPredicted 20604101 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 1328804 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 12707128 # Number of BTB lookups
system.cpu.branchPred.BTBHits 12016947 # Number of BTB hits
system.cpu.branchPred.BTBHits 12016946 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 94.568552 # BTB Hit Percentage
system.cpu.branchPred.BTBHitPct 94.568545 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 1442846 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 16873 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
@ -265,32 +265,32 @@ system.cpu.workload.num_syscalls 400 # Nu
system.cpu.numCycles 158281960 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles 25261186 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 227540228 # Number of instructions fetch has processed
system.cpu.fetch.Branches 20604097 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 13459793 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 131194120 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.icacheStallCycles 25261178 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 227540211 # Number of instructions fetch has processed
system.cpu.fetch.Branches 20604101 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 13459792 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 131194128 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 3196201 # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles 20 # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.MiscStallCycles 1974 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 21216 # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles 13 # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles 47 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 24267792 # Number of cache lines fetched
system.cpu.fetch.CacheLines 24267790 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 266999 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 158076676 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.380152 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.324971 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.324972 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 95737539 60.56% 60.56% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 95737541 60.56% 60.56% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 4758449 3.01% 63.57% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 3804663 2.41% 65.98% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 3804662 2.41% 65.98% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 4365114 2.76% 68.74% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 4234763 2.68% 71.42% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 4816061 3.05% 74.47% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 4706874 2.98% 77.45% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 4816060 3.05% 74.47% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 4706873 2.98% 77.45% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 3702906 2.34% 79.79% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 31950307 20.21% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 31950308 20.21% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
@ -298,61 +298,61 @@ system.cpu.fetch.rateDist::total 158076676 # Nu
system.cpu.fetch.branchRate 0.130173 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.437563 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 15410588 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 96165479 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 23286259 # Number of cycles decode is running
system.cpu.decode.BlockedCycles 96165480 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 23286258 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 21616250 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 1598100 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 336629364 # Number of instructions handled by decode
system.cpu.decode.DecodedInsts 336629357 # Number of instructions handled by decode
system.cpu.rename.SquashCycles 1598100 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 23294905 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 31785654 # Number of cycles rename is blocking
system.cpu.rename.IdleCycles 23294906 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 31785653 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 30420 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 36005072 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 65362525 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 328266719 # Number of instructions processed by rename
system.cpu.rename.RunCycles 36005070 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 65362527 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 328266704 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 1575 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 57713162 # Number of times rename has blocked due to IQ full
system.cpu.rename.IQFullEvents 57713164 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 7745606 # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents 167786 # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands 380441368 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 910027762 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 600617825 # Number of integer rename lookups
system.cpu.rename.RenamedOperands 380441390 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 910027714 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 600617838 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 4182134 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 121011918 # Number of HB maps that are undone due to squashing
system.cpu.rename.UndoneMaps 121011940 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 1942 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 1920 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 120996232 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 82787391 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 29790688 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 59618216 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 20385329 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 317847109 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.rename.skidInsts 120996238 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 82787388 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 29790681 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 59618218 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 20385333 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 317847098 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 5129 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 259397692 # Number of instructions issued
system.cpu.iq.iqInstsIssued 259397684 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 74444 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 96488854 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 197170724 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedInstsExamined 96488843 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 197170698 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 3884 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 158076676 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.640961 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.524821 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 40037944 25.33% 25.33% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 47502917 30.05% 55.38% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 40037945 25.33% 25.33% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 47502914 30.05% 55.38% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 33077309 20.92% 76.30% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 17993681 11.38% 87.69% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 10964078 6.94% 94.62% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 4766946 3.02% 97.64% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 2459939 1.56% 99.19% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 882458 0.56% 99.75% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 17993682 11.38% 87.69% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 10964082 6.94% 94.62% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 4766949 3.02% 97.64% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 2459936 1.56% 99.19% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 882455 0.56% 99.75% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 391404 0.25% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 158076676 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 232299 7.31% 7.31% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 232294 7.31% 7.31% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 7.31% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 7.31% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.31% # attempts to use FU when none available
@ -386,7 +386,7 @@ system.cpu.iq.fu_full::MemWrite 383461 12.07% 100.00% # at
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 1212757 0.47% 0.47% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 161810982 62.38% 62.85% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 161810976 62.38% 62.85% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 789695 0.30% 63.15% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 7037932 2.71% 65.86% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 1186383 0.46% 66.32% # Type of FU issued
@ -415,40 +415,40 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.32% # Ty
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.32% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 64896242 25.02% 91.34% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 22463701 8.66% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 64896241 25.02% 91.34% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 22463700 8.66% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 259397692 # Type of FU issued
system.cpu.iq.FU_type_0::total 259397684 # Type of FU issued
system.cpu.iq.rate 1.638833 # Inst issue rate
system.cpu.iq.fu_busy_cnt 3176512 # FU busy when requested
system.cpu.iq.fu_busy_cnt 3176507 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.012246 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 675268347 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 410944123 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 253662320 # Number of integer instruction queue wakeup accesses
system.cpu.iq.int_inst_queue_reads 675268326 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 410944101 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 253662317 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 4854669 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 3693735 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 2339703 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 258916836 # Number of integer alu accesses
system.cpu.iq.int_alu_accesses 258916823 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 2444611 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 18724074 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.forwLoads 18724072 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 26137804 # Number of loads squashed
system.cpu.iew.lsq.thread0.squashedLoads 26137801 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 13130 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 303242 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 9274971 # Number of stores squashed
system.cpu.iew.lsq.thread0.squashedStores 9274964 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 49888 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.rescheduledLoads 49887 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 39 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 1598100 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 12496396 # Number of cycles IEW is blocking
system.cpu.iew.iewBlockCycles 12496395 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 489060 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 317852238 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispatchedInsts 317852227 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 92568 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 82787391 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 29790688 # Number of dispatched store instructions
system.cpu.iew.iewDispLoadInsts 82787388 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 29790681 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 2962 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 383739 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 63074 # Number of times the LSQ has become full, causing a stall
@ -456,41 +456,41 @@ system.cpu.iew.memOrderViolationEvents 303242 # Nu
system.cpu.iew.predictedTakenIncorrect 551670 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 826736 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 1378406 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 257339863 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 64084690 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 2057829 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 257339859 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 64084689 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 2057825 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
system.cpu.iew.exec_refs 86369702 # number of memory reference insts executed
system.cpu.iew.exec_refs 86369700 # number of memory reference insts executed
system.cpu.iew.exec_branches 14330688 # Number of branches executed
system.cpu.iew.exec_stores 22285012 # Number of stores executed
system.cpu.iew.exec_stores 22285011 # Number of stores executed
system.cpu.iew.exec_rate 1.625832 # Inst execution rate
system.cpu.iew.wb_sent 256690837 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 256002023 # cumulative count of insts written-back
system.cpu.iew.wb_producers 204396158 # num instructions producing a value
system.cpu.iew.wb_consumers 369708068 # num instructions consuming a value
system.cpu.iew.wb_sent 256690834 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 256002020 # cumulative count of insts written-back
system.cpu.iew.wb_producers 204396152 # num instructions producing a value
system.cpu.iew.wb_consumers 369708063 # num instructions consuming a value
system.cpu.iew.wb_rate 1.617380 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.552858 # average fanout of values written-back
system.cpu.commit.commitSquashedInsts 96496531 # The number of squashed insts skipped by commit
system.cpu.commit.commitSquashedInsts 96496520 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 1330625 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 144920748 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::samples 144920750 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.527479 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.956907 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 45508636 31.40% 31.40% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 57312376 39.55% 70.95% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 14158342 9.77% 80.72% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 11991162 8.27% 88.99% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 4086517 2.82% 91.81% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 2858053 1.97% 93.79% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 45508635 31.40% 31.40% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 57312379 39.55% 70.95% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 14158343 9.77% 80.72% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 11991163 8.27% 88.99% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 4086516 2.82% 91.81% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 2858052 1.97% 93.79% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 923800 0.64% 94.42% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 1073191 0.74% 95.16% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 7008671 4.84% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 1073190 0.74% 95.16% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 7008672 4.84% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 144920748 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 144920750 # Number of insts commited each cycle
system.cpu.commit.committedInsts 132071192 # Number of instructions committed
system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
@ -536,9 +536,9 @@ system.cpu.commit.op_class_0::MemWrite 20515717 9.27% 100.00% # Cl
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 221363384 # Class of committed instruction
system.cpu.commit.bw_lim_events 7008671 # number cycles where commit BW limit reached
system.cpu.rob.rob_reads 455771992 # The number of ROB reads
system.cpu.rob.rob_writes 648913303 # The number of ROB writes
system.cpu.commit.bw_lim_events 7008672 # number cycles where commit BW limit reached
system.cpu.rob.rob_reads 455771982 # The number of ROB reads
system.cpu.rob.rob_writes 648913279 # The number of ROB writes
system.cpu.timesIdled 2665 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 205284 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 132071192 # Number of Instructions Simulated
@ -547,19 +547,19 @@ system.cpu.cpi 1.198459 # CP
system.cpu.cpi_total 1.198459 # CPI: Total CPI of All Threads
system.cpu.ipc 0.834405 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.834405 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 448575238 # number of integer regfile reads
system.cpu.int_regfile_reads 448575240 # number of integer regfile reads
system.cpu.int_regfile_writes 232602901 # number of integer regfile writes
system.cpu.fp_regfile_reads 3212636 # number of floating regfile reads
system.cpu.fp_regfile_writes 1997796 # number of floating regfile writes
system.cpu.cc_regfile_reads 102540240 # number of cc regfile reads
system.cpu.cc_regfile_writes 59516414 # number of cc regfile writes
system.cpu.misc_regfile_reads 132474845 # number of misc regfile reads
system.cpu.cc_regfile_reads 102540235 # number of cc regfile reads
system.cpu.cc_regfile_writes 59516419 # number of cc regfile writes
system.cpu.misc_regfile_reads 132474842 # number of misc regfile reads
system.cpu.misc_regfile_writes 1689 # number of misc regfile writes
system.cpu.dcache.tags.replacements 51 # number of replacements
system.cpu.dcache.tags.tagsinuse 1429.115986 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 65747317 # Total number of references to valid blocks.
system.cpu.dcache.tags.total_refs 65747319 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 1995 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 32956.048622 # Average number of references to valid blocks.
system.cpu.dcache.tags.avg_refs 32956.049624 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 1429.115986 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.348905 # Average percentage of cache occupancy
@ -571,40 +571,40 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 498
system.cpu.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1394 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.474609 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 131501473 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 131501473 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 45233028 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 45233028 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 20513911 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 20513911 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 65746939 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 65746939 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 65746939 # number of overall hits
system.cpu.dcache.overall_hits::total 65746939 # number of overall hits
system.cpu.dcache.tags.tag_accesses 131501477 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 131501477 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 45233030 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 45233030 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 20513912 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 20513912 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 65746942 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 65746942 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 65746942 # number of overall hits
system.cpu.dcache.overall_hits::total 65746942 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 980 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 980 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1820 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1820 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 2800 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 2800 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 2800 # number of overall misses
system.cpu.dcache.overall_misses::total 2800 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 65148000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 65148000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 128547000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 128547000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 193695000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 193695000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 193695000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 193695000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 45234008 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 45234008 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_misses::cpu.data 1819 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1819 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 2799 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 2799 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 2799 # number of overall misses
system.cpu.dcache.overall_misses::total 2799 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 65149000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 65149000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 128515000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 128515000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 193664000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 193664000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 193664000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 193664000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 45234010 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 45234010 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 65749739 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 65749739 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 65749739 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 65749739 # number of overall (read+write) accesses
system.cpu.dcache.demand_accesses::cpu.data 65749741 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 65749741 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 65749741 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 65749741 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000022 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000089 # miss rate for WriteReq accesses
@ -613,14 +613,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000043
system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66477.551020 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 66477.551020 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70630.219780 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 70630.219780 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 69176.785714 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 69176.785714 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 69176.785714 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 69176.785714 # average overall miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66478.571429 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 66478.571429 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70651.456844 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 70651.456844 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 69190.425152 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 69190.425152 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 69190.425152 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 69190.425152 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 656 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 70 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 7 # number of cycles access was blocked
@ -641,20 +641,20 @@ system.cpu.dcache.overall_mshr_hits::cpu.data 528
system.cpu.dcache.overall_mshr_hits::total 528 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 454 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 454 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1818 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 1818 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 2272 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 2272 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 2272 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 2272 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36063000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 36063000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 126583000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 126583000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 162646000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 162646000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 162646000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 162646000 # number of overall MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1817 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 1817 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 2271 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 2271 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 2271 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 2271 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36063500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 36063500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 126552000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 126552000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 162615500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 162615500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 162615500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 162615500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses
@ -663,24 +663,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000035
system.cpu.dcache.demand_mshr_miss_rate::total 0.000035 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000035 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79433.920705 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79433.920705 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69627.612761 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69627.612761 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71587.147887 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 71587.147887 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71587.147887 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 71587.147887 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79435.022026 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79435.022026 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69648.871767 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69648.871767 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71605.239982 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 71605.239982 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71605.239982 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 71605.239982 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 5017 # number of replacements
system.cpu.icache.tags.tagsinuse 1636.801929 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 24258361 # Total number of references to valid blocks.
system.cpu.icache.tags.tagsinuse 1636.805094 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 24258360 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 6993 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 3468.949092 # Average number of references to valid blocks.
system.cpu.icache.tags.avg_refs 3468.948949 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1636.801929 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.799220 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.799220 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_blocks::cpu.inst 1636.805094 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.799221 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.799221 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1976 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 188 # Occupied blocks per task id
@ -688,44 +688,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 869
system.cpu.icache.tags.age_task_id_blocks_1024::3 20 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 788 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.964844 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 48542851 # Number of tag accesses
system.cpu.icache.tags.data_accesses 48542851 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 24258362 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 24258362 # number of ReadReq hits
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system.cpu.icache.demand_hits::total 24258362 # number of demand (read+write) hits
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system.cpu.icache.overall_hits::total 24258362 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 9429 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 9429 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 9429 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 9429 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 9429 # number of overall misses
system.cpu.icache.overall_misses::total 9429 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 409019999 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 409019999 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 409019999 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 409019999 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 409019999 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 409019999 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 24267791 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 24267791 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_accesses::total 24267791 # number of demand (read+write) accesses
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system.cpu.icache.overall_accesses::total 24267791 # number of overall (read+write) accesses
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system.cpu.icache.overall_miss_rate::cpu.inst 0.000389 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000389 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43378.937215 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 43378.937215 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 43378.937215 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 43378.937215 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 43378.937215 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 43378.937215 # average overall miss latency
system.cpu.icache.tags.tag_accesses 48542846 # Number of tag accesses
system.cpu.icache.tags.data_accesses 48542846 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 24258361 # number of ReadReq hits
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system.cpu.icache.overall_hits::total 24258361 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 9428 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 9428 # number of ReadReq misses
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system.cpu.icache.demand_misses::total 9428 # number of demand (read+write) misses
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system.cpu.icache.overall_misses::total 9428 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 409015499 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 409015499 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 409015499 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 409015499 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 409015499 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 409015499 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 24267789 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 24267789 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_accesses::total 24267789 # number of demand (read+write) accesses
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system.cpu.icache.overall_accesses::total 24267789 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000388 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000388 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000388 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000388 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000388 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000388 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43383.060989 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 43383.060989 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 43383.060989 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 43383.060989 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 43383.060989 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 43383.060989 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 793 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 13 # number of cycles access was blocked
@ -742,30 +742,30 @@ system.cpu.icache.demand_mshr_hits::cpu.inst 2159
system.cpu.icache.demand_mshr_hits::total 2159 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 2159 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 2159 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7270 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 7270 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 7270 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 7270 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 7270 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 7270 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 311109999 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 311109999 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 311109999 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 311109999 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 311109999 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 311109999 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7269 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 7269 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 7269 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 7269 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 7269 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 7269 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 311106499 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 311106499 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 311106499 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 311106499 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 311106499 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 311106499 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000300 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000300 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000300 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000300 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000300 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000300 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 42793.672490 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 42793.672490 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 42793.672490 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 42793.672490 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 42793.672490 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 42793.672490 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 42799.078140 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 42799.078140 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 42799.078140 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 42799.078140 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 42799.078140 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 42799.078140 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 2581.252539 # Cycle average of tags in use
@ -787,8 +787,8 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 999
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 41 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2611 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.118378 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 119261 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 119261 # Number of data accesses
system.cpu.l2cache.tags.tag_accesses 119253 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 119253 # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks 10 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 10 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 4917 # number of WritebackClean hits
@ -807,8 +807,8 @@ system.cpu.l2cache.demand_hits::total 3572 # nu
system.cpu.l2cache.overall_hits::cpu.inst 3531 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 41 # number of overall hits
system.cpu.l2cache.overall_hits::total 3572 # number of overall hits
system.cpu.l2cache.UpgradeReq_misses::cpu.data 276 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 276 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 275 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 275 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 1535 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 1535 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3460 # number of ReadCleanReq misses
@ -823,22 +823,22 @@ system.cpu.l2cache.overall_misses::cpu.data 1954 #
system.cpu.l2cache.overall_misses::total 5414 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 115784500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 115784500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 262406500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 262406500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 34977000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 34977000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 262406500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 150761500 # number of demand (read+write) miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 262406000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 262406000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 34977500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 34977500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 262406000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 150762000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 413168000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 262406500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 150761500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 262406000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 150762000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 413168000 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 10 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 10 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 4917 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 4917 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 277 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 277 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 276 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 276 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1541 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 1541 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 6991 # number of ReadCleanReq accesses(hits+misses)
@ -851,8 +851,8 @@ system.cpu.l2cache.demand_accesses::total 8986 # n
system.cpu.l2cache.overall_accesses::cpu.inst 6991 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 1995 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 8986 # number of overall (read+write) accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.996390 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.996390 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.996377 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.996377 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.996106 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.996106 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.494922 # miss rate for ReadCleanReq accesses
@ -867,15 +867,15 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 0.979449
system.cpu.l2cache.overall_miss_rate::total 0.602493 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75429.641694 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75429.641694 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75840.028902 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75840.028902 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83477.326969 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83477.326969 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75840.028902 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77155.322416 # average overall miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75839.884393 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75839.884393 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83478.520286 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83478.520286 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75839.884393 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77155.578301 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 76314.739564 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75840.028902 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77155.322416 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75839.884393 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77155.578301 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 76314.739564 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
@ -885,8 +885,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 276 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 276 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 275 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 275 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1535 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 1535 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3460 # number of ReadCleanReq MSHR misses
@ -899,22 +899,22 @@ system.cpu.l2cache.demand_mshr_misses::total 5414
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3460 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 1954 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 5414 # number of overall MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 5237000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 5237000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 5217500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 5217500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 100434500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 100434500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 227816500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 227816500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 30787000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 30787000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 227816500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 131221500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 227816000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 227816000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 30787500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 30787500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 227816000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 131222000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 359038000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 227816500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 131221500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 227816000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 131222000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 359038000 # number of overall MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.996390 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.996390 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.996377 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.996377 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.996106 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.996106 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.494922 # mshr miss rate for ReadCleanReq accesses
@ -927,84 +927,84 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.602493
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.494922 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.979449 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.602493 # mshr miss rate for overall accesses
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18974.637681 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18974.637681 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18972.727273 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18972.727273 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65429.641694 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65429.641694 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65842.919075 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65842.919075 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73477.326969 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73477.326969 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65842.919075 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67155.322416 # average overall mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65842.774566 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65842.774566 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73478.520286 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73478.520286 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65842.774566 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67155.578301 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66316.586627 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65842.919075 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67155.322416 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65842.774566 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67155.578301 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66316.586627 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.snoop_filter.tot_requests 14610 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 5368 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 377 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_requests 14608 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 5367 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 376 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp 7723 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 7722 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 10 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 5017 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 41 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 277 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 277 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 276 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 276 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 1541 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 1541 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 7270 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 7269 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 454 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19277 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4595 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 23872 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19276 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4593 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 23869 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 768448 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 128320 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 896768 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 279 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 9542 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.070845 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.256579 # Request fanout histogram
system.cpu.toL2Bus.snoops 278 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 9540 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.070650 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.256253 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 8866 92.92% 92.92% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 676 7.08% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 8866 92.94% 92.94% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 674 7.06% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 9542 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 12332000 # Layer occupancy (ticks)
system.cpu.toL2Bus.snoop_fanout::total 9540 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 12331000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 10903500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.occupancy 10902000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 3131998 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.occupancy 3131498 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.membus.trans_dist::ReadResp 3878 # Transaction distribution
system.membus.trans_dist::UpgradeReq 276 # Transaction distribution
system.membus.trans_dist::UpgradeReq 275 # Transaction distribution
system.membus.trans_dist::ReadExReq 1535 # Transaction distribution
system.membus.trans_dist::ReadExResp 1535 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 3878 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11102 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11102 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 11102 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11101 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11101 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 11101 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 346432 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 346432 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 346432 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 5689 # Request fanout histogram
system.membus.snoop_fanout::samples 5688 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 5689 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::0 5688 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 5689 # Request fanout histogram
system.membus.reqLayer0.occupancy 6955500 # Layer occupancy (ticks)
system.membus.snoop_fanout::total 5688 # Request fanout histogram
system.membus.reqLayer0.occupancy 6954000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 28681250 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)

7
tests/quick/se/00.hello/ref/alpha/linux/minor-timing/config.ini
View file

@ -135,7 +135,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@ -560,7 +559,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
@ -611,7 +609,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
@ -646,6 +643,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
point_of_coherency=false
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
@ -676,7 +674,7 @@ env=
errout=cerr
euid=100
eventq_index=0
executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
kvmInSE=false
@ -711,6 +709,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4

12
tests/quick/se/00.hello/ref/alpha/linux/minor-timing/simout
View file

@ -1,13 +1,15 @@
Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing/simout
Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 21 2016 13:49:21
gem5 started Jan 21 2016 13:50:03
gem5 executing on zizzer, pid 34007
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing
gem5 compiled Mar 14 2016 21:54:46
gem5 started Mar 14 2016 21:56:23
gem5 executing on phenom, pid 28115
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
Exiting @ tick 37553000 because target called exit()
Exiting @ tick 37629000 because target called exit()

542
tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt
View file

@ -1,16 +1,16 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000038 # Number of seconds simulated
sim_ticks 37553000 # Number of ticks simulated
final_tick 37553000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 37629000 # Number of ticks simulated
final_tick 37629000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 69445 # Simulator instruction rate (inst/s)
host_op_rate 69425 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 407253641 # Simulator tick rate (ticks/s)
host_mem_usage 231420 # Number of bytes of host memory used
host_seconds 0.09 # Real time elapsed on the host
sim_insts 6400 # Number of instructions simulated
sim_ops 6400 # Number of ops (including micro ops) simulated
host_inst_rate 36642 # Simulator instruction rate (inst/s)
host_op_rate 36638 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 214955628 # Simulator tick rate (ticks/s)
host_mem_usage 227692 # Number of bytes of host memory used
host_seconds 0.18 # Real time elapsed on the host
sim_insts 6413 # Number of instructions simulated
sim_ops 6413 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 23296 # Number of bytes read from this memory
@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 23296 # Nu
system.physmem.num_reads::cpu.inst 364 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 169 # Number of read requests responded to by this memory
system.physmem.num_reads::total 533 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 620349905 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 288019599 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 908369504 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 620349905 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 620349905 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 620349905 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 288019599 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 908369504 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 619096973 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 287437880 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 906534853 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 619096973 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 619096973 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 619096973 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 287437880 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 906534853 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 533 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 533 # Number of DRAM read bursts, including those serviced by the write queue
@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 37448500 # Total gap between requests
system.physmem.totGap 37524500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 443 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 85 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::0 444 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 84 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 5 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
@ -186,100 +186,100 @@ system.physmem.wrQLenPdf::60 0 # Wh
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 84 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 384 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 247.290862 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 334.108272 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 20 23.81% 23.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 19 22.62% 46.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 10 11.90% 58.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 11 13.10% 71.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 2 2.38% 73.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 5 5.95% 79.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 3 3.57% 83.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 6 7.14% 90.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 8 9.52% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 84 # Bytes accessed per row activation
system.physmem.totQLat 3307750 # Total ticks spent queuing
system.physmem.totMemAccLat 13301500 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.bytesPerActivate::samples 83 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 388.626506 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 254.752349 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 332.370925 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 18 21.69% 21.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 19 22.89% 44.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 11 13.25% 57.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 11 13.25% 71.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 2 2.41% 73.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 5 6.02% 79.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 2 2.41% 81.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 7 8.43% 90.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 8 9.64% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 83 # Bytes accessed per row activation
system.physmem.totQLat 3516000 # Total ticks spent queuing
system.physmem.totMemAccLat 13509750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2665000 # Total ticks spent in databus transfers
system.physmem.avgQLat 6205.91 # Average queueing delay per DRAM burst
system.physmem.avgQLat 6596.62 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 24955.91 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 908.37 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgMemAccLat 25346.62 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 906.53 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 908.37 # Average system read bandwidth in MiByte/s
system.physmem.avgRdBWSys 906.53 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 7.10 # Data bus utilization in percentage
system.physmem.busUtilRead 7.10 # Data bus utilization in percentage for reads
system.physmem.busUtil 7.08 # Data bus utilization in percentage
system.physmem.busUtilRead 7.08 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.19 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 437 # Number of row buffer hits during reads
system.physmem.readRowHits 438 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 81.99 # Row buffer hit rate for reads
system.physmem.readRowHitRate 82.18 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 70259.85 # Average gap between requests
system.physmem.pageHitRate 81.99 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 226800 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 123750 # Energy for precharge commands per rank (pJ)
system.physmem.avgGap 70402.44 # Average gap between requests
system.physmem.pageHitRate 82.18 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 234360 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 127875 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 2043600 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 2034240 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 21178350 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 265500 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 25872240 # Total energy per rank (pJ)
system.physmem_0.averagePower 823.825505 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 346000 # Time in different power states
system.physmem_0.actBackEnergy 21404070 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 67500 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 25911645 # Total energy per rank (pJ)
system.physmem_0.averagePower 825.080242 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 105750 # Time in different power states
system.physmem_0.memoryStateTime::REF 1040000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 30032750 # Time in different power states
system.physmem_0.memoryStateTime::ACT 30362750 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 347760 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 189750 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 1552200 # Energy for read commands per rank (pJ)
system.physmem_1.actEnergy 332640 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 181500 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 1544400 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 2034240 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 20535390 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 831750 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 25491090 # Total energy per rank (pJ)
system.physmem_1.averagePower 811.591993 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 1333500 # Time in different power states
system.physmem_1.actBackEnergy 20470410 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 886500 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 25449690 # Total energy per rank (pJ)
system.physmem_1.averagePower 810.370642 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 1337750 # Time in different power states
system.physmem_1.memoryStateTime::REF 1040000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 29134000 # Time in different power states
system.physmem_1.memoryStateTime::ACT 29041000 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.branchPred.lookups 1929 # Number of BP lookups
system.cpu.branchPred.condPredicted 1187 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 360 # Number of conditional branches incorrect
system.cpu.branchPred.lookups 1942 # Number of BP lookups
system.cpu.branchPred.condPredicted 1197 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 362 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 1557 # Number of BTB lookups
system.cpu.branchPred.BTBHits 398 # Number of BTB hits
system.cpu.branchPred.BTBHits 406 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 25.561978 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 224 # Number of times the RAS was used to get a target.
system.cpu.branchPred.BTBHitPct 26.075787 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 225 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 14 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 1369 # DTB read hits
system.cpu.dtb.read_hits 1372 # DTB read hits
system.cpu.dtb.read_misses 11 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 1380 # DTB read accesses
system.cpu.dtb.read_accesses 1383 # DTB read accesses
system.cpu.dtb.write_hits 884 # DTB write hits
system.cpu.dtb.write_misses 3 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 887 # DTB write accesses
system.cpu.dtb.data_hits 2253 # DTB hits
system.cpu.dtb.data_hits 2256 # DTB hits
system.cpu.dtb.data_misses 14 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 2267 # DTB accesses
system.cpu.itb.fetch_hits 2651 # ITB hits
system.cpu.dtb.data_accesses 2270 # DTB accesses
system.cpu.itb.fetch_hits 2673 # ITB hits
system.cpu.itb.fetch_misses 17 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 2668 # ITB accesses
system.cpu.itb.fetch_accesses 2690 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@ -293,80 +293,80 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
system.cpu.numCycles 75106 # number of cpu cycles simulated
system.cpu.numCycles 75258 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 6400 # Number of instructions committed
system.cpu.committedOps 6400 # Number of ops (including micro ops) committed
system.cpu.discardedOps 1085 # Number of ops (including micro ops) which were discarded before commit
system.cpu.committedInsts 6413 # Number of instructions committed
system.cpu.committedOps 6413 # Number of ops (including micro ops) committed
system.cpu.discardedOps 1090 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 11.735312 # CPI: cycles per instruction
system.cpu.ipc 0.085213 # IPC: instructions per cycle
system.cpu.tickCycles 12517 # Number of cycles that the object actually ticked
system.cpu.idleCycles 62589 # Total number of cycles that the object has spent stopped
system.cpu.cpi 11.735225 # CPI: cycles per instruction
system.cpu.ipc 0.085214 # IPC: instructions per cycle
system.cpu.tickCycles 12565 # Number of cycles that the object actually ticked
system.cpu.idleCycles 62693 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 103.920661 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 1972 # Total number of references to valid blocks.
system.cpu.dcache.tags.tagsinuse 104.289845 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 1974 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 169 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 11.668639 # Average number of references to valid blocks.
system.cpu.dcache.tags.avg_refs 11.680473 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 103.920661 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.025371 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.025371 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_blocks::cpu.data 104.289845 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.025461 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.025461 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 147 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.041260 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 4567 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 4567 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 1232 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1232 # number of ReadReq hits
system.cpu.dcache.tags.tag_accesses 4573 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 4573 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 1234 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1234 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 740 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 740 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 1972 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 1972 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 1972 # number of overall hits
system.cpu.dcache.overall_hits::total 1972 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 102 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 102 # number of ReadReq misses
system.cpu.dcache.demand_hits::cpu.data 1974 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 1974 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 1974 # number of overall hits
system.cpu.dcache.overall_hits::total 1974 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 103 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 103 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 125 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 125 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 227 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 227 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 227 # number of overall misses
system.cpu.dcache.overall_misses::total 227 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 8311500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 8311500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 9136500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 9136500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 17448000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 17448000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 17448000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 17448000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 1334 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1334 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.demand_misses::cpu.data 228 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 228 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 228 # number of overall misses
system.cpu.dcache.overall_misses::total 228 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 8381500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 8381500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 9164500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 9164500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 17546000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 17546000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 17546000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 17546000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 1337 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1337 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 2199 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 2199 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 2199 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 2199 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076462 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.076462 # miss rate for ReadReq accesses
system.cpu.dcache.demand_accesses::cpu.data 2202 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 2202 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 2202 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 2202 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.077038 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.077038 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.144509 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.144509 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.103229 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.103229 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.103229 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.103229 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 81485.294118 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 81485.294118 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73092 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 73092 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 76863.436123 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 76863.436123 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 76863.436123 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 76863.436123 # average overall miss latency
system.cpu.dcache.demand_miss_rate::cpu.data 0.103542 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.103542 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.103542 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.103542 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 81373.786408 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 81373.786408 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73316 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 73316 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 76956.140351 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 76956.140351 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 76956.140351 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 76956.140351 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -375,14 +375,14 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 7 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 52 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 52 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 58 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 58 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 58 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 58 # number of overall MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 59 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 59 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 59 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 59 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 96 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 96 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses
@ -391,82 +391,82 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 169
system.cpu.dcache.demand_mshr_misses::total 169 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 169 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 169 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7818500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 7818500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5371500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5371500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13190000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 13190000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13190000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 13190000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.071964 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.071964 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7819000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 7819000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5385500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5385500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13204500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 13204500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13204500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 13204500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.071803 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.071803 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076853 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.076853 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076853 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.076853 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 81442.708333 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 81442.708333 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73582.191781 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73582.191781 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78047.337278 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 78047.337278 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78047.337278 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 78047.337278 # average overall mshr miss latency
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076748 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.076748 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076748 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.076748 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 81447.916667 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 81447.916667 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73773.972603 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73773.972603 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78133.136095 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 78133.136095 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78133.136095 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 78133.136095 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 0 # number of replacements
system.cpu.icache.tags.tagsinuse 175.815240 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 2286 # Total number of references to valid blocks.
system.cpu.icache.tags.tagsinuse 175.465909 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 2308 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 365 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 6.263014 # Average number of references to valid blocks.
system.cpu.icache.tags.avg_refs 6.323288 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 175.815240 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.085847 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.085847 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_blocks::cpu.inst 175.465909 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.085677 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.085677 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 259 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.178223 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 5667 # Number of tag accesses
system.cpu.icache.tags.data_accesses 5667 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 2286 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 2286 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 2286 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 2286 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 2286 # number of overall hits
system.cpu.icache.overall_hits::total 2286 # number of overall hits
system.cpu.icache.tags.tag_accesses 5711 # Number of tag accesses
system.cpu.icache.tags.data_accesses 5711 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 2308 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 2308 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 2308 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 2308 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 2308 # number of overall hits
system.cpu.icache.overall_hits::total 2308 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 365 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 365 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 365 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 365 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 365 # number of overall misses
system.cpu.icache.overall_misses::total 365 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 27932500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 27932500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 27932500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 27932500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 27932500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 27932500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 2651 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 2651 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 2651 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 2651 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 2651 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 2651 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.137684 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.137684 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.137684 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.137684 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.137684 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.137684 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76527.397260 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 76527.397260 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 76527.397260 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 76527.397260 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 76527.397260 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 76527.397260 # average overall miss latency
system.cpu.icache.ReadReq_miss_latency::cpu.inst 28127000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 28127000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 28127000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 28127000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 28127000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 28127000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 2673 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 2673 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 2673 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 2673 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 2673 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 2673 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.136551 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.136551 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.136551 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.136551 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.136551 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.136551 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77060.273973 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 77060.273973 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 77060.273973 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 77060.273973 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 77060.273973 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 77060.273973 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -481,36 +481,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 365
system.cpu.icache.demand_mshr_misses::total 365 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 365 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 365 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27567500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 27567500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27567500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 27567500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27567500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 27567500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.137684 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.137684 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.137684 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.137684 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.137684 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.137684 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75527.397260 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75527.397260 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75527.397260 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 75527.397260 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75527.397260 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 75527.397260 # average overall mshr miss latency
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27762000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 27762000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27762000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 27762000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27762000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 27762000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.136551 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.136551 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.136551 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.136551 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.136551 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.136551 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76060.273973 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76060.273973 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76060.273973 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 76060.273973 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76060.273973 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 76060.273973 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 233.452540 # Cycle average of tags in use
system.cpu.l2cache.tags.tagsinuse 233.562418 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 460 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.002174 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst 175.828674 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 57.623866 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005366 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001759 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.007124 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_blocks::cpu.inst 175.479316 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 58.083102 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005355 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001773 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.007128 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 460 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 338 # Occupied blocks per task id
@ -535,18 +535,18 @@ system.cpu.l2cache.demand_misses::total 533 # nu
system.cpu.l2cache.overall_misses::cpu.inst 364 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 169 # number of overall misses
system.cpu.l2cache.overall_misses::total 533 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5261000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 5261000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 27008000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 27008000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7673000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 7673000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 27008000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 12934000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 39942000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 27008000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 12934000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 39942000 # number of overall miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5275000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 5275000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 27202500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 27202500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7673500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 7673500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 27202500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 12948500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 40151000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 27202500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 12948500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 40151000 # number of overall miss cycles
system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 365 # number of ReadCleanReq accesses(hits+misses)
@ -571,18 +571,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.998127 #
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.997260 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.998127 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72068.493151 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72068.493151 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74197.802198 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74197.802198 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 79927.083333 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 79927.083333 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74197.802198 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76532.544379 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 74938.086304 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74197.802198 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76532.544379 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 74938.086304 # average overall miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72260.273973 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72260.273973 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74732.142857 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74732.142857 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 79932.291667 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 79932.291667 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74732.142857 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76618.343195 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 75330.206379 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74732.142857 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76618.343195 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 75330.206379 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -603,18 +603,18 @@ system.cpu.l2cache.demand_mshr_misses::total 533
system.cpu.l2cache.overall_mshr_misses::cpu.inst 364 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 169 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 533 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4531000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4531000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 23368000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 23368000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6713000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6713000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23368000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11244000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 34612000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23368000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11244000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 34612000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4545000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4545000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 23562500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 23562500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6713500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6713500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23562500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11258500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 34821000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23562500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11258500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 34821000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.997260 # mshr miss rate for ReadCleanReq accesses
@ -627,18 +627,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.998127
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.997260 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.998127 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62068.493151 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62068.493151 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64197.802198 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64197.802198 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69927.083333 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69927.083333 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64197.802198 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66532.544379 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64938.086304 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64197.802198 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66532.544379 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64938.086304 # average overall mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62260.273973 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62260.273973 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64732.142857 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64732.142857 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69932.291667 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69932.291667 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64732.142857 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66618.343195 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65330.206379 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64732.142857 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66618.343195 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65330.206379 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.snoop_filter.tot_requests 534 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data.
@ -694,9 +694,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 533 # Request fanout histogram
system.membus.reqLayer0.occupancy 602500 # Layer occupancy (ticks)
system.membus.reqLayer0.occupancy 603000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 1.6 # Layer utilization (%)
system.membus.respLayer1.occupancy 2833000 # Layer occupancy (ticks)
system.membus.respLayer1.occupancy 2833750 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 7.5 # Layer utilization (%)
---------- End Simulation Statistics ----------

10
tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout
View file

@ -1,13 +1,15 @@
Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing/simout
Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Mar 13 2016 22:43:13
gem5 started Mar 13 2016 22:49:02
gem5 executing on phenom, pid 19909
gem5 compiled Mar 14 2016 21:54:46
gem5 started Mar 14 2016 21:57:45
gem5 executing on phenom, pid 28188
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
Exiting @ tick 21900500 because target called exit()
Exiting @ tick 21972500 because target called exit()

1118
tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

3
tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini
View file

@ -116,7 +116,7 @@ env=
errout=cerr
euid=100
eventq_index=0
executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
kvmInSE=false
@ -151,6 +151,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4

12
tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout
View file

@ -1,13 +1,15 @@
Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic/simout
Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 21 2016 13:49:21
gem5 started Jan 21 2016 13:50:02
gem5 executing on zizzer, pid 34000
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic
gem5 compiled Mar 14 2016 21:54:46
gem5 started Mar 14 2016 21:56:00
gem5 executing on phenom, pid 28087
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
Exiting @ tick 3208000 because target called exit()
Exiting @ tick 3214500 because target called exit()

182
tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt
View file

@ -1,61 +1,61 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000003 # Number of seconds simulated
sim_ticks 3208000 # Number of ticks simulated
final_tick 3208000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 3214500 # Number of ticks simulated
final_tick 3214500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 146057 # Simulator instruction rate (inst/s)
host_op_rate 145971 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 73240755 # Simulator tick rate (ticks/s)
host_mem_usage 220608 # Number of bytes of host memory used
host_seconds 0.04 # Real time elapsed on the host
sim_insts 6390 # Number of instructions simulated
sim_ops 6390 # Number of ops (including micro ops) simulated
host_inst_rate 21023 # Simulator instruction rate (inst/s)
host_op_rate 21020 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 10551583 # Simulator tick rate (ticks/s)
host_mem_usage 216888 # Number of bytes of host memory used
host_seconds 0.30 # Real time elapsed on the host
sim_insts 6403 # Number of instructions simulated
sim_ops 6403 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 25600 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 8788 # Number of bytes read from this memory
system.physmem.bytes_read::total 34388 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 25600 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 25600 # Number of instructions bytes read from this memory
system.physmem.bytes_read::cpu.inst 25652 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 8804 # Number of bytes read from this memory
system.physmem.bytes_read::total 34456 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 25652 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 25652 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 6696 # Number of bytes written to this memory
system.physmem.bytes_written::total 6696 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 6400 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1183 # Number of read requests responded to by this memory
system.physmem.num_reads::total 7583 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 6413 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1185 # Number of read requests responded to by this memory
system.physmem.num_reads::total 7598 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 865 # Number of write requests responded to by this memory
system.physmem.num_writes::total 865 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 7980049875 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2739401496 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 10719451372 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7980049875 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7980049875 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 2087281796 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2087281796 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7980049875 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 4826683292 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 12806733167 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 7980090216 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2738839633 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 10718929849 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7980090216 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7980090216 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 2083061129 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2083061129 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7980090216 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 4821900762 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 12801990978 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 1183 # DTB read hits
system.cpu.dtb.read_hits 1185 # DTB read hits
system.cpu.dtb.read_misses 7 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 1190 # DTB read accesses
system.cpu.dtb.read_accesses 1192 # DTB read accesses
system.cpu.dtb.write_hits 865 # DTB write hits
system.cpu.dtb.write_misses 3 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 868 # DTB write accesses
system.cpu.dtb.data_hits 2048 # DTB hits
system.cpu.dtb.data_hits 2050 # DTB hits
system.cpu.dtb.data_misses 10 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 2058 # DTB accesses
system.cpu.itb.fetch_hits 6400 # ITB hits
system.cpu.dtb.data_accesses 2060 # DTB accesses
system.cpu.itb.fetch_hits 6413 # ITB hits
system.cpu.itb.fetch_misses 17 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 6417 # ITB accesses
system.cpu.itb.fetch_accesses 6430 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@ -69,84 +69,84 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
system.cpu.numCycles 6417 # number of cpu cycles simulated
system.cpu.numCycles 6430 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 6390 # Number of instructions committed
system.cpu.committedOps 6390 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses
system.cpu.committedInsts 6403 # Number of instructions committed
system.cpu.committedOps 6403 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 6329 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
system.cpu.num_func_calls 251 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls
system.cpu.num_int_insts 6317 # number of integer instructions
system.cpu.num_conditional_control_insts 754 # number of instructions that are conditional controls
system.cpu.num_int_insts 6329 # number of integer instructions
system.cpu.num_fp_insts 10 # number of float instructions
system.cpu.num_int_register_reads 8285 # number of times the integer registers were read
system.cpu.num_int_register_writes 4568 # number of times the integer registers were written
system.cpu.num_int_register_reads 8297 # number of times the integer registers were read
system.cpu.num_int_register_writes 4575 # number of times the integer registers were written
system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
system.cpu.num_mem_refs 2058 # number of memory refs
system.cpu.num_load_insts 1190 # Number of load instructions
system.cpu.num_mem_refs 2060 # number of memory refs
system.cpu.num_load_insts 1192 # Number of load instructions
system.cpu.num_store_insts 868 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 6417 # Number of busy cycles
system.cpu.num_busy_cycles 6430 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.Branches 1050 # Number of branches fetched
system.cpu.Branches 1056 # Number of branches fetched
system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction
system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction
system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction
system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction
system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction
system.cpu.op_class::IntAlu 4331 67.53% 67.83% # Class of executed instruction
system.cpu.op_class::IntMult 1 0.02% 67.85% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 67.85% # Class of executed instruction
system.cpu.op_class::FloatAdd 2 0.03% 67.88% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::MemRead 1192 18.59% 86.46% # Class of executed instruction
system.cpu.op_class::MemWrite 868 13.54% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 6400 # Class of executed instruction
system.membus.trans_dist::ReadReq 7583 # Transaction distribution
system.membus.trans_dist::ReadResp 7583 # Transaction distribution
system.cpu.op_class::total 6413 # Class of executed instruction
system.membus.trans_dist::ReadReq 7598 # Transaction distribution
system.membus.trans_dist::ReadResp 7598 # Transaction distribution
system.membus.trans_dist::WriteReq 865 # Transaction distribution
system.membus.trans_dist::WriteResp 865 # Transaction distribution
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 12800 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 4096 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 16896 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 25600 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 15484 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 41084 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 12826 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 4100 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 16926 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 25652 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 15500 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 41152 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 8448 # Request fanout histogram
system.membus.snoop_fanout::mean 0.757576 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.428575 # Request fanout histogram
system.membus.snoop_fanout::samples 8463 # Request fanout histogram
system.membus.snoop_fanout::mean 0.757769 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.428459 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 2048 24.24% 24.24% # Request fanout histogram
system.membus.snoop_fanout::1 6400 75.76% 100.00% # Request fanout histogram
system.membus.snoop_fanout::0 2050 24.22% 24.22% # Request fanout histogram
system.membus.snoop_fanout::1 6413 75.78% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 8448 # Request fanout histogram
system.membus.snoop_fanout::total 8463 # Request fanout histogram
---------- End Simulation Statistics ----------

2
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini
View file

@ -120,7 +120,7 @@ env=
errout=cerr
euid=100
eventq_index=0
executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
kvmInSE=false

12
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simout
View file

@ -1,13 +1,15 @@
Redirecting stdout to build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_Two_Level/simout
Redirecting stderr to build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_Two_Level/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 21 2016 14:01:33
gem5 started Jan 21 2016 14:02:10
gem5 executing on zizzer, pid 44721
command line: build/ALPHA_MESI_Two_Level/gem5.opt -d build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_Two_Level -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_Two_Level
gem5 compiled Mar 14 2016 22:00:08
gem5 started Mar 14 2016 22:01:20
gem5 executing on phenom, pid 28860
command line: build/ALPHA_MESI_Two_Level/gem5.opt -d build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_Two_Level -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_Two_Level
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
Exiting @ tick 121460 because target called exit()
Exiting @ tick 121535 because target called exit()

672
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt
View file

@ -1,40 +1,40 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000121 # Number of seconds simulated
sim_ticks 121460 # Number of ticks simulated
final_tick 121460 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_seconds 0.000122 # Number of seconds simulated
sim_ticks 121535 # Number of ticks simulated
final_tick 121535 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_inst_rate 58804 # Simulator instruction rate (inst/s)
host_op_rate 58798 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1117518 # Simulator tick rate (ticks/s)
host_mem_usage 412400 # Number of bytes of host memory used
host_seconds 0.11 # Real time elapsed on the host
sim_insts 6390 # Number of instructions simulated
sim_ops 6390 # Number of ops (including micro ops) simulated
host_inst_rate 23854 # Simulator instruction rate (inst/s)
host_op_rate 23852 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 452710 # Simulator tick rate (ticks/s)
host_mem_usage 387364 # Number of bytes of host memory used
host_seconds 0.27 # Real time elapsed on the host
sim_insts 6403 # Number of instructions simulated
sim_ops 6403 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 93440 # Number of bytes read from this memory
system.mem_ctrls.bytes_read::total 93440 # Number of bytes read from this memory
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 93504 # Number of bytes read from this memory
system.mem_ctrls.bytes_read::total 93504 # Number of bytes read from this memory
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 17728 # Number of bytes written to this memory
system.mem_ctrls.bytes_written::total 17728 # Number of bytes written to this memory
system.mem_ctrls.num_reads::ruby.dir_cntrl0 1460 # Number of read requests responded to by this memory
system.mem_ctrls.num_reads::total 1460 # Number of read requests responded to by this memory
system.mem_ctrls.num_reads::ruby.dir_cntrl0 1461 # Number of read requests responded to by this memory
system.mem_ctrls.num_reads::total 1461 # Number of read requests responded to by this memory
system.mem_ctrls.num_writes::ruby.dir_cntrl0 277 # Number of write requests responded to by this memory
system.mem_ctrls.num_writes::total 277 # Number of write requests responded to by this memory
system.mem_ctrls.bw_read::ruby.dir_cntrl0 769306768 # Total read bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_read::total 769306768 # Total read bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_write::ruby.dir_cntrl0 145957517 # Write bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_write::total 145957517 # Write bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_total::ruby.dir_cntrl0 915264285 # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.bw_total::total 915264285 # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.readReqs 1460 # Number of read requests accepted
system.mem_ctrls.bw_read::ruby.dir_cntrl0 769358621 # Total read bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_read::total 769358621 # Total read bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_write::ruby.dir_cntrl0 145867446 # Write bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_write::total 145867446 # Write bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_total::ruby.dir_cntrl0 915226067 # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.bw_total::total 915226067 # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.readReqs 1461 # Number of read requests accepted
system.mem_ctrls.writeReqs 277 # Number of write requests accepted
system.mem_ctrls.readBursts 1460 # Number of DRAM read bursts, including those serviced by the write queue
system.mem_ctrls.readBursts 1461 # Number of DRAM read bursts, including those serviced by the write queue
system.mem_ctrls.writeBursts 277 # Number of DRAM write bursts, including those merged in the write queue
system.mem_ctrls.bytesReadDRAM 74176 # Total number of bytes read from DRAM
system.mem_ctrls.bytesReadDRAM 74240 # Total number of bytes read from DRAM
system.mem_ctrls.bytesReadWrQ 19264 # Total number of bytes read from write queue
system.mem_ctrls.bytesWritten 5376 # Total number of bytes written to DRAM
system.mem_ctrls.bytesReadSys 93440 # Total read bytes from the system interface side
system.mem_ctrls.bytesReadSys 93504 # Total read bytes from the system interface side
system.mem_ctrls.bytesWrittenSys 17728 # Total written bytes from the system interface side
system.mem_ctrls.servicedByWrQ 301 # Number of DRAM read bursts serviced by the write queue
system.mem_ctrls.mergedWrBursts 163 # Number of DRAM write bursts merged with an existing one
@ -54,7 +54,7 @@ system.mem_ctrls.perBankRdBursts::11 75 # Pe
system.mem_ctrls.perBankRdBursts::12 26 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::13 395 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::14 67 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::15 48 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::15 49 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts
@ -73,14 +73,14 @@ system.mem_ctrls.perBankWrBursts::14 41 # Pe
system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
system.mem_ctrls.totGap 121373 # Total gap between requests
system.mem_ctrls.totGap 121448 # Total gap between requests
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::6 1460 # Read request sizes (log2)
system.mem_ctrls.readPktSize::6 1461 # Read request sizes (log2)
system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
@ -88,7 +88,7 @@ system.mem_ctrls.writePktSize::3 0 # Wr
system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::6 277 # Write request sizes (log2)
system.mem_ctrls.rdQLenPdf::0 1159 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::0 1160 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
@ -184,24 +184,24 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh
system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.mem_ctrls.bytesPerActivate::samples 215 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::mean 361.079070 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::gmean 218.518186 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::stdev 343.911785 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::0-127 62 28.84% 28.84% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::128-255 53 24.65% 53.49% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::256-383 19 8.84% 62.33% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::384-511 18 8.37% 70.70% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::512-639 12 5.58% 76.28% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::640-767 6 2.79% 79.07% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::768-895 11 5.12% 84.19% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::896-1023 8 3.72% 87.91% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::1024-1151 26 12.09% 100.00% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::total 215 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::samples 217 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::mean 357.751152 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::gmean 214.775071 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::stdev 343.064988 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::0-127 66 30.41% 30.41% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::128-255 51 23.50% 53.92% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::256-383 17 7.83% 61.75% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::384-511 18 8.29% 70.05% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::512-639 15 6.91% 76.96% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::640-767 6 2.76% 79.72% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::768-895 12 5.53% 85.25% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::896-1023 4 1.84% 87.10% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::1024-1151 28 12.90% 100.00% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::total 217 # Bytes accessed per row activation
system.mem_ctrls.rdPerTurnAround::samples 5 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::mean 150.200000 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::gmean 107.544474 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::stdev 96.970098 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::mean 150.400000 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::gmean 107.633945 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::stdev 97.202366 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::16-23 1 20.00% 20.00% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::72-79 1 20.00% 40.00% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::200-207 1 20.00% 60.00% # Reads before turning the bus around for writes
@ -215,77 +215,77 @@ system.mem_ctrls.wrPerTurnAround::stdev 1.095445 # Wr
system.mem_ctrls.wrPerTurnAround::16 3 60.00% 60.00% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::18 2 40.00% 100.00% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::total 5 # Writes before turning the bus around for reads
system.mem_ctrls.totQLat 8037 # Total ticks spent queuing
system.mem_ctrls.totMemAccLat 30058 # Total ticks spent from burst creation until serviced by the DRAM
system.mem_ctrls.totBusLat 5795 # Total ticks spent in databus transfers
system.mem_ctrls.avgQLat 6.93 # Average queueing delay per DRAM burst
system.mem_ctrls.totQLat 8011 # Total ticks spent queuing
system.mem_ctrls.totMemAccLat 30051 # Total ticks spent from burst creation until serviced by the DRAM
system.mem_ctrls.totBusLat 5800 # Total ticks spent in databus transfers
system.mem_ctrls.avgQLat 6.91 # Average queueing delay per DRAM burst
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
system.mem_ctrls.avgMemAccLat 25.93 # Average memory access latency per DRAM burst
system.mem_ctrls.avgRdBW 610.70 # Average DRAM read bandwidth in MiByte/s
system.mem_ctrls.avgWrBW 44.26 # Average achieved write bandwidth in MiByte/s
system.mem_ctrls.avgRdBWSys 769.31 # Average system read bandwidth in MiByte/s
system.mem_ctrls.avgWrBWSys 145.96 # Average system write bandwidth in MiByte/s
system.mem_ctrls.avgMemAccLat 25.91 # Average memory access latency per DRAM burst
system.mem_ctrls.avgRdBW 610.85 # Average DRAM read bandwidth in MiByte/s
system.mem_ctrls.avgWrBW 44.23 # Average achieved write bandwidth in MiByte/s
system.mem_ctrls.avgRdBWSys 769.36 # Average system read bandwidth in MiByte/s
system.mem_ctrls.avgWrBWSys 145.87 # Average system write bandwidth in MiByte/s
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.mem_ctrls.busUtil 5.12 # Data bus utilization in percentage
system.mem_ctrls.busUtilRead 4.77 # Data bus utilization in percentage for reads
system.mem_ctrls.busUtilWrite 0.35 # Data bus utilization in percentage for writes
system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing
system.mem_ctrls.avgWrQLen 22.44 # Average write queue length when enqueuing
system.mem_ctrls.readRowHits 944 # Number of row buffer hits during reads
system.mem_ctrls.avgWrQLen 22.41 # Average write queue length when enqueuing
system.mem_ctrls.readRowHits 943 # Number of row buffer hits during reads
system.mem_ctrls.writeRowHits 78 # Number of row buffer hits during writes
system.mem_ctrls.readRowHitRate 81.45 # Row buffer hit rate for reads
system.mem_ctrls.readRowHitRate 81.29 # Row buffer hit rate for reads
system.mem_ctrls.writeRowHitRate 68.42 # Row buffer hit rate for writes
system.mem_ctrls.avgGap 69.88 # Average gap between requests
system.mem_ctrls.pageHitRate 80.28 # Row buffer hit rate, read and write combined
system.mem_ctrls.pageHitRate 80.14 # Row buffer hit rate, read and write combined
system.mem_ctrls_0.actEnergy 506520 # Energy for activate commands per rank (pJ)
system.mem_ctrls_0.preEnergy 281400 # Energy for precharge commands per rank (pJ)
system.mem_ctrls_0.readEnergy 5703360 # Energy for read commands per rank (pJ)
system.mem_ctrls_0.writeEnergy 248832 # Energy for write commands per rank (pJ)
system.mem_ctrls_0.refreshEnergy 7628400 # Energy for refresh commands per rank (pJ)
system.mem_ctrls_0.actBackEnergy 66392460 # Energy for active background per rank (pJ)
system.mem_ctrls_0.preBackEnergy 11991000 # Energy for precharge background per rank (pJ)
system.mem_ctrls_0.totalEnergy 92751972 # Total energy per rank (pJ)
system.mem_ctrls_0.averagePower 792.413259 # Core power per rank (mW)
system.mem_ctrls_0.memoryStateTime::IDLE 22133 # Time in different power states
system.mem_ctrls_0.actBackEnergy 65986164 # Energy for active background per rank (pJ)
system.mem_ctrls_0.preBackEnergy 12347400 # Energy for precharge background per rank (pJ)
system.mem_ctrls_0.totalEnergy 92702076 # Total energy per rank (pJ)
system.mem_ctrls_0.averagePower 791.986980 # Core power per rank (mW)
system.mem_ctrls_0.memoryStateTime::IDLE 22788 # Time in different power states
system.mem_ctrls_0.memoryStateTime::REF 3900 # Time in different power states
system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.mem_ctrls_0.memoryStateTime::ACT 93571 # Time in different power states
system.mem_ctrls_0.memoryStateTime::ACT 92991 # Time in different power states
system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.mem_ctrls_1.actEnergy 1088640 # Energy for activate commands per rank (pJ)
system.mem_ctrls_1.preEnergy 604800 # Energy for precharge commands per rank (pJ)
system.mem_ctrls_1.actEnergy 1103760 # Energy for activate commands per rank (pJ)
system.mem_ctrls_1.preEnergy 613200 # Energy for precharge commands per rank (pJ)
system.mem_ctrls_1.readEnergy 8236800 # Energy for read commands per rank (pJ)
system.mem_ctrls_1.writeEnergy 622080 # Energy for write commands per rank (pJ)
system.mem_ctrls_1.refreshEnergy 7628400 # Energy for refresh commands per rank (pJ)
system.mem_ctrls_1.actBackEnergy 78596388 # Energy for active background per rank (pJ)
system.mem_ctrls_1.preBackEnergy 1285800 # Energy for precharge background per rank (pJ)
system.mem_ctrls_1.totalEnergy 98062908 # Total energy per rank (pJ)
system.mem_ctrls_1.averagePower 837.786484 # Core power per rank (mW)
system.mem_ctrls_1.memoryStateTime::IDLE 1555 # Time in different power states
system.mem_ctrls_1.actBackEnergy 78402132 # Energy for active background per rank (pJ)
system.mem_ctrls_1.preBackEnergy 1456200 # Energy for precharge background per rank (pJ)
system.mem_ctrls_1.totalEnergy 98062572 # Total energy per rank (pJ)
system.mem_ctrls_1.averagePower 837.783614 # Core power per rank (mW)
system.mem_ctrls_1.memoryStateTime::IDLE 1811 # Time in different power states
system.mem_ctrls_1.memoryStateTime::REF 3900 # Time in different power states
system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT 111609 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT 111353 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.clk_domain.clock 1 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 1183 # DTB read hits
system.cpu.dtb.read_hits 1185 # DTB read hits
system.cpu.dtb.read_misses 7 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 1190 # DTB read accesses
system.cpu.dtb.read_accesses 1192 # DTB read accesses
system.cpu.dtb.write_hits 865 # DTB write hits
system.cpu.dtb.write_misses 3 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 868 # DTB write accesses
system.cpu.dtb.data_hits 2048 # DTB hits
system.cpu.dtb.data_hits 2050 # DTB hits
system.cpu.dtb.data_misses 10 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 2058 # DTB accesses
system.cpu.itb.fetch_hits 6401 # ITB hits
system.cpu.dtb.data_accesses 2060 # DTB accesses
system.cpu.itb.fetch_hits 6414 # ITB hits
system.cpu.itb.fetch_misses 17 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 6418 # ITB accesses
system.cpu.itb.fetch_accesses 6431 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@ -299,108 +299,108 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
system.cpu.numCycles 121460 # number of cpu cycles simulated
system.cpu.numCycles 121535 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 6390 # Number of instructions committed
system.cpu.committedOps 6390 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses
system.cpu.committedInsts 6403 # Number of instructions committed
system.cpu.committedOps 6403 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 6329 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
system.cpu.num_func_calls 251 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls
system.cpu.num_int_insts 6317 # number of integer instructions
system.cpu.num_conditional_control_insts 754 # number of instructions that are conditional controls
system.cpu.num_int_insts 6329 # number of integer instructions
system.cpu.num_fp_insts 10 # number of float instructions
system.cpu.num_int_register_reads 8285 # number of times the integer registers were read
system.cpu.num_int_register_writes 4568 # number of times the integer registers were written
system.cpu.num_int_register_reads 8297 # number of times the integer registers were read
system.cpu.num_int_register_writes 4575 # number of times the integer registers were written
system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
system.cpu.num_mem_refs 2058 # number of memory refs
system.cpu.num_load_insts 1190 # Number of load instructions
system.cpu.num_mem_refs 2060 # number of memory refs
system.cpu.num_load_insts 1192 # Number of load instructions
system.cpu.num_store_insts 868 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 121460 # Number of busy cycles
system.cpu.num_busy_cycles 121535 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.Branches 1050 # Number of branches fetched
system.cpu.Branches 1056 # Number of branches fetched
system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction
system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction
system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction
system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction
system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction
system.cpu.op_class::IntAlu 4331 67.53% 67.83% # Class of executed instruction
system.cpu.op_class::IntMult 1 0.02% 67.85% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 67.85% # Class of executed instruction
system.cpu.op_class::FloatAdd 2 0.03% 67.88% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::MemRead 1192 18.59% 86.46% # Class of executed instruction
system.cpu.op_class::MemWrite 868 13.54% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 6400 # Class of executed instruction
system.cpu.op_class::total 6413 # Class of executed instruction
system.ruby.clk_domain.clock 1 # Clock period in ticks
system.ruby.delayHist::bucket_size 1 # delay histogram for all message
system.ruby.delayHist::max_bucket 9 # delay histogram for all message
system.ruby.delayHist::samples 9645 # delay histogram for all message
system.ruby.delayHist::mean 0.164852 # delay histogram for all message
system.ruby.delayHist::stdev 1.012053 # delay histogram for all message
system.ruby.delayHist | 9285 96.27% 96.27% | 0 0.00% 96.27% | 215 2.23% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 145 1.50% 100.00% | 0 0.00% 100.00% # delay histogram for all message
system.ruby.delayHist::total 9645 # delay histogram for all message
system.ruby.delayHist::samples 9652 # delay histogram for all message
system.ruby.delayHist::mean 0.164525 # delay histogram for all message
system.ruby.delayHist::stdev 1.011525 # delay histogram for all message
system.ruby.delayHist | 9293 96.28% 96.28% | 0 0.00% 96.28% | 214 2.22% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 145 1.50% 100.00% | 0 0.00% 100.00% # delay histogram for all message
system.ruby.delayHist::total 9652 # delay histogram for all message
system.ruby.outstanding_req_hist_seqr::bucket_size 1
system.ruby.outstanding_req_hist_seqr::max_bucket 9
system.ruby.outstanding_req_hist_seqr::samples 8449
system.ruby.outstanding_req_hist_seqr::samples 8464
system.ruby.outstanding_req_hist_seqr::mean 1
system.ruby.outstanding_req_hist_seqr::gmean 1
system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 8449 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.outstanding_req_hist_seqr::total 8449
system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 8464 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.outstanding_req_hist_seqr::total 8464
system.ruby.latency_hist_seqr::bucket_size 64
system.ruby.latency_hist_seqr::max_bucket 639
system.ruby.latency_hist_seqr::samples 8448
system.ruby.latency_hist_seqr::mean 13.377367
system.ruby.latency_hist_seqr::gmean 2.098947
system.ruby.latency_hist_seqr::stdev 29.666839
system.ruby.latency_hist_seqr | 7289 86.28% 86.28% | 1140 13.49% 99.78% | 4 0.05% 99.82% | 1 0.01% 99.83% | 5 0.06% 99.89% | 9 0.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.latency_hist_seqr::total 8448
system.ruby.latency_hist_seqr::samples 8463
system.ruby.latency_hist_seqr::mean 13.360747
system.ruby.latency_hist_seqr::gmean 2.097350
system.ruby.latency_hist_seqr::stdev 29.565169
system.ruby.latency_hist_seqr | 7303 86.29% 86.29% | 1141 13.48% 99.78% | 4 0.05% 99.82% | 1 0.01% 99.83% | 8 0.09% 99.93% | 6 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.latency_hist_seqr::total 8463
system.ruby.hit_latency_hist_seqr::bucket_size 1
system.ruby.hit_latency_hist_seqr::max_bucket 9
system.ruby.hit_latency_hist_seqr::samples 6958
system.ruby.hit_latency_hist_seqr::samples 6972
system.ruby.hit_latency_hist_seqr::mean 1
system.ruby.hit_latency_hist_seqr::gmean 1
system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 6958 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.hit_latency_hist_seqr::total 6958
system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 6972 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.hit_latency_hist_seqr::total 6972
system.ruby.miss_latency_hist_seqr::bucket_size 64
system.ruby.miss_latency_hist_seqr::max_bucket 639
system.ruby.miss_latency_hist_seqr::samples 1490
system.ruby.miss_latency_hist_seqr::mean 71.177181
system.ruby.miss_latency_hist_seqr::gmean 66.939744
system.ruby.miss_latency_hist_seqr::stdev 30.560087
system.ruby.miss_latency_hist_seqr | 331 22.21% 22.21% | 1140 76.51% 98.72% | 4 0.27% 98.99% | 1 0.07% 99.06% | 5 0.34% 99.40% | 9 0.60% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.miss_latency_hist_seqr::total 1490
system.ruby.l1_cntrl0.L1Dcache.demand_hits 1249 # Number of cache demand hits
system.ruby.l1_cntrl0.L1Dcache.demand_misses 799 # Number of cache demand misses
system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2048 # Number of cache demand accesses
system.ruby.l1_cntrl0.L1Icache.demand_hits 5709 # Number of cache demand hits
system.ruby.miss_latency_hist_seqr::samples 1491
system.ruby.miss_latency_hist_seqr::mean 71.160295
system.ruby.miss_latency_hist_seqr::gmean 66.961050
system.ruby.miss_latency_hist_seqr::stdev 30.103565
system.ruby.miss_latency_hist_seqr | 331 22.20% 22.20% | 1141 76.53% 98.73% | 4 0.27% 98.99% | 1 0.07% 99.06% | 8 0.54% 99.60% | 6 0.40% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.miss_latency_hist_seqr::total 1491
system.ruby.l1_cntrl0.L1Dcache.demand_hits 1250 # Number of cache demand hits
system.ruby.l1_cntrl0.L1Dcache.demand_misses 800 # Number of cache demand misses
system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2050 # Number of cache demand accesses
system.ruby.l1_cntrl0.L1Icache.demand_hits 5722 # Number of cache demand hits
system.ruby.l1_cntrl0.L1Icache.demand_misses 691 # Number of cache demand misses
system.ruby.l1_cntrl0.L1Icache.demand_accesses 6400 # Number of cache demand accesses
system.ruby.l1_cntrl0.L1Icache.demand_accesses 6413 # Number of cache demand accesses
system.ruby.l1_cntrl0.prefetcher.miss_observed 0 # number of misses observed
system.ruby.l1_cntrl0.prefetcher.allocated_streams 0 # number of streams allocated for prefetching
system.ruby.l1_cntrl0.prefetcher.prefetches_requested 0 # number of prefetch requests made
@ -411,178 +411,178 @@ system.ruby.l1_cntrl0.prefetcher.partial_hits 0
system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages
system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
system.ruby.l2_cntrl0.L2cache.demand_hits 30 # Number of cache demand hits
system.ruby.l2_cntrl0.L2cache.demand_misses 1460 # Number of cache demand misses
system.ruby.l2_cntrl0.L2cache.demand_accesses 1490 # Number of cache demand accesses
system.ruby.l2_cntrl0.L2cache.demand_misses 1461 # Number of cache demand misses
system.ruby.l2_cntrl0.L2cache.demand_accesses 1491 # Number of cache demand accesses
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
system.ruby.network.routers0.percent_links_utilized 4.310267
system.ruby.network.routers0.msg_count.Control::0 1490
system.ruby.network.routers0.percent_links_utilized 4.310281
system.ruby.network.routers0.msg_count.Control::0 1491
system.ruby.network.routers0.msg_count.Request_Control::2 1041
system.ruby.network.routers0.msg_count.Response_Data::1 1490
system.ruby.network.routers0.msg_count.Response_Control::1 1336
system.ruby.network.routers0.msg_count.Response_Control::2 799
system.ruby.network.routers0.msg_count.Response_Data::1 1491
system.ruby.network.routers0.msg_count.Response_Control::1 1337
system.ruby.network.routers0.msg_count.Response_Control::2 800
system.ruby.network.routers0.msg_count.Writeback_Data::0 145
system.ruby.network.routers0.msg_count.Writeback_Data::1 141
system.ruby.network.routers0.msg_count.Writeback_Control::0 291
system.ruby.network.routers0.msg_bytes.Control::0 11920
system.ruby.network.routers0.msg_count.Writeback_Control::0 292
system.ruby.network.routers0.msg_bytes.Control::0 11928
system.ruby.network.routers0.msg_bytes.Request_Control::2 8328
system.ruby.network.routers0.msg_bytes.Response_Data::1 107280
system.ruby.network.routers0.msg_bytes.Response_Control::1 10688
system.ruby.network.routers0.msg_bytes.Response_Control::2 6392
system.ruby.network.routers0.msg_bytes.Response_Data::1 107352
system.ruby.network.routers0.msg_bytes.Response_Control::1 10696
system.ruby.network.routers0.msg_bytes.Response_Control::2 6400
system.ruby.network.routers0.msg_bytes.Writeback_Data::0 10440
system.ruby.network.routers0.msg_bytes.Writeback_Data::1 10152
system.ruby.network.routers0.msg_bytes.Writeback_Control::0 2328
system.ruby.network.routers1.percent_links_utilized 8.369216
system.ruby.network.routers1.msg_count.Control::0 2950
system.ruby.network.routers0.msg_bytes.Writeback_Control::0 2336
system.ruby.network.routers1.percent_links_utilized 8.369194
system.ruby.network.routers1.msg_count.Control::0 2952
system.ruby.network.routers1.msg_count.Request_Control::2 1041
system.ruby.network.routers1.msg_count.Response_Data::1 3227
system.ruby.network.routers1.msg_count.Response_Control::1 3963
system.ruby.network.routers1.msg_count.Response_Control::2 799
system.ruby.network.routers1.msg_count.Response_Data::1 3229
system.ruby.network.routers1.msg_count.Response_Control::1 3966
system.ruby.network.routers1.msg_count.Response_Control::2 800
system.ruby.network.routers1.msg_count.Writeback_Data::0 145
system.ruby.network.routers1.msg_count.Writeback_Data::1 141
system.ruby.network.routers1.msg_count.Writeback_Control::0 291
system.ruby.network.routers1.msg_bytes.Control::0 23600
system.ruby.network.routers1.msg_count.Writeback_Control::0 292
system.ruby.network.routers1.msg_bytes.Control::0 23616
system.ruby.network.routers1.msg_bytes.Request_Control::2 8328
system.ruby.network.routers1.msg_bytes.Response_Data::1 232344
system.ruby.network.routers1.msg_bytes.Response_Control::1 31704
system.ruby.network.routers1.msg_bytes.Response_Control::2 6392
system.ruby.network.routers1.msg_bytes.Response_Data::1 232488
system.ruby.network.routers1.msg_bytes.Response_Control::1 31728
system.ruby.network.routers1.msg_bytes.Response_Control::2 6400
system.ruby.network.routers1.msg_bytes.Writeback_Data::0 10440
system.ruby.network.routers1.msg_bytes.Writeback_Data::1 10152
system.ruby.network.routers1.msg_bytes.Writeback_Control::0 2328
system.ruby.network.routers2.percent_links_utilized 4.058949
system.ruby.network.routers2.msg_count.Control::0 1460
system.ruby.network.routers2.msg_count.Response_Data::1 1737
system.ruby.network.routers2.msg_count.Response_Control::1 2627
system.ruby.network.routers2.msg_bytes.Control::0 11680
system.ruby.network.routers2.msg_bytes.Response_Data::1 125064
system.ruby.network.routers2.msg_bytes.Response_Control::1 21016
system.ruby.network.routers3.percent_links_utilized 5.579477
system.ruby.network.routers3.msg_count.Control::0 2950
system.ruby.network.routers1.msg_bytes.Writeback_Control::0 2336
system.ruby.network.routers2.percent_links_utilized 4.058913
system.ruby.network.routers2.msg_count.Control::0 1461
system.ruby.network.routers2.msg_count.Response_Data::1 1738
system.ruby.network.routers2.msg_count.Response_Control::1 2629
system.ruby.network.routers2.msg_bytes.Control::0 11688
system.ruby.network.routers2.msg_bytes.Response_Data::1 125136
system.ruby.network.routers2.msg_bytes.Response_Control::1 21032
system.ruby.network.routers3.percent_links_utilized 5.579463
system.ruby.network.routers3.msg_count.Control::0 2952
system.ruby.network.routers3.msg_count.Request_Control::2 1041
system.ruby.network.routers3.msg_count.Response_Data::1 3227
system.ruby.network.routers3.msg_count.Response_Control::1 3963
system.ruby.network.routers3.msg_count.Response_Control::2 799
system.ruby.network.routers3.msg_count.Response_Data::1 3229
system.ruby.network.routers3.msg_count.Response_Control::1 3966
system.ruby.network.routers3.msg_count.Response_Control::2 800
system.ruby.network.routers3.msg_count.Writeback_Data::0 145
system.ruby.network.routers3.msg_count.Writeback_Data::1 141
system.ruby.network.routers3.msg_count.Writeback_Control::0 291
system.ruby.network.routers3.msg_bytes.Control::0 23600
system.ruby.network.routers3.msg_count.Writeback_Control::0 292
system.ruby.network.routers3.msg_bytes.Control::0 23616
system.ruby.network.routers3.msg_bytes.Request_Control::2 8328
system.ruby.network.routers3.msg_bytes.Response_Data::1 232344
system.ruby.network.routers3.msg_bytes.Response_Control::1 31704
system.ruby.network.routers3.msg_bytes.Response_Control::2 6392
system.ruby.network.routers3.msg_bytes.Response_Data::1 232488
system.ruby.network.routers3.msg_bytes.Response_Control::1 31728
system.ruby.network.routers3.msg_bytes.Response_Control::2 6400
system.ruby.network.routers3.msg_bytes.Writeback_Data::0 10440
system.ruby.network.routers3.msg_bytes.Writeback_Data::1 10152
system.ruby.network.routers3.msg_bytes.Writeback_Control::0 2328
system.ruby.network.msg_count.Control 8850
system.ruby.network.routers3.msg_bytes.Writeback_Control::0 2336
system.ruby.network.msg_count.Control 8856
system.ruby.network.msg_count.Request_Control 3123
system.ruby.network.msg_count.Response_Data 9681
system.ruby.network.msg_count.Response_Control 14286
system.ruby.network.msg_count.Response_Data 9687
system.ruby.network.msg_count.Response_Control 14298
system.ruby.network.msg_count.Writeback_Data 858
system.ruby.network.msg_count.Writeback_Control 873
system.ruby.network.msg_byte.Control 70800
system.ruby.network.msg_count.Writeback_Control 876
system.ruby.network.msg_byte.Control 70848
system.ruby.network.msg_byte.Request_Control 24984
system.ruby.network.msg_byte.Response_Data 697032
system.ruby.network.msg_byte.Response_Control 114288
system.ruby.network.msg_byte.Response_Data 697464
system.ruby.network.msg_byte.Response_Control 114384
system.ruby.network.msg_byte.Writeback_Data 61776
system.ruby.network.msg_byte.Writeback_Control 6984
system.ruby.network.routers0.throttle0.link_utilization 6.128355
system.ruby.network.msg_byte.Writeback_Control 7008
system.ruby.network.routers0.throttle0.link_utilization 6.128687
system.ruby.network.routers0.throttle0.msg_count.Request_Control::2 1041
system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 1490
system.ruby.network.routers0.throttle0.msg_count.Response_Control::1 436
system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 1491
system.ruby.network.routers0.throttle0.msg_count.Response_Control::1 437
system.ruby.network.routers0.throttle0.msg_bytes.Request_Control::2 8328
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::1 107280
system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::1 3488
system.ruby.network.routers0.throttle1.link_utilization 2.492178
system.ruby.network.routers0.throttle1.msg_count.Control::0 1490
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::1 107352
system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::1 3496
system.ruby.network.routers0.throttle1.link_utilization 2.491875
system.ruby.network.routers0.throttle1.msg_count.Control::0 1491
system.ruby.network.routers0.throttle1.msg_count.Response_Control::1 900
system.ruby.network.routers0.throttle1.msg_count.Response_Control::2 799
system.ruby.network.routers0.throttle1.msg_count.Response_Control::2 800
system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::0 145
system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::1 141
system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 291
system.ruby.network.routers0.throttle1.msg_bytes.Control::0 11920
system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 292
system.ruby.network.routers0.throttle1.msg_bytes.Control::0 11928
system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::1 7200
system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::2 6392
system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::2 6400
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::0 10440
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::1 10152
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 2328
system.ruby.network.routers1.throttle0.link_utilization 8.499094
system.ruby.network.routers1.throttle0.msg_count.Control::0 1490
system.ruby.network.routers1.throttle0.msg_count.Response_Data::1 1460
system.ruby.network.routers1.throttle0.msg_count.Response_Control::1 2352
system.ruby.network.routers1.throttle0.msg_count.Response_Control::2 799
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 2336
system.ruby.network.routers1.throttle0.link_utilization 8.499198
system.ruby.network.routers1.throttle0.msg_count.Control::0 1491
system.ruby.network.routers1.throttle0.msg_count.Response_Data::1 1461
system.ruby.network.routers1.throttle0.msg_count.Response_Control::1 2353
system.ruby.network.routers1.throttle0.msg_count.Response_Control::2 800
system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::0 145
system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::1 141
system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::0 291
system.ruby.network.routers1.throttle0.msg_bytes.Control::0 11920
system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::1 105120
system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::1 18816
system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::2 6392
system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::0 292
system.ruby.network.routers1.throttle0.msg_bytes.Control::0 11928
system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::1 105192
system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::1 18824
system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::2 6400
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::0 10440
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::1 10152
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0 2328
system.ruby.network.routers1.throttle1.link_utilization 8.239338
system.ruby.network.routers1.throttle1.msg_count.Control::0 1460
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0 2336
system.ruby.network.routers1.throttle1.link_utilization 8.239190
system.ruby.network.routers1.throttle1.msg_count.Control::0 1461
system.ruby.network.routers1.throttle1.msg_count.Request_Control::2 1041
system.ruby.network.routers1.throttle1.msg_count.Response_Data::1 1767
system.ruby.network.routers1.throttle1.msg_count.Response_Control::1 1611
system.ruby.network.routers1.throttle1.msg_bytes.Control::0 11680
system.ruby.network.routers1.throttle1.msg_count.Response_Data::1 1768
system.ruby.network.routers1.throttle1.msg_count.Response_Control::1 1613
system.ruby.network.routers1.throttle1.msg_bytes.Control::0 11688
system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::2 8328
system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::1 127224
system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::1 12888
system.ruby.network.routers2.throttle0.link_utilization 2.110983
system.ruby.network.routers2.throttle0.msg_count.Control::0 1460
system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::1 127296
system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::1 12904
system.ruby.network.routers2.throttle0.link_utilization 2.110503
system.ruby.network.routers2.throttle0.msg_count.Control::0 1461
system.ruby.network.routers2.throttle0.msg_count.Response_Data::1 277
system.ruby.network.routers2.throttle0.msg_count.Response_Control::1 1175
system.ruby.network.routers2.throttle0.msg_bytes.Control::0 11680
system.ruby.network.routers2.throttle0.msg_count.Response_Control::1 1176
system.ruby.network.routers2.throttle0.msg_bytes.Control::0 11688
system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::1 19944
system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::1 9400
system.ruby.network.routers2.throttle1.link_utilization 6.006916
system.ruby.network.routers2.throttle1.msg_count.Response_Data::1 1460
system.ruby.network.routers2.throttle1.msg_count.Response_Control::1 1452
system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::1 105120
system.ruby.network.routers2.throttle1.msg_bytes.Response_Control::1 11616
system.ruby.network.routers3.throttle0.link_utilization 6.128355
system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::1 9408
system.ruby.network.routers2.throttle1.link_utilization 6.007323
system.ruby.network.routers2.throttle1.msg_count.Response_Data::1 1461
system.ruby.network.routers2.throttle1.msg_count.Response_Control::1 1453
system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::1 105192
system.ruby.network.routers2.throttle1.msg_bytes.Response_Control::1 11624
system.ruby.network.routers3.throttle0.link_utilization 6.128687
system.ruby.network.routers3.throttle0.msg_count.Request_Control::2 1041
system.ruby.network.routers3.throttle0.msg_count.Response_Data::1 1490
system.ruby.network.routers3.throttle0.msg_count.Response_Control::1 436
system.ruby.network.routers3.throttle0.msg_count.Response_Data::1 1491
system.ruby.network.routers3.throttle0.msg_count.Response_Control::1 437
system.ruby.network.routers3.throttle0.msg_bytes.Request_Control::2 8328
system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::1 107280
system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::1 3488
system.ruby.network.routers3.throttle1.link_utilization 8.499094
system.ruby.network.routers3.throttle1.msg_count.Control::0 1490
system.ruby.network.routers3.throttle1.msg_count.Response_Data::1 1460
system.ruby.network.routers3.throttle1.msg_count.Response_Control::1 2352
system.ruby.network.routers3.throttle1.msg_count.Response_Control::2 799
system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::1 107352
system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::1 3496
system.ruby.network.routers3.throttle1.link_utilization 8.499198
system.ruby.network.routers3.throttle1.msg_count.Control::0 1491
system.ruby.network.routers3.throttle1.msg_count.Response_Data::1 1461
system.ruby.network.routers3.throttle1.msg_count.Response_Control::1 2353
system.ruby.network.routers3.throttle1.msg_count.Response_Control::2 800
system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::0 145
system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::1 141
system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::0 291
system.ruby.network.routers3.throttle1.msg_bytes.Control::0 11920
system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::1 105120
system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::1 18816
system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::2 6392
system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::0 292
system.ruby.network.routers3.throttle1.msg_bytes.Control::0 11928
system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::1 105192
system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::1 18824
system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::2 6400
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::0 10440
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::1 10152
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0 2328
system.ruby.network.routers3.throttle2.link_utilization 2.110983
system.ruby.network.routers3.throttle2.msg_count.Control::0 1460
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0 2336
system.ruby.network.routers3.throttle2.link_utilization 2.110503
system.ruby.network.routers3.throttle2.msg_count.Control::0 1461
system.ruby.network.routers3.throttle2.msg_count.Response_Data::1 277
system.ruby.network.routers3.throttle2.msg_count.Response_Control::1 1175
system.ruby.network.routers3.throttle2.msg_bytes.Control::0 11680
system.ruby.network.routers3.throttle2.msg_count.Response_Control::1 1176
system.ruby.network.routers3.throttle2.msg_bytes.Control::0 11688
system.ruby.network.routers3.throttle2.msg_bytes.Response_Data::1 19944
system.ruby.network.routers3.throttle2.msg_bytes.Response_Control::1 9400
system.ruby.network.routers3.throttle2.msg_bytes.Response_Control::1 9408
system.ruby.delayVCHist.vnet_0::bucket_size 1 # delay histogram for vnet_0
system.ruby.delayVCHist.vnet_0::max_bucket 9 # delay histogram for vnet_0
system.ruby.delayVCHist.vnet_0::samples 2725 # delay histogram for vnet_0
system.ruby.delayVCHist.vnet_0::mean 0.425688 # delay histogram for vnet_0
system.ruby.delayVCHist.vnet_0::stdev 1.795962 # delay histogram for vnet_0
system.ruby.delayVCHist.vnet_0 | 2580 94.68% 94.68% | 0 0.00% 94.68% | 0 0.00% 94.68% | 0 0.00% 94.68% | 0 0.00% 94.68% | 0 0.00% 94.68% | 0 0.00% 94.68% | 0 0.00% 94.68% | 145 5.32% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_0
system.ruby.delayVCHist.vnet_0::total 2725 # delay histogram for vnet_0
system.ruby.delayVCHist.vnet_0::samples 2728 # delay histogram for vnet_0
system.ruby.delayVCHist.vnet_0::mean 0.425220 # delay histogram for vnet_0
system.ruby.delayVCHist.vnet_0::stdev 1.795029 # delay histogram for vnet_0
system.ruby.delayVCHist.vnet_0 | 2583 94.68% 94.68% | 0 0.00% 94.68% | 0 0.00% 94.68% | 0 0.00% 94.68% | 0 0.00% 94.68% | 0 0.00% 94.68% | 0 0.00% 94.68% | 0 0.00% 94.68% | 145 5.32% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_0
system.ruby.delayVCHist.vnet_0::total 2728 # delay histogram for vnet_0
system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1::samples 5879 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1::mean 0.073142 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1::stdev 0.375443 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1 | 5664 96.34% 96.34% | 0 0.00% 96.34% | 215 3.66% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1::total 5879 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1::samples 5883 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1::mean 0.072752 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1::stdev 0.374480 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1 | 5669 96.36% 96.36% | 0 0.00% 96.36% | 214 3.64% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1::total 5883 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2::samples 1041 # delay histogram for vnet_2
@ -590,34 +590,34 @@ system.ruby.delayVCHist.vnet_2 | 1041 100.00% 100.00% |
system.ruby.delayVCHist.vnet_2::total 1041 # delay histogram for vnet_2
system.ruby.LD.latency_hist_seqr::bucket_size 64
system.ruby.LD.latency_hist_seqr::max_bucket 639
system.ruby.LD.latency_hist_seqr::samples 1183
system.ruby.LD.latency_hist_seqr::mean 33.972105
system.ruby.LD.latency_hist_seqr::gmean 7.701642
system.ruby.LD.latency_hist_seqr::stdev 40.478944
system.ruby.LD.latency_hist_seqr | 802 67.79% 67.79% | 375 31.70% 99.49% | 0 0.00% 99.49% | 0 0.00% 99.49% | 2 0.17% 99.66% | 4 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.latency_hist_seqr::total 1183
system.ruby.LD.latency_hist_seqr::samples 1185
system.ruby.LD.latency_hist_seqr::mean 33.565401
system.ruby.LD.latency_hist_seqr::gmean 7.686795
system.ruby.LD.latency_hist_seqr::stdev 38.515936
system.ruby.LD.latency_hist_seqr | 803 67.76% 67.76% | 378 31.90% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 3 0.25% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.latency_hist_seqr::total 1185
system.ruby.LD.hit_latency_hist_seqr::bucket_size 1
system.ruby.LD.hit_latency_hist_seqr::max_bucket 9
system.ruby.LD.hit_latency_hist_seqr::samples 600
system.ruby.LD.hit_latency_hist_seqr::samples 601
system.ruby.LD.hit_latency_hist_seqr::mean 1
system.ruby.LD.hit_latency_hist_seqr::gmean 1
system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 600 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.hit_latency_hist_seqr::total 600
system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 601 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.hit_latency_hist_seqr::total 601
system.ruby.LD.miss_latency_hist_seqr::bucket_size 64
system.ruby.LD.miss_latency_hist_seqr::max_bucket 639
system.ruby.LD.miss_latency_hist_seqr::samples 583
system.ruby.LD.miss_latency_hist_seqr::mean 67.905660
system.ruby.LD.miss_latency_hist_seqr::gmean 62.953372
system.ruby.LD.miss_latency_hist_seqr::stdev 32.457951
system.ruby.LD.miss_latency_hist_seqr | 202 34.65% 34.65% | 375 64.32% 98.97% | 0 0.00% 98.97% | 0 0.00% 98.97% | 2 0.34% 99.31% | 4 0.69% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.miss_latency_hist_seqr::total 583
system.ruby.LD.miss_latency_hist_seqr::samples 584
system.ruby.LD.miss_latency_hist_seqr::mean 67.078767
system.ruby.LD.miss_latency_hist_seqr::gmean 62.700967
system.ruby.LD.miss_latency_hist_seqr::stdev 28.185747
system.ruby.LD.miss_latency_hist_seqr | 202 34.59% 34.59% | 378 64.73% 99.32% | 0 0.00% 99.32% | 0 0.00% 99.32% | 3 0.51% 99.83% | 1 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.miss_latency_hist_seqr::total 584
system.ruby.ST.latency_hist_seqr::bucket_size 64
system.ruby.ST.latency_hist_seqr::max_bucket 639
system.ruby.ST.latency_hist_seqr::samples 865
system.ruby.ST.latency_hist_seqr::mean 15.273988
system.ruby.ST.latency_hist_seqr::gmean 2.701326
system.ruby.ST.latency_hist_seqr::stdev 28.276128
system.ruby.ST.latency_hist_seqr | 773 89.36% 89.36% | 91 10.52% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 1 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.latency_hist_seqr::mean 15.551445
system.ruby.ST.latency_hist_seqr::gmean 2.706248
system.ruby.ST.latency_hist_seqr::stdev 29.831548
system.ruby.ST.latency_hist_seqr | 773 89.36% 89.36% | 90 10.40% 99.77% | 0 0.00% 99.77% | 0 0.00% 99.77% | 1 0.12% 99.88% | 1 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.latency_hist_seqr::total 865
system.ruby.ST.hit_latency_hist_seqr::bucket_size 1
system.ruby.ST.hit_latency_hist_seqr::max_bucket 9
@ -629,53 +629,53 @@ system.ruby.ST.hit_latency_hist_seqr::total 649
system.ruby.ST.miss_latency_hist_seqr::bucket_size 64
system.ruby.ST.miss_latency_hist_seqr::max_bucket 639
system.ruby.ST.miss_latency_hist_seqr::samples 216
system.ruby.ST.miss_latency_hist_seqr::mean 58.162037
system.ruby.ST.miss_latency_hist_seqr::gmean 53.494090
system.ruby.ST.miss_latency_hist_seqr::stdev 27.387260
system.ruby.ST.miss_latency_hist_seqr | 124 57.41% 57.41% | 91 42.13% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 1 0.46% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.miss_latency_hist_seqr::mean 59.273148
system.ruby.ST.miss_latency_hist_seqr::gmean 53.885554
system.ruby.ST.miss_latency_hist_seqr::stdev 31.884011
system.ruby.ST.miss_latency_hist_seqr | 124 57.41% 57.41% | 90 41.67% 99.07% | 0 0.00% 99.07% | 0 0.00% 99.07% | 1 0.46% 99.54% | 1 0.46% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.miss_latency_hist_seqr::total 216
system.ruby.IFETCH.latency_hist_seqr::bucket_size 64
system.ruby.IFETCH.latency_hist_seqr::max_bucket 639
system.ruby.IFETCH.latency_hist_seqr::samples 6400
system.ruby.IFETCH.latency_hist_seqr::mean 9.314219
system.ruby.IFETCH.latency_hist_seqr::gmean 1.595263
system.ruby.IFETCH.latency_hist_seqr::stdev 25.608064
system.ruby.IFETCH.latency_hist_seqr | 5714 89.28% 89.28% | 674 10.53% 99.81% | 4 0.06% 99.88% | 1 0.02% 99.89% | 3 0.05% 99.94% | 4 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.latency_hist_seqr::total 6400
system.ruby.IFETCH.latency_hist_seqr::samples 6413
system.ruby.IFETCH.latency_hist_seqr::mean 9.331826
system.ruby.IFETCH.latency_hist_seqr::gmean 1.594079
system.ruby.IFETCH.latency_hist_seqr::stdev 25.833878
system.ruby.IFETCH.latency_hist_seqr | 5727 89.30% 89.30% | 673 10.49% 99.80% | 4 0.06% 99.86% | 1 0.02% 99.88% | 4 0.06% 99.94% | 4 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.latency_hist_seqr::total 6413
system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1
system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9
system.ruby.IFETCH.hit_latency_hist_seqr::samples 5709
system.ruby.IFETCH.hit_latency_hist_seqr::samples 5722
system.ruby.IFETCH.hit_latency_hist_seqr::mean 1
system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1
system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 5709 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.hit_latency_hist_seqr::total 5709
system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 5722 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.hit_latency_hist_seqr::total 5722
system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64
system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639
system.ruby.IFETCH.miss_latency_hist_seqr::samples 691
system.ruby.IFETCH.miss_latency_hist_seqr::mean 78.005789
system.ruby.IFETCH.miss_latency_hist_seqr::gmean 75.617268
system.ruby.IFETCH.miss_latency_hist_seqr::stdev 28.004761
system.ruby.IFETCH.miss_latency_hist_seqr | 5 0.72% 0.72% | 674 97.54% 98.26% | 4 0.58% 98.84% | 1 0.14% 98.99% | 3 0.43% 99.42% | 4 0.58% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.miss_latency_hist_seqr::mean 78.325615
system.ruby.IFETCH.miss_latency_hist_seqr::gmean 75.760449
system.ruby.IFETCH.miss_latency_hist_seqr::stdev 29.311514
system.ruby.IFETCH.miss_latency_hist_seqr | 5 0.72% 0.72% | 673 97.40% 98.12% | 4 0.58% 98.70% | 1 0.14% 98.84% | 4 0.58% 99.42% | 4 0.58% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.miss_latency_hist_seqr::total 691
system.ruby.Directory_Controller.Fetch 1460 0.00% 0.00%
system.ruby.Directory_Controller.Fetch 1461 0.00% 0.00%
system.ruby.Directory_Controller.Data 277 0.00% 0.00%
system.ruby.Directory_Controller.Memory_Data 1460 0.00% 0.00%
system.ruby.Directory_Controller.Memory_Data 1461 0.00% 0.00%
system.ruby.Directory_Controller.Memory_Ack 277 0.00% 0.00%
system.ruby.Directory_Controller.CleanReplacement 1175 0.00% 0.00%
system.ruby.Directory_Controller.I.Fetch 1460 0.00% 0.00%
system.ruby.Directory_Controller.CleanReplacement 1176 0.00% 0.00%
system.ruby.Directory_Controller.I.Fetch 1461 0.00% 0.00%
system.ruby.Directory_Controller.M.Data 277 0.00% 0.00%
system.ruby.Directory_Controller.M.CleanReplacement 1175 0.00% 0.00%
system.ruby.Directory_Controller.IM.Memory_Data 1460 0.00% 0.00%
system.ruby.Directory_Controller.M.CleanReplacement 1176 0.00% 0.00%
system.ruby.Directory_Controller.IM.Memory_Data 1461 0.00% 0.00%
system.ruby.Directory_Controller.MI.Memory_Ack 277 0.00% 0.00%
system.ruby.L1Cache_Controller.Load 1183 0.00% 0.00%
system.ruby.L1Cache_Controller.Ifetch 6400 0.00% 0.00%
system.ruby.L1Cache_Controller.Load 1185 0.00% 0.00%
system.ruby.L1Cache_Controller.Ifetch 6413 0.00% 0.00%
system.ruby.L1Cache_Controller.Store 865 0.00% 0.00%
system.ruby.L1Cache_Controller.Inv 1041 0.00% 0.00%
system.ruby.L1Cache_Controller.L1_Replacement 1354 0.00% 0.00%
system.ruby.L1Cache_Controller.Data_Exclusive 583 0.00% 0.00%
system.ruby.L1Cache_Controller.L1_Replacement 1355 0.00% 0.00%
system.ruby.L1Cache_Controller.Data_Exclusive 584 0.00% 0.00%
system.ruby.L1Cache_Controller.Data_all_Acks 907 0.00% 0.00%
system.ruby.L1Cache_Controller.WB_Ack 436 0.00% 0.00%
system.ruby.L1Cache_Controller.NP.Load 525 0.00% 0.00%
system.ruby.L1Cache_Controller.WB_Ack 437 0.00% 0.00%
system.ruby.L1Cache_Controller.NP.Load 526 0.00% 0.00%
system.ruby.L1Cache_Controller.NP.Ifetch 646 0.00% 0.00%
system.ruby.L1Cache_Controller.NP.Store 191 0.00% 0.00%
system.ruby.L1Cache_Controller.NP.Inv 356 0.00% 0.00%
@ -683,53 +683,53 @@ system.ruby.L1Cache_Controller.I.Load 58 0.00% 0.00%
system.ruby.L1Cache_Controller.I.Ifetch 45 0.00% 0.00%
system.ruby.L1Cache_Controller.I.Store 25 0.00% 0.00%
system.ruby.L1Cache_Controller.I.L1_Replacement 556 0.00% 0.00%
system.ruby.L1Cache_Controller.S.Ifetch 5709 0.00% 0.00%
system.ruby.L1Cache_Controller.S.Ifetch 5722 0.00% 0.00%
system.ruby.L1Cache_Controller.S.Inv 325 0.00% 0.00%
system.ruby.L1Cache_Controller.S.L1_Replacement 362 0.00% 0.00%
system.ruby.L1Cache_Controller.E.Load 452 0.00% 0.00%
system.ruby.L1Cache_Controller.E.Load 453 0.00% 0.00%
system.ruby.L1Cache_Controller.E.Store 71 0.00% 0.00%
system.ruby.L1Cache_Controller.E.Inv 219 0.00% 0.00%
system.ruby.L1Cache_Controller.E.L1_Replacement 291 0.00% 0.00%
system.ruby.L1Cache_Controller.E.L1_Replacement 292 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Load 148 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Store 578 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Inv 141 0.00% 0.00%
system.ruby.L1Cache_Controller.M.L1_Replacement 145 0.00% 0.00%
system.ruby.L1Cache_Controller.IS.Data_Exclusive 583 0.00% 0.00%
system.ruby.L1Cache_Controller.IS.Data_Exclusive 584 0.00% 0.00%
system.ruby.L1Cache_Controller.IS.Data_all_Acks 691 0.00% 0.00%
system.ruby.L1Cache_Controller.IM.Data_all_Acks 216 0.00% 0.00%
system.ruby.L1Cache_Controller.M_I.WB_Ack 436 0.00% 0.00%
system.ruby.L1Cache_Controller.M_I.WB_Ack 437 0.00% 0.00%
system.ruby.L2Cache_Controller.L1_GET_INSTR 691 0.00% 0.00%
system.ruby.L2Cache_Controller.L1_GETS 583 0.00% 0.00%
system.ruby.L2Cache_Controller.L1_GETS 584 0.00% 0.00%
system.ruby.L2Cache_Controller.L1_GETX 216 0.00% 0.00%
system.ruby.L2Cache_Controller.L1_PUTX 436 0.00% 0.00%
system.ruby.L2Cache_Controller.L1_PUTX 437 0.00% 0.00%
system.ruby.L2Cache_Controller.L2_Replacement 142 0.00% 0.00%
system.ruby.L2Cache_Controller.L2_Replacement_clean 1310 0.00% 0.00%
system.ruby.L2Cache_Controller.Mem_Data 1460 0.00% 0.00%
system.ruby.L2Cache_Controller.Mem_Ack 1452 0.00% 0.00%
system.ruby.L2Cache_Controller.L2_Replacement_clean 1311 0.00% 0.00%
system.ruby.L2Cache_Controller.Mem_Data 1461 0.00% 0.00%
system.ruby.L2Cache_Controller.Mem_Ack 1453 0.00% 0.00%
system.ruby.L2Cache_Controller.WB_Data 141 0.00% 0.00%
system.ruby.L2Cache_Controller.Ack_all 900 0.00% 0.00%
system.ruby.L2Cache_Controller.Exclusive_Unblock 799 0.00% 0.00%
system.ruby.L2Cache_Controller.Exclusive_Unblock 800 0.00% 0.00%
system.ruby.L2Cache_Controller.NP.L1_GET_INSTR 686 0.00% 0.00%
system.ruby.L2Cache_Controller.NP.L1_GETS 570 0.00% 0.00%
system.ruby.L2Cache_Controller.NP.L1_GETS 571 0.00% 0.00%
system.ruby.L2Cache_Controller.NP.L1_GETX 204 0.00% 0.00%
system.ruby.L2Cache_Controller.SS.L1_GET_INSTR 5 0.00% 0.00%
system.ruby.L2Cache_Controller.SS.L2_Replacement_clean 681 0.00% 0.00%
system.ruby.L2Cache_Controller.M.L1_GETS 13 0.00% 0.00%
system.ruby.L2Cache_Controller.M.L1_GETX 12 0.00% 0.00%
system.ruby.L2Cache_Controller.M.L2_Replacement 134 0.00% 0.00%
system.ruby.L2Cache_Controller.M.L2_Replacement_clean 277 0.00% 0.00%
system.ruby.L2Cache_Controller.MT.L1_PUTX 436 0.00% 0.00%
system.ruby.L2Cache_Controller.M.L2_Replacement_clean 278 0.00% 0.00%
system.ruby.L2Cache_Controller.MT.L1_PUTX 437 0.00% 0.00%
system.ruby.L2Cache_Controller.MT.L2_Replacement 8 0.00% 0.00%
system.ruby.L2Cache_Controller.MT.L2_Replacement_clean 352 0.00% 0.00%
system.ruby.L2Cache_Controller.M_I.Mem_Ack 1452 0.00% 0.00%
system.ruby.L2Cache_Controller.M_I.Mem_Ack 1453 0.00% 0.00%
system.ruby.L2Cache_Controller.MT_I.WB_Data 6 0.00% 0.00%
system.ruby.L2Cache_Controller.MT_I.Ack_all 2 0.00% 0.00%
system.ruby.L2Cache_Controller.MCT_I.WB_Data 135 0.00% 0.00%
system.ruby.L2Cache_Controller.MCT_I.Ack_all 217 0.00% 0.00%
system.ruby.L2Cache_Controller.I_I.Ack_all 681 0.00% 0.00%
system.ruby.L2Cache_Controller.ISS.Mem_Data 570 0.00% 0.00%
system.ruby.L2Cache_Controller.ISS.Mem_Data 571 0.00% 0.00%
system.ruby.L2Cache_Controller.IS.Mem_Data 686 0.00% 0.00%
system.ruby.L2Cache_Controller.IM.Mem_Data 204 0.00% 0.00%
system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 799 0.00% 0.00%
system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 800 0.00% 0.00%
---------- End Simulation Statistics ----------

2
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
View file

@ -120,7 +120,7 @@ env=
errout=cerr
euid=100
eventq_index=0
executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
kvmInSE=false

12
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout
View file

@ -1,13 +1,15 @@
Redirecting stdout to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout
Redirecting stderr to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 21 2016 14:06:59
gem5 started Jan 21 2016 14:07:35
gem5 executing on zizzer, pid 50076
command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory
gem5 compiled Mar 14 2016 22:01:23
gem5 started Mar 14 2016 22:02:29
gem5 executing on phenom, pid 29128
command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
Exiting @ tick 108694 because target called exit()
Exiting @ tick 108878 because target called exit()

713
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
View file

@ -1,43 +1,43 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000109 # Number of seconds simulated
sim_ticks 108694 # Number of ticks simulated
final_tick 108694 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 108878 # Number of ticks simulated
final_tick 108878 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_inst_rate 71872 # Simulator instruction rate (inst/s)
host_op_rate 71865 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1222276 # Simulator tick rate (ticks/s)
host_mem_usage 417856 # Number of bytes of host memory used
host_seconds 0.09 # Real time elapsed on the host
sim_insts 6390 # Number of instructions simulated
sim_ops 6390 # Number of ops (including micro ops) simulated
host_inst_rate 17471 # Simulator instruction rate (inst/s)
host_op_rate 17470 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 297052 # Simulator tick rate (ticks/s)
host_mem_usage 393472 # Number of bytes of host memory used
host_seconds 0.37 # Real time elapsed on the host
sim_insts 6403 # Number of instructions simulated
sim_ops 6403 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 75648 # Number of bytes read from this memory
system.mem_ctrls.bytes_read::total 75648 # Number of bytes read from this memory
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 75712 # Number of bytes read from this memory
system.mem_ctrls.bytes_read::total 75712 # Number of bytes read from this memory
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 12416 # Number of bytes written to this memory
system.mem_ctrls.bytes_written::total 12416 # Number of bytes written to this memory
system.mem_ctrls.num_reads::ruby.dir_cntrl0 1182 # Number of read requests responded to by this memory
system.mem_ctrls.num_reads::total 1182 # Number of read requests responded to by this memory
system.mem_ctrls.num_reads::ruby.dir_cntrl0 1183 # Number of read requests responded to by this memory
system.mem_ctrls.num_reads::total 1183 # Number of read requests responded to by this memory
system.mem_ctrls.num_writes::ruby.dir_cntrl0 194 # Number of write requests responded to by this memory
system.mem_ctrls.num_writes::total 194 # Number of write requests responded to by this memory
system.mem_ctrls.bw_read::ruby.dir_cntrl0 695972179 # Total read bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_read::total 695972179 # Total read bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_write::ruby.dir_cntrl0 114228936 # Write bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_write::total 114228936 # Write bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_total::ruby.dir_cntrl0 810201115 # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.bw_total::total 810201115 # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.readReqs 1182 # Number of read requests accepted
system.mem_ctrls.bw_read::ruby.dir_cntrl0 695383824 # Total read bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_read::total 695383824 # Total read bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_write::ruby.dir_cntrl0 114035893 # Write bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_write::total 114035893 # Write bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_total::ruby.dir_cntrl0 809419717 # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.bw_total::total 809419717 # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.readReqs 1183 # Number of read requests accepted
system.mem_ctrls.writeReqs 194 # Number of write requests accepted
system.mem_ctrls.readBursts 1182 # Number of DRAM read bursts, including those serviced by the write queue
system.mem_ctrls.readBursts 1183 # Number of DRAM read bursts, including those serviced by the write queue
system.mem_ctrls.writeBursts 194 # Number of DRAM write bursts, including those merged in the write queue
system.mem_ctrls.bytesReadDRAM 64448 # Total number of bytes read from DRAM
system.mem_ctrls.bytesReadWrQ 11200 # Total number of bytes read from write queue
system.mem_ctrls.bytesWritten 5440 # Total number of bytes written to DRAM
system.mem_ctrls.bytesReadSys 75648 # Total read bytes from the system interface side
system.mem_ctrls.bytesReadDRAM 64576 # Total number of bytes read from DRAM
system.mem_ctrls.bytesReadWrQ 11136 # Total number of bytes read from write queue
system.mem_ctrls.bytesWritten 5504 # Total number of bytes written to DRAM
system.mem_ctrls.bytesReadSys 75712 # Total read bytes from the system interface side
system.mem_ctrls.bytesWrittenSys 12416 # Total written bytes from the system interface side
system.mem_ctrls.servicedByWrQ 175 # Number of DRAM read bursts serviced by the write queue
system.mem_ctrls.mergedWrBursts 82 # Number of DRAM write bursts merged with an existing one
system.mem_ctrls.servicedByWrQ 174 # Number of DRAM read bursts serviced by the write queue
system.mem_ctrls.mergedWrBursts 81 # Number of DRAM write bursts merged with an existing one
system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.mem_ctrls.perBankRdBursts::0 83 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::1 51 # Per bank write bursts
@ -53,13 +53,13 @@ system.mem_ctrls.perBankRdBursts::10 56 # Pe
system.mem_ctrls.perBankRdBursts::11 51 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::12 21 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::13 365 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::14 66 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::15 40 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::14 67 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::15 41 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::4 17 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::4 18 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::5 6 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts
@ -73,14 +73,14 @@ system.mem_ctrls.perBankWrBursts::14 41 # Pe
system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
system.mem_ctrls.totGap 108642 # Total gap between requests
system.mem_ctrls.totGap 108826 # Total gap between requests
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::6 1182 # Read request sizes (log2)
system.mem_ctrls.readPktSize::6 1183 # Read request sizes (log2)
system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
@ -88,7 +88,7 @@ system.mem_ctrls.writePktSize::3 0 # Wr
system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::6 194 # Write request sizes (log2)
system.mem_ctrls.rdQLenPdf::0 1007 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::0 1009 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
@ -135,18 +135,18 @@ system.mem_ctrls.wrQLenPdf::11 1 # Wh
system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::15 3 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::15 4 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::16 4 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::17 5 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::17 4 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::18 6 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::19 6 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::20 7 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::20 6 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::21 6 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::22 6 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::23 6 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::23 7 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::24 6 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::25 6 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::26 6 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::26 7 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::27 5 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::28 5 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::29 5 # What write queue length does an incoming req see
@ -184,109 +184,108 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh
system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.mem_ctrls.bytesPerActivate::samples 202 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::mean 335.524752 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::gmean 204.886741 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::stdev 324.305016 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::0-127 65 32.18% 32.18% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::128-255 47 23.27% 55.45% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::256-383 21 10.40% 65.84% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::384-511 14 6.93% 72.77% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::512-639 12 5.94% 78.71% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::640-767 11 5.45% 84.16% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::768-895 6 2.97% 87.13% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::896-1023 5 2.48% 89.60% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::1024-1151 21 10.40% 100.00% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::total 202 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::samples 203 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::mean 334.817734 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::gmean 202.715946 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::stdev 328.878595 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::0-127 65 32.02% 32.02% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::128-255 47 23.15% 55.17% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::256-383 25 12.32% 67.49% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::384-511 11 5.42% 72.91% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::512-639 11 5.42% 78.33% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::640-767 10 4.93% 83.25% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::768-895 5 2.46% 85.71% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::896-1023 8 3.94% 89.66% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::1024-1151 21 10.34% 100.00% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::total 203 # Bytes accessed per row activation
system.mem_ctrls.rdPerTurnAround::samples 5 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::mean 141.200000 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::gmean 107.481731 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::stdev 78.180560 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::mean 138.600000 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::gmean 101.703151 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::stdev 85.219129 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::16-23 1 20.00% 20.00% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::128-135 1 20.00% 40.00% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::136-143 1 20.00% 60.00% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::80-87 1 20.00% 40.00% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::168-175 1 20.00% 60.00% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::192-199 1 20.00% 80.00% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::216-223 1 20.00% 100.00% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::total 5 # Reads before turning the bus around for writes
system.mem_ctrls.wrPerTurnAround::samples 5 # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::mean 17 # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::gmean 16.976446 # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::stdev 1 # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::mean 17.200000 # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::gmean 17.171629 # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::stdev 1.095445 # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::16 2 40.00% 40.00% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::17 1 20.00% 60.00% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::18 2 40.00% 100.00% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::18 3 60.00% 100.00% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::total 5 # Writes before turning the bus around for reads
system.mem_ctrls.totQLat 6988 # Total ticks spent queuing
system.mem_ctrls.totMemAccLat 26121 # Total ticks spent from burst creation until serviced by the DRAM
system.mem_ctrls.totBusLat 5035 # Total ticks spent in databus transfers
system.mem_ctrls.avgQLat 6.94 # Average queueing delay per DRAM burst
system.mem_ctrls.totQLat 7036 # Total ticks spent queuing
system.mem_ctrls.totMemAccLat 26207 # Total ticks spent from burst creation until serviced by the DRAM
system.mem_ctrls.totBusLat 5045 # Total ticks spent in databus transfers
system.mem_ctrls.avgQLat 6.97 # Average queueing delay per DRAM burst
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
system.mem_ctrls.avgMemAccLat 25.94 # Average memory access latency per DRAM burst
system.mem_ctrls.avgRdBW 592.93 # Average DRAM read bandwidth in MiByte/s
system.mem_ctrls.avgWrBW 50.05 # Average achieved write bandwidth in MiByte/s
system.mem_ctrls.avgRdBWSys 695.97 # Average system read bandwidth in MiByte/s
system.mem_ctrls.avgWrBWSys 114.23 # Average system write bandwidth in MiByte/s
system.mem_ctrls.avgMemAccLat 25.97 # Average memory access latency per DRAM burst
system.mem_ctrls.avgRdBW 593.10 # Average DRAM read bandwidth in MiByte/s
system.mem_ctrls.avgWrBW 50.55 # Average achieved write bandwidth in MiByte/s
system.mem_ctrls.avgRdBWSys 695.38 # Average system read bandwidth in MiByte/s
system.mem_ctrls.avgWrBWSys 114.04 # Average system write bandwidth in MiByte/s
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.mem_ctrls.busUtil 5.02 # Data bus utilization in percentage
system.mem_ctrls.busUtil 5.03 # Data bus utilization in percentage
system.mem_ctrls.busUtilRead 4.63 # Data bus utilization in percentage for reads
system.mem_ctrls.busUtilWrite 0.39 # Data bus utilization in percentage for writes
system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing
system.mem_ctrls.avgWrQLen 21.56 # Average write queue length when enqueuing
system.mem_ctrls.readRowHits 807 # Number of row buffer hits during reads
system.mem_ctrls.writeRowHits 77 # Number of row buffer hits during writes
system.mem_ctrls.readRowHitRate 80.14 # Row buffer hit rate for reads
system.mem_ctrls.writeRowHitRate 68.75 # Row buffer hit rate for writes
system.mem_ctrls.avgGap 78.95 # Average gap between requests
system.mem_ctrls.pageHitRate 79.00 # Row buffer hit rate, read and write combined
system.mem_ctrls.avgWrQLen 21.05 # Average write queue length when enqueuing
system.mem_ctrls.readRowHits 806 # Number of row buffer hits during reads
system.mem_ctrls.writeRowHits 80 # Number of row buffer hits during writes
system.mem_ctrls.readRowHitRate 79.88 # Row buffer hit rate for reads
system.mem_ctrls.writeRowHitRate 70.80 # Row buffer hit rate for writes
system.mem_ctrls.avgGap 79.03 # Average gap between requests
system.mem_ctrls.pageHitRate 78.97 # Row buffer hit rate, read and write combined
system.mem_ctrls_0.actEnergy 529200 # Energy for activate commands per rank (pJ)
system.mem_ctrls_0.preEnergy 294000 # Energy for precharge commands per rank (pJ)
system.mem_ctrls_0.readEnergy 5004480 # Energy for read commands per rank (pJ)
system.mem_ctrls_0.writeEnergy 238464 # Energy for write commands per rank (pJ)
system.mem_ctrls_0.writeEnergy 248832 # Energy for write commands per rank (pJ)
system.mem_ctrls_0.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ)
system.mem_ctrls_0.actBackEnergy 62170812 # Energy for active background per rank (pJ)
system.mem_ctrls_0.preBackEnergy 6351000 # Energy for precharge background per rank (pJ)
system.mem_ctrls_0.totalEnergy 81199236 # Total energy per rank (pJ)
system.mem_ctrls_0.averagePower 800.165908 # Core power per rank (mW)
system.mem_ctrls_0.memoryStateTime::IDLE 15769 # Time in different power states
system.mem_ctrls_0.actBackEnergy 61961508 # Energy for active background per rank (pJ)
system.mem_ctrls_0.preBackEnergy 6534600 # Energy for precharge background per rank (pJ)
system.mem_ctrls_0.totalEnergy 81183900 # Total energy per rank (pJ)
system.mem_ctrls_0.averagePower 800.014782 # Core power per rank (mW)
system.mem_ctrls_0.memoryStateTime::IDLE 16245 # Time in different power states
system.mem_ctrls_0.memoryStateTime::REF 3380 # Time in different power states
system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.mem_ctrls_0.memoryStateTime::ACT 87863 # Time in different power states
system.mem_ctrls_0.memoryStateTime::ACT 87571 # Time in different power states
system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.mem_ctrls_1.actEnergy 907200 # Energy for activate commands per rank (pJ)
system.mem_ctrls_1.preEnergy 504000 # Energy for precharge commands per rank (pJ)
system.mem_ctrls_1.readEnergy 6764160 # Energy for read commands per rank (pJ)
system.mem_ctrls_1.writeEnergy 642816 # Energy for write commands per rank (pJ)
system.mem_ctrls_1.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ)
system.mem_ctrls_1.actBackEnergy 67286448 # Energy for active background per rank (pJ)
system.mem_ctrls_1.preBackEnergy 1863600 # Energy for precharge background per rank (pJ)
system.mem_ctrls_1.totalEnergy 84579504 # Total energy per rank (pJ)
system.mem_ctrls_1.averagePower 833.476261 # Core power per rank (mW)
system.mem_ctrls_1.memoryStateTime::IDLE 2630 # Time in different power states
system.mem_ctrls_1.actBackEnergy 67902048 # Energy for active background per rank (pJ)
system.mem_ctrls_1.preBackEnergy 1323600 # Energy for precharge background per rank (pJ)
system.mem_ctrls_1.totalEnergy 84655104 # Total energy per rank (pJ)
system.mem_ctrls_1.averagePower 834.221250 # Core power per rank (mW)
system.mem_ctrls_1.memoryStateTime::IDLE 1730 # Time in different power states
system.mem_ctrls_1.memoryStateTime::REF 3380 # Time in different power states
system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT 95482 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT 96382 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.clk_domain.clock 1 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 1183 # DTB read hits
system.cpu.dtb.read_hits 1185 # DTB read hits
system.cpu.dtb.read_misses 7 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 1190 # DTB read accesses
system.cpu.dtb.read_accesses 1192 # DTB read accesses
system.cpu.dtb.write_hits 865 # DTB write hits
system.cpu.dtb.write_misses 3 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 868 # DTB write accesses
system.cpu.dtb.data_hits 2048 # DTB hits
system.cpu.dtb.data_hits 2050 # DTB hits
system.cpu.dtb.data_misses 10 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 2058 # DTB accesses
system.cpu.itb.fetch_hits 6401 # ITB hits
system.cpu.dtb.data_accesses 2060 # DTB accesses
system.cpu.itb.fetch_hits 6414 # ITB hits
system.cpu.itb.fetch_misses 17 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 6418 # ITB accesses
system.cpu.itb.fetch_accesses 6431 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@ -300,292 +299,292 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
system.cpu.numCycles 108694 # number of cpu cycles simulated
system.cpu.numCycles 108878 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 6390 # Number of instructions committed
system.cpu.committedOps 6390 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses
system.cpu.committedInsts 6403 # Number of instructions committed
system.cpu.committedOps 6403 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 6329 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
system.cpu.num_func_calls 251 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls
system.cpu.num_int_insts 6317 # number of integer instructions
system.cpu.num_conditional_control_insts 754 # number of instructions that are conditional controls
system.cpu.num_int_insts 6329 # number of integer instructions
system.cpu.num_fp_insts 10 # number of float instructions
system.cpu.num_int_register_reads 8285 # number of times the integer registers were read
system.cpu.num_int_register_writes 4568 # number of times the integer registers were written
system.cpu.num_int_register_reads 8297 # number of times the integer registers were read
system.cpu.num_int_register_writes 4575 # number of times the integer registers were written
system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
system.cpu.num_mem_refs 2058 # number of memory refs
system.cpu.num_load_insts 1190 # Number of load instructions
system.cpu.num_mem_refs 2060 # number of memory refs
system.cpu.num_load_insts 1192 # Number of load instructions
system.cpu.num_store_insts 868 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 108694 # Number of busy cycles
system.cpu.num_busy_cycles 108878 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.Branches 1050 # Number of branches fetched
system.cpu.Branches 1056 # Number of branches fetched
system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction
system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction
system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction
system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction
system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction
system.cpu.op_class::IntAlu 4331 67.53% 67.83% # Class of executed instruction
system.cpu.op_class::IntMult 1 0.02% 67.85% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 67.85% # Class of executed instruction
system.cpu.op_class::FloatAdd 2 0.03% 67.88% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::MemRead 1192 18.59% 86.46% # Class of executed instruction
system.cpu.op_class::MemWrite 868 13.54% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 6400 # Class of executed instruction
system.cpu.op_class::total 6413 # Class of executed instruction
system.ruby.clk_domain.clock 1 # Clock period in ticks
system.ruby.outstanding_req_hist_seqr::bucket_size 1
system.ruby.outstanding_req_hist_seqr::max_bucket 9
system.ruby.outstanding_req_hist_seqr::samples 8449
system.ruby.outstanding_req_hist_seqr::samples 8464
system.ruby.outstanding_req_hist_seqr::mean 1
system.ruby.outstanding_req_hist_seqr::gmean 1
system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 8449 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.outstanding_req_hist_seqr::total 8449
system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 8464 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.outstanding_req_hist_seqr::total 8464
system.ruby.latency_hist_seqr::bucket_size 64
system.ruby.latency_hist_seqr::max_bucket 639
system.ruby.latency_hist_seqr::samples 8448
system.ruby.latency_hist_seqr::mean 11.866241
system.ruby.latency_hist_seqr::gmean 1.974485
system.ruby.latency_hist_seqr::stdev 27.814086
system.ruby.latency_hist_seqr | 7440 88.07% 88.07% | 991 11.73% 99.80% | 4 0.05% 99.85% | 1 0.01% 99.86% | 9 0.11% 99.96% | 3 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.latency_hist_seqr::total 8448
system.ruby.latency_hist_seqr::samples 8463
system.ruby.latency_hist_seqr::mean 11.865178
system.ruby.latency_hist_seqr::gmean 1.973283
system.ruby.latency_hist_seqr::stdev 27.863065
system.ruby.latency_hist_seqr | 7453 88.07% 88.07% | 995 11.76% 99.82% | 2 0.02% 99.85% | 0 0.00% 99.85% | 9 0.11% 99.95% | 4 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.latency_hist_seqr::total 8463
system.ruby.hit_latency_hist_seqr::bucket_size 1
system.ruby.hit_latency_hist_seqr::max_bucket 9
system.ruby.hit_latency_hist_seqr::samples 7027
system.ruby.hit_latency_hist_seqr::samples 7041
system.ruby.hit_latency_hist_seqr::mean 1
system.ruby.hit_latency_hist_seqr::gmean 1
system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 7027 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.hit_latency_hist_seqr::total 7027
system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 7041 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.hit_latency_hist_seqr::total 7041
system.ruby.miss_latency_hist_seqr::bucket_size 64
system.ruby.miss_latency_hist_seqr::max_bucket 639
system.ruby.miss_latency_hist_seqr::samples 1421
system.ruby.miss_latency_hist_seqr::mean 65.600985
system.ruby.miss_latency_hist_seqr::gmean 57.082853
system.ruby.miss_latency_hist_seqr::stdev 33.588801
system.ruby.miss_latency_hist_seqr | 413 29.06% 29.06% | 991 69.74% 98.80% | 4 0.28% 99.09% | 1 0.07% 99.16% | 9 0.63% 99.79% | 3 0.21% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.miss_latency_hist_seqr::total 1421
system.ruby.l1_cntrl0.L1Dcache.demand_hits 1273 # Number of cache demand hits
system.ruby.l1_cntrl0.L1Dcache.demand_misses 775 # Number of cache demand misses
system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2048 # Number of cache demand accesses
system.ruby.l1_cntrl0.L1Icache.demand_hits 5754 # Number of cache demand hits
system.ruby.miss_latency_hist_seqr::samples 1422
system.ruby.miss_latency_hist_seqr::mean 65.663854
system.ruby.miss_latency_hist_seqr::gmean 57.123275
system.ruby.miss_latency_hist_seqr::stdev 33.791401
system.ruby.miss_latency_hist_seqr | 412 28.97% 28.97% | 995 69.97% 98.95% | 2 0.14% 99.09% | 0 0.00% 99.09% | 9 0.63% 99.72% | 4 0.28% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.miss_latency_hist_seqr::total 1422
system.ruby.l1_cntrl0.L1Dcache.demand_hits 1274 # Number of cache demand hits
system.ruby.l1_cntrl0.L1Dcache.demand_misses 776 # Number of cache demand misses
system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2050 # Number of cache demand accesses
system.ruby.l1_cntrl0.L1Icache.demand_hits 5767 # Number of cache demand hits
system.ruby.l1_cntrl0.L1Icache.demand_misses 646 # Number of cache demand misses
system.ruby.l1_cntrl0.L1Icache.demand_accesses 6400 # Number of cache demand accesses
system.ruby.l1_cntrl0.L1Icache.demand_accesses 6413 # Number of cache demand accesses
system.ruby.l2_cntrl0.L2cache.demand_hits 239 # Number of cache demand hits
system.ruby.l2_cntrl0.L2cache.demand_misses 1182 # Number of cache demand misses
system.ruby.l2_cntrl0.L2cache.demand_accesses 1421 # Number of cache demand accesses
system.ruby.l2_cntrl0.L2cache.demand_misses 1183 # Number of cache demand misses
system.ruby.l2_cntrl0.L2cache.demand_accesses 1422 # Number of cache demand accesses
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
system.ruby.network.routers0.percent_links_utilized 6.936215
system.ruby.network.routers0.msg_count.Request_Control::0 1421
system.ruby.network.routers0.msg_count.Response_Data::2 1182
system.ruby.network.routers0.percent_links_utilized 6.929545
system.ruby.network.routers0.msg_count.Request_Control::0 1422
system.ruby.network.routers0.msg_count.Response_Data::2 1183
system.ruby.network.routers0.msg_count.ResponseL2hit_Data::2 239
system.ruby.network.routers0.msg_count.Writeback_Data::2 1308
system.ruby.network.routers0.msg_count.Writeback_Control::0 2708
system.ruby.network.routers0.msg_count.Unblock_Control::2 1467
system.ruby.network.routers0.msg_bytes.Request_Control::0 11368
system.ruby.network.routers0.msg_bytes.Response_Data::2 85104
system.ruby.network.routers0.msg_count.Writeback_Data::2 1309
system.ruby.network.routers0.msg_count.Writeback_Control::0 2710
system.ruby.network.routers0.msg_count.Unblock_Control::2 1468
system.ruby.network.routers0.msg_bytes.Request_Control::0 11376
system.ruby.network.routers0.msg_bytes.Response_Data::2 85176
system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::2 17208
system.ruby.network.routers0.msg_bytes.Writeback_Data::2 94176
system.ruby.network.routers0.msg_bytes.Writeback_Control::0 21664
system.ruby.network.routers0.msg_bytes.Unblock_Control::2 11736
system.ruby.network.routers1.percent_links_utilized 10.417548
system.ruby.network.routers1.msg_count.Request_Control::0 1421
system.ruby.network.routers1.msg_count.Request_Control::1 1182
system.ruby.network.routers1.msg_count.Response_Data::2 2364
system.ruby.network.routers0.msg_bytes.Writeback_Data::2 94248
system.ruby.network.routers0.msg_bytes.Writeback_Control::0 21680
system.ruby.network.routers0.msg_bytes.Unblock_Control::2 11744
system.ruby.network.routers1.percent_links_utilized 10.407520
system.ruby.network.routers1.msg_count.Request_Control::0 1422
system.ruby.network.routers1.msg_count.Request_Control::1 1183
system.ruby.network.routers1.msg_count.Response_Data::2 2366
system.ruby.network.routers1.msg_count.ResponseL2hit_Data::2 239
system.ruby.network.routers1.msg_count.Writeback_Data::2 1502
system.ruby.network.routers1.msg_count.Writeback_Control::0 2708
system.ruby.network.routers1.msg_count.Writeback_Data::2 1503
system.ruby.network.routers1.msg_count.Writeback_Control::0 2710
system.ruby.network.routers1.msg_count.Writeback_Control::1 388
system.ruby.network.routers1.msg_count.Unblock_Control::2 2649
system.ruby.network.routers1.msg_bytes.Request_Control::0 11368
system.ruby.network.routers1.msg_bytes.Request_Control::1 9456
system.ruby.network.routers1.msg_bytes.Response_Data::2 170208
system.ruby.network.routers1.msg_count.Unblock_Control::2 2651
system.ruby.network.routers1.msg_bytes.Request_Control::0 11376
system.ruby.network.routers1.msg_bytes.Request_Control::1 9464
system.ruby.network.routers1.msg_bytes.Response_Data::2 170352
system.ruby.network.routers1.msg_bytes.ResponseL2hit_Data::2 17208
system.ruby.network.routers1.msg_bytes.Writeback_Data::2 108144
system.ruby.network.routers1.msg_bytes.Writeback_Control::0 21664
system.ruby.network.routers1.msg_bytes.Writeback_Data::2 108216
system.ruby.network.routers1.msg_bytes.Writeback_Control::0 21680
system.ruby.network.routers1.msg_bytes.Writeback_Control::1 3104
system.ruby.network.routers1.msg_bytes.Unblock_Control::2 21192
system.ruby.network.routers2.percent_links_utilized 3.481333
system.ruby.network.routers2.msg_count.Request_Control::1 1182
system.ruby.network.routers2.msg_count.Response_Data::2 1182
system.ruby.network.routers1.msg_bytes.Unblock_Control::2 21208
system.ruby.network.routers2.percent_links_utilized 3.477975
system.ruby.network.routers2.msg_count.Request_Control::1 1183
system.ruby.network.routers2.msg_count.Response_Data::2 1183
system.ruby.network.routers2.msg_count.Writeback_Data::2 194
system.ruby.network.routers2.msg_count.Writeback_Control::1 388
system.ruby.network.routers2.msg_count.Unblock_Control::2 1182
system.ruby.network.routers2.msg_bytes.Request_Control::1 9456
system.ruby.network.routers2.msg_bytes.Response_Data::2 85104
system.ruby.network.routers2.msg_count.Unblock_Control::2 1183
system.ruby.network.routers2.msg_bytes.Request_Control::1 9464
system.ruby.network.routers2.msg_bytes.Response_Data::2 85176
system.ruby.network.routers2.msg_bytes.Writeback_Data::2 13968
system.ruby.network.routers2.msg_bytes.Writeback_Control::1 3104
system.ruby.network.routers2.msg_bytes.Unblock_Control::2 9456
system.ruby.network.routers3.percent_links_utilized 6.945032
system.ruby.network.routers3.msg_count.Request_Control::0 1421
system.ruby.network.routers3.msg_count.Request_Control::1 1182
system.ruby.network.routers3.msg_count.Response_Data::2 2364
system.ruby.network.routers2.msg_bytes.Unblock_Control::2 9464
system.ruby.network.routers3.percent_links_utilized 6.938347
system.ruby.network.routers3.msg_count.Request_Control::0 1422
system.ruby.network.routers3.msg_count.Request_Control::1 1183
system.ruby.network.routers3.msg_count.Response_Data::2 2366
system.ruby.network.routers3.msg_count.ResponseL2hit_Data::2 239
system.ruby.network.routers3.msg_count.Writeback_Data::2 1502
system.ruby.network.routers3.msg_count.Writeback_Control::0 2708
system.ruby.network.routers3.msg_count.Writeback_Data::2 1503
system.ruby.network.routers3.msg_count.Writeback_Control::0 2710
system.ruby.network.routers3.msg_count.Writeback_Control::1 388
system.ruby.network.routers3.msg_count.Unblock_Control::2 2649
system.ruby.network.routers3.msg_bytes.Request_Control::0 11368
system.ruby.network.routers3.msg_bytes.Request_Control::1 9456
system.ruby.network.routers3.msg_bytes.Response_Data::2 170208
system.ruby.network.routers3.msg_count.Unblock_Control::2 2651
system.ruby.network.routers3.msg_bytes.Request_Control::0 11376
system.ruby.network.routers3.msg_bytes.Request_Control::1 9464
system.ruby.network.routers3.msg_bytes.Response_Data::2 170352
system.ruby.network.routers3.msg_bytes.ResponseL2hit_Data::2 17208
system.ruby.network.routers3.msg_bytes.Writeback_Data::2 108144
system.ruby.network.routers3.msg_bytes.Writeback_Control::0 21664
system.ruby.network.routers3.msg_bytes.Writeback_Data::2 108216
system.ruby.network.routers3.msg_bytes.Writeback_Control::0 21680
system.ruby.network.routers3.msg_bytes.Writeback_Control::1 3104
system.ruby.network.routers3.msg_bytes.Unblock_Control::2 21192
system.ruby.network.msg_count.Request_Control 7809
system.ruby.network.msg_count.Response_Data 7092
system.ruby.network.routers3.msg_bytes.Unblock_Control::2 21208
system.ruby.network.msg_count.Request_Control 7815
system.ruby.network.msg_count.Response_Data 7098
system.ruby.network.msg_count.ResponseL2hit_Data 717
system.ruby.network.msg_count.Writeback_Data 4506
system.ruby.network.msg_count.Writeback_Control 9288
system.ruby.network.msg_count.Unblock_Control 7947
system.ruby.network.msg_byte.Request_Control 62472
system.ruby.network.msg_byte.Response_Data 510624
system.ruby.network.msg_count.Writeback_Data 4509
system.ruby.network.msg_count.Writeback_Control 9294
system.ruby.network.msg_count.Unblock_Control 7953
system.ruby.network.msg_byte.Request_Control 62520
system.ruby.network.msg_byte.Response_Data 511056
system.ruby.network.msg_byte.ResponseL2hit_Data 51624
system.ruby.network.msg_byte.Writeback_Data 324432
system.ruby.network.msg_byte.Writeback_Control 74304
system.ruby.network.msg_byte.Unblock_Control 63576
system.ruby.network.routers0.throttle0.link_utilization 6.505879
system.ruby.network.routers0.throttle0.msg_count.Response_Data::2 1182
system.ruby.network.msg_byte.Writeback_Data 324648
system.ruby.network.msg_byte.Writeback_Control 74352
system.ruby.network.msg_byte.Unblock_Control 63624
system.ruby.network.routers0.throttle0.link_utilization 6.499476
system.ruby.network.routers0.throttle0.msg_count.Response_Data::2 1183
system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::2 239
system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::0 1354
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::2 85104
system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::0 1355
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::2 85176
system.ruby.network.routers0.throttle0.msg_bytes.ResponseL2hit_Data::2 17208
system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::0 10832
system.ruby.network.routers0.throttle1.link_utilization 7.366552
system.ruby.network.routers0.throttle1.msg_count.Request_Control::0 1421
system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::2 1308
system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 1354
system.ruby.network.routers0.throttle1.msg_count.Unblock_Control::2 1467
system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::0 11368
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::2 94176
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 10832
system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::2 11736
system.ruby.network.routers1.throttle0.link_utilization 12.349348
system.ruby.network.routers1.throttle0.msg_count.Request_Control::0 1421
system.ruby.network.routers1.throttle0.msg_count.Response_Data::2 1182
system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::2 1308
system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::0 1354
system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::0 10840
system.ruby.network.routers0.throttle1.link_utilization 7.359614
system.ruby.network.routers0.throttle1.msg_count.Request_Control::0 1422
system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::2 1309
system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 1355
system.ruby.network.routers0.throttle1.msg_count.Unblock_Control::2 1468
system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::0 11376
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::2 94248
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 10840
system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::2 11744
system.ruby.network.routers1.throttle0.link_utilization 12.338122
system.ruby.network.routers1.throttle0.msg_count.Request_Control::0 1422
system.ruby.network.routers1.throttle0.msg_count.Response_Data::2 1183
system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::2 1309
system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::0 1355
system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::1 194
system.ruby.network.routers1.throttle0.msg_count.Unblock_Control::2 1467
system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::0 11368
system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::2 85104
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::2 94176
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0 10832
system.ruby.network.routers1.throttle0.msg_count.Unblock_Control::2 1468
system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::0 11376
system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::2 85176
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::2 94248
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0 10840
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::1 1552
system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::2 11736
system.ruby.network.routers1.throttle1.link_utilization 8.485749
system.ruby.network.routers1.throttle1.msg_count.Request_Control::1 1182
system.ruby.network.routers1.throttle1.msg_count.Response_Data::2 1182
system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::2 11744
system.ruby.network.routers1.throttle1.link_utilization 8.476919
system.ruby.network.routers1.throttle1.msg_count.Request_Control::1 1183
system.ruby.network.routers1.throttle1.msg_count.Response_Data::2 1183
system.ruby.network.routers1.throttle1.msg_count.ResponseL2hit_Data::2 239
system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::2 194
system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::0 1354
system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::0 1355
system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::1 194
system.ruby.network.routers1.throttle1.msg_count.Unblock_Control::2 1182
system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::1 9456
system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::2 85104
system.ruby.network.routers1.throttle1.msg_count.Unblock_Control::2 1183
system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::1 9464
system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::2 85176
system.ruby.network.routers1.throttle1.msg_bytes.ResponseL2hit_Data::2 17208
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::2 13968
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::0 10832
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::0 10840
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::1 1552
system.ruby.network.routers1.throttle1.msg_bytes.Unblock_Control::2 9456
system.ruby.network.routers2.throttle0.link_utilization 1.979870
system.ruby.network.routers2.throttle0.msg_count.Request_Control::1 1182
system.ruby.network.routers1.throttle1.msg_bytes.Unblock_Control::2 9464
system.ruby.network.routers2.throttle0.link_utilization 1.977443
system.ruby.network.routers2.throttle0.msg_count.Request_Control::1 1183
system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::2 194
system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::1 194
system.ruby.network.routers2.throttle0.msg_count.Unblock_Control::2 1182
system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::1 9456
system.ruby.network.routers2.throttle0.msg_count.Unblock_Control::2 1183
system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::1 9464
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::2 13968
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::1 1552
system.ruby.network.routers2.throttle0.msg_bytes.Unblock_Control::2 9456
system.ruby.network.routers2.throttle1.link_utilization 4.982796
system.ruby.network.routers2.throttle1.msg_count.Response_Data::2 1182
system.ruby.network.routers2.throttle0.msg_bytes.Unblock_Control::2 9464
system.ruby.network.routers2.throttle1.link_utilization 4.978508
system.ruby.network.routers2.throttle1.msg_count.Response_Data::2 1183
system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::1 194
system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::2 85104
system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::2 85176
system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::1 1552
system.ruby.network.routers3.throttle0.link_utilization 6.505879
system.ruby.network.routers3.throttle0.msg_count.Response_Data::2 1182
system.ruby.network.routers3.throttle0.link_utilization 6.499476
system.ruby.network.routers3.throttle0.msg_count.Response_Data::2 1183
system.ruby.network.routers3.throttle0.msg_count.ResponseL2hit_Data::2 239
system.ruby.network.routers3.throttle0.msg_count.Writeback_Control::0 1354
system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::2 85104
system.ruby.network.routers3.throttle0.msg_count.Writeback_Control::0 1355
system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::2 85176
system.ruby.network.routers3.throttle0.msg_bytes.ResponseL2hit_Data::2 17208
system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::0 10832
system.ruby.network.routers3.throttle1.link_utilization 12.349348
system.ruby.network.routers3.throttle1.msg_count.Request_Control::0 1421
system.ruby.network.routers3.throttle1.msg_count.Response_Data::2 1182
system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::2 1308
system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::0 1354
system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::0 10840
system.ruby.network.routers3.throttle1.link_utilization 12.338122
system.ruby.network.routers3.throttle1.msg_count.Request_Control::0 1422
system.ruby.network.routers3.throttle1.msg_count.Response_Data::2 1183
system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::2 1309
system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::0 1355
system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::1 194
system.ruby.network.routers3.throttle1.msg_count.Unblock_Control::2 1467
system.ruby.network.routers3.throttle1.msg_bytes.Request_Control::0 11368
system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::2 85104
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::2 94176
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0 10832
system.ruby.network.routers3.throttle1.msg_count.Unblock_Control::2 1468
system.ruby.network.routers3.throttle1.msg_bytes.Request_Control::0 11376
system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::2 85176
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::2 94248
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0 10840
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::1 1552
system.ruby.network.routers3.throttle1.msg_bytes.Unblock_Control::2 11736
system.ruby.network.routers3.throttle2.link_utilization 1.979870
system.ruby.network.routers3.throttle2.msg_count.Request_Control::1 1182
system.ruby.network.routers3.throttle1.msg_bytes.Unblock_Control::2 11744
system.ruby.network.routers3.throttle2.link_utilization 1.977443
system.ruby.network.routers3.throttle2.msg_count.Request_Control::1 1183
system.ruby.network.routers3.throttle2.msg_count.Writeback_Data::2 194
system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::1 194
system.ruby.network.routers3.throttle2.msg_count.Unblock_Control::2 1182
system.ruby.network.routers3.throttle2.msg_bytes.Request_Control::1 9456
system.ruby.network.routers3.throttle2.msg_count.Unblock_Control::2 1183
system.ruby.network.routers3.throttle2.msg_bytes.Request_Control::1 9464
system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Data::2 13968
system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Control::1 1552
system.ruby.network.routers3.throttle2.msg_bytes.Unblock_Control::2 9456
system.ruby.LD.latency_hist_seqr::bucket_size 64
system.ruby.LD.latency_hist_seqr::max_bucket 639
system.ruby.LD.latency_hist_seqr::samples 1183
system.ruby.LD.latency_hist_seqr::mean 27.265427
system.ruby.LD.latency_hist_seqr::gmean 5.733715
system.ruby.LD.latency_hist_seqr::stdev 35.817674
system.ruby.LD.latency_hist_seqr | 862 72.87% 72.87% | 317 26.80% 99.66% | 2 0.17% 99.83% | 1 0.08% 99.92% | 0 0.00% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.latency_hist_seqr::total 1183
system.ruby.network.routers3.throttle2.msg_bytes.Unblock_Control::2 9464
system.ruby.LD.latency_hist_seqr::bucket_size 32
system.ruby.LD.latency_hist_seqr::max_bucket 319
system.ruby.LD.latency_hist_seqr::samples 1185
system.ruby.LD.latency_hist_seqr::mean 27.428692
system.ruby.LD.latency_hist_seqr::gmean 5.747000
system.ruby.LD.latency_hist_seqr::stdev 36.091782
system.ruby.LD.latency_hist_seqr | 775 65.40% 65.40% | 87 7.34% 72.74% | 279 23.54% 96.29% | 40 3.38% 99.66% | 1 0.08% 99.75% | 1 0.08% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 1 0.08% 99.92% | 1 0.08% 100.00%
system.ruby.LD.latency_hist_seqr::total 1185
system.ruby.LD.hit_latency_hist_seqr::bucket_size 1
system.ruby.LD.hit_latency_hist_seqr::max_bucket 9
system.ruby.LD.hit_latency_hist_seqr::samples 658
system.ruby.LD.hit_latency_hist_seqr::samples 659
system.ruby.LD.hit_latency_hist_seqr::mean 1
system.ruby.LD.hit_latency_hist_seqr::gmean 1
system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 658 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.hit_latency_hist_seqr::total 658
system.ruby.LD.miss_latency_hist_seqr::bucket_size 64
system.ruby.LD.miss_latency_hist_seqr::max_bucket 639
system.ruby.LD.miss_latency_hist_seqr::samples 525
system.ruby.LD.miss_latency_hist_seqr::mean 60.184762
system.ruby.LD.miss_latency_hist_seqr::gmean 51.169278
system.ruby.LD.miss_latency_hist_seqr::stdev 30.689440
system.ruby.LD.miss_latency_hist_seqr | 204 38.86% 38.86% | 317 60.38% 99.24% | 2 0.38% 99.62% | 1 0.19% 99.81% | 0 0.00% 99.81% | 1 0.19% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.miss_latency_hist_seqr::total 525
system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 659 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.hit_latency_hist_seqr::total 659
system.ruby.LD.miss_latency_hist_seqr::bucket_size 32
system.ruby.LD.miss_latency_hist_seqr::max_bucket 319
system.ruby.LD.miss_latency_hist_seqr::samples 526
system.ruby.LD.miss_latency_hist_seqr::mean 60.539924
system.ruby.LD.miss_latency_hist_seqr::gmean 51.393520
system.ruby.LD.miss_latency_hist_seqr::stdev 31.024435
system.ruby.LD.miss_latency_hist_seqr | 116 22.05% 22.05% | 87 16.54% 38.59% | 279 53.04% 91.63% | 40 7.60% 99.24% | 1 0.19% 99.43% | 1 0.19% 99.62% | 0 0.00% 99.62% | 0 0.00% 99.62% | 1 0.19% 99.81% | 1 0.19% 100.00%
system.ruby.LD.miss_latency_hist_seqr::total 526
system.ruby.ST.latency_hist_seqr::bucket_size 64
system.ruby.ST.latency_hist_seqr::max_bucket 639
system.ruby.ST.latency_hist_seqr::samples 865
system.ruby.ST.latency_hist_seqr::mean 17.593064
system.ruby.ST.latency_hist_seqr::gmean 3.080574
system.ruby.ST.latency_hist_seqr::stdev 34.156278
system.ruby.ST.latency_hist_seqr | 753 87.05% 87.05% | 108 12.49% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 2 0.23% 99.77% | 2 0.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.latency_hist_seqr::mean 17.057803
system.ruby.ST.latency_hist_seqr::gmean 3.071194
system.ruby.ST.latency_hist_seqr::stdev 31.094076
system.ruby.ST.latency_hist_seqr | 753 87.05% 87.05% | 110 12.72% 99.77% | 0 0.00% 99.77% | 0 0.00% 99.77% | 1 0.12% 99.88% | 1 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.latency_hist_seqr::total 865
system.ruby.ST.hit_latency_hist_seqr::bucket_size 1
system.ruby.ST.hit_latency_hist_seqr::max_bucket 9
@ -597,73 +596,73 @@ system.ruby.ST.hit_latency_hist_seqr::total 615
system.ruby.ST.miss_latency_hist_seqr::bucket_size 64
system.ruby.ST.miss_latency_hist_seqr::max_bucket 639
system.ruby.ST.miss_latency_hist_seqr::samples 250
system.ruby.ST.miss_latency_hist_seqr::mean 58.412000
system.ruby.ST.miss_latency_hist_seqr::gmean 49.053018
system.ruby.ST.miss_latency_hist_seqr::stdev 41.173185
system.ruby.ST.miss_latency_hist_seqr | 138 55.20% 55.20% | 108 43.20% 98.40% | 0 0.00% 98.40% | 0 0.00% 98.40% | 2 0.80% 99.20% | 2 0.80% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.miss_latency_hist_seqr::mean 56.560000
system.ruby.ST.miss_latency_hist_seqr::gmean 48.538116
system.ruby.ST.miss_latency_hist_seqr::stdev 33.930333
system.ruby.ST.miss_latency_hist_seqr | 138 55.20% 55.20% | 110 44.00% 99.20% | 0 0.00% 99.20% | 0 0.00% 99.20% | 1 0.40% 99.60% | 1 0.40% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.miss_latency_hist_seqr::total 250
system.ruby.IFETCH.latency_hist_seqr::bucket_size 32
system.ruby.IFETCH.latency_hist_seqr::max_bucket 319
system.ruby.IFETCH.latency_hist_seqr::samples 6400
system.ruby.IFETCH.latency_hist_seqr::mean 8.245781
system.ruby.IFETCH.latency_hist_seqr::gmean 1.526741
system.ruby.IFETCH.latency_hist_seqr::stdev 23.776931
system.ruby.IFETCH.latency_hist_seqr | 5825 91.02% 91.02% | 0 0.00% 91.02% | 525 8.20% 99.22% | 41 0.64% 99.86% | 2 0.03% 99.89% | 0 0.00% 99.89% | 0 0.00% 99.89% | 0 0.00% 99.89% | 2 0.03% 99.92% | 5 0.08% 100.00%
system.ruby.IFETCH.latency_hist_seqr::total 6400
system.ruby.IFETCH.latency_hist_seqr::bucket_size 64
system.ruby.IFETCH.latency_hist_seqr::max_bucket 639
system.ruby.IFETCH.latency_hist_seqr::samples 6413
system.ruby.IFETCH.latency_hist_seqr::mean 8.288944
system.ruby.IFETCH.latency_hist_seqr::gmean 1.525778
system.ruby.IFETCH.latency_hist_seqr::stdev 24.342417
system.ruby.IFETCH.latency_hist_seqr | 5838 91.03% 91.03% | 566 8.83% 99.86% | 0 0.00% 99.86% | 0 0.00% 99.86% | 6 0.09% 99.95% | 3 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.latency_hist_seqr::total 6413
system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1
system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9
system.ruby.IFETCH.hit_latency_hist_seqr::samples 5754
system.ruby.IFETCH.hit_latency_hist_seqr::samples 5767
system.ruby.IFETCH.hit_latency_hist_seqr::mean 1
system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1
system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 5754 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.hit_latency_hist_seqr::total 5754
system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 32
system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 319
system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 5767 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.hit_latency_hist_seqr::total 5767
system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64
system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639
system.ruby.IFETCH.miss_latency_hist_seqr::samples 646
system.ruby.IFETCH.miss_latency_hist_seqr::mean 72.784830
system.ruby.IFETCH.miss_latency_hist_seqr::gmean 66.158480
system.ruby.IFETCH.miss_latency_hist_seqr::stdev 31.122591
system.ruby.IFETCH.miss_latency_hist_seqr | 71 10.99% 10.99% | 0 0.00% 10.99% | 525 81.27% 92.26% | 41 6.35% 98.61% | 2 0.31% 98.92% | 0 0.00% 98.92% | 0 0.00% 98.92% | 0 0.00% 98.92% | 2 0.31% 99.23% | 5 0.77% 100.00%
system.ruby.IFETCH.miss_latency_hist_seqr::mean 73.359133
system.ruby.IFETCH.miss_latency_hist_seqr::gmean 66.307554
system.ruby.IFETCH.miss_latency_hist_seqr::stdev 34.276818
system.ruby.IFETCH.miss_latency_hist_seqr | 71 10.99% 10.99% | 566 87.62% 98.61% | 0 0.00% 98.61% | 0 0.00% 98.61% | 6 0.93% 99.54% | 3 0.46% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.miss_latency_hist_seqr::total 646
system.ruby.Directory_Controller.GETX 198 0.00% 0.00%
system.ruby.Directory_Controller.GETS 984 0.00% 0.00%
system.ruby.Directory_Controller.GETS 985 0.00% 0.00%
system.ruby.Directory_Controller.PUTX 194 0.00% 0.00%
system.ruby.Directory_Controller.Unblock 466 0.00% 0.00%
system.ruby.Directory_Controller.Last_Unblock 517 0.00% 0.00%
system.ruby.Directory_Controller.Last_Unblock 518 0.00% 0.00%
system.ruby.Directory_Controller.Exclusive_Unblock 198 0.00% 0.00%
system.ruby.Directory_Controller.Dirty_Writeback 194 0.00% 0.00%
system.ruby.Directory_Controller.Memory_Data 1182 0.00% 0.00%
system.ruby.Directory_Controller.Memory_Data 1183 0.00% 0.00%
system.ruby.Directory_Controller.Memory_Ack 194 0.00% 0.00%
system.ruby.Directory_Controller.I.GETX 111 0.00% 0.00%
system.ruby.Directory_Controller.I.GETS 466 0.00% 0.00%
system.ruby.Directory_Controller.I.Memory_Ack 194 0.00% 0.00%
system.ruby.Directory_Controller.S.GETX 87 0.00% 0.00%
system.ruby.Directory_Controller.S.GETS 518 0.00% 0.00%
system.ruby.Directory_Controller.S.GETS 519 0.00% 0.00%
system.ruby.Directory_Controller.M.PUTX 194 0.00% 0.00%
system.ruby.Directory_Controller.IS.Unblock 466 0.00% 0.00%
system.ruby.Directory_Controller.IS.Memory_Data 466 0.00% 0.00%
system.ruby.Directory_Controller.SS.Last_Unblock 517 0.00% 0.00%
system.ruby.Directory_Controller.SS.Memory_Data 518 0.00% 0.00%
system.ruby.Directory_Controller.SS.Last_Unblock 518 0.00% 0.00%
system.ruby.Directory_Controller.SS.Memory_Data 519 0.00% 0.00%
system.ruby.Directory_Controller.MM.Exclusive_Unblock 198 0.00% 0.00%
system.ruby.Directory_Controller.MM.Memory_Data 198 0.00% 0.00%
system.ruby.Directory_Controller.MI.Dirty_Writeback 194 0.00% 0.00%
system.ruby.L1Cache_Controller.Load 1183 0.00% 0.00%
system.ruby.L1Cache_Controller.Ifetch 6400 0.00% 0.00%
system.ruby.L1Cache_Controller.Load 1185 0.00% 0.00%
system.ruby.L1Cache_Controller.Ifetch 6413 0.00% 0.00%
system.ruby.L1Cache_Controller.Store 865 0.00% 0.00%
system.ruby.L1Cache_Controller.L1_Replacement 1368 0.00% 0.00%
system.ruby.L1Cache_Controller.Data 1125 0.00% 0.00%
system.ruby.L1Cache_Controller.L1_Replacement 1369 0.00% 0.00%
system.ruby.L1Cache_Controller.Data 1126 0.00% 0.00%
system.ruby.L1Cache_Controller.Exclusive_Data 296 0.00% 0.00%
system.ruby.L1Cache_Controller.Writeback_Ack 46 0.00% 0.00%
system.ruby.L1Cache_Controller.Writeback_Ack_Data 1308 0.00% 0.00%
system.ruby.L1Cache_Controller.Writeback_Ack_Data 1309 0.00% 0.00%
system.ruby.L1Cache_Controller.All_acks 250 0.00% 0.00%
system.ruby.L1Cache_Controller.Use_Timeout 296 0.00% 0.00%
system.ruby.L1Cache_Controller.I.Load 525 0.00% 0.00%
system.ruby.L1Cache_Controller.I.Load 526 0.00% 0.00%
system.ruby.L1Cache_Controller.I.Ifetch 646 0.00% 0.00%
system.ruby.L1Cache_Controller.I.Store 191 0.00% 0.00%
system.ruby.L1Cache_Controller.S.Load 299 0.00% 0.00%
system.ruby.L1Cache_Controller.S.Ifetch 5754 0.00% 0.00%
system.ruby.L1Cache_Controller.S.Load 300 0.00% 0.00%
system.ruby.L1Cache_Controller.S.Ifetch 5767 0.00% 0.00%
system.ruby.L1Cache_Controller.S.Store 59 0.00% 0.00%
system.ruby.L1Cache_Controller.S.L1_Replacement 1059 0.00% 0.00%
system.ruby.L1Cache_Controller.S.L1_Replacement 1060 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Load 79 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Store 18 0.00% 0.00%
system.ruby.L1Cache_Controller.M.L1_Replacement 27 0.00% 0.00%
@ -680,42 +679,42 @@ system.ruby.L1Cache_Controller.MM_W.Use_Timeout 251 0.00% 0.0
system.ruby.L1Cache_Controller.IM.Exclusive_Data 191 0.00% 0.00%
system.ruby.L1Cache_Controller.SM.Exclusive_Data 59 0.00% 0.00%
system.ruby.L1Cache_Controller.OM.All_acks 250 0.00% 0.00%
system.ruby.L1Cache_Controller.IS.Data 1125 0.00% 0.00%
system.ruby.L1Cache_Controller.IS.Data 1126 0.00% 0.00%
system.ruby.L1Cache_Controller.IS.Exclusive_Data 46 0.00% 0.00%
system.ruby.L1Cache_Controller.SI.Writeback_Ack 46 0.00% 0.00%
system.ruby.L1Cache_Controller.SI.Writeback_Ack_Data 1013 0.00% 0.00%
system.ruby.L1Cache_Controller.SI.Writeback_Ack_Data 1014 0.00% 0.00%
system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data 295 0.00% 0.00%
system.ruby.L2Cache_Controller.L1_GETS 1171 0.00% 0.00%
system.ruby.L2Cache_Controller.L1_GETS 1172 0.00% 0.00%
system.ruby.L2Cache_Controller.L1_GETX 250 0.00% 0.00%
system.ruby.L2Cache_Controller.L1_PUTX 295 0.00% 0.00%
system.ruby.L2Cache_Controller.L1_PUTS_only 1059 0.00% 0.00%
system.ruby.L2Cache_Controller.L1_PUTS_only 1060 0.00% 0.00%
system.ruby.L2Cache_Controller.All_Acks 198 0.00% 0.00%
system.ruby.L2Cache_Controller.Data 1182 0.00% 0.00%
system.ruby.L2Cache_Controller.L1_WBCLEANDATA 1013 0.00% 0.00%
system.ruby.L2Cache_Controller.Data 1183 0.00% 0.00%
system.ruby.L2Cache_Controller.L1_WBCLEANDATA 1014 0.00% 0.00%
system.ruby.L2Cache_Controller.L1_WBDIRTYDATA 295 0.00% 0.00%
system.ruby.L2Cache_Controller.Writeback_Ack 194 0.00% 0.00%
system.ruby.L2Cache_Controller.Unblock 1171 0.00% 0.00%
system.ruby.L2Cache_Controller.Unblock 1172 0.00% 0.00%
system.ruby.L2Cache_Controller.Exclusive_Unblock 296 0.00% 0.00%
system.ruby.L2Cache_Controller.L2_Replacement 1193 0.00% 0.00%
system.ruby.L2Cache_Controller.NP.L1_GETS 984 0.00% 0.00%
system.ruby.L2Cache_Controller.L2_Replacement 1194 0.00% 0.00%
system.ruby.L2Cache_Controller.NP.L1_GETS 985 0.00% 0.00%
system.ruby.L2Cache_Controller.NP.L1_GETX 132 0.00% 0.00%
system.ruby.L2Cache_Controller.ILS.L1_GETX 57 0.00% 0.00%
system.ruby.L2Cache_Controller.ILS.L1_PUTS_only 1013 0.00% 0.00%
system.ruby.L2Cache_Controller.ILS.L1_PUTS_only 1014 0.00% 0.00%
system.ruby.L2Cache_Controller.ILX.L1_PUTX 295 0.00% 0.00%
system.ruby.L2Cache_Controller.S.L1_GETS 141 0.00% 0.00%
system.ruby.L2Cache_Controller.S.L1_GETX 7 0.00% 0.00%
system.ruby.L2Cache_Controller.S.L2_Replacement 906 0.00% 0.00%
system.ruby.L2Cache_Controller.S.L2_Replacement 907 0.00% 0.00%
system.ruby.L2Cache_Controller.SLS.L1_GETX 2 0.00% 0.00%
system.ruby.L2Cache_Controller.SLS.L1_PUTS_only 46 0.00% 0.00%
system.ruby.L2Cache_Controller.SLS.L2_Replacement 93 0.00% 0.00%
system.ruby.L2Cache_Controller.M.L1_GETS 46 0.00% 0.00%
system.ruby.L2Cache_Controller.M.L1_GETX 52 0.00% 0.00%
system.ruby.L2Cache_Controller.M.L2_Replacement 194 0.00% 0.00%
system.ruby.L2Cache_Controller.IW.L1_WBCLEANDATA 1013 0.00% 0.00%
system.ruby.L2Cache_Controller.IW.L1_WBCLEANDATA 1014 0.00% 0.00%
system.ruby.L2Cache_Controller.SW.Unblock 46 0.00% 0.00%
system.ruby.L2Cache_Controller.ILXW.L1_WBDIRTYDATA 295 0.00% 0.00%
system.ruby.L2Cache_Controller.IGS.Data 984 0.00% 0.00%
system.ruby.L2Cache_Controller.IGS.Unblock 984 0.00% 0.00%
system.ruby.L2Cache_Controller.IGS.Data 985 0.00% 0.00%
system.ruby.L2Cache_Controller.IGS.Unblock 985 0.00% 0.00%
system.ruby.L2Cache_Controller.IGM.Data 139 0.00% 0.00%
system.ruby.L2Cache_Controller.IGMLS.Data 59 0.00% 0.00%
system.ruby.L2Cache_Controller.IGMO.All_Acks 198 0.00% 0.00%

2
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
View file

@ -120,7 +120,7 @@ env=
errout=cerr
euid=100
eventq_index=0
executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
kvmInSE=false

10
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout
View file

@ -1,10 +1,12 @@
Redirecting stdout to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout
Redirecting stderr to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 21 2016 14:12:23
gem5 started Jan 21 2016 14:12:59
gem5 executing on zizzer, pid 55399
command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token
gem5 compiled Mar 14 2016 22:02:54
gem5 started Mar 14 2016 22:04:07
gem5 executing on phenom, pid 29513
command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

638
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt
View file

@ -4,37 +4,37 @@ sim_seconds 0.000108 # Nu
sim_ticks 108253 # Number of ticks simulated
final_tick 108253 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_inst_rate 33873 # Simulator instruction rate (inst/s)
host_op_rate 33870 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 573730 # Simulator tick rate (ticks/s)
host_mem_usage 391892 # Number of bytes of host memory used
host_seconds 0.19 # Real time elapsed on the host
sim_insts 6390 # Number of instructions simulated
sim_ops 6390 # Number of ops (including micro ops) simulated
host_inst_rate 39556 # Simulator instruction rate (inst/s)
host_op_rate 39552 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 668635 # Simulator tick rate (ticks/s)
host_mem_usage 388512 # Number of bytes of host memory used
host_seconds 0.16 # Real time elapsed on the host
sim_insts 6403 # Number of instructions simulated
sim_ops 6403 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 75392 # Number of bytes read from this memory
system.mem_ctrls.bytes_read::total 75392 # Number of bytes read from this memory
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 75456 # Number of bytes read from this memory
system.mem_ctrls.bytes_read::total 75456 # Number of bytes read from this memory
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 14656 # Number of bytes written to this memory
system.mem_ctrls.bytes_written::total 14656 # Number of bytes written to this memory
system.mem_ctrls.num_reads::ruby.dir_cntrl0 1178 # Number of read requests responded to by this memory
system.mem_ctrls.num_reads::total 1178 # Number of read requests responded to by this memory
system.mem_ctrls.num_reads::ruby.dir_cntrl0 1179 # Number of read requests responded to by this memory
system.mem_ctrls.num_reads::total 1179 # Number of read requests responded to by this memory
system.mem_ctrls.num_writes::ruby.dir_cntrl0 229 # Number of write requests responded to by this memory
system.mem_ctrls.num_writes::total 229 # Number of write requests responded to by this memory
system.mem_ctrls.bw_read::ruby.dir_cntrl0 696442593 # Total read bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_read::total 696442593 # Total read bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_read::ruby.dir_cntrl0 697033800 # Total read bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_read::total 697033800 # Total read bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_write::ruby.dir_cntrl0 135386548 # Write bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_write::total 135386548 # Write bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_total::ruby.dir_cntrl0 831829141 # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.bw_total::total 831829141 # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.readReqs 1178 # Number of read requests accepted
system.mem_ctrls.bw_total::ruby.dir_cntrl0 832420349 # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.bw_total::total 832420349 # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.readReqs 1179 # Number of read requests accepted
system.mem_ctrls.writeReqs 229 # Number of write requests accepted
system.mem_ctrls.readBursts 1178 # Number of DRAM read bursts, including those serviced by the write queue
system.mem_ctrls.readBursts 1179 # Number of DRAM read bursts, including those serviced by the write queue
system.mem_ctrls.writeBursts 229 # Number of DRAM write bursts, including those merged in the write queue
system.mem_ctrls.bytesReadDRAM 65024 # Total number of bytes read from DRAM
system.mem_ctrls.bytesReadDRAM 65088 # Total number of bytes read from DRAM
system.mem_ctrls.bytesReadWrQ 10368 # Total number of bytes read from write queue
system.mem_ctrls.bytesWritten 6144 # Total number of bytes written to DRAM
system.mem_ctrls.bytesReadSys 75392 # Total read bytes from the system interface side
system.mem_ctrls.bytesReadSys 75456 # Total read bytes from the system interface side
system.mem_ctrls.bytesWrittenSys 14656 # Total written bytes from the system interface side
system.mem_ctrls.servicedByWrQ 162 # Number of DRAM read bursts serviced by the write queue
system.mem_ctrls.mergedWrBursts 112 # Number of DRAM write bursts merged with an existing one
@ -54,7 +54,7 @@ system.mem_ctrls.perBankRdBursts::11 53 # Pe
system.mem_ctrls.perBankRdBursts::12 22 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::13 361 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::14 61 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::15 44 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::15 45 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts
@ -80,7 +80,7 @@ system.mem_ctrls.readPktSize::2 0 # Re
system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::6 1178 # Read request sizes (log2)
system.mem_ctrls.readPktSize::6 1179 # Read request sizes (log2)
system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
@ -88,7 +88,7 @@ system.mem_ctrls.writePktSize::3 0 # Wr
system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::6 229 # Write request sizes (log2)
system.mem_ctrls.rdQLenPdf::0 1016 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::0 1017 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
@ -185,9 +185,9 @@ system.mem_ctrls.wrQLenPdf::61 0 # Wh
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.mem_ctrls.bytesPerActivate::samples 203 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::mean 338.600985 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::gmean 206.377683 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::stdev 325.274619 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::mean 338.916256 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::gmean 206.604664 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::stdev 325.225174 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::0-127 65 32.02% 32.02% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::128-255 46 22.66% 54.68% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::256-383 21 10.34% 65.02% # Bytes accessed per row activation
@ -199,9 +199,9 @@ system.mem_ctrls.bytesPerActivate::896-1023 4 1.97% 89.66% #
system.mem_ctrls.bytesPerActivate::1024-1151 21 10.34% 100.00% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::total 203 # Bytes accessed per row activation
system.mem_ctrls.rdPerTurnAround::samples 6 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::mean 156.333333 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::gmean 116.994790 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::stdev 90.254455 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::mean 156.500000 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::gmean 117.084065 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::stdev 90.391924 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::16-31 1 16.67% 16.67% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::80-95 1 16.67% 33.33% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::160-175 1 16.67% 50.00% # Reads before turning the bus around for writes
@ -214,77 +214,77 @@ system.mem_ctrls.wrPerTurnAround::mean 16 # Wr
system.mem_ctrls.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::16 6 100.00% 100.00% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::total 6 # Writes before turning the bus around for reads
system.mem_ctrls.totQLat 7316 # Total ticks spent queuing
system.mem_ctrls.totMemAccLat 26620 # Total ticks spent from burst creation until serviced by the DRAM
system.mem_ctrls.totBusLat 5080 # Total ticks spent in databus transfers
system.mem_ctrls.avgQLat 7.20 # Average queueing delay per DRAM burst
system.mem_ctrls.totQLat 7213 # Total ticks spent queuing
system.mem_ctrls.totMemAccLat 26536 # Total ticks spent from burst creation until serviced by the DRAM
system.mem_ctrls.totBusLat 5085 # Total ticks spent in databus transfers
system.mem_ctrls.avgQLat 7.09 # Average queueing delay per DRAM burst
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
system.mem_ctrls.avgMemAccLat 26.20 # Average memory access latency per DRAM burst
system.mem_ctrls.avgRdBW 600.67 # Average DRAM read bandwidth in MiByte/s
system.mem_ctrls.avgMemAccLat 26.09 # Average memory access latency per DRAM burst
system.mem_ctrls.avgRdBW 601.26 # Average DRAM read bandwidth in MiByte/s
system.mem_ctrls.avgWrBW 56.76 # Average achieved write bandwidth in MiByte/s
system.mem_ctrls.avgRdBWSys 696.44 # Average system read bandwidth in MiByte/s
system.mem_ctrls.avgRdBWSys 697.03 # Average system read bandwidth in MiByte/s
system.mem_ctrls.avgWrBWSys 135.39 # Average system write bandwidth in MiByte/s
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.mem_ctrls.busUtil 5.14 # Data bus utilization in percentage
system.mem_ctrls.busUtilRead 4.69 # Data bus utilization in percentage for reads
system.mem_ctrls.busUtilRead 4.70 # Data bus utilization in percentage for reads
system.mem_ctrls.busUtilWrite 0.44 # Data bus utilization in percentage for writes
system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing
system.mem_ctrls.avgWrQLen 23.01 # Average write queue length when enqueuing
system.mem_ctrls.readRowHits 815 # Number of row buffer hits during reads
system.mem_ctrls.readRowHits 816 # Number of row buffer hits during reads
system.mem_ctrls.writeRowHits 88 # Number of row buffer hits during writes
system.mem_ctrls.readRowHitRate 80.22 # Row buffer hit rate for reads
system.mem_ctrls.readRowHitRate 80.24 # Row buffer hit rate for reads
system.mem_ctrls.writeRowHitRate 75.21 # Row buffer hit rate for writes
system.mem_ctrls.avgGap 76.88 # Average gap between requests
system.mem_ctrls.pageHitRate 79.70 # Row buffer hit rate, read and write combined
system.mem_ctrls.avgGap 76.83 # Average gap between requests
system.mem_ctrls.pageHitRate 79.72 # Row buffer hit rate, read and write combined
system.mem_ctrls_0.actEnergy 521640 # Energy for activate commands per rank (pJ)
system.mem_ctrls_0.preEnergy 289800 # Energy for precharge commands per rank (pJ)
system.mem_ctrls_0.readEnergy 5104320 # Energy for read commands per rank (pJ)
system.mem_ctrls_0.writeEnergy 311040 # Energy for write commands per rank (pJ)
system.mem_ctrls_0.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ)
system.mem_ctrls_0.actBackEnergy 57834936 # Energy for active background per rank (pJ)
system.mem_ctrls_0.preBackEnergy 10154400 # Energy for precharge background per rank (pJ)
system.mem_ctrls_0.totalEnergy 80827416 # Total energy per rank (pJ)
system.mem_ctrls_0.averagePower 796.501862 # Core power per rank (mW)
system.mem_ctrls_0.memoryStateTime::IDLE 21697 # Time in different power states
system.mem_ctrls_0.actBackEnergy 57840408 # Energy for active background per rank (pJ)
system.mem_ctrls_0.preBackEnergy 10149600 # Energy for precharge background per rank (pJ)
system.mem_ctrls_0.totalEnergy 80828088 # Total energy per rank (pJ)
system.mem_ctrls_0.averagePower 796.508485 # Core power per rank (mW)
system.mem_ctrls_0.memoryStateTime::IDLE 21689 # Time in different power states
system.mem_ctrls_0.memoryStateTime::REF 3380 # Time in different power states
system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.mem_ctrls_0.memoryStateTime::ACT 81524 # Time in different power states
system.mem_ctrls_0.memoryStateTime::ACT 81532 # Time in different power states
system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.mem_ctrls_1.actEnergy 945000 # Energy for activate commands per rank (pJ)
system.mem_ctrls_1.preEnergy 525000 # Energy for precharge commands per rank (pJ)
system.mem_ctrls_1.readEnergy 6751680 # Energy for read commands per rank (pJ)
system.mem_ctrls_1.readEnergy 6764160 # Energy for read commands per rank (pJ)
system.mem_ctrls_1.writeEnergy 684288 # Energy for write commands per rank (pJ)
system.mem_ctrls_1.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ)
system.mem_ctrls_1.actBackEnergy 67458132 # Energy for active background per rank (pJ)
system.mem_ctrls_1.preBackEnergy 1721400 # Energy for precharge background per rank (pJ)
system.mem_ctrls_1.totalEnergy 84696780 # Total energy per rank (pJ)
system.mem_ctrls_1.averagePower 834.516809 # Core power per rank (mW)
system.mem_ctrls_1.memoryStateTime::IDLE 2421 # Time in different power states
system.mem_ctrls_1.actBackEnergy 67474548 # Energy for active background per rank (pJ)
system.mem_ctrls_1.preBackEnergy 1707000 # Energy for precharge background per rank (pJ)
system.mem_ctrls_1.totalEnergy 84711276 # Total energy per rank (pJ)
system.mem_ctrls_1.averagePower 834.659638 # Core power per rank (mW)
system.mem_ctrls_1.memoryStateTime::IDLE 2397 # Time in different power states
system.mem_ctrls_1.memoryStateTime::REF 3380 # Time in different power states
system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT 95705 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT 95729 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.clk_domain.clock 1 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 1183 # DTB read hits
system.cpu.dtb.read_hits 1185 # DTB read hits
system.cpu.dtb.read_misses 7 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 1190 # DTB read accesses
system.cpu.dtb.read_accesses 1192 # DTB read accesses
system.cpu.dtb.write_hits 865 # DTB write hits
system.cpu.dtb.write_misses 3 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 868 # DTB write accesses
system.cpu.dtb.data_hits 2048 # DTB hits
system.cpu.dtb.data_hits 2050 # DTB hits
system.cpu.dtb.data_misses 10 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 2058 # DTB accesses
system.cpu.itb.fetch_hits 6401 # ITB hits
system.cpu.dtb.data_accesses 2060 # DTB accesses
system.cpu.itb.fetch_hits 6414 # ITB hits
system.cpu.itb.fetch_misses 17 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 6418 # ITB accesses
system.cpu.itb.fetch_accesses 6431 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@ -301,338 +301,338 @@ system.cpu.workload.num_syscalls 17 # Nu
system.cpu.numCycles 108253 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 6390 # Number of instructions committed
system.cpu.committedOps 6390 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses
system.cpu.committedInsts 6403 # Number of instructions committed
system.cpu.committedOps 6403 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 6329 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
system.cpu.num_func_calls 251 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls
system.cpu.num_int_insts 6317 # number of integer instructions
system.cpu.num_conditional_control_insts 754 # number of instructions that are conditional controls
system.cpu.num_int_insts 6329 # number of integer instructions
system.cpu.num_fp_insts 10 # number of float instructions
system.cpu.num_int_register_reads 8285 # number of times the integer registers were read
system.cpu.num_int_register_writes 4568 # number of times the integer registers were written
system.cpu.num_int_register_reads 8297 # number of times the integer registers were read
system.cpu.num_int_register_writes 4575 # number of times the integer registers were written
system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
system.cpu.num_mem_refs 2058 # number of memory refs
system.cpu.num_load_insts 1190 # Number of load instructions
system.cpu.num_mem_refs 2060 # number of memory refs
system.cpu.num_load_insts 1192 # Number of load instructions
system.cpu.num_store_insts 868 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 108253 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.Branches 1050 # Number of branches fetched
system.cpu.Branches 1056 # Number of branches fetched
system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction
system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction
system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction
system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction
system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction
system.cpu.op_class::IntAlu 4331 67.53% 67.83% # Class of executed instruction
system.cpu.op_class::IntMult 1 0.02% 67.85% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 67.85% # Class of executed instruction
system.cpu.op_class::FloatAdd 2 0.03% 67.88% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::MemRead 1192 18.59% 86.46% # Class of executed instruction
system.cpu.op_class::MemWrite 868 13.54% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 6400 # Class of executed instruction
system.cpu.op_class::total 6413 # Class of executed instruction
system.ruby.clk_domain.clock 1 # Clock period in ticks
system.ruby.outstanding_req_hist_seqr::bucket_size 1
system.ruby.outstanding_req_hist_seqr::max_bucket 9
system.ruby.outstanding_req_hist_seqr::samples 8449
system.ruby.outstanding_req_hist_seqr::samples 8464
system.ruby.outstanding_req_hist_seqr::mean 1
system.ruby.outstanding_req_hist_seqr::gmean 1
system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 8449 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.outstanding_req_hist_seqr::total 8449
system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 8464 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.outstanding_req_hist_seqr::total 8464
system.ruby.latency_hist_seqr::bucket_size 64
system.ruby.latency_hist_seqr::max_bucket 639
system.ruby.latency_hist_seqr::samples 8448
system.ruby.latency_hist_seqr::mean 11.814039
system.ruby.latency_hist_seqr::gmean 1.958059
system.ruby.latency_hist_seqr::stdev 27.675120
system.ruby.latency_hist_seqr | 7432 87.97% 87.97% | 995 11.78% 99.75% | 8 0.09% 99.85% | 3 0.04% 99.88% | 6 0.07% 99.95% | 4 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.latency_hist_seqr::total 8448
system.ruby.latency_hist_seqr::samples 8463
system.ruby.latency_hist_seqr::mean 11.791327
system.ruby.latency_hist_seqr::gmean 1.956562
system.ruby.latency_hist_seqr::stdev 27.556143
system.ruby.latency_hist_seqr | 7446 87.98% 87.98% | 996 11.77% 99.75% | 8 0.09% 99.85% | 4 0.05% 99.89% | 5 0.06% 99.95% | 4 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.latency_hist_seqr::total 8463
system.ruby.hit_latency_hist_seqr::bucket_size 8
system.ruby.hit_latency_hist_seqr::max_bucket 79
system.ruby.hit_latency_hist_seqr::samples 7270
system.ruby.hit_latency_hist_seqr::mean 1.637552
system.ruby.hit_latency_hist_seqr::gmean 1.092853
system.ruby.hit_latency_hist_seqr::stdev 3.762080
system.ruby.hit_latency_hist_seqr | 7066 97.19% 97.19% | 0 0.00% 97.19% | 19 0.26% 97.46% | 184 2.53% 99.99% | 0 0.00% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.hit_latency_hist_seqr::total 7270
system.ruby.hit_latency_hist_seqr::samples 7284
system.ruby.hit_latency_hist_seqr::mean 1.635502
system.ruby.hit_latency_hist_seqr::gmean 1.092626
system.ruby.hit_latency_hist_seqr::stdev 3.754063
system.ruby.hit_latency_hist_seqr | 7080 97.20% 97.20% | 0 0.00% 97.20% | 21 0.29% 97.49% | 182 2.50% 99.99% | 0 0.00% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.hit_latency_hist_seqr::total 7284
system.ruby.miss_latency_hist_seqr::bucket_size 64
system.ruby.miss_latency_hist_seqr::max_bucket 639
system.ruby.miss_latency_hist_seqr::samples 1178
system.ruby.miss_latency_hist_seqr::mean 74.617997
system.ruby.miss_latency_hist_seqr::gmean 71.587772
system.ruby.miss_latency_hist_seqr::stdev 28.670099
system.ruby.miss_latency_hist_seqr | 162 13.75% 13.75% | 995 84.47% 98.22% | 8 0.68% 98.90% | 3 0.25% 99.15% | 6 0.51% 99.66% | 4 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.miss_latency_hist_seqr::total 1178
system.ruby.Directory.incomplete_times_seqr 1177
system.ruby.l1_cntrl0.L1Dcache.demand_hits 1312 # Number of cache demand hits
system.ruby.l1_cntrl0.L1Dcache.demand_misses 736 # Number of cache demand misses
system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2048 # Number of cache demand accesses
system.ruby.l1_cntrl0.L1Icache.demand_hits 5754 # Number of cache demand hits
system.ruby.miss_latency_hist_seqr::samples 1179
system.ruby.miss_latency_hist_seqr::mean 74.535199
system.ruby.miss_latency_hist_seqr::gmean 71.564149
system.ruby.miss_latency_hist_seqr::stdev 28.099799
system.ruby.miss_latency_hist_seqr | 162 13.74% 13.74% | 996 84.48% 98.22% | 8 0.68% 98.90% | 4 0.34% 99.24% | 5 0.42% 99.66% | 4 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.miss_latency_hist_seqr::total 1179
system.ruby.Directory.incomplete_times_seqr 1178
system.ruby.l1_cntrl0.L1Dcache.demand_hits 1313 # Number of cache demand hits
system.ruby.l1_cntrl0.L1Dcache.demand_misses 737 # Number of cache demand misses
system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2050 # Number of cache demand accesses
system.ruby.l1_cntrl0.L1Icache.demand_hits 5767 # Number of cache demand hits
system.ruby.l1_cntrl0.L1Icache.demand_misses 646 # Number of cache demand misses
system.ruby.l1_cntrl0.L1Icache.demand_accesses 6400 # Number of cache demand accesses
system.ruby.l1_cntrl0.L1Icache.demand_accesses 6413 # Number of cache demand accesses
system.ruby.l2_cntrl0.L2cache.demand_hits 187 # Number of cache demand hits
system.ruby.l2_cntrl0.L2cache.demand_misses 1195 # Number of cache demand misses
system.ruby.l2_cntrl0.L2cache.demand_accesses 1382 # Number of cache demand accesses
system.ruby.l2_cntrl0.L2cache.demand_misses 1196 # Number of cache demand misses
system.ruby.l2_cntrl0.L2cache.demand_accesses 1383 # Number of cache demand accesses
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
system.ruby.network.routers0.percent_links_utilized 6.018078
system.ruby.network.routers0.msg_count.Request_Control::1 1382
system.ruby.network.routers0.msg_count.Response_Data::4 1178
system.ruby.network.routers0.percent_links_utilized 6.022466
system.ruby.network.routers0.msg_count.Request_Control::1 1383
system.ruby.network.routers0.msg_count.Response_Data::4 1179
system.ruby.network.routers0.msg_count.ResponseL2hit_Data::4 204
system.ruby.network.routers0.msg_count.Response_Control::4 1
system.ruby.network.routers0.msg_count.Writeback_Data::4 1354
system.ruby.network.routers0.msg_count.Writeback_Data::4 1355
system.ruby.network.routers0.msg_count.Persistent_Control::3 52
system.ruby.network.routers0.msg_bytes.Request_Control::1 11056
system.ruby.network.routers0.msg_bytes.Response_Data::4 84816
system.ruby.network.routers0.msg_bytes.Request_Control::1 11064
system.ruby.network.routers0.msg_bytes.Response_Data::4 84888
system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::4 14688
system.ruby.network.routers0.msg_bytes.Response_Control::4 8
system.ruby.network.routers0.msg_bytes.Writeback_Data::4 97488
system.ruby.network.routers0.msg_bytes.Writeback_Data::4 97560
system.ruby.network.routers0.msg_bytes.Persistent_Control::3 416
system.ruby.network.routers1.percent_links_utilized 4.538904
system.ruby.network.routers1.msg_count.Request_Control::1 1382
system.ruby.network.routers1.msg_count.Request_Control::2 1195
system.ruby.network.routers1.percent_links_utilized 4.541676
system.ruby.network.routers1.msg_count.Request_Control::1 1383
system.ruby.network.routers1.msg_count.Request_Control::2 1196
system.ruby.network.routers1.msg_count.ResponseL2hit_Data::4 204
system.ruby.network.routers1.msg_count.Response_Control::4 1
system.ruby.network.routers1.msg_count.Writeback_Data::4 1583
system.ruby.network.routers1.msg_count.Writeback_Control::4 967
system.ruby.network.routers1.msg_count.Writeback_Data::4 1584
system.ruby.network.routers1.msg_count.Writeback_Control::4 968
system.ruby.network.routers1.msg_count.Persistent_Control::3 26
system.ruby.network.routers1.msg_bytes.Request_Control::1 11056
system.ruby.network.routers1.msg_bytes.Request_Control::2 9560
system.ruby.network.routers1.msg_bytes.Request_Control::1 11064
system.ruby.network.routers1.msg_bytes.Request_Control::2 9568
system.ruby.network.routers1.msg_bytes.ResponseL2hit_Data::4 14688
system.ruby.network.routers1.msg_bytes.Response_Control::4 8
system.ruby.network.routers1.msg_bytes.Writeback_Data::4 113976
system.ruby.network.routers1.msg_bytes.Writeback_Control::4 7736
system.ruby.network.routers1.msg_bytes.Writeback_Data::4 114048
system.ruby.network.routers1.msg_bytes.Writeback_Control::4 7744
system.ruby.network.routers1.msg_bytes.Persistent_Control::3 208
system.ruby.network.routers2.percent_links_utilized 3.429697
system.ruby.network.routers2.msg_count.Request_Control::2 1195
system.ruby.network.routers2.msg_count.Response_Data::4 1178
system.ruby.network.routers2.percent_links_utilized 3.432237
system.ruby.network.routers2.msg_count.Request_Control::2 1196
system.ruby.network.routers2.msg_count.Response_Data::4 1179
system.ruby.network.routers2.msg_count.Writeback_Data::4 229
system.ruby.network.routers2.msg_count.Writeback_Control::4 967
system.ruby.network.routers2.msg_count.Writeback_Control::4 968
system.ruby.network.routers2.msg_count.Persistent_Control::3 26
system.ruby.network.routers2.msg_bytes.Request_Control::2 9560
system.ruby.network.routers2.msg_bytes.Response_Data::4 84816
system.ruby.network.routers2.msg_bytes.Request_Control::2 9568
system.ruby.network.routers2.msg_bytes.Response_Data::4 84888
system.ruby.network.routers2.msg_bytes.Writeback_Data::4 16488
system.ruby.network.routers2.msg_bytes.Writeback_Control::4 7736
system.ruby.network.routers2.msg_bytes.Writeback_Control::4 7744
system.ruby.network.routers2.msg_bytes.Persistent_Control::3 208
system.ruby.network.routers3.percent_links_utilized 4.662226
system.ruby.network.routers3.msg_count.Request_Control::1 1382
system.ruby.network.routers3.msg_count.Request_Control::2 1195
system.ruby.network.routers3.msg_count.Response_Data::4 1178
system.ruby.network.routers3.percent_links_utilized 4.665460
system.ruby.network.routers3.msg_count.Request_Control::1 1383
system.ruby.network.routers3.msg_count.Request_Control::2 1196
system.ruby.network.routers3.msg_count.Response_Data::4 1179
system.ruby.network.routers3.msg_count.ResponseL2hit_Data::4 204
system.ruby.network.routers3.msg_count.Response_Control::4 1
system.ruby.network.routers3.msg_count.Writeback_Data::4 1583
system.ruby.network.routers3.msg_count.Writeback_Control::4 967
system.ruby.network.routers3.msg_count.Writeback_Data::4 1584
system.ruby.network.routers3.msg_count.Writeback_Control::4 968
system.ruby.network.routers3.msg_count.Persistent_Control::3 52
system.ruby.network.routers3.msg_bytes.Request_Control::1 11056
system.ruby.network.routers3.msg_bytes.Request_Control::2 9560
system.ruby.network.routers3.msg_bytes.Response_Data::4 84816
system.ruby.network.routers3.msg_bytes.Request_Control::1 11064
system.ruby.network.routers3.msg_bytes.Request_Control::2 9568
system.ruby.network.routers3.msg_bytes.Response_Data::4 84888
system.ruby.network.routers3.msg_bytes.ResponseL2hit_Data::4 14688
system.ruby.network.routers3.msg_bytes.Response_Control::4 8
system.ruby.network.routers3.msg_bytes.Writeback_Data::4 113976
system.ruby.network.routers3.msg_bytes.Writeback_Control::4 7736
system.ruby.network.routers3.msg_bytes.Writeback_Data::4 114048
system.ruby.network.routers3.msg_bytes.Writeback_Control::4 7744
system.ruby.network.routers3.msg_bytes.Persistent_Control::3 416
system.ruby.network.msg_count.Request_Control 7731
system.ruby.network.msg_count.Response_Data 3534
system.ruby.network.msg_count.Request_Control 7737
system.ruby.network.msg_count.Response_Data 3537
system.ruby.network.msg_count.ResponseL2hit_Data 612
system.ruby.network.msg_count.Response_Control 3
system.ruby.network.msg_count.Writeback_Data 4749
system.ruby.network.msg_count.Writeback_Control 2901
system.ruby.network.msg_count.Writeback_Data 4752
system.ruby.network.msg_count.Writeback_Control 2904
system.ruby.network.msg_count.Persistent_Control 156
system.ruby.network.msg_byte.Request_Control 61848
system.ruby.network.msg_byte.Response_Data 254448
system.ruby.network.msg_byte.Request_Control 61896
system.ruby.network.msg_byte.Response_Data 254664
system.ruby.network.msg_byte.ResponseL2hit_Data 44064
system.ruby.network.msg_byte.Response_Control 24
system.ruby.network.msg_byte.Writeback_Data 341928
system.ruby.network.msg_byte.Writeback_Control 23208
system.ruby.network.msg_byte.Writeback_Data 342144
system.ruby.network.msg_byte.Writeback_Control 23232
system.ruby.network.msg_byte.Persistent_Control 1248
system.ruby.network.routers0.throttle0.link_utilization 5.757346
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1178
system.ruby.network.routers0.throttle0.link_utilization 5.761503
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1179
system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::4 204
system.ruby.network.routers0.throttle0.msg_count.Response_Control::4 1
system.ruby.network.routers0.throttle0.msg_count.Persistent_Control::3 26
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 84816
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 84888
system.ruby.network.routers0.throttle0.msg_bytes.ResponseL2hit_Data::4 14688
system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::4 8
system.ruby.network.routers0.throttle0.msg_bytes.Persistent_Control::3 208
system.ruby.network.routers0.throttle1.link_utilization 6.278810
system.ruby.network.routers0.throttle1.msg_count.Request_Control::1 1382
system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::4 1354
system.ruby.network.routers0.throttle1.link_utilization 6.283429
system.ruby.network.routers0.throttle1.msg_count.Request_Control::1 1383
system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::4 1355
system.ruby.network.routers0.throttle1.msg_count.Persistent_Control::3 26
system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::1 11056
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::4 97488
system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::1 11064
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::4 97560
system.ruby.network.routers0.throttle1.msg_bytes.Persistent_Control::3 208
system.ruby.network.routers1.throttle0.link_utilization 6.278810
system.ruby.network.routers1.throttle0.msg_count.Request_Control::1 1382
system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::4 1354
system.ruby.network.routers1.throttle0.link_utilization 6.283429
system.ruby.network.routers1.throttle0.msg_count.Request_Control::1 1383
system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::4 1355
system.ruby.network.routers1.throttle0.msg_count.Persistent_Control::3 26
system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::1 11056
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::4 97488
system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::1 11064
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::4 97560
system.ruby.network.routers1.throttle0.msg_bytes.Persistent_Control::3 208
system.ruby.network.routers1.throttle1.link_utilization 2.798999
system.ruby.network.routers1.throttle1.msg_count.Request_Control::2 1195
system.ruby.network.routers1.throttle1.link_utilization 2.799922
system.ruby.network.routers1.throttle1.msg_count.Request_Control::2 1196
system.ruby.network.routers1.throttle1.msg_count.ResponseL2hit_Data::4 204
system.ruby.network.routers1.throttle1.msg_count.Response_Control::4 1
system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::4 229
system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::4 967
system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::2 9560
system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::4 968
system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::2 9568
system.ruby.network.routers1.throttle1.msg_bytes.ResponseL2hit_Data::4 14688
system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::4 8
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::4 16488
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::4 7736
system.ruby.network.routers2.throttle0.link_utilization 1.962532
system.ruby.network.routers2.throttle0.msg_count.Request_Control::2 1195
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::4 7744
system.ruby.network.routers2.throttle0.link_utilization 1.963456
system.ruby.network.routers2.throttle0.msg_count.Request_Control::2 1196
system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::4 229
system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::4 967
system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::4 968
system.ruby.network.routers2.throttle0.msg_count.Persistent_Control::3 26
system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::2 9560
system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::2 9568
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::4 16488
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::4 7736
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::4 7744
system.ruby.network.routers2.throttle0.msg_bytes.Persistent_Control::3 208
system.ruby.network.routers2.throttle1.link_utilization 4.896862
system.ruby.network.routers2.throttle1.msg_count.Response_Data::4 1178
system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::4 84816
system.ruby.network.routers3.throttle0.link_utilization 5.745337
system.ruby.network.routers3.throttle0.msg_count.Response_Data::4 1178
system.ruby.network.routers2.throttle1.link_utilization 4.901019
system.ruby.network.routers2.throttle1.msg_count.Response_Data::4 1179
system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::4 84888
system.ruby.network.routers3.throttle0.link_utilization 5.749494
system.ruby.network.routers3.throttle0.msg_count.Response_Data::4 1179
system.ruby.network.routers3.throttle0.msg_count.ResponseL2hit_Data::4 204
system.ruby.network.routers3.throttle0.msg_count.Response_Control::4 1
system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::4 84816
system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::4 84888
system.ruby.network.routers3.throttle0.msg_bytes.ResponseL2hit_Data::4 14688
system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::4 8
system.ruby.network.routers3.throttle1.link_utilization 6.278810
system.ruby.network.routers3.throttle1.msg_count.Request_Control::1 1382
system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::4 1354
system.ruby.network.routers3.throttle1.link_utilization 6.283429
system.ruby.network.routers3.throttle1.msg_count.Request_Control::1 1383
system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::4 1355
system.ruby.network.routers3.throttle1.msg_count.Persistent_Control::3 26
system.ruby.network.routers3.throttle1.msg_bytes.Request_Control::1 11056
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::4 97488
system.ruby.network.routers3.throttle1.msg_bytes.Request_Control::1 11064
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::4 97560
system.ruby.network.routers3.throttle1.msg_bytes.Persistent_Control::3 208
system.ruby.network.routers3.throttle2.link_utilization 1.962532
system.ruby.network.routers3.throttle2.msg_count.Request_Control::2 1195
system.ruby.network.routers3.throttle2.link_utilization 1.963456
system.ruby.network.routers3.throttle2.msg_count.Request_Control::2 1196
system.ruby.network.routers3.throttle2.msg_count.Writeback_Data::4 229
system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::4 967
system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::4 968
system.ruby.network.routers3.throttle2.msg_count.Persistent_Control::3 26
system.ruby.network.routers3.throttle2.msg_bytes.Request_Control::2 9560
system.ruby.network.routers3.throttle2.msg_bytes.Request_Control::2 9568
system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Data::4 16488
system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Control::4 7736
system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Control::4 7744
system.ruby.network.routers3.throttle2.msg_bytes.Persistent_Control::3 208
system.ruby.LD.latency_hist_seqr::bucket_size 64
system.ruby.LD.latency_hist_seqr::max_bucket 639
system.ruby.LD.latency_hist_seqr::samples 1183
system.ruby.LD.latency_hist_seqr::mean 28.775148
system.ruby.LD.latency_hist_seqr::gmean 6.010104
system.ruby.LD.latency_hist_seqr::stdev 37.379747
system.ruby.LD.latency_hist_seqr | 842 71.17% 71.17% | 336 28.40% 99.58% | 2 0.17% 99.75% | 0 0.00% 99.75% | 2 0.17% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.latency_hist_seqr::total 1183
system.ruby.LD.latency_hist_seqr::samples 1185
system.ruby.LD.latency_hist_seqr::mean 28.779747
system.ruby.LD.latency_hist_seqr::gmean 6.012520
system.ruby.LD.latency_hist_seqr::stdev 37.360727
system.ruby.LD.latency_hist_seqr | 843 71.14% 71.14% | 337 28.44% 99.58% | 2 0.17% 99.75% | 0 0.00% 99.75% | 2 0.17% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.latency_hist_seqr::total 1185
system.ruby.LD.hit_latency_hist_seqr::bucket_size 4
system.ruby.LD.hit_latency_hist_seqr::max_bucket 39
system.ruby.LD.hit_latency_hist_seqr::samples 758
system.ruby.LD.hit_latency_hist_seqr::mean 4.034301
system.ruby.LD.hit_latency_hist_seqr::gmean 1.520848
system.ruby.LD.hit_latency_hist_seqr::stdev 7.788579
system.ruby.LD.hit_latency_hist_seqr | 658 86.81% 86.81% | 0 0.00% 86.81% | 0 0.00% 86.81% | 0 0.00% 86.81% | 0 0.00% 86.81% | 0 0.00% 86.81% | 100 13.19% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.hit_latency_hist_seqr::total 758
system.ruby.LD.hit_latency_hist_seqr::samples 759
system.ruby.LD.hit_latency_hist_seqr::mean 4.030303
system.ruby.LD.hit_latency_hist_seqr::gmean 1.520008
system.ruby.LD.hit_latency_hist_seqr::stdev 7.784219
system.ruby.LD.hit_latency_hist_seqr | 659 86.82% 86.82% | 0 0.00% 86.82% | 0 0.00% 86.82% | 0 0.00% 86.82% | 0 0.00% 86.82% | 0 0.00% 86.82% | 100 13.18% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.hit_latency_hist_seqr::total 759
system.ruby.LD.miss_latency_hist_seqr::bucket_size 64
system.ruby.LD.miss_latency_hist_seqr::max_bucket 639
system.ruby.LD.miss_latency_hist_seqr::samples 425
system.ruby.LD.miss_latency_hist_seqr::mean 72.901176
system.ruby.LD.miss_latency_hist_seqr::gmean 69.708423
system.ruby.LD.miss_latency_hist_seqr::stdev 27.218709
system.ruby.LD.miss_latency_hist_seqr | 84 19.76% 19.76% | 336 79.06% 98.82% | 2 0.47% 99.29% | 0 0.00% 99.29% | 2 0.47% 99.76% | 1 0.24% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.miss_latency_hist_seqr::total 425
system.ruby.LD.miss_latency_hist_seqr::samples 426
system.ruby.LD.miss_latency_hist_seqr::mean 72.875587
system.ruby.LD.miss_latency_hist_seqr::gmean 69.678801
system.ruby.LD.miss_latency_hist_seqr::stdev 27.158723
system.ruby.LD.miss_latency_hist_seqr | 84 19.72% 19.72% | 337 79.11% 98.83% | 2 0.47% 99.30% | 0 0.00% 99.30% | 2 0.47% 99.77% | 1 0.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.miss_latency_hist_seqr::total 426
system.ruby.ST.latency_hist_seqr::bucket_size 32
system.ruby.ST.latency_hist_seqr::max_bucket 319
system.ruby.ST.latency_hist_seqr::samples 865
system.ruby.ST.latency_hist_seqr::mean 14.011561
system.ruby.ST.latency_hist_seqr::gmean 2.583043
system.ruby.ST.latency_hist_seqr::stdev 26.009033
system.ruby.ST.latency_hist_seqr::mean 13.996532
system.ruby.ST.latency_hist_seqr::gmean 2.581393
system.ruby.ST.latency_hist_seqr::stdev 26.004028
system.ruby.ST.latency_hist_seqr | 697 80.58% 80.58% | 78 9.02% 89.60% | 85 9.83% 99.42% | 3 0.35% 99.77% | 0 0.00% 99.77% | 1 0.12% 99.88% | 1 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.latency_hist_seqr::total 865
system.ruby.ST.hit_latency_hist_seqr::bucket_size 4
system.ruby.ST.hit_latency_hist_seqr::max_bucket 39
system.ruby.ST.hit_latency_hist_seqr::samples 697
system.ruby.ST.hit_latency_hist_seqr::mean 2.321377
system.ruby.ST.hit_latency_hist_seqr::gmean 1.211206
system.ruby.ST.hit_latency_hist_seqr::stdev 5.179814
system.ruby.ST.hit_latency_hist_seqr | 654 93.83% 93.83% | 0 0.00% 93.83% | 0 0.00% 93.83% | 0 0.00% 93.83% | 0 0.00% 93.83% | 17 2.44% 96.27% | 26 3.73% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.hit_latency_hist_seqr::mean 2.305595
system.ruby.ST.hit_latency_hist_seqr::gmean 1.210352
system.ruby.ST.hit_latency_hist_seqr::stdev 5.118132
system.ruby.ST.hit_latency_hist_seqr | 654 93.83% 93.83% | 0 0.00% 93.83% | 0 0.00% 93.83% | 0 0.00% 93.83% | 0 0.00% 93.83% | 21 3.01% 96.84% | 22 3.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.hit_latency_hist_seqr::total 697
system.ruby.ST.miss_latency_hist_seqr::bucket_size 32
system.ruby.ST.miss_latency_hist_seqr::max_bucket 319
system.ruby.ST.miss_latency_hist_seqr::samples 168
system.ruby.ST.miss_latency_hist_seqr::mean 62.511905
system.ruby.ST.miss_latency_hist_seqr::gmean 59.804102
system.ruby.ST.miss_latency_hist_seqr::stdev 21.242819
system.ruby.ST.miss_latency_hist_seqr::mean 62.500000
system.ruby.ST.miss_latency_hist_seqr::gmean 59.782556
system.ruby.ST.miss_latency_hist_seqr::stdev 21.264516
system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 78 46.43% 46.43% | 85 50.60% 97.02% | 3 1.79% 98.81% | 0 0.00% 98.81% | 1 0.60% 99.40% | 1 0.60% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.miss_latency_hist_seqr::total 168
system.ruby.IFETCH.latency_hist_seqr::bucket_size 64
system.ruby.IFETCH.latency_hist_seqr::max_bucket 639
system.ruby.IFETCH.latency_hist_seqr::samples 6400
system.ruby.IFETCH.latency_hist_seqr::mean 8.381875
system.ruby.IFETCH.latency_hist_seqr::gmean 1.532979
system.ruby.IFETCH.latency_hist_seqr::stdev 24.412953
system.ruby.IFETCH.latency_hist_seqr | 5815 90.86% 90.86% | 571 8.92% 99.78% | 5 0.08% 99.86% | 2 0.03% 99.89% | 4 0.06% 99.95% | 3 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.latency_hist_seqr::total 6400
system.ruby.IFETCH.latency_hist_seqr::samples 6413
system.ruby.IFETCH.latency_hist_seqr::mean 8.354748
system.ruby.IFETCH.latency_hist_seqr::gmean 1.531676
system.ruby.IFETCH.latency_hist_seqr::stdev 24.237273
system.ruby.IFETCH.latency_hist_seqr | 5828 90.88% 90.88% | 571 8.90% 99.78% | 5 0.08% 99.86% | 3 0.05% 99.91% | 3 0.05% 99.95% | 3 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.latency_hist_seqr::total 6413
system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 8
system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 79
system.ruby.IFETCH.hit_latency_hist_seqr::samples 5815
system.ruby.IFETCH.hit_latency_hist_seqr::mean 1.243164
system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1.033952
system.ruby.IFETCH.hit_latency_hist_seqr::stdev 2.371578
system.ruby.IFETCH.hit_latency_hist_seqr | 5754 98.95% 98.95% | 0 0.00% 98.95% | 2 0.03% 98.99% | 58 1.00% 99.98% | 0 0.00% 99.98% | 1 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.hit_latency_hist_seqr::total 5815
system.ruby.IFETCH.hit_latency_hist_seqr::samples 5828
system.ruby.IFETCH.hit_latency_hist_seqr::mean 1.243480
system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1.033914
system.ruby.IFETCH.hit_latency_hist_seqr::stdev 2.376718
system.ruby.IFETCH.hit_latency_hist_seqr | 5767 98.95% 98.95% | 0 0.00% 98.95% | 0 0.00% 98.95% | 60 1.03% 99.98% | 0 0.00% 99.98% | 1 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.hit_latency_hist_seqr::total 5828
system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64
system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639
system.ruby.IFETCH.miss_latency_hist_seqr::samples 585
system.ruby.IFETCH.miss_latency_hist_seqr::mean 79.341880
system.ruby.IFETCH.miss_latency_hist_seqr::gmean 76.853466
system.ruby.IFETCH.miss_latency_hist_seqr::stdev 30.381468
system.ruby.IFETCH.miss_latency_hist_seqr | 0 0.00% 0.00% | 571 97.61% 97.61% | 5 0.85% 98.46% | 2 0.34% 98.80% | 4 0.68% 99.49% | 3 0.51% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.miss_latency_hist_seqr::mean 79.200000
system.ruby.IFETCH.miss_latency_hist_seqr::gmean 76.837583
system.ruby.IFETCH.miss_latency_hist_seqr::stdev 29.345532
system.ruby.IFETCH.miss_latency_hist_seqr | 0 0.00% 0.00% | 571 97.61% 97.61% | 5 0.85% 98.46% | 3 0.51% 98.97% | 3 0.51% 99.49% | 3 0.51% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.miss_latency_hist_seqr::total 585
system.ruby.L1Cache.hit_mach_latency_hist_seqr::bucket_size 1
system.ruby.L1Cache.hit_mach_latency_hist_seqr::max_bucket 9
system.ruby.L1Cache.hit_mach_latency_hist_seqr::samples 7066
system.ruby.L1Cache.hit_mach_latency_hist_seqr::samples 7080
system.ruby.L1Cache.hit_mach_latency_hist_seqr::mean 1
system.ruby.L1Cache.hit_mach_latency_hist_seqr::gmean 1
system.ruby.L1Cache.hit_mach_latency_hist_seqr | 0 0.00% 0.00% | 7066 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.L1Cache.hit_mach_latency_hist_seqr::total 7066
system.ruby.L1Cache.hit_mach_latency_hist_seqr | 0 0.00% 0.00% | 7080 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.L1Cache.hit_mach_latency_hist_seqr::total 7080
system.ruby.L2Cache.hit_mach_latency_hist_seqr::bucket_size 8
system.ruby.L2Cache.hit_mach_latency_hist_seqr::max_bucket 79
system.ruby.L2Cache.hit_mach_latency_hist_seqr::samples 204
system.ruby.L2Cache.hit_mach_latency_hist_seqr::mean 23.720588
system.ruby.L2Cache.hit_mach_latency_hist_seqr::gmean 23.671773
system.ruby.L2Cache.hit_mach_latency_hist_seqr::stdev 1.608281
system.ruby.L2Cache.hit_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 19 9.31% 9.31% | 184 90.20% 99.51% | 0 0.00% 99.51% | 1 0.49% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.L2Cache.hit_mach_latency_hist_seqr::mean 23.691176
system.ruby.L2Cache.hit_mach_latency_hist_seqr::gmean 23.640301
system.ruby.L2Cache.hit_mach_latency_hist_seqr::stdev 1.636324
system.ruby.L2Cache.hit_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 21 10.29% 10.29% | 182 89.22% 99.51% | 0 0.00% 99.51% | 1 0.49% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.L2Cache.hit_mach_latency_hist_seqr::total 204
system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64
system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639
system.ruby.Directory.miss_mach_latency_hist_seqr::samples 1178
system.ruby.Directory.miss_mach_latency_hist_seqr::mean 74.617997
system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 71.587772
system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 28.670099
system.ruby.Directory.miss_mach_latency_hist_seqr | 162 13.75% 13.75% | 995 84.47% 98.22% | 8 0.68% 98.90% | 3 0.25% 99.15% | 6 0.51% 99.66% | 4 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.Directory.miss_mach_latency_hist_seqr::total 1178
system.ruby.Directory.miss_mach_latency_hist_seqr::samples 1179
system.ruby.Directory.miss_mach_latency_hist_seqr::mean 74.535199
system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 71.564149
system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 28.099799
system.ruby.Directory.miss_mach_latency_hist_seqr | 162 13.74% 13.74% | 996 84.48% 98.22% | 8 0.68% 98.90% | 4 0.34% 99.24% | 5 0.42% 99.66% | 4 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.Directory.miss_mach_latency_hist_seqr::total 1179
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 1
@ -661,11 +661,11 @@ system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion |
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1
system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1
system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9
system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::samples 658
system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::samples 659
system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::mean 1
system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::gmean 1
system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 658 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::total 658
system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 659 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::total 659
system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 4
system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 39
system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::samples 100
@ -675,12 +675,12 @@ system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00%
system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::total 100
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 425
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 72.901176
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 69.708423
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 27.218709
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 84 19.76% 19.76% | 336 79.06% 98.82% | 2 0.47% 99.29% | 0 0.00% 99.29% | 2 0.47% 99.76% | 1 0.24% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 425
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 426
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 72.875587
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 69.678801
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 27.158723
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 84 19.72% 19.72% | 337 79.11% 98.83% | 2 0.47% 99.30% | 0 0.00% 99.30% | 2 0.47% 99.77% | 1 0.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 426
system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1
system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9
system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::samples 654
@ -691,99 +691,99 @@ system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::total 654
system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 4
system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 39
system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::samples 43
system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::mean 22.418605
system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::gmean 22.330941
system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::stdev 1.978847
system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 17 39.53% 39.53% | 26 60.47% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::mean 22.162791
system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::gmean 22.076919
system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::stdev 1.963115
system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 21 48.84% 48.84% | 22 51.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::total 43
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 168
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 62.511905
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 59.804102
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 21.242819
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 62.500000
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 59.782556
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 21.264516
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 78 46.43% 46.43% | 85 50.60% 97.02% | 3 1.79% 98.81% | 0 0.00% 98.81% | 1 0.60% 99.40% | 1 0.60% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 168
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::samples 5754
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::samples 5767
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::mean 1
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::gmean 1
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 5754 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::total 5754
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 5767 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::total 5767
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 8
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 79
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::samples 61
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::mean 24.180328
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::gmean 24.114482
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::stdev 2.109567
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 3.28% 3.28% | 58 95.08% 98.36% | 0 0.00% 98.36% | 1 1.64% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::mean 24.262295
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::gmean 24.201824
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::stdev 2.048590
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 60 98.36% 98.36% | 0 0.00% 98.36% | 1 1.64% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::total 61
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 585
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 79.341880
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 76.853466
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 30.381468
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 571 97.61% 97.61% | 5 0.85% 98.46% | 2 0.34% 98.80% | 4 0.68% 99.49% | 3 0.51% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 79.200000
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 76.837583
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 29.345532
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 571 97.61% 97.61% | 5 0.85% 98.46% | 3 0.51% 98.97% | 3 0.51% 99.49% | 3 0.51% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 585
system.ruby.Directory_Controller.GETX 208 0.00% 0.00%
system.ruby.Directory_Controller.GETS 1016 0.00% 0.00%
system.ruby.Directory_Controller.GETS 1017 0.00% 0.00%
system.ruby.Directory_Controller.Lockdown 13 0.00% 0.00%
system.ruby.Directory_Controller.Unlockdown 13 0.00% 0.00%
system.ruby.Directory_Controller.Data_Owner 9 0.00% 0.00%
system.ruby.Directory_Controller.Data_All_Tokens 220 0.00% 0.00%
system.ruby.Directory_Controller.Ack_Owner 29 0.00% 0.00%
system.ruby.Directory_Controller.Ack_Owner_All_Tokens 904 0.00% 0.00%
system.ruby.Directory_Controller.Ack_Owner_All_Tokens 905 0.00% 0.00%
system.ruby.Directory_Controller.Ack_All_Tokens 34 0.00% 0.00%
system.ruby.Directory_Controller.Memory_Data 1178 0.00% 0.00%
system.ruby.Directory_Controller.Memory_Data 1179 0.00% 0.00%
system.ruby.Directory_Controller.Memory_Ack 229 0.00% 0.00%
system.ruby.Directory_Controller.O.GETX 168 0.00% 0.00%
system.ruby.Directory_Controller.O.GETS 1010 0.00% 0.00%
system.ruby.Directory_Controller.O.GETS 1011 0.00% 0.00%
system.ruby.Directory_Controller.O.Ack_All_Tokens 34 0.00% 0.00%
system.ruby.Directory_Controller.NO.GETX 17 0.00% 0.00%
system.ruby.Directory_Controller.NO.Lockdown 2 0.00% 0.00%
system.ruby.Directory_Controller.NO.Data_Owner 9 0.00% 0.00%
system.ruby.Directory_Controller.NO.Data_All_Tokens 220 0.00% 0.00%
system.ruby.Directory_Controller.NO.Ack_Owner 29 0.00% 0.00%
system.ruby.Directory_Controller.NO.Ack_Owner_All_Tokens 904 0.00% 0.00%
system.ruby.Directory_Controller.NO.Ack_Owner_All_Tokens 905 0.00% 0.00%
system.ruby.Directory_Controller.L.Unlockdown 13 0.00% 0.00%
system.ruby.Directory_Controller.O_W.GETX 23 0.00% 0.00%
system.ruby.Directory_Controller.O_W.GETS 6 0.00% 0.00%
system.ruby.Directory_Controller.O_W.Memory_Ack 229 0.00% 0.00%
system.ruby.Directory_Controller.L_NO_W.Memory_Data 11 0.00% 0.00%
system.ruby.Directory_Controller.NO_W.Lockdown 11 0.00% 0.00%
system.ruby.Directory_Controller.NO_W.Memory_Data 1167 0.00% 0.00%
system.ruby.L1Cache_Controller.Load 1183 0.00% 0.00%
system.ruby.L1Cache_Controller.Ifetch 6400 0.00% 0.00%
system.ruby.Directory_Controller.NO_W.Memory_Data 1168 0.00% 0.00%
system.ruby.L1Cache_Controller.Load 1185 0.00% 0.00%
system.ruby.L1Cache_Controller.Ifetch 6413 0.00% 0.00%
system.ruby.L1Cache_Controller.Store 865 0.00% 0.00%
system.ruby.L1Cache_Controller.L1_Replacement 1367 0.00% 0.00%
system.ruby.L1Cache_Controller.L1_Replacement 1368 0.00% 0.00%
system.ruby.L1Cache_Controller.Data_Shared 161 0.00% 0.00%
system.ruby.L1Cache_Controller.Data_All_Tokens 1221 0.00% 0.00%
system.ruby.L1Cache_Controller.Data_All_Tokens 1222 0.00% 0.00%
system.ruby.L1Cache_Controller.Ack 1 0.00% 0.00%
system.ruby.L1Cache_Controller.Own_Lock_or_Unlock 26 0.00% 0.00%
system.ruby.L1Cache_Controller.Request_Timeout 13 0.00% 0.00%
system.ruby.L1Cache_Controller.Use_TimeoutNoStarvers 1220 0.00% 0.00%
system.ruby.L1Cache_Controller.NP.Load 525 0.00% 0.00%
system.ruby.L1Cache_Controller.Use_TimeoutNoStarvers 1221 0.00% 0.00%
system.ruby.L1Cache_Controller.NP.Load 526 0.00% 0.00%
system.ruby.L1Cache_Controller.NP.Ifetch 646 0.00% 0.00%
system.ruby.L1Cache_Controller.NP.Store 191 0.00% 0.00%
system.ruby.L1Cache_Controller.S.Load 153 0.00% 0.00%
system.ruby.L1Cache_Controller.S.Ifetch 331 0.00% 0.00%
system.ruby.L1Cache_Controller.S.Store 20 0.00% 0.00%
system.ruby.L1Cache_Controller.S.L1_Replacement 141 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Load 180 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Ifetch 3187 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Load 181 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Ifetch 3194 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Store 33 0.00% 0.00%
system.ruby.L1Cache_Controller.M.L1_Replacement 945 0.00% 0.00%
system.ruby.L1Cache_Controller.M.L1_Replacement 946 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Own_Lock_or_Unlock 13 0.00% 0.00%
system.ruby.L1Cache_Controller.MM.Load 218 0.00% 0.00%
system.ruby.L1Cache_Controller.MM.Store 265 0.00% 0.00%
system.ruby.L1Cache_Controller.MM.L1_Replacement 268 0.00% 0.00%
system.ruby.L1Cache_Controller.M_W.Load 84 0.00% 0.00%
system.ruby.L1Cache_Controller.M_W.Ifetch 2236 0.00% 0.00%
system.ruby.L1Cache_Controller.M_W.Ifetch 2242 0.00% 0.00%
system.ruby.L1Cache_Controller.M_W.Store 25 0.00% 0.00%
system.ruby.L1Cache_Controller.M_W.L1_Replacement 9 0.00% 0.00%
system.ruby.L1Cache_Controller.M_W.Use_TimeoutNoStarvers 984 0.00% 0.00%
system.ruby.L1Cache_Controller.M_W.Use_TimeoutNoStarvers 985 0.00% 0.00%
system.ruby.L1Cache_Controller.MM_W.Load 23 0.00% 0.00%
system.ruby.L1Cache_Controller.MM_W.Store 331 0.00% 0.00%
system.ruby.L1Cache_Controller.MM_W.L1_Replacement 4 0.00% 0.00%
@ -792,21 +792,21 @@ system.ruby.L1Cache_Controller.IM.Data_All_Tokens 191 0.00% 0
system.ruby.L1Cache_Controller.IM.Ack 1 0.00% 0.00%
system.ruby.L1Cache_Controller.SM.Data_All_Tokens 20 0.00% 0.00%
system.ruby.L1Cache_Controller.IS.Data_Shared 161 0.00% 0.00%
system.ruby.L1Cache_Controller.IS.Data_All_Tokens 1010 0.00% 0.00%
system.ruby.L1Cache_Controller.IS.Data_All_Tokens 1011 0.00% 0.00%
system.ruby.L1Cache_Controller.IS.Own_Lock_or_Unlock 13 0.00% 0.00%
system.ruby.L1Cache_Controller.IS.Request_Timeout 13 0.00% 0.00%
system.ruby.L2Cache_Controller.L1_GETS 1122 0.00% 0.00%
system.ruby.L2Cache_Controller.L1_GETS 1123 0.00% 0.00%
system.ruby.L2Cache_Controller.L1_GETS_Last_Token 49 0.00% 0.00%
system.ruby.L2Cache_Controller.L1_GETX 211 0.00% 0.00%
system.ruby.L2Cache_Controller.L2_Replacement 1265 0.00% 0.00%
system.ruby.L2Cache_Controller.L2_Replacement 1266 0.00% 0.00%
system.ruby.L2Cache_Controller.Writeback_Shared_Data 84 0.00% 0.00%
system.ruby.L2Cache_Controller.Writeback_All_Tokens 1270 0.00% 0.00%
system.ruby.L2Cache_Controller.Writeback_All_Tokens 1271 0.00% 0.00%
system.ruby.L2Cache_Controller.Persistent_GETS 13 0.00% 0.00%
system.ruby.L2Cache_Controller.Own_Lock_or_Unlock 13 0.00% 0.00%
system.ruby.L2Cache_Controller.NP.L1_GETS 1010 0.00% 0.00%
system.ruby.L2Cache_Controller.NP.L1_GETS 1011 0.00% 0.00%
system.ruby.L2Cache_Controller.NP.L1_GETX 166 0.00% 0.00%
system.ruby.L2Cache_Controller.NP.Writeback_Shared_Data 81 0.00% 0.00%
system.ruby.L2Cache_Controller.NP.Writeback_All_Tokens 1192 0.00% 0.00%
system.ruby.L2Cache_Controller.NP.Writeback_All_Tokens 1193 0.00% 0.00%
system.ruby.L2Cache_Controller.NP.Own_Lock_or_Unlock 13 0.00% 0.00%
system.ruby.L2Cache_Controller.I.L1_GETX 1 0.00% 0.00%
system.ruby.L2Cache_Controller.I.L2_Replacement 69 0.00% 0.00%
@ -820,7 +820,7 @@ system.ruby.L2Cache_Controller.O.L2_Replacement 38 0.00% 0.0
system.ruby.L2Cache_Controller.O.Writeback_All_Tokens 57 0.00% 0.00%
system.ruby.L2Cache_Controller.M.L1_GETS 112 0.00% 0.00%
system.ruby.L2Cache_Controller.M.L1_GETX 26 0.00% 0.00%
system.ruby.L2Cache_Controller.M.L2_Replacement 1124 0.00% 0.00%
system.ruby.L2Cache_Controller.M.L2_Replacement 1125 0.00% 0.00%
system.ruby.L2Cache_Controller.I_L.Persistent_GETS 13 0.00% 0.00%
---------- End Simulation Statistics ----------

2
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
View file

@ -120,7 +120,7 @@ env=
errout=cerr
euid=100
eventq_index=0
executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
kvmInSE=false

12
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
View file

@ -1,13 +1,15 @@
Redirecting stdout to build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
Redirecting stderr to build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 21 2016 13:56:08
gem5 started Jan 21 2016 13:56:42
gem5 executing on zizzer, pid 39359
command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer
gem5 compiled Mar 14 2016 21:55:52
gem5 started Mar 14 2016 21:57:33
gem5 executing on phenom, pid 28167
command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
Exiting @ tick 86673 because target called exit()
Exiting @ tick 86770 because target called exit()

652
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
View file

@ -1,40 +1,40 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000087 # Number of seconds simulated
sim_ticks 86673 # Number of ticks simulated
final_tick 86673 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 86770 # Number of ticks simulated
final_tick 86770 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_inst_rate 58973 # Simulator instruction rate (inst/s)
host_op_rate 58962 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 799609 # Simulator tick rate (ticks/s)
host_mem_usage 411856 # Number of bytes of host memory used
host_seconds 0.11 # Real time elapsed on the host
sim_insts 6390 # Number of instructions simulated
sim_ops 6390 # Number of ops (including micro ops) simulated
host_inst_rate 43915 # Simulator instruction rate (inst/s)
host_op_rate 43910 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 594975 # Simulator tick rate (ticks/s)
host_mem_usage 388108 # Number of bytes of host memory used
host_seconds 0.15 # Real time elapsed on the host
sim_insts 6403 # Number of instructions simulated
sim_ops 6403 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 74176 # Number of bytes read from this memory
system.mem_ctrls.bytes_read::total 74176 # Number of bytes read from this memory
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 74240 # Number of bytes read from this memory
system.mem_ctrls.bytes_read::total 74240 # Number of bytes read from this memory
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 14080 # Number of bytes written to this memory
system.mem_ctrls.bytes_written::total 14080 # Number of bytes written to this memory
system.mem_ctrls.num_reads::ruby.dir_cntrl0 1159 # Number of read requests responded to by this memory
system.mem_ctrls.num_reads::total 1159 # Number of read requests responded to by this memory
system.mem_ctrls.num_reads::ruby.dir_cntrl0 1160 # Number of read requests responded to by this memory
system.mem_ctrls.num_reads::total 1160 # Number of read requests responded to by this memory
system.mem_ctrls.num_writes::ruby.dir_cntrl0 220 # Number of write requests responded to by this memory
system.mem_ctrls.num_writes::total 220 # Number of write requests responded to by this memory
system.mem_ctrls.bw_read::ruby.dir_cntrl0 855814383 # Total read bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_read::total 855814383 # Total read bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_write::ruby.dir_cntrl0 162449667 # Write bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_write::total 162449667 # Write bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_total::ruby.dir_cntrl0 1018264050 # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.bw_total::total 1018264050 # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.readReqs 1159 # Number of read requests accepted
system.mem_ctrls.bw_read::ruby.dir_cntrl0 855595252 # Total read bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_read::total 855595252 # Total read bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_write::ruby.dir_cntrl0 162268065 # Write bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_write::total 162268065 # Write bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_total::ruby.dir_cntrl0 1017863317 # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.bw_total::total 1017863317 # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.readReqs 1160 # Number of read requests accepted
system.mem_ctrls.writeReqs 220 # Number of write requests accepted
system.mem_ctrls.readBursts 1159 # Number of DRAM read bursts, including those serviced by the write queue
system.mem_ctrls.readBursts 1160 # Number of DRAM read bursts, including those serviced by the write queue
system.mem_ctrls.writeBursts 220 # Number of DRAM write bursts, including those merged in the write queue
system.mem_ctrls.bytesReadDRAM 63680 # Total number of bytes read from DRAM
system.mem_ctrls.bytesReadDRAM 63744 # Total number of bytes read from DRAM
system.mem_ctrls.bytesReadWrQ 10496 # Total number of bytes read from write queue
system.mem_ctrls.bytesWritten 5504 # Total number of bytes written to DRAM
system.mem_ctrls.bytesReadSys 74176 # Total read bytes from the system interface side
system.mem_ctrls.bytesReadSys 74240 # Total read bytes from the system interface side
system.mem_ctrls.bytesWrittenSys 14080 # Total written bytes from the system interface side
system.mem_ctrls.servicedByWrQ 164 # Number of DRAM read bursts serviced by the write queue
system.mem_ctrls.mergedWrBursts 109 # Number of DRAM write bursts merged with an existing one
@ -54,7 +54,7 @@ system.mem_ctrls.perBankRdBursts::11 47 # Pe
system.mem_ctrls.perBankRdBursts::12 22 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::13 358 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::14 61 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::15 40 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::15 41 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts
@ -73,14 +73,14 @@ system.mem_ctrls.perBankWrBursts::14 42 # Pe
system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
system.mem_ctrls.totGap 86601 # Total gap between requests
system.mem_ctrls.totGap 86698 # Total gap between requests
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::6 1159 # Read request sizes (log2)
system.mem_ctrls.readPktSize::6 1160 # Read request sizes (log2)
system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
@ -88,7 +88,7 @@ system.mem_ctrls.writePktSize::3 0 # Wr
system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::6 220 # Write request sizes (log2)
system.mem_ctrls.rdQLenPdf::0 995 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::0 996 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
@ -184,24 +184,24 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh
system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.mem_ctrls.bytesPerActivate::samples 190 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::mean 360.757895 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::gmean 214.175980 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::stdev 351.466789 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::0-127 60 31.58% 31.58% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::128-255 43 22.63% 54.21% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::256-383 19 10.00% 64.21% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::384-511 13 6.84% 71.05% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::512-639 11 5.79% 76.84% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::640-767 4 2.11% 78.95% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::768-895 8 4.21% 83.16% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::896-1023 5 2.63% 85.79% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::1024-1151 27 14.21% 100.00% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::total 190 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::samples 191 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::mean 358.869110 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::gmean 215.937059 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::stdev 347.377875 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::0-127 57 29.84% 29.84% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::128-255 46 24.08% 53.93% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::256-383 20 10.47% 64.40% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::384-511 14 7.33% 71.73% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::512-639 10 5.24% 76.96% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::640-767 4 2.09% 79.06% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::768-895 7 3.66% 82.72% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::896-1023 8 4.19% 86.91% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::1024-1151 25 13.09% 100.00% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::total 191 # Bytes accessed per row activation
system.mem_ctrls.rdPerTurnAround::samples 5 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::mean 143.200000 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::gmean 107.762756 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::stdev 83.250826 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::mean 143.400000 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::gmean 107.861440 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::stdev 83.476344 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::16-23 1 20.00% 20.00% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::120-127 1 20.00% 40.00% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::128-135 1 20.00% 60.00% # Reads before turning the bus around for writes
@ -214,77 +214,77 @@ system.mem_ctrls.wrPerTurnAround::stdev 1.095445 # Wr
system.mem_ctrls.wrPerTurnAround::16 2 40.00% 40.00% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::18 3 60.00% 100.00% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::total 5 # Writes before turning the bus around for reads
system.mem_ctrls.totQLat 6132 # Total ticks spent queuing
system.mem_ctrls.totMemAccLat 25037 # Total ticks spent from burst creation until serviced by the DRAM
system.mem_ctrls.totBusLat 4975 # Total ticks spent in databus transfers
system.mem_ctrls.avgQLat 6.16 # Average queueing delay per DRAM burst
system.mem_ctrls.totQLat 6142 # Total ticks spent queuing
system.mem_ctrls.totMemAccLat 25066 # Total ticks spent from burst creation until serviced by the DRAM
system.mem_ctrls.totBusLat 4980 # Total ticks spent in databus transfers
system.mem_ctrls.avgQLat 6.17 # Average queueing delay per DRAM burst
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
system.mem_ctrls.avgMemAccLat 25.16 # Average memory access latency per DRAM burst
system.mem_ctrls.avgRdBW 734.72 # Average DRAM read bandwidth in MiByte/s
system.mem_ctrls.avgWrBW 63.50 # Average achieved write bandwidth in MiByte/s
system.mem_ctrls.avgRdBWSys 855.81 # Average system read bandwidth in MiByte/s
system.mem_ctrls.avgWrBWSys 162.45 # Average system write bandwidth in MiByte/s
system.mem_ctrls.avgMemAccLat 25.17 # Average memory access latency per DRAM burst
system.mem_ctrls.avgRdBW 734.63 # Average DRAM read bandwidth in MiByte/s
system.mem_ctrls.avgWrBW 63.43 # Average achieved write bandwidth in MiByte/s
system.mem_ctrls.avgRdBWSys 855.60 # Average system read bandwidth in MiByte/s
system.mem_ctrls.avgWrBWSys 162.27 # Average system write bandwidth in MiByte/s
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.mem_ctrls.busUtil 6.24 # Data bus utilization in percentage
system.mem_ctrls.busUtil 6.23 # Data bus utilization in percentage
system.mem_ctrls.busUtilRead 5.74 # Data bus utilization in percentage for reads
system.mem_ctrls.busUtilWrite 0.50 # Data bus utilization in percentage for writes
system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing
system.mem_ctrls.avgWrQLen 20.56 # Average write queue length when enqueuing
system.mem_ctrls.avgWrQLen 20.55 # Average write queue length when enqueuing
system.mem_ctrls.readRowHits 808 # Number of row buffer hits during reads
system.mem_ctrls.writeRowHits 78 # Number of row buffer hits during writes
system.mem_ctrls.readRowHitRate 81.21 # Row buffer hit rate for reads
system.mem_ctrls.readRowHitRate 81.12 # Row buffer hit rate for reads
system.mem_ctrls.writeRowHitRate 70.27 # Row buffer hit rate for writes
system.mem_ctrls.avgGap 62.80 # Average gap between requests
system.mem_ctrls.pageHitRate 80.11 # Row buffer hit rate, read and write combined
system.mem_ctrls_0.actEnergy 461160 # Energy for activate commands per rank (pJ)
system.mem_ctrls_0.preEnergy 256200 # Energy for precharge commands per rank (pJ)
system.mem_ctrls.avgGap 62.82 # Average gap between requests
system.mem_ctrls.pageHitRate 80.04 # Row buffer hit rate, read and write combined
system.mem_ctrls_0.actEnergy 476280 # Energy for activate commands per rank (pJ)
system.mem_ctrls_0.preEnergy 264600 # Energy for precharge commands per rank (pJ)
system.mem_ctrls_0.readEnergy 5091840 # Energy for read commands per rank (pJ)
system.mem_ctrls_0.writeEnergy 259200 # Energy for write commands per rank (pJ)
system.mem_ctrls_0.refreshEnergy 5594160 # Energy for refresh commands per rank (pJ)
system.mem_ctrls_0.actBackEnergy 49992876 # Energy for active background per rank (pJ)
system.mem_ctrls_0.preBackEnergy 7690200 # Energy for precharge background per rank (pJ)
system.mem_ctrls_0.totalEnergy 69345636 # Total energy per rank (pJ)
system.mem_ctrls_0.averagePower 807.226922 # Core power per rank (mW)
system.mem_ctrls_0.memoryStateTime::IDLE 12934 # Time in different power states
system.mem_ctrls_0.actBackEnergy 50178924 # Energy for active background per rank (pJ)
system.mem_ctrls_0.preBackEnergy 7527000 # Energy for precharge background per rank (pJ)
system.mem_ctrls_0.totalEnergy 69392004 # Total energy per rank (pJ)
system.mem_ctrls_0.averagePower 807.766675 # Core power per rank (mW)
system.mem_ctrls_0.memoryStateTime::IDLE 12759 # Time in different power states
system.mem_ctrls_0.memoryStateTime::REF 2860 # Time in different power states
system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.mem_ctrls_0.memoryStateTime::ACT 70523 # Time in different power states
system.mem_ctrls_0.memoryStateTime::ACT 70795 # Time in different power states
system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.mem_ctrls_1.actEnergy 975240 # Energy for activate commands per rank (pJ)
system.mem_ctrls_1.preEnergy 541800 # Energy for precharge commands per rank (pJ)
system.mem_ctrls_1.actEnergy 967680 # Energy for activate commands per rank (pJ)
system.mem_ctrls_1.preEnergy 537600 # Energy for precharge commands per rank (pJ)
system.mem_ctrls_1.readEnergy 7200960 # Energy for read commands per rank (pJ)
system.mem_ctrls_1.writeEnergy 632448 # Energy for write commands per rank (pJ)
system.mem_ctrls_1.refreshEnergy 5594160 # Energy for refresh commands per rank (pJ)
system.mem_ctrls_1.actBackEnergy 57826728 # Energy for active background per rank (pJ)
system.mem_ctrls_1.preBackEnergy 818400 # Energy for precharge background per rank (pJ)
system.mem_ctrls_1.totalEnergy 73589736 # Total energy per rank (pJ)
system.mem_ctrls_1.averagePower 856.630922 # Core power per rank (mW)
system.mem_ctrls_1.memoryStateTime::IDLE 958 # Time in different power states
system.mem_ctrls_1.actBackEnergy 57849984 # Energy for active background per rank (pJ)
system.mem_ctrls_1.preBackEnergy 798000 # Energy for precharge background per rank (pJ)
system.mem_ctrls_1.totalEnergy 73580832 # Total energy per rank (pJ)
system.mem_ctrls_1.averagePower 856.527274 # Core power per rank (mW)
system.mem_ctrls_1.memoryStateTime::IDLE 910 # Time in different power states
system.mem_ctrls_1.memoryStateTime::REF 2860 # Time in different power states
system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT 82102 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT 82150 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.clk_domain.clock 1 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 1183 # DTB read hits
system.cpu.dtb.read_hits 1185 # DTB read hits
system.cpu.dtb.read_misses 7 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 1190 # DTB read accesses
system.cpu.dtb.read_accesses 1192 # DTB read accesses
system.cpu.dtb.write_hits 865 # DTB write hits
system.cpu.dtb.write_misses 3 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 868 # DTB write accesses
system.cpu.dtb.data_hits 2048 # DTB hits
system.cpu.dtb.data_hits 2050 # DTB hits
system.cpu.dtb.data_misses 10 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 2058 # DTB accesses
system.cpu.itb.fetch_hits 6401 # ITB hits
system.cpu.dtb.data_accesses 2060 # DTB accesses
system.cpu.itb.fetch_hits 6414 # ITB hits
system.cpu.itb.fetch_misses 17 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 6418 # ITB accesses
system.cpu.itb.fetch_accesses 6431 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@ -298,238 +298,238 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
system.cpu.numCycles 86673 # number of cpu cycles simulated
system.cpu.numCycles 86770 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 6390 # Number of instructions committed
system.cpu.committedOps 6390 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses
system.cpu.committedInsts 6403 # Number of instructions committed
system.cpu.committedOps 6403 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 6329 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
system.cpu.num_func_calls 251 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls
system.cpu.num_int_insts 6317 # number of integer instructions
system.cpu.num_conditional_control_insts 754 # number of instructions that are conditional controls
system.cpu.num_int_insts 6329 # number of integer instructions
system.cpu.num_fp_insts 10 # number of float instructions
system.cpu.num_int_register_reads 8285 # number of times the integer registers were read
system.cpu.num_int_register_writes 4568 # number of times the integer registers were written
system.cpu.num_int_register_reads 8297 # number of times the integer registers were read
system.cpu.num_int_register_writes 4575 # number of times the integer registers were written
system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
system.cpu.num_mem_refs 2058 # number of memory refs
system.cpu.num_load_insts 1190 # Number of load instructions
system.cpu.num_mem_refs 2060 # number of memory refs
system.cpu.num_load_insts 1192 # Number of load instructions
system.cpu.num_store_insts 868 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 86673 # Number of busy cycles
system.cpu.num_busy_cycles 86770 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.Branches 1050 # Number of branches fetched
system.cpu.Branches 1056 # Number of branches fetched
system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction
system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction
system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction
system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction
system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction
system.cpu.op_class::IntAlu 4331 67.53% 67.83% # Class of executed instruction
system.cpu.op_class::IntMult 1 0.02% 67.85% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 67.85% # Class of executed instruction
system.cpu.op_class::FloatAdd 2 0.03% 67.88% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::MemRead 1192 18.59% 86.46% # Class of executed instruction
system.cpu.op_class::MemWrite 868 13.54% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 6400 # Class of executed instruction
system.cpu.op_class::total 6413 # Class of executed instruction
system.ruby.clk_domain.clock 1 # Clock period in ticks
system.ruby.outstanding_req_hist_seqr::bucket_size 1
system.ruby.outstanding_req_hist_seqr::max_bucket 9
system.ruby.outstanding_req_hist_seqr::samples 8449
system.ruby.outstanding_req_hist_seqr::samples 8464
system.ruby.outstanding_req_hist_seqr::mean 1
system.ruby.outstanding_req_hist_seqr::gmean 1
system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 8449 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.outstanding_req_hist_seqr::total 8449
system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 8464 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.outstanding_req_hist_seqr::total 8464
system.ruby.latency_hist_seqr::bucket_size 64
system.ruby.latency_hist_seqr::max_bucket 639
system.ruby.latency_hist_seqr::samples 8448
system.ruby.latency_hist_seqr::mean 9.259588
system.ruby.latency_hist_seqr::gmean 1.841457
system.ruby.latency_hist_seqr::stdev 22.233278
system.ruby.latency_hist_seqr | 8216 97.25% 97.25% | 221 2.62% 99.87% | 0 0.00% 99.87% | 3 0.04% 99.91% | 6 0.07% 99.98% | 2 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.latency_hist_seqr::total 8448
system.ruby.latency_hist_seqr::samples 8463
system.ruby.latency_hist_seqr::mean 9.252865
system.ruby.latency_hist_seqr::gmean 1.840314
system.ruby.latency_hist_seqr::stdev 22.282539
system.ruby.latency_hist_seqr | 8231 97.26% 97.26% | 222 2.62% 99.88% | 0 0.00% 99.88% | 1 0.01% 99.89% | 7 0.08% 99.98% | 2 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.latency_hist_seqr::total 8463
system.ruby.hit_latency_hist_seqr::bucket_size 2
system.ruby.hit_latency_hist_seqr::max_bucket 19
system.ruby.hit_latency_hist_seqr::samples 7289
system.ruby.hit_latency_hist_seqr::mean 1.278502
system.ruby.hit_latency_hist_seqr::gmean 1.069062
system.ruby.hit_latency_hist_seqr::stdev 1.645548
system.ruby.hit_latency_hist_seqr | 7086 97.21% 97.21% | 0 0.00% 97.21% | 0 0.00% 97.21% | 0 0.00% 97.21% | 0 0.00% 97.21% | 203 2.79% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.hit_latency_hist_seqr::total 7289
system.ruby.hit_latency_hist_seqr::samples 7303
system.ruby.hit_latency_hist_seqr::mean 1.277968
system.ruby.hit_latency_hist_seqr::gmean 1.068925
system.ruby.hit_latency_hist_seqr::stdev 1.644014
system.ruby.hit_latency_hist_seqr | 7100 97.22% 97.22% | 0 0.00% 97.22% | 0 0.00% 97.22% | 0 0.00% 97.22% | 0 0.00% 97.22% | 203 2.78% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.hit_latency_hist_seqr::total 7303
system.ruby.miss_latency_hist_seqr::bucket_size 64
system.ruby.miss_latency_hist_seqr::max_bucket 639
system.ruby.miss_latency_hist_seqr::samples 1159
system.ruby.miss_latency_hist_seqr::mean 59.452977
system.ruby.miss_latency_hist_seqr::gmean 56.282360
system.ruby.miss_latency_hist_seqr::stdev 25.811948
system.ruby.miss_latency_hist_seqr | 927 79.98% 79.98% | 221 19.07% 99.05% | 0 0.00% 99.05% | 3 0.26% 99.31% | 6 0.52% 99.83% | 2 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.miss_latency_hist_seqr::total 1159
system.ruby.Directory.incomplete_times_seqr 1158
system.ruby.miss_latency_hist_seqr::samples 1160
system.ruby.miss_latency_hist_seqr::mean 59.460345
system.ruby.miss_latency_hist_seqr::gmean 56.276317
system.ruby.miss_latency_hist_seqr::stdev 26.160126
system.ruby.miss_latency_hist_seqr | 928 80.00% 80.00% | 222 19.14% 99.14% | 0 0.00% 99.14% | 1 0.09% 99.22% | 7 0.60% 99.83% | 2 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.miss_latency_hist_seqr::total 1160
system.ruby.Directory.incomplete_times_seqr 1159
system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits
system.ruby.dir_cntrl0.probeFilter.demand_misses 0 # Number of cache demand misses
system.ruby.dir_cntrl0.probeFilter.demand_accesses 0 # Number of cache demand accesses
system.ruby.l1_cntrl0.L1Dcache.demand_hits 1332 # Number of cache demand hits
system.ruby.l1_cntrl0.L1Dcache.demand_misses 716 # Number of cache demand misses
system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2048 # Number of cache demand accesses
system.ruby.l1_cntrl0.L1Icache.demand_hits 5754 # Number of cache demand hits
system.ruby.l1_cntrl0.L1Dcache.demand_hits 1333 # Number of cache demand hits
system.ruby.l1_cntrl0.L1Dcache.demand_misses 717 # Number of cache demand misses
system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2050 # Number of cache demand accesses
system.ruby.l1_cntrl0.L1Icache.demand_hits 5767 # Number of cache demand hits
system.ruby.l1_cntrl0.L1Icache.demand_misses 646 # Number of cache demand misses
system.ruby.l1_cntrl0.L1Icache.demand_accesses 6400 # Number of cache demand accesses
system.ruby.l1_cntrl0.L1Icache.demand_accesses 6413 # Number of cache demand accesses
system.ruby.l1_cntrl0.L2cache.demand_hits 203 # Number of cache demand hits
system.ruby.l1_cntrl0.L2cache.demand_misses 1159 # Number of cache demand misses
system.ruby.l1_cntrl0.L2cache.demand_accesses 1362 # Number of cache demand accesses
system.ruby.l1_cntrl0.L2cache.demand_misses 1160 # Number of cache demand misses
system.ruby.l1_cntrl0.L2cache.demand_accesses 1363 # Number of cache demand accesses
system.ruby.l1_cntrl0.fully_busy_cycles 7 # cycles for which number of transistions == max transitions
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
system.ruby.network.routers0.percent_links_utilized 5.174045
system.ruby.network.routers0.msg_count.Request_Control::2 1159
system.ruby.network.routers0.msg_count.Response_Data::4 1159
system.ruby.network.routers0.percent_links_utilized 5.172295
system.ruby.network.routers0.msg_count.Request_Control::2 1160
system.ruby.network.routers0.msg_count.Response_Data::4 1160
system.ruby.network.routers0.msg_count.Writeback_Data::5 220
system.ruby.network.routers0.msg_count.Writeback_Control::2 1143
system.ruby.network.routers0.msg_count.Writeback_Control::3 1143
system.ruby.network.routers0.msg_count.Writeback_Control::5 923
system.ruby.network.routers0.msg_count.Unblock_Control::5 1159
system.ruby.network.routers0.msg_bytes.Request_Control::2 9272
system.ruby.network.routers0.msg_bytes.Response_Data::4 83448
system.ruby.network.routers0.msg_count.Writeback_Control::2 1144
system.ruby.network.routers0.msg_count.Writeback_Control::3 1144
system.ruby.network.routers0.msg_count.Writeback_Control::5 924
system.ruby.network.routers0.msg_count.Unblock_Control::5 1160
system.ruby.network.routers0.msg_bytes.Request_Control::2 9280
system.ruby.network.routers0.msg_bytes.Response_Data::4 83520
system.ruby.network.routers0.msg_bytes.Writeback_Data::5 15840
system.ruby.network.routers0.msg_bytes.Writeback_Control::2 9144
system.ruby.network.routers0.msg_bytes.Writeback_Control::3 9144
system.ruby.network.routers0.msg_bytes.Writeback_Control::5 7384
system.ruby.network.routers0.msg_bytes.Unblock_Control::5 9272
system.ruby.network.routers1.percent_links_utilized 5.173757
system.ruby.network.routers1.msg_count.Request_Control::2 1159
system.ruby.network.routers1.msg_count.Response_Data::4 1159
system.ruby.network.routers0.msg_bytes.Writeback_Control::2 9152
system.ruby.network.routers0.msg_bytes.Writeback_Control::3 9152
system.ruby.network.routers0.msg_bytes.Writeback_Control::5 7392
system.ruby.network.routers0.msg_bytes.Unblock_Control::5 9280
system.ruby.network.routers1.percent_links_utilized 5.172006
system.ruby.network.routers1.msg_count.Request_Control::2 1160
system.ruby.network.routers1.msg_count.Response_Data::4 1160
system.ruby.network.routers1.msg_count.Writeback_Data::5 220
system.ruby.network.routers1.msg_count.Writeback_Control::2 1143
system.ruby.network.routers1.msg_count.Writeback_Control::3 1143
system.ruby.network.routers1.msg_count.Writeback_Control::5 923
system.ruby.network.routers1.msg_count.Unblock_Control::5 1158
system.ruby.network.routers1.msg_bytes.Request_Control::2 9272
system.ruby.network.routers1.msg_bytes.Response_Data::4 83448
system.ruby.network.routers1.msg_count.Writeback_Control::2 1144
system.ruby.network.routers1.msg_count.Writeback_Control::3 1144
system.ruby.network.routers1.msg_count.Writeback_Control::5 924
system.ruby.network.routers1.msg_count.Unblock_Control::5 1159
system.ruby.network.routers1.msg_bytes.Request_Control::2 9280
system.ruby.network.routers1.msg_bytes.Response_Data::4 83520
system.ruby.network.routers1.msg_bytes.Writeback_Data::5 15840
system.ruby.network.routers1.msg_bytes.Writeback_Control::2 9144
system.ruby.network.routers1.msg_bytes.Writeback_Control::3 9144
system.ruby.network.routers1.msg_bytes.Writeback_Control::5 7384
system.ruby.network.routers1.msg_bytes.Unblock_Control::5 9264
system.ruby.network.routers2.percent_links_utilized 5.174045
system.ruby.network.routers2.msg_count.Request_Control::2 1159
system.ruby.network.routers2.msg_count.Response_Data::4 1159
system.ruby.network.routers1.msg_bytes.Writeback_Control::2 9152
system.ruby.network.routers1.msg_bytes.Writeback_Control::3 9152
system.ruby.network.routers1.msg_bytes.Writeback_Control::5 7392
system.ruby.network.routers1.msg_bytes.Unblock_Control::5 9272
system.ruby.network.routers2.percent_links_utilized 5.172295
system.ruby.network.routers2.msg_count.Request_Control::2 1160
system.ruby.network.routers2.msg_count.Response_Data::4 1160
system.ruby.network.routers2.msg_count.Writeback_Data::5 220
system.ruby.network.routers2.msg_count.Writeback_Control::2 1143
system.ruby.network.routers2.msg_count.Writeback_Control::3 1143
system.ruby.network.routers2.msg_count.Writeback_Control::5 923
system.ruby.network.routers2.msg_count.Unblock_Control::5 1159
system.ruby.network.routers2.msg_bytes.Request_Control::2 9272
system.ruby.network.routers2.msg_bytes.Response_Data::4 83448
system.ruby.network.routers2.msg_count.Writeback_Control::2 1144
system.ruby.network.routers2.msg_count.Writeback_Control::3 1144
system.ruby.network.routers2.msg_count.Writeback_Control::5 924
system.ruby.network.routers2.msg_count.Unblock_Control::5 1160
system.ruby.network.routers2.msg_bytes.Request_Control::2 9280
system.ruby.network.routers2.msg_bytes.Response_Data::4 83520
system.ruby.network.routers2.msg_bytes.Writeback_Data::5 15840
system.ruby.network.routers2.msg_bytes.Writeback_Control::2 9144
system.ruby.network.routers2.msg_bytes.Writeback_Control::3 9144
system.ruby.network.routers2.msg_bytes.Writeback_Control::5 7384
system.ruby.network.routers2.msg_bytes.Unblock_Control::5 9272
system.ruby.network.msg_count.Request_Control 3477
system.ruby.network.msg_count.Response_Data 3477
system.ruby.network.routers2.msg_bytes.Writeback_Control::2 9152
system.ruby.network.routers2.msg_bytes.Writeback_Control::3 9152
system.ruby.network.routers2.msg_bytes.Writeback_Control::5 7392
system.ruby.network.routers2.msg_bytes.Unblock_Control::5 9280
system.ruby.network.msg_count.Request_Control 3480
system.ruby.network.msg_count.Response_Data 3480
system.ruby.network.msg_count.Writeback_Data 660
system.ruby.network.msg_count.Writeback_Control 9627
system.ruby.network.msg_count.Unblock_Control 3476
system.ruby.network.msg_byte.Request_Control 27816
system.ruby.network.msg_byte.Response_Data 250344
system.ruby.network.msg_count.Writeback_Control 9636
system.ruby.network.msg_count.Unblock_Control 3479
system.ruby.network.msg_byte.Request_Control 27840
system.ruby.network.msg_byte.Response_Data 250560
system.ruby.network.msg_byte.Writeback_Data 47520
system.ruby.network.msg_byte.Writeback_Control 77016
system.ruby.network.msg_byte.Unblock_Control 27808
system.ruby.network.routers0.throttle0.link_utilization 6.676820
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1159
system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1143
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 83448
system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 9144
system.ruby.network.routers0.throttle1.link_utilization 3.671270
system.ruby.network.routers0.throttle1.msg_count.Request_Control::2 1159
system.ruby.network.msg_byte.Writeback_Control 77088
system.ruby.network.msg_byte.Unblock_Control 27832
system.ruby.network.routers0.throttle0.link_utilization 6.675118
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1160
system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1144
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 83520
system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 9152
system.ruby.network.routers0.throttle1.link_utilization 3.669471
system.ruby.network.routers0.throttle1.msg_count.Request_Control::2 1160
system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::5 220
system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::2 1143
system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::5 923
system.ruby.network.routers0.throttle1.msg_count.Unblock_Control::5 1159
system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::2 9272
system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::2 1144
system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::5 924
system.ruby.network.routers0.throttle1.msg_count.Unblock_Control::5 1160
system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::2 9280
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::5 15840
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::2 9144
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::5 7384
system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::5 9272
system.ruby.network.routers1.throttle0.link_utilization 3.670693
system.ruby.network.routers1.throttle0.msg_count.Request_Control::2 1159
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::2 9152
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::5 7392
system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::5 9280
system.ruby.network.routers1.throttle0.link_utilization 3.668895
system.ruby.network.routers1.throttle0.msg_count.Request_Control::2 1160
system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::5 220
system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::2 1143
system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::5 923
system.ruby.network.routers1.throttle0.msg_count.Unblock_Control::5 1158
system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::2 9272
system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::2 1144
system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::5 924
system.ruby.network.routers1.throttle0.msg_count.Unblock_Control::5 1159
system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::2 9280
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::5 15840
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::2 9144
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::5 7384
system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::5 9264
system.ruby.network.routers1.throttle1.link_utilization 6.676820
system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1159
system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1143
system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 83448
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 9144
system.ruby.network.routers2.throttle0.link_utilization 6.676820
system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1159
system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1143
system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 83448
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 9144
system.ruby.network.routers2.throttle1.link_utilization 3.671270
system.ruby.network.routers2.throttle1.msg_count.Request_Control::2 1159
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::2 9152
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::5 7392
system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::5 9272
system.ruby.network.routers1.throttle1.link_utilization 6.675118
system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1160
system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1144
system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 83520
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 9152
system.ruby.network.routers2.throttle0.link_utilization 6.675118
system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1160
system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1144
system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 83520
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 9152
system.ruby.network.routers2.throttle1.link_utilization 3.669471
system.ruby.network.routers2.throttle1.msg_count.Request_Control::2 1160
system.ruby.network.routers2.throttle1.msg_count.Writeback_Data::5 220
system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::2 1143
system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::5 923
system.ruby.network.routers2.throttle1.msg_count.Unblock_Control::5 1159
system.ruby.network.routers2.throttle1.msg_bytes.Request_Control::2 9272
system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::2 1144
system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::5 924
system.ruby.network.routers2.throttle1.msg_count.Unblock_Control::5 1160
system.ruby.network.routers2.throttle1.msg_bytes.Request_Control::2 9280
system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Data::5 15840
system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::2 9144
system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::5 7384
system.ruby.network.routers2.throttle1.msg_bytes.Unblock_Control::5 9272
system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::2 9152
system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::5 7392
system.ruby.network.routers2.throttle1.msg_bytes.Unblock_Control::5 9280
system.ruby.LD.latency_hist_seqr::bucket_size 32
system.ruby.LD.latency_hist_seqr::max_bucket 319
system.ruby.LD.latency_hist_seqr::samples 1183
system.ruby.LD.latency_hist_seqr::mean 21.460693
system.ruby.LD.latency_hist_seqr::gmean 5.052192
system.ruby.LD.latency_hist_seqr::stdev 28.940454
system.ruby.LD.latency_hist_seqr | 852 72.02% 72.02% | 242 20.46% 92.48% | 85 7.19% 99.66% | 2 0.17% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 1 0.08% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00%
system.ruby.LD.latency_hist_seqr::total 1183
system.ruby.LD.latency_hist_seqr::samples 1185
system.ruby.LD.latency_hist_seqr::mean 21.677637
system.ruby.LD.latency_hist_seqr::gmean 5.060853
system.ruby.LD.latency_hist_seqr::stdev 30.245768
system.ruby.LD.latency_hist_seqr | 853 71.98% 71.98% | 244 20.59% 92.57% | 84 7.09% 99.66% | 1 0.08% 99.75% | 0 0.00% 99.75% | 0 0.00% 99.75% | 0 0.00% 99.75% | 0 0.00% 99.75% | 1 0.08% 99.83% | 2 0.17% 100.00%
system.ruby.LD.latency_hist_seqr::total 1185
system.ruby.LD.hit_latency_hist_seqr::bucket_size 2
system.ruby.LD.hit_latency_hist_seqr::max_bucket 19
system.ruby.LD.hit_latency_hist_seqr::samples 763
system.ruby.LD.hit_latency_hist_seqr::mean 2.376147
system.ruby.LD.hit_latency_hist_seqr::gmean 1.390948
system.ruby.LD.hit_latency_hist_seqr::stdev 3.447211
system.ruby.LD.hit_latency_hist_seqr | 658 86.24% 86.24% | 0 0.00% 86.24% | 0 0.00% 86.24% | 0 0.00% 86.24% | 0 0.00% 86.24% | 105 13.76% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.hit_latency_hist_seqr::total 763
system.ruby.LD.hit_latency_hist_seqr::samples 764
system.ruby.LD.hit_latency_hist_seqr::mean 2.374346
system.ruby.LD.hit_latency_hist_seqr::gmean 1.390347
system.ruby.LD.hit_latency_hist_seqr::stdev 3.445311
system.ruby.LD.hit_latency_hist_seqr | 659 86.26% 86.26% | 0 0.00% 86.26% | 0 0.00% 86.26% | 0 0.00% 86.26% | 0 0.00% 86.26% | 105 13.74% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.hit_latency_hist_seqr::total 764
system.ruby.LD.miss_latency_hist_seqr::bucket_size 32
system.ruby.LD.miss_latency_hist_seqr::max_bucket 319
system.ruby.LD.miss_latency_hist_seqr::samples 420
system.ruby.LD.miss_latency_hist_seqr::mean 56.130952
system.ruby.LD.miss_latency_hist_seqr::gmean 52.616261
system.ruby.LD.miss_latency_hist_seqr::stdev 21.748058
system.ruby.LD.miss_latency_hist_seqr | 89 21.19% 21.19% | 242 57.62% 78.81% | 85 20.24% 99.05% | 2 0.48% 99.52% | 0 0.00% 99.52% | 0 0.00% 99.52% | 0 0.00% 99.52% | 1 0.24% 99.76% | 1 0.24% 100.00% | 0 0.00% 100.00%
system.ruby.LD.miss_latency_hist_seqr::total 420
system.ruby.LD.miss_latency_hist_seqr::samples 421
system.ruby.LD.miss_latency_hist_seqr::mean 56.707838
system.ruby.LD.miss_latency_hist_seqr::gmean 52.779793
system.ruby.LD.miss_latency_hist_seqr::stdev 25.484779
system.ruby.LD.miss_latency_hist_seqr | 89 21.14% 21.14% | 244 57.96% 79.10% | 84 19.95% 99.05% | 1 0.24% 99.29% | 0 0.00% 99.29% | 0 0.00% 99.29% | 0 0.00% 99.29% | 0 0.00% 99.29% | 1 0.24% 99.52% | 2 0.48% 100.00%
system.ruby.LD.miss_latency_hist_seqr::total 421
system.ruby.ST.latency_hist_seqr::bucket_size 16
system.ruby.ST.latency_hist_seqr::max_bucket 159
system.ruby.ST.latency_hist_seqr::samples 865
@ -556,35 +556,35 @@ system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% |
system.ruby.ST.miss_latency_hist_seqr::total 158
system.ruby.IFETCH.latency_hist_seqr::bucket_size 64
system.ruby.IFETCH.latency_hist_seqr::max_bucket 639
system.ruby.IFETCH.latency_hist_seqr::samples 6400
system.ruby.IFETCH.latency_hist_seqr::mean 6.828750
system.ruby.IFETCH.latency_hist_seqr::gmean 1.489407
system.ruby.IFETCH.latency_hist_seqr::stdev 20.190166
system.ruby.IFETCH.latency_hist_seqr | 6294 98.34% 98.34% | 97 1.52% 99.86% | 0 0.00% 99.86% | 2 0.03% 99.89% | 5 0.08% 99.97% | 2 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.latency_hist_seqr::total 6400
system.ruby.IFETCH.latency_hist_seqr::samples 6413
system.ruby.IFETCH.latency_hist_seqr::mean 6.780914
system.ruby.IFETCH.latency_hist_seqr::gmean 1.487888
system.ruby.IFETCH.latency_hist_seqr::stdev 19.876102
system.ruby.IFETCH.latency_hist_seqr | 6306 98.33% 98.33% | 100 1.56% 99.89% | 0 0.00% 99.89% | 1 0.02% 99.91% | 4 0.06% 99.97% | 2 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.latency_hist_seqr::total 6413
system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 2
system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 19
system.ruby.IFETCH.hit_latency_hist_seqr::samples 5819
system.ruby.IFETCH.hit_latency_hist_seqr::mean 1.111703
system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1.027147
system.ruby.IFETCH.hit_latency_hist_seqr::stdev 1.051067
system.ruby.IFETCH.hit_latency_hist_seqr | 5754 98.88% 98.88% | 0 0.00% 98.88% | 0 0.00% 98.88% | 0 0.00% 98.88% | 0 0.00% 98.88% | 65 1.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.hit_latency_hist_seqr::total 5819
system.ruby.IFETCH.hit_latency_hist_seqr::samples 5832
system.ruby.IFETCH.hit_latency_hist_seqr::mean 1.111454
system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1.027086
system.ruby.IFETCH.hit_latency_hist_seqr::stdev 1.049908
system.ruby.IFETCH.hit_latency_hist_seqr | 5767 98.89% 98.89% | 0 0.00% 98.89% | 0 0.00% 98.89% | 0 0.00% 98.89% | 0 0.00% 98.89% | 65 1.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.hit_latency_hist_seqr::total 5832
system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64
system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639
system.ruby.IFETCH.miss_latency_hist_seqr::samples 581
system.ruby.IFETCH.miss_latency_hist_seqr::mean 64.087780
system.ruby.IFETCH.miss_latency_hist_seqr::gmean 61.562973
system.ruby.IFETCH.miss_latency_hist_seqr::stdev 29.566480
system.ruby.IFETCH.miss_latency_hist_seqr | 475 81.76% 81.76% | 97 16.70% 98.45% | 0 0.00% 98.45% | 2 0.34% 98.80% | 5 0.86% 99.66% | 2 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.miss_latency_hist_seqr::mean 63.690189
system.ruby.IFETCH.miss_latency_hist_seqr::gmean 61.418649
system.ruby.IFETCH.miss_latency_hist_seqr::stdev 28.087678
system.ruby.IFETCH.miss_latency_hist_seqr | 474 81.58% 81.58% | 100 17.21% 98.80% | 0 0.00% 98.80% | 1 0.17% 98.97% | 4 0.69% 99.66% | 2 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.miss_latency_hist_seqr::total 581
system.ruby.L1Cache.hit_mach_latency_hist_seqr::bucket_size 1
system.ruby.L1Cache.hit_mach_latency_hist_seqr::max_bucket 9
system.ruby.L1Cache.hit_mach_latency_hist_seqr::samples 7086
system.ruby.L1Cache.hit_mach_latency_hist_seqr::samples 7100
system.ruby.L1Cache.hit_mach_latency_hist_seqr::mean 1
system.ruby.L1Cache.hit_mach_latency_hist_seqr::gmean 1
system.ruby.L1Cache.hit_mach_latency_hist_seqr | 0 0.00% 0.00% | 7086 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.L1Cache.hit_mach_latency_hist_seqr::total 7086
system.ruby.L1Cache.hit_mach_latency_hist_seqr | 0 0.00% 0.00% | 7100 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.L1Cache.hit_mach_latency_hist_seqr::total 7100
system.ruby.L2Cache.hit_mach_latency_hist_seqr::bucket_size 2
system.ruby.L2Cache.hit_mach_latency_hist_seqr::max_bucket 19
system.ruby.L2Cache.hit_mach_latency_hist_seqr::samples 203
@ -594,12 +594,12 @@ system.ruby.L2Cache.hit_mach_latency_hist_seqr | 0 0.00% 0.0
system.ruby.L2Cache.hit_mach_latency_hist_seqr::total 203
system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64
system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639
system.ruby.Directory.miss_mach_latency_hist_seqr::samples 1159
system.ruby.Directory.miss_mach_latency_hist_seqr::mean 59.452977
system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 56.282360
system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 25.811948
system.ruby.Directory.miss_mach_latency_hist_seqr | 927 79.98% 79.98% | 221 19.07% 99.05% | 0 0.00% 99.05% | 3 0.26% 99.31% | 6 0.52% 99.83% | 2 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.Directory.miss_mach_latency_hist_seqr::total 1159
system.ruby.Directory.miss_mach_latency_hist_seqr::samples 1160
system.ruby.Directory.miss_mach_latency_hist_seqr::mean 59.460345
system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 56.276317
system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 26.160126
system.ruby.Directory.miss_mach_latency_hist_seqr | 928 80.00% 80.00% | 222 19.14% 99.14% | 0 0.00% 99.14% | 1 0.09% 99.22% | 7 0.60% 99.83% | 2 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.Directory.miss_mach_latency_hist_seqr::total 1160
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 1
@ -628,11 +628,11 @@ system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion |
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1
system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1
system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9
system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::samples 658
system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::samples 659
system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::mean 1
system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::gmean 1
system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 658 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::total 658
system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 659 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::total 659
system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 2
system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 19
system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::samples 105
@ -642,12 +642,12 @@ system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00%
system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::total 105
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 420
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 56.130952
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 52.616261
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 21.748058
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 89 21.19% 21.19% | 242 57.62% 78.81% | 85 20.24% 99.05% | 2 0.48% 99.52% | 0 0.00% 99.52% | 0 0.00% 99.52% | 0 0.00% 99.52% | 1 0.24% 99.76% | 1 0.24% 100.00% | 0 0.00% 100.00%
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 420
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 421
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 56.707838
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 52.779793
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 25.484779
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 89 21.14% 21.14% | 244 57.96% 79.10% | 84 19.95% 99.05% | 1 0.24% 99.29% | 0 0.00% 99.29% | 0 0.00% 99.29% | 0 0.00% 99.29% | 0 0.00% 99.29% | 1 0.24% 99.52% | 2 0.48% 100.00%
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 421
system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1
system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9
system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::samples 674
@ -672,11 +672,11 @@ system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 0 0.0
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 158
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::samples 5754
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::samples 5767
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::mean 1
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::gmean 1
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 5754 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::total 5754
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 5767 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::total 5767
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 2
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 19
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::samples 65
@ -687,48 +687,48 @@ system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::total 65
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 581
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 64.087780
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 61.562973
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 29.566480
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 475 81.76% 81.76% | 97 16.70% 98.45% | 0 0.00% 98.45% | 2 0.34% 98.80% | 5 0.86% 99.66% | 2 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 63.690189
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 61.418649
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 28.087678
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 474 81.58% 81.58% | 100 17.21% 98.80% | 0 0.00% 98.80% | 1 0.17% 98.97% | 4 0.69% 99.66% | 2 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 581
system.ruby.Directory_Controller.GETX 185 0.00% 0.00%
system.ruby.Directory_Controller.GETS 1020 0.00% 0.00%
system.ruby.Directory_Controller.PUT 1143 0.00% 0.00%
system.ruby.Directory_Controller.UnblockM 1158 0.00% 0.00%
system.ruby.Directory_Controller.Writeback_Exclusive_Clean 923 0.00% 0.00%
system.ruby.Directory_Controller.GETS 1021 0.00% 0.00%
system.ruby.Directory_Controller.PUT 1144 0.00% 0.00%
system.ruby.Directory_Controller.UnblockM 1159 0.00% 0.00%
system.ruby.Directory_Controller.Writeback_Exclusive_Clean 924 0.00% 0.00%
system.ruby.Directory_Controller.Writeback_Exclusive_Dirty 220 0.00% 0.00%
system.ruby.Directory_Controller.Memory_Data 1159 0.00% 0.00%
system.ruby.Directory_Controller.Memory_Data 1160 0.00% 0.00%
system.ruby.Directory_Controller.Memory_Ack 220 0.00% 0.00%
system.ruby.Directory_Controller.NO.PUT 1143 0.00% 0.00%
system.ruby.Directory_Controller.NO.PUT 1144 0.00% 0.00%
system.ruby.Directory_Controller.E.GETX 158 0.00% 0.00%
system.ruby.Directory_Controller.E.GETS 1001 0.00% 0.00%
system.ruby.Directory_Controller.NO_B.UnblockM 1158 0.00% 0.00%
system.ruby.Directory_Controller.NO_B_W.Memory_Data 1159 0.00% 0.00%
system.ruby.Directory_Controller.E.GETS 1002 0.00% 0.00%
system.ruby.Directory_Controller.NO_B.UnblockM 1159 0.00% 0.00%
system.ruby.Directory_Controller.NO_B_W.Memory_Data 1160 0.00% 0.00%
system.ruby.Directory_Controller.WB.GETX 27 0.00% 0.00%
system.ruby.Directory_Controller.WB.GETS 19 0.00% 0.00%
system.ruby.Directory_Controller.WB.Writeback_Exclusive_Clean 923 0.00% 0.00%
system.ruby.Directory_Controller.WB.Writeback_Exclusive_Clean 924 0.00% 0.00%
system.ruby.Directory_Controller.WB.Writeback_Exclusive_Dirty 220 0.00% 0.00%
system.ruby.Directory_Controller.WB_E_W.Memory_Ack 220 0.00% 0.00%
system.ruby.L1Cache_Controller.Load 1191 0.00% 0.00%
system.ruby.L1Cache_Controller.Ifetch 6411 0.00% 0.00%
system.ruby.L1Cache_Controller.Load 1193 0.00% 0.00%
system.ruby.L1Cache_Controller.Ifetch 6424 0.00% 0.00%
system.ruby.L1Cache_Controller.Store 892 0.00% 0.00%
system.ruby.L1Cache_Controller.L2_Replacement 1143 0.00% 0.00%
system.ruby.L1Cache_Controller.L1_to_L2 1354 0.00% 0.00%
system.ruby.L1Cache_Controller.L2_Replacement 1144 0.00% 0.00%
system.ruby.L1Cache_Controller.L1_to_L2 1355 0.00% 0.00%
system.ruby.L1Cache_Controller.Trigger_L2_to_L1D 138 0.00% 0.00%
system.ruby.L1Cache_Controller.Trigger_L2_to_L1I 65 0.00% 0.00%
system.ruby.L1Cache_Controller.Complete_L2_to_L1 203 0.00% 0.00%
system.ruby.L1Cache_Controller.Exclusive_Data 1159 0.00% 0.00%
system.ruby.L1Cache_Controller.Writeback_Ack 1143 0.00% 0.00%
system.ruby.L1Cache_Controller.All_acks_no_sharers 1159 0.00% 0.00%
system.ruby.L1Cache_Controller.I.Load 420 0.00% 0.00%
system.ruby.L1Cache_Controller.Exclusive_Data 1160 0.00% 0.00%
system.ruby.L1Cache_Controller.Writeback_Ack 1144 0.00% 0.00%
system.ruby.L1Cache_Controller.All_acks_no_sharers 1160 0.00% 0.00%
system.ruby.L1Cache_Controller.I.Load 421 0.00% 0.00%
system.ruby.L1Cache_Controller.I.Ifetch 581 0.00% 0.00%
system.ruby.L1Cache_Controller.I.Store 158 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Load 304 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Ifetch 5754 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Load 305 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Ifetch 5767 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Store 60 0.00% 0.00%
system.ruby.L1Cache_Controller.M.L2_Replacement 923 0.00% 0.00%
system.ruby.L1Cache_Controller.M.L1_to_L2 1061 0.00% 0.00%
system.ruby.L1Cache_Controller.M.L2_Replacement 924 0.00% 0.00%
system.ruby.L1Cache_Controller.M.L1_to_L2 1062 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Trigger_L2_to_L1D 68 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Trigger_L2_to_L1I 65 0.00% 0.00%
system.ruby.L1Cache_Controller.MM.Load 354 0.00% 0.00%
@ -742,13 +742,13 @@ system.ruby.L1Cache_Controller.MR.Store 6 0.00% 0.00%
system.ruby.L1Cache_Controller.MMR.Load 43 0.00% 0.00%
system.ruby.L1Cache_Controller.MMR.Store 27 0.00% 0.00%
system.ruby.L1Cache_Controller.IM.Exclusive_Data 158 0.00% 0.00%
system.ruby.L1Cache_Controller.M_W.All_acks_no_sharers 1001 0.00% 0.00%
system.ruby.L1Cache_Controller.M_W.All_acks_no_sharers 1002 0.00% 0.00%
system.ruby.L1Cache_Controller.MM_W.All_acks_no_sharers 158 0.00% 0.00%
system.ruby.L1Cache_Controller.IS.Exclusive_Data 1001 0.00% 0.00%
system.ruby.L1Cache_Controller.IS.Exclusive_Data 1002 0.00% 0.00%
system.ruby.L1Cache_Controller.MI.Load 8 0.00% 0.00%
system.ruby.L1Cache_Controller.MI.Ifetch 11 0.00% 0.00%
system.ruby.L1Cache_Controller.MI.Store 27 0.00% 0.00%
system.ruby.L1Cache_Controller.MI.Writeback_Ack 1143 0.00% 0.00%
system.ruby.L1Cache_Controller.MI.Writeback_Ack 1144 0.00% 0.00%
system.ruby.L1Cache_Controller.MT.Complete_L2_to_L1 133 0.00% 0.00%
system.ruby.L1Cache_Controller.MMT.Complete_L2_to_L1 70 0.00% 0.00%

2
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
View file

@ -120,7 +120,7 @@ env=
errout=cerr
euid=100
eventq_index=0
executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
kvmInSE=false

12
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout
View file

@ -1,13 +1,15 @@
Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby/simout
Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 21 2016 13:49:21
gem5 started Jan 21 2016 13:50:00
gem5 executing on zizzer, pid 33967
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby
gem5 compiled Mar 14 2016 21:54:46
gem5 started Mar 14 2016 21:55:58
gem5 executing on phenom, pid 28070
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
Exiting @ tick 107210 because target called exit()
Exiting @ tick 107065 because target called exit()

744
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
View file

@ -1,94 +1,94 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000107 # Number of seconds simulated
sim_ticks 107210 # Number of ticks simulated
final_tick 107210 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 107065 # Number of ticks simulated
final_tick 107065 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_inst_rate 108799 # Simulator instruction rate (inst/s)
host_op_rate 108769 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1824399 # Simulator tick rate (ticks/s)
host_mem_usage 416280 # Number of bytes of host memory used
host_seconds 0.06 # Real time elapsed on the host
sim_insts 6390 # Number of instructions simulated
sim_ops 6390 # Number of ops (including micro ops) simulated
host_inst_rate 18652 # Simulator instruction rate (inst/s)
host_op_rate 18652 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 311861 # Simulator tick rate (ticks/s)
host_mem_usage 390536 # Number of bytes of host memory used
host_seconds 0.34 # Real time elapsed on the host
sim_insts 6403 # Number of instructions simulated
sim_ops 6403 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 110720 # Number of bytes read from this memory
system.mem_ctrls.bytes_read::total 110720 # Number of bytes read from this memory
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 110464 # Number of bytes written to this memory
system.mem_ctrls.bytes_written::total 110464 # Number of bytes written to this memory
system.mem_ctrls.num_reads::ruby.dir_cntrl0 1730 # Number of read requests responded to by this memory
system.mem_ctrls.num_reads::total 1730 # Number of read requests responded to by this memory
system.mem_ctrls.num_writes::ruby.dir_cntrl0 1726 # Number of write requests responded to by this memory
system.mem_ctrls.num_writes::total 1726 # Number of write requests responded to by this memory
system.mem_ctrls.bw_read::ruby.dir_cntrl0 1032739483 # Total read bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_read::total 1032739483 # Total read bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_write::ruby.dir_cntrl0 1030351646 # Write bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_write::total 1030351646 # Write bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_total::ruby.dir_cntrl0 2063091130 # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.bw_total::total 2063091130 # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.readReqs 1730 # Number of read requests accepted
system.mem_ctrls.writeReqs 1726 # Number of write requests accepted
system.mem_ctrls.readBursts 1730 # Number of DRAM read bursts, including those serviced by the write queue
system.mem_ctrls.writeBursts 1726 # Number of DRAM write bursts, including those merged in the write queue
system.mem_ctrls.bytesReadDRAM 56896 # Total number of bytes read from DRAM
system.mem_ctrls.bytesReadWrQ 53824 # Total number of bytes read from write queue
system.mem_ctrls.bytesWritten 56448 # Total number of bytes written to DRAM
system.mem_ctrls.bytesReadSys 110720 # Total read bytes from the system interface side
system.mem_ctrls.bytesWrittenSys 110464 # Total written bytes from the system interface side
system.mem_ctrls.servicedByWrQ 841 # Number of DRAM read bursts serviced by the write queue
system.mem_ctrls.mergedWrBursts 814 # Number of DRAM write bursts merged with an existing one
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 110784 # Number of bytes read from this memory
system.mem_ctrls.bytes_read::total 110784 # Number of bytes read from this memory
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 110528 # Number of bytes written to this memory
system.mem_ctrls.bytes_written::total 110528 # Number of bytes written to this memory
system.mem_ctrls.num_reads::ruby.dir_cntrl0 1731 # Number of read requests responded to by this memory
system.mem_ctrls.num_reads::total 1731 # Number of read requests responded to by this memory
system.mem_ctrls.num_writes::ruby.dir_cntrl0 1727 # Number of write requests responded to by this memory
system.mem_ctrls.num_writes::total 1727 # Number of write requests responded to by this memory
system.mem_ctrls.bw_read::ruby.dir_cntrl0 1034735908 # Total read bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_read::total 1034735908 # Total read bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_write::ruby.dir_cntrl0 1032344837 # Write bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_write::total 1032344837 # Write bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_total::ruby.dir_cntrl0 2067080745 # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.bw_total::total 2067080745 # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.readReqs 1731 # Number of read requests accepted
system.mem_ctrls.writeReqs 1727 # Number of write requests accepted
system.mem_ctrls.readBursts 1731 # Number of DRAM read bursts, including those serviced by the write queue
system.mem_ctrls.writeBursts 1727 # Number of DRAM write bursts, including those merged in the write queue
system.mem_ctrls.bytesReadDRAM 56512 # Total number of bytes read from DRAM
system.mem_ctrls.bytesReadWrQ 54272 # Total number of bytes read from write queue
system.mem_ctrls.bytesWritten 57856 # Total number of bytes written to DRAM
system.mem_ctrls.bytesReadSys 110784 # Total read bytes from the system interface side
system.mem_ctrls.bytesWrittenSys 110528 # Total written bytes from the system interface side
system.mem_ctrls.servicedByWrQ 848 # Number of DRAM read bursts serviced by the write queue
system.mem_ctrls.mergedWrBursts 792 # Number of DRAM write bursts merged with an existing one
system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.mem_ctrls.perBankRdBursts::0 82 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::1 48 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::2 85 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::3 66 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::4 116 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::5 24 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::0 85 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::1 47 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::2 74 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::3 68 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::4 112 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::5 23 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::6 1 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::7 3 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::9 1 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::10 49 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::11 31 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::12 19 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::13 266 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::11 33 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::12 17 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::13 263 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::14 79 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::15 19 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::0 81 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::1 49 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::2 85 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::3 62 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::4 126 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::5 27 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::15 28 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::0 83 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::1 47 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::2 80 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::3 68 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::4 133 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::5 25 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::6 1 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::7 3 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::7 4 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::9 1 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::10 44 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::11 29 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::12 13 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::13 262 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::14 79 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::15 20 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::10 46 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::11 28 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::12 11 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::13 268 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::14 81 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::15 28 # Per bank write bursts
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
system.mem_ctrls.totGap 107138 # Total gap between requests
system.mem_ctrls.totGap 106993 # Total gap between requests
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::6 1730 # Read request sizes (log2)
system.mem_ctrls.readPktSize::6 1731 # Read request sizes (log2)
system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::6 1726 # Write request sizes (log2)
system.mem_ctrls.rdQLenPdf::0 889 # What read queue length does an incoming req see
system.mem_ctrls.writePktSize::6 1727 # Write request sizes (log2)
system.mem_ctrls.rdQLenPdf::0 883 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
@ -135,25 +135,25 @@ system.mem_ctrls.wrQLenPdf::11 1 # Wh
system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::15 8 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::16 8 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::17 52 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::18 56 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::19 57 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::20 57 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::15 9 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::16 10 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::17 50 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::18 57 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::19 60 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::20 61 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::21 57 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::22 55 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::23 55 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::24 55 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::25 55 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::26 55 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::27 55 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::28 55 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::29 55 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::30 54 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::31 54 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::32 54 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::22 56 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::23 57 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::24 56 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::25 56 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::26 56 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::27 56 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::28 56 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::29 56 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::30 56 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::31 55 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::32 55 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::33 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see
@ -184,110 +184,110 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh
system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.mem_ctrls.bytesPerActivate::samples 253 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::mean 437.122530 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::gmean 269.105572 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::stdev 371.515393 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::0-127 63 24.90% 24.90% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::128-255 51 20.16% 45.06% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::256-383 24 9.49% 54.55% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::384-511 18 7.11% 61.66% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::512-639 14 5.53% 67.19% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::640-767 10 3.95% 71.15% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::768-895 18 7.11% 78.26% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::896-1023 10 3.95% 82.21% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::1024-1151 45 17.79% 100.00% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::total 253 # Bytes accessed per row activation
system.mem_ctrls.rdPerTurnAround::samples 54 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::mean 16.203704 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::gmean 16.028046 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::stdev 2.999243 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::12-13 1 1.85% 1.85% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::14-15 20 37.04% 38.89% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::16-17 27 50.00% 88.89% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::18-19 4 7.41% 96.30% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::20-21 1 1.85% 98.15% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::36-37 1 1.85% 100.00% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::total 54 # Reads before turning the bus around for writes
system.mem_ctrls.wrPerTurnAround::samples 54 # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::mean 16.333333 # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::gmean 16.311361 # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::stdev 0.890198 # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::16 47 87.04% 87.04% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::18 3 5.56% 92.59% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::19 4 7.41% 100.00% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::total 54 # Writes before turning the bus around for reads
system.mem_ctrls.totQLat 10919 # Total ticks spent queuing
system.mem_ctrls.totMemAccLat 27810 # Total ticks spent from burst creation until serviced by the DRAM
system.mem_ctrls.totBusLat 4445 # Total ticks spent in databus transfers
system.mem_ctrls.avgQLat 12.28 # Average queueing delay per DRAM burst
system.mem_ctrls.bytesPerActivate::samples 275 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::mean 406.341818 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::gmean 258.682678 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::stdev 357.059585 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::0-127 55 20.00% 20.00% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::128-255 74 26.91% 46.91% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::256-383 37 13.45% 60.36% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::384-511 16 5.82% 66.18% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::512-639 18 6.55% 72.73% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::640-767 12 4.36% 77.09% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::768-895 8 2.91% 80.00% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::896-1023 6 2.18% 82.18% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::1024-1151 49 17.82% 100.00% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::total 275 # Bytes accessed per row activation
system.mem_ctrls.rdPerTurnAround::samples 55 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::mean 15.781818 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::gmean 15.596648 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::stdev 2.973282 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::12-13 4 7.27% 7.27% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::14-15 25 45.45% 52.73% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::16-17 21 38.18% 90.91% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::18-19 4 7.27% 98.18% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::34-35 1 1.82% 100.00% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::total 55 # Reads before turning the bus around for writes
system.mem_ctrls.wrPerTurnAround::samples 55 # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::mean 16.436364 # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::gmean 16.408895 # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::stdev 0.995613 # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::16 45 81.82% 81.82% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::17 2 3.64% 85.45% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::18 2 3.64% 89.09% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::19 6 10.91% 100.00% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::total 55 # Writes before turning the bus around for reads
system.mem_ctrls.totQLat 10887 # Total ticks spent queuing
system.mem_ctrls.totMemAccLat 27664 # Total ticks spent from burst creation until serviced by the DRAM
system.mem_ctrls.totBusLat 4415 # Total ticks spent in databus transfers
system.mem_ctrls.avgQLat 12.33 # Average queueing delay per DRAM burst
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
system.mem_ctrls.avgMemAccLat 31.28 # Average memory access latency per DRAM burst
system.mem_ctrls.avgRdBW 530.70 # Average DRAM read bandwidth in MiByte/s
system.mem_ctrls.avgWrBW 526.52 # Average achieved write bandwidth in MiByte/s
system.mem_ctrls.avgRdBWSys 1032.74 # Average system read bandwidth in MiByte/s
system.mem_ctrls.avgWrBWSys 1030.35 # Average system write bandwidth in MiByte/s
system.mem_ctrls.avgMemAccLat 31.33 # Average memory access latency per DRAM burst
system.mem_ctrls.avgRdBW 527.83 # Average DRAM read bandwidth in MiByte/s
system.mem_ctrls.avgWrBW 540.38 # Average achieved write bandwidth in MiByte/s
system.mem_ctrls.avgRdBWSys 1034.74 # Average system read bandwidth in MiByte/s
system.mem_ctrls.avgWrBWSys 1032.34 # Average system write bandwidth in MiByte/s
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.mem_ctrls.busUtil 8.26 # Data bus utilization in percentage
system.mem_ctrls.busUtilRead 4.15 # Data bus utilization in percentage for reads
system.mem_ctrls.busUtilWrite 4.11 # Data bus utilization in percentage for writes
system.mem_ctrls.busUtil 8.35 # Data bus utilization in percentage
system.mem_ctrls.busUtilRead 4.12 # Data bus utilization in percentage for reads
system.mem_ctrls.busUtilWrite 4.22 # Data bus utilization in percentage for writes
system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing
system.mem_ctrls.avgWrQLen 25.52 # Average write queue length when enqueuing
system.mem_ctrls.readRowHits 682 # Number of row buffer hits during reads
system.mem_ctrls.writeRowHits 829 # Number of row buffer hits during writes
system.mem_ctrls.readRowHitRate 76.72 # Row buffer hit rate for reads
system.mem_ctrls.writeRowHitRate 90.90 # Row buffer hit rate for writes
system.mem_ctrls.avgGap 31.00 # Average gap between requests
system.mem_ctrls.pageHitRate 83.90 # Row buffer hit rate, read and write combined
system.mem_ctrls_0.actEnergy 748440 # Energy for activate commands per rank (pJ)
system.mem_ctrls_0.preEnergy 415800 # Energy for precharge commands per rank (pJ)
system.mem_ctrls_0.readEnergy 5166720 # Energy for read commands per rank (pJ)
system.mem_ctrls_0.writeEnergy 4447872 # Energy for write commands per rank (pJ)
system.mem_ctrls.avgWrQLen 26.13 # Average write queue length when enqueuing
system.mem_ctrls.readRowHits 670 # Number of row buffer hits during reads
system.mem_ctrls.writeRowHits 835 # Number of row buffer hits during writes
system.mem_ctrls.readRowHitRate 75.88 # Row buffer hit rate for reads
system.mem_ctrls.writeRowHitRate 89.30 # Row buffer hit rate for writes
system.mem_ctrls.avgGap 30.94 # Average gap between requests
system.mem_ctrls.pageHitRate 82.78 # Row buffer hit rate, read and write combined
system.mem_ctrls_0.actEnergy 876960 # Energy for activate commands per rank (pJ)
system.mem_ctrls_0.preEnergy 487200 # Energy for precharge commands per rank (pJ)
system.mem_ctrls_0.readEnergy 4992000 # Energy for read commands per rank (pJ)
system.mem_ctrls_0.writeEnergy 4489344 # Energy for write commands per rank (pJ)
system.mem_ctrls_0.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ)
system.mem_ctrls_0.actBackEnergy 64735128 # Energy for active background per rank (pJ)
system.mem_ctrls_0.preBackEnergy 4101600 # Energy for precharge background per rank (pJ)
system.mem_ctrls_0.totalEnergy 86226840 # Total energy per rank (pJ)
system.mem_ctrls_0.averagePower 849.709691 # Core power per rank (mW)
system.mem_ctrls_0.memoryStateTime::IDLE 7218 # Time in different power states
system.mem_ctrls_0.actBackEnergy 63943740 # Energy for active background per rank (pJ)
system.mem_ctrls_0.preBackEnergy 4795800 # Energy for precharge background per rank (pJ)
system.mem_ctrls_0.totalEnergy 86196324 # Total energy per rank (pJ)
system.mem_ctrls_0.averagePower 849.408975 # Core power per rank (mW)
system.mem_ctrls_0.memoryStateTime::IDLE 8418 # Time in different power states
system.mem_ctrls_0.memoryStateTime::REF 3380 # Time in different power states
system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.mem_ctrls_0.memoryStateTime::ACT 91640 # Time in different power states
system.mem_ctrls_0.memoryStateTime::ACT 90483 # Time in different power states
system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.mem_ctrls_1.actEnergy 1088640 # Energy for activate commands per rank (pJ)
system.mem_ctrls_1.preEnergy 604800 # Energy for precharge commands per rank (pJ)
system.mem_ctrls_1.readEnergy 5241600 # Energy for read commands per rank (pJ)
system.mem_ctrls_1.writeEnergy 4167936 # Energy for write commands per rank (pJ)
system.mem_ctrls_1.actEnergy 1156680 # Energy for activate commands per rank (pJ)
system.mem_ctrls_1.preEnergy 642600 # Energy for precharge commands per rank (pJ)
system.mem_ctrls_1.readEnergy 5366400 # Energy for read commands per rank (pJ)
system.mem_ctrls_1.writeEnergy 4385664 # Energy for write commands per rank (pJ)
system.mem_ctrls_1.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ)
system.mem_ctrls_1.actBackEnergy 64577808 # Energy for active background per rank (pJ)
system.mem_ctrls_1.preBackEnergy 4239600 # Energy for precharge background per rank (pJ)
system.mem_ctrls_1.totalEnergy 86531664 # Total energy per rank (pJ)
system.mem_ctrls_1.averagePower 852.713534 # Core power per rank (mW)
system.mem_ctrls_1.memoryStateTime::IDLE 6460 # Time in different power states
system.mem_ctrls_1.actBackEnergy 65375352 # Energy for active background per rank (pJ)
system.mem_ctrls_1.preBackEnergy 3540000 # Energy for precharge background per rank (pJ)
system.mem_ctrls_1.totalEnergy 87077976 # Total energy per rank (pJ)
system.mem_ctrls_1.averagePower 858.097085 # Core power per rank (mW)
system.mem_ctrls_1.memoryStateTime::IDLE 5471 # Time in different power states
system.mem_ctrls_1.memoryStateTime::REF 3380 # Time in different power states
system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT 91652 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT 92641 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.clk_domain.clock 1 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 1183 # DTB read hits
system.cpu.dtb.read_hits 1185 # DTB read hits
system.cpu.dtb.read_misses 7 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 1190 # DTB read accesses
system.cpu.dtb.read_accesses 1192 # DTB read accesses
system.cpu.dtb.write_hits 865 # DTB write hits
system.cpu.dtb.write_misses 3 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 868 # DTB write accesses
system.cpu.dtb.data_hits 2048 # DTB hits
system.cpu.dtb.data_hits 2050 # DTB hits
system.cpu.dtb.data_misses 10 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 2058 # DTB accesses
system.cpu.itb.fetch_hits 6401 # ITB hits
system.cpu.dtb.data_accesses 2060 # DTB accesses
system.cpu.itb.fetch_hits 6414 # ITB hits
system.cpu.itb.fetch_misses 17 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 6418 # ITB accesses
system.cpu.itb.fetch_accesses 6431 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@ -301,210 +301,210 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
system.cpu.numCycles 107210 # number of cpu cycles simulated
system.cpu.numCycles 107065 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 6390 # Number of instructions committed
system.cpu.committedOps 6390 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses
system.cpu.committedInsts 6403 # Number of instructions committed
system.cpu.committedOps 6403 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 6329 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
system.cpu.num_func_calls 251 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls
system.cpu.num_int_insts 6317 # number of integer instructions
system.cpu.num_conditional_control_insts 754 # number of instructions that are conditional controls
system.cpu.num_int_insts 6329 # number of integer instructions
system.cpu.num_fp_insts 10 # number of float instructions
system.cpu.num_int_register_reads 8285 # number of times the integer registers were read
system.cpu.num_int_register_writes 4568 # number of times the integer registers were written
system.cpu.num_int_register_reads 8297 # number of times the integer registers were read
system.cpu.num_int_register_writes 4575 # number of times the integer registers were written
system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
system.cpu.num_mem_refs 2058 # number of memory refs
system.cpu.num_load_insts 1190 # Number of load instructions
system.cpu.num_mem_refs 2060 # number of memory refs
system.cpu.num_load_insts 1192 # Number of load instructions
system.cpu.num_store_insts 868 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 107210 # Number of busy cycles
system.cpu.num_busy_cycles 107065 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.Branches 1050 # Number of branches fetched
system.cpu.Branches 1056 # Number of branches fetched
system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction
system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction
system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction
system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction
system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction
system.cpu.op_class::IntAlu 4331 67.53% 67.83% # Class of executed instruction
system.cpu.op_class::IntMult 1 0.02% 67.85% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 67.85% # Class of executed instruction
system.cpu.op_class::FloatAdd 2 0.03% 67.88% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::MemRead 1192 18.59% 86.46% # Class of executed instruction
system.cpu.op_class::MemWrite 868 13.54% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 6400 # Class of executed instruction
system.cpu.op_class::total 6413 # Class of executed instruction
system.ruby.clk_domain.clock 1 # Clock period in ticks
system.ruby.delayHist::bucket_size 1 # delay histogram for all message
system.ruby.delayHist::max_bucket 9 # delay histogram for all message
system.ruby.delayHist::samples 3456 # delay histogram for all message
system.ruby.delayHist | 3456 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message
system.ruby.delayHist::total 3456 # delay histogram for all message
system.ruby.delayHist::samples 3458 # delay histogram for all message
system.ruby.delayHist | 3458 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message
system.ruby.delayHist::total 3458 # delay histogram for all message
system.ruby.outstanding_req_hist_seqr::bucket_size 1
system.ruby.outstanding_req_hist_seqr::max_bucket 9
system.ruby.outstanding_req_hist_seqr::samples 8449
system.ruby.outstanding_req_hist_seqr::samples 8464
system.ruby.outstanding_req_hist_seqr::mean 1
system.ruby.outstanding_req_hist_seqr::gmean 1
system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 8449 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.outstanding_req_hist_seqr::total 8449
system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 8464 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.outstanding_req_hist_seqr::total 8464
system.ruby.latency_hist_seqr::bucket_size 64
system.ruby.latency_hist_seqr::max_bucket 639
system.ruby.latency_hist_seqr::samples 8448
system.ruby.latency_hist_seqr::mean 11.690578
system.ruby.latency_hist_seqr::gmean 2.205273
system.ruby.latency_hist_seqr::stdev 25.830363
system.ruby.latency_hist_seqr | 8209 97.17% 97.17% | 184 2.18% 99.35% | 38 0.45% 99.80% | 7 0.08% 99.88% | 6 0.07% 99.95% | 3 0.04% 99.99% | 0 0.00% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.latency_hist_seqr::total 8448
system.ruby.latency_hist_seqr::samples 8463
system.ruby.latency_hist_seqr::mean 11.650951
system.ruby.latency_hist_seqr::gmean 2.202191
system.ruby.latency_hist_seqr::stdev 25.742711
system.ruby.latency_hist_seqr | 8220 97.13% 97.13% | 190 2.25% 99.37% | 41 0.48% 99.86% | 1 0.01% 99.87% | 6 0.07% 99.94% | 4 0.05% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.latency_hist_seqr::total 8463
system.ruby.hit_latency_hist_seqr::bucket_size 1
system.ruby.hit_latency_hist_seqr::max_bucket 9
system.ruby.hit_latency_hist_seqr::samples 6718
system.ruby.hit_latency_hist_seqr::samples 6732
system.ruby.hit_latency_hist_seqr::mean 1
system.ruby.hit_latency_hist_seqr::gmean 1
system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 6718 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.hit_latency_hist_seqr::total 6718
system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 6732 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.hit_latency_hist_seqr::total 6732
system.ruby.miss_latency_hist_seqr::bucket_size 64
system.ruby.miss_latency_hist_seqr::max_bucket 639
system.ruby.miss_latency_hist_seqr::samples 1730
system.ruby.miss_latency_hist_seqr::mean 53.204624
system.ruby.miss_latency_hist_seqr::gmean 47.556283
system.ruby.miss_latency_hist_seqr::stdev 33.032605
system.ruby.miss_latency_hist_seqr | 1491 86.18% 86.18% | 184 10.64% 96.82% | 38 2.20% 99.02% | 7 0.40% 99.42% | 6 0.35% 99.77% | 3 0.17% 99.94% | 0 0.00% 99.94% | 1 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.miss_latency_hist_seqr::total 1730
system.ruby.Directory.incomplete_times_seqr 1729
system.ruby.l1_cntrl0.cacheMemory.demand_hits 6718 # Number of cache demand hits
system.ruby.l1_cntrl0.cacheMemory.demand_misses 1730 # Number of cache demand misses
system.ruby.l1_cntrl0.cacheMemory.demand_accesses 8448 # Number of cache demand accesses
system.ruby.miss_latency_hist_seqr::samples 1731
system.ruby.miss_latency_hist_seqr::mean 53.073368
system.ruby.miss_latency_hist_seqr::gmean 47.451096
system.ruby.miss_latency_hist_seqr::stdev 32.911544
system.ruby.miss_latency_hist_seqr | 1488 85.96% 85.96% | 190 10.98% 96.94% | 41 2.37% 99.31% | 1 0.06% 99.36% | 6 0.35% 99.71% | 4 0.23% 99.94% | 1 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.miss_latency_hist_seqr::total 1731
system.ruby.Directory.incomplete_times_seqr 1730
system.ruby.l1_cntrl0.cacheMemory.demand_hits 6732 # Number of cache demand hits
system.ruby.l1_cntrl0.cacheMemory.demand_misses 1731 # Number of cache demand misses
system.ruby.l1_cntrl0.cacheMemory.demand_accesses 8463 # Number of cache demand accesses
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
system.ruby.network.routers0.percent_links_utilized 8.058950
system.ruby.network.routers0.msg_count.Control::2 1730
system.ruby.network.routers0.msg_count.Data::2 1726
system.ruby.network.routers0.msg_count.Response_Data::4 1730
system.ruby.network.routers0.msg_count.Writeback_Control::3 1726
system.ruby.network.routers0.msg_bytes.Control::2 13840
system.ruby.network.routers0.msg_bytes.Data::2 124272
system.ruby.network.routers0.msg_bytes.Response_Data::4 124560
system.ruby.network.routers0.msg_bytes.Writeback_Control::3 13808
system.ruby.network.routers1.percent_links_utilized 8.058950
system.ruby.network.routers1.msg_count.Control::2 1730
system.ruby.network.routers1.msg_count.Data::2 1726
system.ruby.network.routers1.msg_count.Response_Data::4 1730
system.ruby.network.routers1.msg_count.Writeback_Control::3 1726
system.ruby.network.routers1.msg_bytes.Control::2 13840
system.ruby.network.routers1.msg_bytes.Data::2 124272
system.ruby.network.routers1.msg_bytes.Response_Data::4 124560
system.ruby.network.routers1.msg_bytes.Writeback_Control::3 13808
system.ruby.network.routers2.percent_links_utilized 8.058950
system.ruby.network.routers2.msg_count.Control::2 1730
system.ruby.network.routers2.msg_count.Data::2 1726
system.ruby.network.routers2.msg_count.Response_Data::4 1730
system.ruby.network.routers2.msg_count.Writeback_Control::3 1726
system.ruby.network.routers2.msg_bytes.Control::2 13840
system.ruby.network.routers2.msg_bytes.Data::2 124272
system.ruby.network.routers2.msg_bytes.Response_Data::4 124560
system.ruby.network.routers2.msg_bytes.Writeback_Control::3 13808
system.ruby.network.msg_count.Control 5190
system.ruby.network.msg_count.Data 5178
system.ruby.network.msg_count.Response_Data 5190
system.ruby.network.msg_count.Writeback_Control 5178
system.ruby.network.msg_byte.Control 41520
system.ruby.network.msg_byte.Data 372816
system.ruby.network.msg_byte.Response_Data 373680
system.ruby.network.msg_byte.Writeback_Control 41424
system.ruby.network.routers0.throttle0.link_utilization 8.066412
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1730
system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1726
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 124560
system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 13808
system.ruby.network.routers0.throttle1.link_utilization 8.051488
system.ruby.network.routers0.throttle1.msg_count.Control::2 1730
system.ruby.network.routers0.throttle1.msg_count.Data::2 1726
system.ruby.network.routers0.throttle1.msg_bytes.Control::2 13840
system.ruby.network.routers0.throttle1.msg_bytes.Data::2 124272
system.ruby.network.routers1.throttle0.link_utilization 8.051488
system.ruby.network.routers1.throttle0.msg_count.Control::2 1730
system.ruby.network.routers1.throttle0.msg_count.Data::2 1726
system.ruby.network.routers1.throttle0.msg_bytes.Control::2 13840
system.ruby.network.routers1.throttle0.msg_bytes.Data::2 124272
system.ruby.network.routers1.throttle1.link_utilization 8.066412
system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1730
system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1726
system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 124560
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 13808
system.ruby.network.routers2.throttle0.link_utilization 8.066412
system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1730
system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1726
system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 124560
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 13808
system.ruby.network.routers2.throttle1.link_utilization 8.051488
system.ruby.network.routers2.throttle1.msg_count.Control::2 1730
system.ruby.network.routers2.throttle1.msg_count.Data::2 1726
system.ruby.network.routers2.throttle1.msg_bytes.Control::2 13840
system.ruby.network.routers2.throttle1.msg_bytes.Data::2 124272
system.ruby.network.routers0.percent_links_utilized 8.074534
system.ruby.network.routers0.msg_count.Control::2 1731
system.ruby.network.routers0.msg_count.Data::2 1727
system.ruby.network.routers0.msg_count.Response_Data::4 1731
system.ruby.network.routers0.msg_count.Writeback_Control::3 1727
system.ruby.network.routers0.msg_bytes.Control::2 13848
system.ruby.network.routers0.msg_bytes.Data::2 124344
system.ruby.network.routers0.msg_bytes.Response_Data::4 124632
system.ruby.network.routers0.msg_bytes.Writeback_Control::3 13816
system.ruby.network.routers1.percent_links_utilized 8.074534
system.ruby.network.routers1.msg_count.Control::2 1731
system.ruby.network.routers1.msg_count.Data::2 1727
system.ruby.network.routers1.msg_count.Response_Data::4 1731
system.ruby.network.routers1.msg_count.Writeback_Control::3 1727
system.ruby.network.routers1.msg_bytes.Control::2 13848
system.ruby.network.routers1.msg_bytes.Data::2 124344
system.ruby.network.routers1.msg_bytes.Response_Data::4 124632
system.ruby.network.routers1.msg_bytes.Writeback_Control::3 13816
system.ruby.network.routers2.percent_links_utilized 8.074534
system.ruby.network.routers2.msg_count.Control::2 1731
system.ruby.network.routers2.msg_count.Data::2 1727
system.ruby.network.routers2.msg_count.Response_Data::4 1731
system.ruby.network.routers2.msg_count.Writeback_Control::3 1727
system.ruby.network.routers2.msg_bytes.Control::2 13848
system.ruby.network.routers2.msg_bytes.Data::2 124344
system.ruby.network.routers2.msg_bytes.Response_Data::4 124632
system.ruby.network.routers2.msg_bytes.Writeback_Control::3 13816
system.ruby.network.msg_count.Control 5193
system.ruby.network.msg_count.Data 5181
system.ruby.network.msg_count.Response_Data 5193
system.ruby.network.msg_count.Writeback_Control 5181
system.ruby.network.msg_byte.Control 41544
system.ruby.network.msg_byte.Data 373032
system.ruby.network.msg_byte.Response_Data 373896
system.ruby.network.msg_byte.Writeback_Control 41448
system.ruby.network.routers0.throttle0.link_utilization 8.082006
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1731
system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1727
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 124632
system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 13816
system.ruby.network.routers0.throttle1.link_utilization 8.067062
system.ruby.network.routers0.throttle1.msg_count.Control::2 1731
system.ruby.network.routers0.throttle1.msg_count.Data::2 1727
system.ruby.network.routers0.throttle1.msg_bytes.Control::2 13848
system.ruby.network.routers0.throttle1.msg_bytes.Data::2 124344
system.ruby.network.routers1.throttle0.link_utilization 8.067062
system.ruby.network.routers1.throttle0.msg_count.Control::2 1731
system.ruby.network.routers1.throttle0.msg_count.Data::2 1727
system.ruby.network.routers1.throttle0.msg_bytes.Control::2 13848
system.ruby.network.routers1.throttle0.msg_bytes.Data::2 124344
system.ruby.network.routers1.throttle1.link_utilization 8.082006
system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1731
system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1727
system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 124632
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 13816
system.ruby.network.routers2.throttle0.link_utilization 8.082006
system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1731
system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1727
system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 124632
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 13816
system.ruby.network.routers2.throttle1.link_utilization 8.067062
system.ruby.network.routers2.throttle1.msg_count.Control::2 1731
system.ruby.network.routers2.throttle1.msg_count.Data::2 1727
system.ruby.network.routers2.throttle1.msg_bytes.Control::2 13848
system.ruby.network.routers2.throttle1.msg_bytes.Data::2 124344
system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1::samples 1730 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1 | 1730 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1::total 1730 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1::samples 1731 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1 | 1731 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1::total 1731 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2::samples 1726 # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2 | 1726 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2::total 1726 # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2::samples 1727 # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2 | 1727 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2::total 1727 # delay histogram for vnet_2
system.ruby.LD.latency_hist_seqr::bucket_size 64
system.ruby.LD.latency_hist_seqr::max_bucket 639
system.ruby.LD.latency_hist_seqr::samples 1183
system.ruby.LD.latency_hist_seqr::mean 31.638208
system.ruby.LD.latency_hist_seqr::gmean 10.419015
system.ruby.LD.latency_hist_seqr::stdev 35.065266
system.ruby.LD.latency_hist_seqr | 1085 91.72% 91.72% | 74 6.26% 97.97% | 18 1.52% 99.49% | 2 0.17% 99.66% | 3 0.25% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.latency_hist_seqr::total 1183
system.ruby.LD.latency_hist_seqr::samples 1185
system.ruby.LD.latency_hist_seqr::mean 31.532489
system.ruby.LD.latency_hist_seqr::gmean 10.421226
system.ruby.LD.latency_hist_seqr::stdev 34.906160
system.ruby.LD.latency_hist_seqr | 1091 92.07% 92.07% | 75 6.33% 98.40% | 15 1.27% 99.66% | 0 0.00% 99.66% | 2 0.17% 99.83% | 1 0.08% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.latency_hist_seqr::total 1185
system.ruby.LD.hit_latency_hist_seqr::bucket_size 1
system.ruby.LD.hit_latency_hist_seqr::max_bucket 9
system.ruby.LD.hit_latency_hist_seqr::samples 456
system.ruby.LD.hit_latency_hist_seqr::samples 457
system.ruby.LD.hit_latency_hist_seqr::mean 1
system.ruby.LD.hit_latency_hist_seqr::gmean 1
system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 456 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.hit_latency_hist_seqr::total 456
system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 457 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.hit_latency_hist_seqr::total 457
system.ruby.LD.miss_latency_hist_seqr::bucket_size 64
system.ruby.LD.miss_latency_hist_seqr::max_bucket 639
system.ruby.LD.miss_latency_hist_seqr::samples 727
system.ruby.LD.miss_latency_hist_seqr::mean 50.855571
system.ruby.LD.miss_latency_hist_seqr::gmean 45.315147
system.ruby.LD.miss_latency_hist_seqr::stdev 32.287061
system.ruby.LD.miss_latency_hist_seqr | 629 86.52% 86.52% | 74 10.18% 96.70% | 18 2.48% 99.17% | 2 0.28% 99.45% | 3 0.41% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.miss_latency_hist_seqr::total 727
system.ruby.LD.miss_latency_hist_seqr::samples 728
system.ruby.LD.miss_latency_hist_seqr::mean 50.699176
system.ruby.LD.miss_latency_hist_seqr::gmean 45.385232
system.ruby.LD.miss_latency_hist_seqr::stdev 32.101179
system.ruby.LD.miss_latency_hist_seqr | 634 87.09% 87.09% | 75 10.30% 97.39% | 15 2.06% 99.45% | 0 0.00% 99.45% | 2 0.27% 99.73% | 1 0.14% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.miss_latency_hist_seqr::total 728
system.ruby.ST.latency_hist_seqr::bucket_size 32
system.ruby.ST.latency_hist_seqr::max_bucket 319
system.ruby.ST.latency_hist_seqr::samples 865
system.ruby.ST.latency_hist_seqr::mean 16.483237
system.ruby.ST.latency_hist_seqr::gmean 3.324735
system.ruby.ST.latency_hist_seqr::stdev 28.016571
system.ruby.ST.latency_hist_seqr | 592 68.44% 68.44% | 244 28.21% 96.65% | 18 2.08% 98.73% | 2 0.23% 98.96% | 5 0.58% 99.54% | 2 0.23% 99.77% | 1 0.12% 99.88% | 0 0.00% 99.88% | 1 0.12% 100.00% | 0 0.00% 100.00%
system.ruby.ST.latency_hist_seqr::mean 16.426590
system.ruby.ST.latency_hist_seqr::gmean 3.318487
system.ruby.ST.latency_hist_seqr::stdev 28.264983
system.ruby.ST.latency_hist_seqr | 592 68.44% 68.44% | 242 27.98% 96.42% | 21 2.43% 98.84% | 1 0.12% 98.96% | 4 0.46% 99.42% | 4 0.46% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 1 0.12% 100.00%
system.ruby.ST.latency_hist_seqr::total 865
system.ruby.ST.hit_latency_hist_seqr::bucket_size 1
system.ruby.ST.hit_latency_hist_seqr::max_bucket 9
@ -516,42 +516,42 @@ system.ruby.ST.hit_latency_hist_seqr::total 592
system.ruby.ST.miss_latency_hist_seqr::bucket_size 32
system.ruby.ST.miss_latency_hist_seqr::max_bucket 319
system.ruby.ST.miss_latency_hist_seqr::samples 273
system.ruby.ST.miss_latency_hist_seqr::mean 50.058608
system.ruby.ST.miss_latency_hist_seqr::gmean 44.997273
system.ruby.ST.miss_latency_hist_seqr::stdev 28.984216
system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 244 89.38% 89.38% | 18 6.59% 95.97% | 2 0.73% 96.70% | 5 1.83% 98.53% | 2 0.73% 99.27% | 1 0.37% 99.63% | 0 0.00% 99.63% | 1 0.37% 100.00% | 0 0.00% 100.00%
system.ruby.ST.miss_latency_hist_seqr::mean 49.879121
system.ruby.ST.miss_latency_hist_seqr::gmean 44.729882
system.ruby.ST.miss_latency_hist_seqr::stdev 29.942777
system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 242 88.64% 88.64% | 21 7.69% 96.34% | 1 0.37% 96.70% | 4 1.47% 98.17% | 4 1.47% 99.63% | 0 0.00% 99.63% | 0 0.00% 99.63% | 0 0.00% 99.63% | 1 0.37% 100.00%
system.ruby.ST.miss_latency_hist_seqr::total 273
system.ruby.IFETCH.latency_hist_seqr::bucket_size 64
system.ruby.IFETCH.latency_hist_seqr::max_bucket 639
system.ruby.IFETCH.latency_hist_seqr::samples 6400
system.ruby.IFETCH.latency_hist_seqr::mean 7.355625
system.ruby.IFETCH.latency_hist_seqr::gmean 1.565715
system.ruby.IFETCH.latency_hist_seqr::stdev 21.264557
system.ruby.IFETCH.latency_hist_seqr | 6288 98.25% 98.25% | 90 1.41% 99.66% | 13 0.20% 99.86% | 4 0.06% 99.92% | 2 0.03% 99.95% | 2 0.03% 99.98% | 0 0.00% 99.98% | 1 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.latency_hist_seqr::total 6400
system.ruby.IFETCH.latency_hist_seqr::samples 6413
system.ruby.IFETCH.latency_hist_seqr::mean 7.333073
system.ruby.IFETCH.latency_hist_seqr::gmean 1.563492
system.ruby.IFETCH.latency_hist_seqr::stdev 21.145733
system.ruby.IFETCH.latency_hist_seqr | 6295 98.16% 98.16% | 93 1.45% 99.61% | 18 0.28% 99.89% | 1 0.02% 99.91% | 3 0.05% 99.95% | 3 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.latency_hist_seqr::total 6413
system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1
system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9
system.ruby.IFETCH.hit_latency_hist_seqr::samples 5670
system.ruby.IFETCH.hit_latency_hist_seqr::samples 5683
system.ruby.IFETCH.hit_latency_hist_seqr::mean 1
system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1
system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 5670 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.hit_latency_hist_seqr::total 5670
system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 5683 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.hit_latency_hist_seqr::total 5683
system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64
system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639
system.ruby.IFETCH.miss_latency_hist_seqr::samples 730
system.ruby.IFETCH.miss_latency_hist_seqr::mean 56.720548
system.ruby.IFETCH.miss_latency_hist_seqr::gmean 50.941265
system.ruby.IFETCH.miss_latency_hist_seqr::stdev 34.853032
system.ruby.IFETCH.miss_latency_hist_seqr | 618 84.66% 84.66% | 90 12.33% 96.99% | 13 1.78% 98.77% | 4 0.55% 99.32% | 2 0.27% 99.59% | 2 0.27% 99.86% | 0 0.00% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.miss_latency_hist_seqr::mean 56.635616
system.ruby.IFETCH.miss_latency_hist_seqr::gmean 50.712708
system.ruby.IFETCH.miss_latency_hist_seqr::stdev 34.440483
system.ruby.IFETCH.miss_latency_hist_seqr | 612 83.84% 83.84% | 93 12.74% 96.58% | 18 2.47% 99.04% | 1 0.14% 99.18% | 3 0.41% 99.59% | 3 0.41% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.miss_latency_hist_seqr::total 730
system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64
system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639
system.ruby.Directory.miss_mach_latency_hist_seqr::samples 1730
system.ruby.Directory.miss_mach_latency_hist_seqr::mean 53.204624
system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 47.556283
system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 33.032605
system.ruby.Directory.miss_mach_latency_hist_seqr | 1491 86.18% 86.18% | 184 10.64% 96.82% | 38 2.20% 99.02% | 7 0.40% 99.42% | 6 0.35% 99.77% | 3 0.17% 99.94% | 0 0.00% 99.94% | 1 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.Directory.miss_mach_latency_hist_seqr::total 1730
system.ruby.Directory.miss_mach_latency_hist_seqr::samples 1731
system.ruby.Directory.miss_mach_latency_hist_seqr::mean 53.073368
system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 47.451096
system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 32.911544
system.ruby.Directory.miss_mach_latency_hist_seqr | 1488 85.96% 85.96% | 190 10.98% 96.94% | 41 2.37% 99.31% | 1 0.06% 99.36% | 6 0.35% 99.71% | 4 0.23% 99.94% | 1 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.Directory.miss_mach_latency_hist_seqr::total 1731
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 1
@ -580,51 +580,51 @@ system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion |
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 727
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 50.855571
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 45.315147
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 32.287061
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 629 86.52% 86.52% | 74 10.18% 96.70% | 18 2.48% 99.17% | 2 0.28% 99.45% | 3 0.41% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 727
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 728
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 50.699176
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 45.385232
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 32.101179
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 634 87.09% 87.09% | 75 10.30% 97.39% | 15 2.06% 99.45% | 0 0.00% 99.45% | 2 0.27% 99.73% | 1 0.14% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 728
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 273
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 50.058608
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 44.997273
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 28.984216
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 244 89.38% 89.38% | 18 6.59% 95.97% | 2 0.73% 96.70% | 5 1.83% 98.53% | 2 0.73% 99.27% | 1 0.37% 99.63% | 0 0.00% 99.63% | 1 0.37% 100.00% | 0 0.00% 100.00%
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 49.879121
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 44.729882
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 29.942777
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 242 88.64% 88.64% | 21 7.69% 96.34% | 1 0.37% 96.70% | 4 1.47% 98.17% | 4 1.47% 99.63% | 0 0.00% 99.63% | 0 0.00% 99.63% | 0 0.00% 99.63% | 1 0.37% 100.00%
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 273
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 730
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 56.720548
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 50.941265
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 34.853032
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 618 84.66% 84.66% | 90 12.33% 96.99% | 13 1.78% 98.77% | 4 0.55% 99.32% | 2 0.27% 99.59% | 2 0.27% 99.86% | 0 0.00% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 56.635616
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 50.712708
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 34.440483
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 612 83.84% 83.84% | 93 12.74% 96.58% | 18 2.47% 99.04% | 1 0.14% 99.18% | 3 0.41% 99.59% | 3 0.41% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 730
system.ruby.Directory_Controller.GETX 1730 0.00% 0.00%
system.ruby.Directory_Controller.PUTX 1726 0.00% 0.00%
system.ruby.Directory_Controller.Memory_Data 1730 0.00% 0.00%
system.ruby.Directory_Controller.Memory_Ack 1726 0.00% 0.00%
system.ruby.Directory_Controller.I.GETX 1730 0.00% 0.00%
system.ruby.Directory_Controller.M.PUTX 1726 0.00% 0.00%
system.ruby.Directory_Controller.IM.Memory_Data 1730 0.00% 0.00%
system.ruby.Directory_Controller.MI.Memory_Ack 1726 0.00% 0.00%
system.ruby.L1Cache_Controller.Load 1183 0.00% 0.00%
system.ruby.L1Cache_Controller.Ifetch 6400 0.00% 0.00%
system.ruby.Directory_Controller.GETX 1731 0.00% 0.00%
system.ruby.Directory_Controller.PUTX 1727 0.00% 0.00%
system.ruby.Directory_Controller.Memory_Data 1731 0.00% 0.00%
system.ruby.Directory_Controller.Memory_Ack 1727 0.00% 0.00%
system.ruby.Directory_Controller.I.GETX 1731 0.00% 0.00%
system.ruby.Directory_Controller.M.PUTX 1727 0.00% 0.00%
system.ruby.Directory_Controller.IM.Memory_Data 1731 0.00% 0.00%
system.ruby.Directory_Controller.MI.Memory_Ack 1727 0.00% 0.00%
system.ruby.L1Cache_Controller.Load 1185 0.00% 0.00%
system.ruby.L1Cache_Controller.Ifetch 6413 0.00% 0.00%
system.ruby.L1Cache_Controller.Store 865 0.00% 0.00%
system.ruby.L1Cache_Controller.Data 1730 0.00% 0.00%
system.ruby.L1Cache_Controller.Replacement 1726 0.00% 0.00%
system.ruby.L1Cache_Controller.Writeback_Ack 1726 0.00% 0.00%
system.ruby.L1Cache_Controller.I.Load 727 0.00% 0.00%
system.ruby.L1Cache_Controller.Data 1731 0.00% 0.00%
system.ruby.L1Cache_Controller.Replacement 1727 0.00% 0.00%
system.ruby.L1Cache_Controller.Writeback_Ack 1727 0.00% 0.00%
system.ruby.L1Cache_Controller.I.Load 728 0.00% 0.00%
system.ruby.L1Cache_Controller.I.Ifetch 730 0.00% 0.00%
system.ruby.L1Cache_Controller.I.Store 273 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Load 456 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Ifetch 5670 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Load 457 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Ifetch 5683 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Store 592 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Replacement 1726 0.00% 0.00%
system.ruby.L1Cache_Controller.MI.Writeback_Ack 1726 0.00% 0.00%
system.ruby.L1Cache_Controller.IS.Data 1457 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Replacement 1727 0.00% 0.00%
system.ruby.L1Cache_Controller.MI.Writeback_Ack 1727 0.00% 0.00%
system.ruby.L1Cache_Controller.IS.Data 1458 0.00% 0.00%
system.ruby.L1Cache_Controller.IM.Data 273 0.00% 0.00%
---------- End Simulation Statistics ----------

7
tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini
View file

@ -88,7 +88,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@ -130,7 +129,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
@ -181,7 +179,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
@ -216,6 +213,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
point_of_coherency=false
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
@ -246,7 +244,7 @@ env=
errout=cerr
euid=100
eventq_index=0
executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
kvmInSE=false
@ -281,6 +279,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4

12
tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout
View file

@ -1,13 +1,15 @@
Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing/simout
Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 21 2016 13:49:21
gem5 started Jan 21 2016 13:50:02
gem5 executing on zizzer, pid 34003
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing
gem5 compiled Mar 14 2016 21:54:46
gem5 started Mar 14 2016 21:56:12
gem5 executing on phenom, pid 28101
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
Exiting @ tick 35667500 because target called exit()
Exiting @ tick 35682500 because target called exit()

276
tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt
View file

@ -1,16 +1,16 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000036 # Number of seconds simulated
sim_ticks 35667500 # Number of ticks simulated
final_tick 35667500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 35682500 # Number of ticks simulated
final_tick 35682500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 102057 # Simulator instruction rate (inst/s)
host_op_rate 102013 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 569174066 # Simulator tick rate (ticks/s)
host_mem_usage 230332 # Number of bytes of host memory used
host_seconds 0.06 # Real time elapsed on the host
sim_insts 6390 # Number of instructions simulated
sim_ops 6390 # Number of ops (including micro ops) simulated
host_inst_rate 44587 # Simulator instruction rate (inst/s)
host_op_rate 44581 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 248411942 # Simulator tick rate (ticks/s)
host_mem_usage 226904 # Number of bytes of host memory used
host_seconds 0.14 # Real time elapsed on the host
sim_insts 6403 # Number of instructions simulated
sim_ops 6403 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory
@ -21,35 +21,35 @@ system.physmem.bytes_inst_read::total 17792 # Nu
system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory
system.physmem.num_reads::total 446 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 498829467 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 301450901 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 800280367 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 498829467 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 498829467 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 498829467 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 301450901 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 800280367 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 498619772 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 301324179 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 799943950 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 498619772 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 498619772 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 498619772 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 301324179 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 799943950 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 1183 # DTB read hits
system.cpu.dtb.read_hits 1185 # DTB read hits
system.cpu.dtb.read_misses 7 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 1190 # DTB read accesses
system.cpu.dtb.read_accesses 1192 # DTB read accesses
system.cpu.dtb.write_hits 865 # DTB write hits
system.cpu.dtb.write_misses 3 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 868 # DTB write accesses
system.cpu.dtb.data_hits 2048 # DTB hits
system.cpu.dtb.data_hits 2050 # DTB hits
system.cpu.dtb.data_misses 10 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 2058 # DTB accesses
system.cpu.itb.fetch_hits 6401 # ITB hits
system.cpu.dtb.data_accesses 2060 # DTB accesses
system.cpu.itb.fetch_hits 6414 # ITB hits
system.cpu.itb.fetch_misses 17 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 6418 # ITB accesses
system.cpu.itb.fetch_accesses 6431 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@ -63,87 +63,87 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
system.cpu.numCycles 71335 # number of cpu cycles simulated
system.cpu.numCycles 71365 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 6390 # Number of instructions committed
system.cpu.committedOps 6390 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses
system.cpu.committedInsts 6403 # Number of instructions committed
system.cpu.committedOps 6403 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 6329 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
system.cpu.num_func_calls 251 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls
system.cpu.num_int_insts 6317 # number of integer instructions
system.cpu.num_conditional_control_insts 754 # number of instructions that are conditional controls
system.cpu.num_int_insts 6329 # number of integer instructions
system.cpu.num_fp_insts 10 # number of float instructions
system.cpu.num_int_register_reads 8285 # number of times the integer registers were read
system.cpu.num_int_register_writes 4568 # number of times the integer registers were written
system.cpu.num_int_register_reads 8297 # number of times the integer registers were read
system.cpu.num_int_register_writes 4575 # number of times the integer registers were written
system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
system.cpu.num_mem_refs 2058 # number of memory refs
system.cpu.num_load_insts 1190 # Number of load instructions
system.cpu.num_mem_refs 2060 # number of memory refs
system.cpu.num_load_insts 1192 # Number of load instructions
system.cpu.num_store_insts 868 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 71335 # Number of busy cycles
system.cpu.num_busy_cycles 71365 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.Branches 1050 # Number of branches fetched
system.cpu.Branches 1056 # Number of branches fetched
system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction
system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction
system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction
system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction
system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction
system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction
system.cpu.op_class::IntAlu 4331 67.53% 67.83% # Class of executed instruction
system.cpu.op_class::IntMult 1 0.02% 67.85% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 67.85% # Class of executed instruction
system.cpu.op_class::FloatAdd 2 0.03% 67.88% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.88% # Class of executed instruction
system.cpu.op_class::MemRead 1192 18.59% 86.46% # Class of executed instruction
system.cpu.op_class::MemWrite 868 13.54% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 6400 # Class of executed instruction
system.cpu.op_class::total 6413 # Class of executed instruction
system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 103.427155 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 1880 # Total number of references to valid blocks.
system.cpu.dcache.tags.tagsinuse 103.763836 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 1882 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 11.190476 # Average number of references to valid blocks.
system.cpu.dcache.tags.avg_refs 11.202381 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 103.427155 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.025251 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.025251 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_blocks::cpu.data 103.763836 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.025333 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.025333 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 143 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.041016 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 4264 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 4264 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 1088 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1088 # number of ReadReq hits
system.cpu.dcache.tags.tag_accesses 4268 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 4268 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 1090 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1090 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 792 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 1880 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 1880 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 1880 # number of overall hits
system.cpu.dcache.overall_hits::total 1880 # number of overall hits
system.cpu.dcache.demand_hits::cpu.data 1882 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 1882 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 1882 # number of overall hits
system.cpu.dcache.overall_hits::total 1882 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 95 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 95 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 73 # number of WriteReq misses
@ -160,22 +160,22 @@ system.cpu.dcache.demand_miss_latency::cpu.data 10416000
system.cpu.dcache.demand_miss_latency::total 10416000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 10416000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 10416000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::cpu.data 1185 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1185 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 2048 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 2048 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 2048 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 2048 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.080304 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.080304 # miss rate for ReadReq accesses
system.cpu.dcache.demand_accesses::cpu.data 2050 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 2050 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 2050 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 2050 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.080169 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.080169 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084393 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.084393 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.082031 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.082031 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.082031 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.082031 # miss rate for overall accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.081951 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.081951 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.081951 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.081951 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62000 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 62000 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency
@ -208,14 +208,14 @@ system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10248000
system.cpu.dcache.demand_mshr_miss_latency::total 10248000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10248000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 10248000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080169 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080169 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.081951 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.081951 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.081951 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.081951 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency
@ -226,26 +226,26 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000
system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 0 # number of replacements
system.cpu.icache.tags.tagsinuse 127.519931 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 6122 # Total number of references to valid blocks.
system.cpu.icache.tags.tagsinuse 127.232065 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 6135 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 279 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 21.942652 # Average number of references to valid blocks.
system.cpu.icache.tags.avg_refs 21.989247 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 127.519931 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.062266 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.062266 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_blocks::cpu.inst 127.232065 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.062125 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.062125 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 279 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 184 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.136230 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 13081 # Number of tag accesses
system.cpu.icache.tags.data_accesses 13081 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 6122 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 6122 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 6122 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 6122 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 6122 # number of overall hits
system.cpu.icache.overall_hits::total 6122 # number of overall hits
system.cpu.icache.tags.tag_accesses 13107 # Number of tag accesses
system.cpu.icache.tags.data_accesses 13107 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 6135 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 6135 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 6135 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 6135 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 6135 # number of overall hits
system.cpu.icache.overall_hits::total 6135 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 279 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 279 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 279 # number of demand (read+write) misses
@ -258,18 +258,18 @@ system.cpu.icache.demand_miss_latency::cpu.inst 17250500
system.cpu.icache.demand_miss_latency::total 17250500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 17250500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 17250500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 6401 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 6401 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 6401 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 6401 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 6401 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 6401 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.043587 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.043587 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.043587 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.043587 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.043587 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.043587 # miss rate for overall accesses
system.cpu.icache.ReadReq_accesses::cpu.inst 6414 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 6414 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 6414 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 6414 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 6414 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 6414 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.043499 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.043499 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.043499 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.043499 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.043499 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.043499 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61829.749104 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 61829.749104 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 61829.749104 # average overall miss latency
@ -296,12 +296,12 @@ system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16971500
system.cpu.icache.demand_mshr_miss_latency::total 16971500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16971500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 16971500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.043587 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.043587 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.043587 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043499 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.043499 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043499 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.043499 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043499 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.043499 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60829.749104 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60829.749104 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60829.749104 # average overall mshr miss latency
@ -310,16 +310,16 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60829.749104
system.cpu.icache.overall_avg_mshr_miss_latency::total 60829.749104 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 183.843350 # Cycle average of tags in use
system.cpu.l2cache.tags.tagsinuse 184.000496 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 373 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.002681 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst 127.517941 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 56.325409 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003892 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001719 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.005610 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_blocks::cpu.inst 127.230075 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 56.770421 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003883 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001732 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.005615 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 373 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 261 # Occupied blocks per task id
@ -506,6 +506,6 @@ system.membus.snoop_fanout::total 446 # Re
system.membus.reqLayer0.occupancy 446500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 1.3 # Layer utilization (%)
system.membus.respLayer1.occupancy 2230000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 6.3 # Layer utilization (%)
system.membus.respLayer1.utilization 6.2 # Layer utilization (%)
---------- End Simulation Statistics ----------

8
tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout
View file

@ -1,9 +1,11 @@
Redirecting stdout to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing/simout
Redirecting stderr to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Mar 13 2016 22:42:39
gem5 started Mar 13 2016 22:47:14
gem5 executing on phenom, pid 19880
gem5 compiled Mar 14 2016 22:04:10
gem5 started Mar 14 2016 22:06:34
gem5 executing on phenom, pid 29859
command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing
Global frequency set at 1000000000000 ticks per second

942
tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

3
tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini
View file

@ -118,7 +118,7 @@ env=
errout=cerr
euid=100
eventq_index=0
executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello
executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/mips/linux/hello
gid=100
input=cin
kvmInSE=false
@ -153,6 +153,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4

1
tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simerr
View file

@ -1,2 +1 @@
warn: Sockets disabled, not accepting gdb connections
warn: mmap failing: arguments not page-aligned: start 0x0 offset 0x7efefeff

12
tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout
View file

@ -1,13 +1,15 @@
Redirecting stdout to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic/simout
Redirecting stderr to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 21 2016 14:17:41
gem5 started Jan 21 2016 14:18:13
gem5 executing on zizzer, pid 60571
command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic -re /z/atgutier/gem5/gem5-commit/tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic
gem5 compiled Mar 14 2016 22:04:10
gem5 started Mar 14 2016 22:06:34
gem5 executing on phenom, pid 29858
command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello World!
Exiting @ tick 2812000 because target called exit()
Exiting @ tick 2820500 because target called exit()

174
tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt
View file

@ -1,40 +1,40 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000003 # Number of seconds simulated
sim_ticks 2812000 # Number of ticks simulated
final_tick 2812000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 2820500 # Number of ticks simulated
final_tick 2820500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 70039 # Simulator instruction rate (inst/s)
host_op_rate 70020 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 35000361 # Simulator tick rate (ticks/s)
host_mem_usage 218484 # Number of bytes of host memory used
host_seconds 0.08 # Real time elapsed on the host
sim_insts 5624 # Number of instructions simulated
sim_ops 5624 # Number of ops (including micro ops) simulated
host_inst_rate 42403 # Simulator instruction rate (inst/s)
host_op_rate 42398 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 21196256 # Simulator tick rate (ticks/s)
host_mem_usage 214708 # Number of bytes of host memory used
host_seconds 0.13 # Real time elapsed on the host
sim_insts 5641 # Number of instructions simulated
sim_ops 5641 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 22500 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 4289 # Number of bytes read from this memory
system.physmem.bytes_read::total 26789 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 22500 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 22500 # Number of instructions bytes read from this memory
system.physmem.bytes_read::cpu.inst 22568 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 4301 # Number of bytes read from this memory
system.physmem.bytes_read::total 26869 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 22568 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 22568 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 3601 # Number of bytes written to this memory
system.physmem.bytes_written::total 3601 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 5625 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1132 # Number of read requests responded to by this memory
system.physmem.num_reads::total 6757 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 5642 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1135 # Number of read requests responded to by this memory
system.physmem.num_reads::total 6777 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 901 # Number of write requests responded to by this memory
system.physmem.num_writes::total 901 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 8001422475 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1525248933 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 9526671408 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 8001422475 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 8001422475 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1280583215 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1280583215 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 8001422475 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2805832148 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 10807254623 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 8001418188 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1524906931 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 9526325120 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 8001418188 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 8001418188 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1276723985 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1276723985 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 8001418188 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2801630917 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 10803049105 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
@ -55,84 +55,84 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 7 # Number of system calls
system.cpu.numCycles 5625 # number of cpu cycles simulated
system.cpu.numCycles 5642 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 5624 # Number of instructions committed
system.cpu.committedOps 5624 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 4944 # Number of integer alu accesses
system.cpu.committedInsts 5641 # Number of instructions committed
system.cpu.committedOps 5641 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 4957 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses
system.cpu.num_func_calls 190 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 649 # number of instructions that are conditional controls
system.cpu.num_int_insts 4944 # number of integer instructions
system.cpu.num_func_calls 191 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 651 # number of instructions that are conditional controls
system.cpu.num_int_insts 4957 # number of integer instructions
system.cpu.num_fp_insts 2 # number of float instructions
system.cpu.num_int_register_reads 7054 # number of times the integer registers were read
system.cpu.num_int_register_writes 3281 # number of times the integer registers were written
system.cpu.num_int_register_reads 7072 # number of times the integer registers were read
system.cpu.num_int_register_writes 3291 # number of times the integer registers were written
system.cpu.num_fp_register_reads 3 # number of times the floating registers were read
system.cpu.num_fp_register_writes 1 # number of times the floating registers were written
system.cpu.num_mem_refs 2034 # number of memory refs
system.cpu.num_load_insts 1132 # Number of load instructions
system.cpu.num_mem_refs 2037 # number of memory refs
system.cpu.num_load_insts 1135 # Number of load instructions
system.cpu.num_store_insts 902 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 5625 # Number of busy cycles
system.cpu.num_busy_cycles 5642 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.Branches 883 # Number of branches fetched
system.cpu.op_class::No_OpClass 637 11.32% 11.32% # Class of executed instruction
system.cpu.op_class::IntAlu 2950 52.44% 63.77% # Class of executed instruction
system.cpu.op_class::IntMult 2 0.04% 63.80% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 63.80% # Class of executed instruction
system.cpu.op_class::FloatAdd 2 0.04% 63.84% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::MemRead 1132 20.12% 83.96% # Class of executed instruction
system.cpu.op_class::MemWrite 902 16.04% 100.00% # Class of executed instruction
system.cpu.Branches 886 # Number of branches fetched
system.cpu.op_class::No_OpClass 641 11.36% 11.36% # Class of executed instruction
system.cpu.op_class::IntAlu 2960 52.46% 63.82% # Class of executed instruction
system.cpu.op_class::IntMult 2 0.04% 63.86% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 63.86% # Class of executed instruction
system.cpu.op_class::FloatAdd 2 0.04% 63.90% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::MemRead 1135 20.12% 84.01% # Class of executed instruction
system.cpu.op_class::MemWrite 902 15.99% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 5625 # Class of executed instruction
system.membus.trans_dist::ReadReq 6757 # Transaction distribution
system.membus.trans_dist::ReadResp 6757 # Transaction distribution
system.cpu.op_class::total 5642 # Class of executed instruction
system.membus.trans_dist::ReadReq 6777 # Transaction distribution
system.membus.trans_dist::ReadResp 6777 # Transaction distribution
system.membus.trans_dist::WriteReq 901 # Transaction distribution
system.membus.trans_dist::WriteResp 901 # Transaction distribution
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 11250 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 4066 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 15316 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 22500 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 7890 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 30390 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 11284 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 4072 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 15356 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 22568 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 7902 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 30470 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 7658 # Request fanout histogram
system.membus.snoop_fanout::mean 0.734526 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.441614 # Request fanout histogram
system.membus.snoop_fanout::samples 7678 # Request fanout histogram
system.membus.snoop_fanout::mean 0.734827 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.441454 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 2033 26.55% 26.55% # Request fanout histogram
system.membus.snoop_fanout::1 5625 73.45% 100.00% # Request fanout histogram
system.membus.snoop_fanout::0 2036 26.52% 26.52% # Request fanout histogram
system.membus.snoop_fanout::1 5642 73.48% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 7658 # Request fanout histogram
system.membus.snoop_fanout::total 7678 # Request fanout histogram
---------- End Simulation Statistics ----------

2
tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
View file

@ -122,7 +122,7 @@ env=
errout=cerr
euid=100
eventq_index=0
executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello
executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/mips/linux/hello
gid=100
input=cin
kvmInSE=false

1
tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simerr
View file

@ -7,4 +7,3 @@ warn: rounding error > tolerance
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
warn: mmap failing: arguments not page-aligned: start 0x0 offset 0x7efefeff

12
tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout
View file

@ -1,13 +1,15 @@
Redirecting stdout to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby/simout
Redirecting stderr to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 21 2016 14:17:41
gem5 started Jan 21 2016 14:18:13
gem5 executing on zizzer, pid 60577
command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby -re /z/atgutier/gem5/gem5-commit/tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby
gem5 compiled Mar 14 2016 22:04:10
gem5 started Mar 14 2016 22:06:34
gem5 executing on phenom, pid 29860
command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello World!
Exiting @ tick 100307 because target called exit()
Exiting @ tick 100232 because target called exit()

758
tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt
View file

@ -1,94 +1,94 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000100 # Number of seconds simulated
sim_ticks 100307 # Number of ticks simulated
final_tick 100307 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 100232 # Number of ticks simulated
final_tick 100232 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_inst_rate 28982 # Simulator instruction rate (inst/s)
host_op_rate 28978 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 516775 # Simulator tick rate (ticks/s)
host_mem_usage 393304 # Number of bytes of host memory used
host_seconds 0.19 # Real time elapsed on the host
sim_insts 5624 # Number of instructions simulated
sim_ops 5624 # Number of ops (including micro ops) simulated
host_inst_rate 20831 # Simulator instruction rate (inst/s)
host_op_rate 20830 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 370097 # Simulator tick rate (ticks/s)
host_mem_usage 389556 # Number of bytes of host memory used
host_seconds 0.27 # Real time elapsed on the host
sim_insts 5641 # Number of instructions simulated
sim_ops 5641 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 94080 # Number of bytes read from this memory
system.mem_ctrls.bytes_read::total 94080 # Number of bytes read from this memory
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 93824 # Number of bytes written to this memory
system.mem_ctrls.bytes_written::total 93824 # Number of bytes written to this memory
system.mem_ctrls.num_reads::ruby.dir_cntrl0 1470 # Number of read requests responded to by this memory
system.mem_ctrls.num_reads::total 1470 # Number of read requests responded to by this memory
system.mem_ctrls.num_writes::ruby.dir_cntrl0 1466 # Number of write requests responded to by this memory
system.mem_ctrls.num_writes::total 1466 # Number of write requests responded to by this memory
system.mem_ctrls.bw_read::ruby.dir_cntrl0 937920584 # Total read bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_read::total 937920584 # Total read bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_write::ruby.dir_cntrl0 935368419 # Write bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_write::total 935368419 # Write bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_total::ruby.dir_cntrl0 1873289003 # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.bw_total::total 1873289003 # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.readReqs 1470 # Number of read requests accepted
system.mem_ctrls.writeReqs 1466 # Number of write requests accepted
system.mem_ctrls.readBursts 1470 # Number of DRAM read bursts, including those serviced by the write queue
system.mem_ctrls.writeBursts 1466 # Number of DRAM write bursts, including those merged in the write queue
system.mem_ctrls.bytesReadDRAM 58560 # Total number of bytes read from DRAM
system.mem_ctrls.bytesReadWrQ 35520 # Total number of bytes read from write queue
system.mem_ctrls.bytesWritten 59456 # Total number of bytes written to DRAM
system.mem_ctrls.bytesReadSys 94080 # Total read bytes from the system interface side
system.mem_ctrls.bytesWrittenSys 93824 # Total written bytes from the system interface side
system.mem_ctrls.servicedByWrQ 555 # Number of DRAM read bursts serviced by the write queue
system.mem_ctrls.mergedWrBursts 516 # Number of DRAM write bursts merged with an existing one
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 94208 # Number of bytes read from this memory
system.mem_ctrls.bytes_read::total 94208 # Number of bytes read from this memory
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 93952 # Number of bytes written to this memory
system.mem_ctrls.bytes_written::total 93952 # Number of bytes written to this memory
system.mem_ctrls.num_reads::ruby.dir_cntrl0 1472 # Number of read requests responded to by this memory
system.mem_ctrls.num_reads::total 1472 # Number of read requests responded to by this memory
system.mem_ctrls.num_writes::ruby.dir_cntrl0 1468 # Number of write requests responded to by this memory
system.mem_ctrls.num_writes::total 1468 # Number of write requests responded to by this memory
system.mem_ctrls.bw_read::ruby.dir_cntrl0 939899433 # Total read bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_read::total 939899433 # Total read bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_write::ruby.dir_cntrl0 937345359 # Write bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_write::total 937345359 # Write bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_total::ruby.dir_cntrl0 1877244792 # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.bw_total::total 1877244792 # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.readReqs 1472 # Number of read requests accepted
system.mem_ctrls.writeReqs 1468 # Number of write requests accepted
system.mem_ctrls.readBursts 1472 # Number of DRAM read bursts, including those serviced by the write queue
system.mem_ctrls.writeBursts 1468 # Number of DRAM write bursts, including those merged in the write queue
system.mem_ctrls.bytesReadDRAM 58752 # Total number of bytes read from DRAM
system.mem_ctrls.bytesReadWrQ 35456 # Total number of bytes read from write queue
system.mem_ctrls.bytesWritten 60352 # Total number of bytes written to DRAM
system.mem_ctrls.bytesReadSys 94208 # Total read bytes from the system interface side
system.mem_ctrls.bytesWrittenSys 93952 # Total written bytes from the system interface side
system.mem_ctrls.servicedByWrQ 554 # Number of DRAM read bursts serviced by the write queue
system.mem_ctrls.mergedWrBursts 502 # Number of DRAM write bursts merged with an existing one
system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.mem_ctrls.perBankRdBursts::0 31 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::0 33 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::1 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::2 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::3 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::4 7 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::5 3 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::6 12 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::7 84 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::6 13 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::7 81 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::8 66 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::9 243 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::10 97 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::11 46 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::12 113 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::13 44 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::14 160 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::15 9 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::0 32 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::9 245 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::10 98 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::11 45 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::12 114 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::13 45 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::14 154 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::15 14 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::0 34 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::4 7 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::5 3 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::6 12 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::7 83 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::8 61 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::9 239 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::10 97 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::11 47 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::12 117 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::13 44 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::14 176 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::15 11 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::6 13 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::7 74 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::8 60 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::9 247 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::10 100 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::11 46 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::12 118 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::13 49 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::14 178 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::15 14 # Per bank write bursts
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
system.mem_ctrls.totGap 100258 # Total gap between requests
system.mem_ctrls.totGap 100183 # Total gap between requests
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::6 1470 # Read request sizes (log2)
system.mem_ctrls.readPktSize::6 1472 # Read request sizes (log2)
system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::6 1466 # Write request sizes (log2)
system.mem_ctrls.rdQLenPdf::0 915 # What read queue length does an incoming req see
system.mem_ctrls.writePktSize::6 1468 # Write request sizes (log2)
system.mem_ctrls.rdQLenPdf::0 918 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
@ -135,25 +135,25 @@ system.mem_ctrls.wrQLenPdf::11 1 # Wh
system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::15 6 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::16 7 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::17 54 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::18 59 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::19 61 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::20 62 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::21 59 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::22 57 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::23 57 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::24 57 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::25 57 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::26 57 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::27 57 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::28 57 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::29 57 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::30 57 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::31 57 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::32 57 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::15 5 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::16 8 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::17 50 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::18 60 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::19 60 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::20 67 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::21 61 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::22 59 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::23 58 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::24 58 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::25 58 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::26 58 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::27 58 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::28 58 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::29 58 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::30 58 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::31 58 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::32 58 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::33 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see
@ -184,88 +184,88 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh
system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.mem_ctrls.bytesPerActivate::samples 346 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::mean 337.017341 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::gmean 221.831279 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::stdev 312.425842 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::0-127 75 21.68% 21.68% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::128-255 111 32.08% 53.76% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::256-383 54 15.61% 69.36% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::384-511 22 6.36% 75.72% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::512-639 14 4.05% 79.77% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::640-767 16 4.62% 84.39% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::768-895 11 3.18% 87.57% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::896-1023 8 2.31% 89.88% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::1024-1151 35 10.12% 100.00% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::total 346 # Bytes accessed per row activation
system.mem_ctrls.rdPerTurnAround::samples 57 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::mean 15.982456 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::gmean 15.826931 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::stdev 2.722205 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::12-13 2 3.51% 3.51% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::14-15 25 43.86% 47.37% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::16-17 25 43.86% 91.23% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::18-19 4 7.02% 98.25% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::34-35 1 1.75% 100.00% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::total 57 # Reads before turning the bus around for writes
system.mem_ctrls.wrPerTurnAround::samples 57 # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::mean 16.298246 # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::gmean 16.275827 # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::stdev 0.905635 # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::16 51 89.47% 89.47% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::18 2 3.51% 92.98% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::19 3 5.26% 98.25% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::20 1 1.75% 100.00% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::total 57 # Writes before turning the bus around for reads
system.mem_ctrls.totQLat 12902 # Total ticks spent queuing
system.mem_ctrls.totMemAccLat 30287 # Total ticks spent from burst creation until serviced by the DRAM
system.mem_ctrls.totBusLat 4575 # Total ticks spent in databus transfers
system.mem_ctrls.avgQLat 14.10 # Average queueing delay per DRAM burst
system.mem_ctrls.bytesPerActivate::samples 336 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::mean 348.571429 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::gmean 224.382213 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::stdev 328.447975 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::0-127 77 22.92% 22.92% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::128-255 103 30.65% 53.57% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::256-383 48 14.29% 67.86% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::384-511 26 7.74% 75.60% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::512-639 11 3.27% 78.87% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::640-767 8 2.38% 81.25% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::768-895 13 3.87% 85.12% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::896-1023 7 2.08% 87.20% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::1024-1151 43 12.80% 100.00% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::total 336 # Bytes accessed per row activation
system.mem_ctrls.rdPerTurnAround::samples 58 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::mean 15.706897 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::gmean 15.549891 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::stdev 2.720995 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::12-13 5 8.62% 8.62% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::14-15 26 44.83% 53.45% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::16-17 25 43.10% 96.55% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::18-19 1 1.72% 98.28% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::34-35 1 1.72% 100.00% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::total 58 # Reads before turning the bus around for writes
system.mem_ctrls.wrPerTurnAround::samples 58 # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::mean 16.258621 # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::gmean 16.240724 # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::stdev 0.806995 # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::16 52 89.66% 89.66% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::18 4 6.90% 96.55% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::19 1 1.72% 98.28% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::20 1 1.72% 100.00% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::total 58 # Writes before turning the bus around for reads
system.mem_ctrls.totQLat 12638 # Total ticks spent queuing
system.mem_ctrls.totMemAccLat 30080 # Total ticks spent from burst creation until serviced by the DRAM
system.mem_ctrls.totBusLat 4590 # Total ticks spent in databus transfers
system.mem_ctrls.avgQLat 13.77 # Average queueing delay per DRAM burst
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
system.mem_ctrls.avgMemAccLat 33.10 # Average memory access latency per DRAM burst
system.mem_ctrls.avgRdBW 583.81 # Average DRAM read bandwidth in MiByte/s
system.mem_ctrls.avgWrBW 592.74 # Average achieved write bandwidth in MiByte/s
system.mem_ctrls.avgRdBWSys 937.92 # Average system read bandwidth in MiByte/s
system.mem_ctrls.avgWrBWSys 935.37 # Average system write bandwidth in MiByte/s
system.mem_ctrls.avgMemAccLat 32.77 # Average memory access latency per DRAM burst
system.mem_ctrls.avgRdBW 586.16 # Average DRAM read bandwidth in MiByte/s
system.mem_ctrls.avgWrBW 602.12 # Average achieved write bandwidth in MiByte/s
system.mem_ctrls.avgRdBWSys 939.90 # Average system read bandwidth in MiByte/s
system.mem_ctrls.avgWrBWSys 937.35 # Average system write bandwidth in MiByte/s
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.mem_ctrls.busUtil 9.19 # Data bus utilization in percentage
system.mem_ctrls.busUtilRead 4.56 # Data bus utilization in percentage for reads
system.mem_ctrls.busUtilWrite 4.63 # Data bus utilization in percentage for writes
system.mem_ctrls.busUtil 9.28 # Data bus utilization in percentage
system.mem_ctrls.busUtilRead 4.58 # Data bus utilization in percentage for reads
system.mem_ctrls.busUtilWrite 4.70 # Data bus utilization in percentage for writes
system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing
system.mem_ctrls.avgWrQLen 25.61 # Average write queue length when enqueuing
system.mem_ctrls.readRowHits 627 # Number of row buffer hits during reads
system.mem_ctrls.writeRowHits 865 # Number of row buffer hits during writes
system.mem_ctrls.readRowHitRate 68.52 # Row buffer hit rate for reads
system.mem_ctrls.writeRowHitRate 91.05 # Row buffer hit rate for writes
system.mem_ctrls.avgGap 34.15 # Average gap between requests
system.mem_ctrls.pageHitRate 80.00 # Row buffer hit rate, read and write combined
system.mem_ctrls_0.actEnergy 506520 # Energy for activate commands per rank (pJ)
system.mem_ctrls_0.preEnergy 281400 # Energy for precharge commands per rank (pJ)
system.mem_ctrls_0.readEnergy 1497600 # Energy for read commands per rank (pJ)
system.mem_ctrls_0.writeEnergy 1254528 # Energy for write commands per rank (pJ)
system.mem_ctrls.avgWrQLen 25.54 # Average write queue length when enqueuing
system.mem_ctrls.readRowHits 642 # Number of row buffer hits during reads
system.mem_ctrls.writeRowHits 873 # Number of row buffer hits during writes
system.mem_ctrls.readRowHitRate 69.93 # Row buffer hit rate for reads
system.mem_ctrls.writeRowHitRate 90.37 # Row buffer hit rate for writes
system.mem_ctrls.avgGap 34.08 # Average gap between requests
system.mem_ctrls.pageHitRate 80.41 # Row buffer hit rate, read and write combined
system.mem_ctrls_0.actEnergy 491400 # Energy for activate commands per rank (pJ)
system.mem_ctrls_0.preEnergy 273000 # Energy for precharge commands per rank (pJ)
system.mem_ctrls_0.readEnergy 1547520 # Energy for read commands per rank (pJ)
system.mem_ctrls_0.writeEnergy 1099008 # Energy for write commands per rank (pJ)
system.mem_ctrls_0.refreshEnergy 6102720 # Energy for refresh commands per rank (pJ)
system.mem_ctrls_0.actBackEnergy 47014056 # Energy for active background per rank (pJ)
system.mem_ctrls_0.preBackEnergy 14974800 # Energy for precharge background per rank (pJ)
system.mem_ctrls_0.totalEnergy 71631624 # Total energy per rank (pJ)
system.mem_ctrls_0.averagePower 764.543654 # Core power per rank (mW)
system.mem_ctrls_0.memoryStateTime::IDLE 25717 # Time in different power states
system.mem_ctrls_0.actBackEnergy 55680336 # Energy for active background per rank (pJ)
system.mem_ctrls_0.preBackEnergy 7372800 # Energy for precharge background per rank (pJ)
system.mem_ctrls_0.totalEnergy 72566784 # Total energy per rank (pJ)
system.mem_ctrls_0.averagePower 774.524869 # Core power per rank (mW)
system.mem_ctrls_0.memoryStateTime::IDLE 11950 # Time in different power states
system.mem_ctrls_0.memoryStateTime::REF 3120 # Time in different power states
system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.mem_ctrls_0.memoryStateTime::ACT 71078 # Time in different power states
system.mem_ctrls_0.memoryStateTime::ACT 78690 # Time in different power states
system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.mem_ctrls_1.actEnergy 1950480 # Energy for activate commands per rank (pJ)
system.mem_ctrls_1.preEnergy 1083600 # Energy for precharge commands per rank (pJ)
system.mem_ctrls_1.readEnergy 9197760 # Energy for read commands per rank (pJ)
system.mem_ctrls_1.writeEnergy 7713792 # Energy for write commands per rank (pJ)
system.mem_ctrls_1.actEnergy 1882440 # Energy for activate commands per rank (pJ)
system.mem_ctrls_1.preEnergy 1045800 # Energy for precharge commands per rank (pJ)
system.mem_ctrls_1.readEnergy 9247680 # Energy for read commands per rank (pJ)
system.mem_ctrls_1.writeEnergy 7993728 # Energy for write commands per rank (pJ)
system.mem_ctrls_1.refreshEnergy 6102720 # Energy for refresh commands per rank (pJ)
system.mem_ctrls_1.actBackEnergy 63796680 # Energy for active background per rank (pJ)
system.mem_ctrls_1.preBackEnergy 253200 # Energy for precharge background per rank (pJ)
system.mem_ctrls_1.totalEnergy 90098232 # Total energy per rank (pJ)
system.mem_ctrls_1.averagePower 961.642744 # Core power per rank (mW)
system.mem_ctrls_1.memoryStateTime::IDLE 100 # Time in different power states
system.mem_ctrls_1.actBackEnergy 63740592 # Energy for active background per rank (pJ)
system.mem_ctrls_1.preBackEnergy 302400 # Energy for precharge background per rank (pJ)
system.mem_ctrls_1.totalEnergy 90315360 # Total energy per rank (pJ)
system.mem_ctrls_1.averagePower 963.960210 # Core power per rank (mW)
system.mem_ctrls_1.memoryStateTime::IDLE 182 # Time in different power states
system.mem_ctrls_1.memoryStateTime::REF 3120 # Time in different power states
system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT 90486 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT 90404 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.clk_domain.clock 1 # Clock period in ticks
system.cpu.dtb.read_hits 0 # DTB read hits
@ -287,210 +287,210 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 7 # Number of system calls
system.cpu.numCycles 100307 # number of cpu cycles simulated
system.cpu.numCycles 100232 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 5624 # Number of instructions committed
system.cpu.committedOps 5624 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 4944 # Number of integer alu accesses
system.cpu.committedInsts 5641 # Number of instructions committed
system.cpu.committedOps 5641 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 4957 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses
system.cpu.num_func_calls 190 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 649 # number of instructions that are conditional controls
system.cpu.num_int_insts 4944 # number of integer instructions
system.cpu.num_func_calls 191 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 651 # number of instructions that are conditional controls
system.cpu.num_int_insts 4957 # number of integer instructions
system.cpu.num_fp_insts 2 # number of float instructions
system.cpu.num_int_register_reads 7054 # number of times the integer registers were read
system.cpu.num_int_register_writes 3281 # number of times the integer registers were written
system.cpu.num_int_register_reads 7072 # number of times the integer registers were read
system.cpu.num_int_register_writes 3291 # number of times the integer registers were written
system.cpu.num_fp_register_reads 3 # number of times the floating registers were read
system.cpu.num_fp_register_writes 1 # number of times the floating registers were written
system.cpu.num_mem_refs 2034 # number of memory refs
system.cpu.num_load_insts 1132 # Number of load instructions
system.cpu.num_mem_refs 2037 # number of memory refs
system.cpu.num_load_insts 1135 # Number of load instructions
system.cpu.num_store_insts 902 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 100307 # Number of busy cycles
system.cpu.num_busy_cycles 100232 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.Branches 883 # Number of branches fetched
system.cpu.op_class::No_OpClass 637 11.32% 11.32% # Class of executed instruction
system.cpu.op_class::IntAlu 2950 52.44% 63.77% # Class of executed instruction
system.cpu.op_class::IntMult 2 0.04% 63.80% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 63.80% # Class of executed instruction
system.cpu.op_class::FloatAdd 2 0.04% 63.84% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::MemRead 1132 20.12% 83.96% # Class of executed instruction
system.cpu.op_class::MemWrite 902 16.04% 100.00% # Class of executed instruction
system.cpu.Branches 886 # Number of branches fetched
system.cpu.op_class::No_OpClass 641 11.36% 11.36% # Class of executed instruction
system.cpu.op_class::IntAlu 2960 52.46% 63.82% # Class of executed instruction
system.cpu.op_class::IntMult 2 0.04% 63.86% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 63.86% # Class of executed instruction
system.cpu.op_class::FloatAdd 2 0.04% 63.90% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::MemRead 1135 20.12% 84.01% # Class of executed instruction
system.cpu.op_class::MemWrite 902 15.99% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 5625 # Class of executed instruction
system.cpu.op_class::total 5642 # Class of executed instruction
system.ruby.clk_domain.clock 1 # Clock period in ticks
system.ruby.delayHist::bucket_size 1 # delay histogram for all message
system.ruby.delayHist::max_bucket 9 # delay histogram for all message
system.ruby.delayHist::samples 2936 # delay histogram for all message
system.ruby.delayHist | 2936 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message
system.ruby.delayHist::total 2936 # delay histogram for all message
system.ruby.delayHist::samples 2940 # delay histogram for all message
system.ruby.delayHist | 2940 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message
system.ruby.delayHist::total 2940 # delay histogram for all message
system.ruby.outstanding_req_hist_seqr::bucket_size 1
system.ruby.outstanding_req_hist_seqr::max_bucket 9
system.ruby.outstanding_req_hist_seqr::samples 7659
system.ruby.outstanding_req_hist_seqr::samples 7679
system.ruby.outstanding_req_hist_seqr::mean 1
system.ruby.outstanding_req_hist_seqr::gmean 1
system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 7659 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.outstanding_req_hist_seqr::total 7659
system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 7679 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.outstanding_req_hist_seqr::total 7679
system.ruby.latency_hist_seqr::bucket_size 64
system.ruby.latency_hist_seqr::max_bucket 639
system.ruby.latency_hist_seqr::samples 7658
system.ruby.latency_hist_seqr::mean 12.098329
system.ruby.latency_hist_seqr::gmean 2.138684
system.ruby.latency_hist_seqr::stdev 27.490264
system.ruby.latency_hist_seqr | 7348 95.95% 95.95% | 251 3.28% 99.23% | 42 0.55% 99.78% | 5 0.07% 99.84% | 10 0.13% 99.97% | 2 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.latency_hist_seqr::total 7658
system.ruby.latency_hist_seqr::samples 7678
system.ruby.latency_hist_seqr::mean 12.054441
system.ruby.latency_hist_seqr::gmean 2.136034
system.ruby.latency_hist_seqr::stdev 27.599754
system.ruby.latency_hist_seqr | 7372 96.01% 96.01% | 253 3.30% 99.31% | 37 0.48% 99.79% | 4 0.05% 99.84% | 6 0.08% 99.92% | 5 0.07% 99.99% | 0 0.00% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.latency_hist_seqr::total 7678
system.ruby.hit_latency_hist_seqr::bucket_size 1
system.ruby.hit_latency_hist_seqr::max_bucket 9
system.ruby.hit_latency_hist_seqr::samples 6188
system.ruby.hit_latency_hist_seqr::samples 6206
system.ruby.hit_latency_hist_seqr::mean 1
system.ruby.hit_latency_hist_seqr::gmean 1
system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 6188 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.hit_latency_hist_seqr::total 6188
system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 6206 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.hit_latency_hist_seqr::total 6206
system.ruby.miss_latency_hist_seqr::bucket_size 64
system.ruby.miss_latency_hist_seqr::max_bucket 639
system.ruby.miss_latency_hist_seqr::samples 1470
system.ruby.miss_latency_hist_seqr::mean 58.817007
system.ruby.miss_latency_hist_seqr::gmean 52.469450
system.ruby.miss_latency_hist_seqr::stdev 35.158300
system.ruby.miss_latency_hist_seqr | 1160 78.91% 78.91% | 251 17.07% 95.99% | 42 2.86% 98.84% | 5 0.34% 99.18% | 10 0.68% 99.86% | 2 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.miss_latency_hist_seqr::total 1470
system.ruby.Directory.incomplete_times_seqr 1469
system.ruby.l1_cntrl0.cacheMemory.demand_hits 6188 # Number of cache demand hits
system.ruby.l1_cntrl0.cacheMemory.demand_misses 1470 # Number of cache demand misses
system.ruby.l1_cntrl0.cacheMemory.demand_accesses 7658 # Number of cache demand accesses
system.ruby.miss_latency_hist_seqr::samples 1472
system.ruby.miss_latency_hist_seqr::mean 58.660326
system.ruby.miss_latency_hist_seqr::gmean 52.389786
system.ruby.miss_latency_hist_seqr::stdev 35.865583
system.ruby.miss_latency_hist_seqr | 1166 79.21% 79.21% | 253 17.19% 96.40% | 37 2.51% 98.91% | 4 0.27% 99.18% | 6 0.41% 99.59% | 5 0.34% 99.93% | 0 0.00% 99.93% | 1 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.miss_latency_hist_seqr::total 1472
system.ruby.Directory.incomplete_times_seqr 1471
system.ruby.l1_cntrl0.cacheMemory.demand_hits 6206 # Number of cache demand hits
system.ruby.l1_cntrl0.cacheMemory.demand_misses 1472 # Number of cache demand misses
system.ruby.l1_cntrl0.cacheMemory.demand_accesses 7678 # Number of cache demand accesses
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
system.ruby.network.routers0.percent_links_utilized 7.317535
system.ruby.network.routers0.msg_count.Control::2 1470
system.ruby.network.routers0.msg_count.Data::2 1466
system.ruby.network.routers0.msg_count.Response_Data::4 1470
system.ruby.network.routers0.msg_count.Writeback_Control::3 1466
system.ruby.network.routers0.msg_bytes.Control::2 11760
system.ruby.network.routers0.msg_bytes.Data::2 105552
system.ruby.network.routers0.msg_bytes.Response_Data::4 105840
system.ruby.network.routers0.msg_bytes.Writeback_Control::3 11728
system.ruby.network.routers1.percent_links_utilized 7.317535
system.ruby.network.routers1.msg_count.Control::2 1470
system.ruby.network.routers1.msg_count.Data::2 1466
system.ruby.network.routers1.msg_count.Response_Data::4 1470
system.ruby.network.routers1.msg_count.Writeback_Control::3 1466
system.ruby.network.routers1.msg_bytes.Control::2 11760
system.ruby.network.routers1.msg_bytes.Data::2 105552
system.ruby.network.routers1.msg_bytes.Response_Data::4 105840
system.ruby.network.routers1.msg_bytes.Writeback_Control::3 11728
system.ruby.network.routers2.percent_links_utilized 7.317535
system.ruby.network.routers2.msg_count.Control::2 1470
system.ruby.network.routers2.msg_count.Data::2 1466
system.ruby.network.routers2.msg_count.Response_Data::4 1470
system.ruby.network.routers2.msg_count.Writeback_Control::3 1466
system.ruby.network.routers2.msg_bytes.Control::2 11760
system.ruby.network.routers2.msg_bytes.Data::2 105552
system.ruby.network.routers2.msg_bytes.Response_Data::4 105840
system.ruby.network.routers2.msg_bytes.Writeback_Control::3 11728
system.ruby.network.msg_count.Control 4410
system.ruby.network.msg_count.Data 4398
system.ruby.network.msg_count.Response_Data 4410
system.ruby.network.msg_count.Writeback_Control 4398
system.ruby.network.msg_byte.Control 35280
system.ruby.network.msg_byte.Data 316656
system.ruby.network.msg_byte.Response_Data 317520
system.ruby.network.msg_byte.Writeback_Control 35184
system.ruby.network.routers0.throttle0.link_utilization 7.325511
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1470
system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1466
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 105840
system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 11728
system.ruby.network.routers0.throttle1.link_utilization 7.309560
system.ruby.network.routers0.throttle1.msg_count.Control::2 1470
system.ruby.network.routers0.throttle1.msg_count.Data::2 1466
system.ruby.network.routers0.throttle1.msg_bytes.Control::2 11760
system.ruby.network.routers0.throttle1.msg_bytes.Data::2 105552
system.ruby.network.routers1.throttle0.link_utilization 7.309560
system.ruby.network.routers1.throttle0.msg_count.Control::2 1470
system.ruby.network.routers1.throttle0.msg_count.Data::2 1466
system.ruby.network.routers1.throttle0.msg_bytes.Control::2 11760
system.ruby.network.routers1.throttle0.msg_bytes.Data::2 105552
system.ruby.network.routers1.throttle1.link_utilization 7.325511
system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1470
system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1466
system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 105840
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 11728
system.ruby.network.routers2.throttle0.link_utilization 7.325511
system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1470
system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1466
system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 105840
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 11728
system.ruby.network.routers2.throttle1.link_utilization 7.309560
system.ruby.network.routers2.throttle1.msg_count.Control::2 1470
system.ruby.network.routers2.throttle1.msg_count.Data::2 1466
system.ruby.network.routers2.throttle1.msg_bytes.Control::2 11760
system.ruby.network.routers2.throttle1.msg_bytes.Data::2 105552
system.ruby.network.routers0.percent_links_utilized 7.332987
system.ruby.network.routers0.msg_count.Control::2 1472
system.ruby.network.routers0.msg_count.Data::2 1468
system.ruby.network.routers0.msg_count.Response_Data::4 1472
system.ruby.network.routers0.msg_count.Writeback_Control::3 1468
system.ruby.network.routers0.msg_bytes.Control::2 11776
system.ruby.network.routers0.msg_bytes.Data::2 105696
system.ruby.network.routers0.msg_bytes.Response_Data::4 105984
system.ruby.network.routers0.msg_bytes.Writeback_Control::3 11744
system.ruby.network.routers1.percent_links_utilized 7.332987
system.ruby.network.routers1.msg_count.Control::2 1472
system.ruby.network.routers1.msg_count.Data::2 1468
system.ruby.network.routers1.msg_count.Response_Data::4 1472
system.ruby.network.routers1.msg_count.Writeback_Control::3 1468
system.ruby.network.routers1.msg_bytes.Control::2 11776
system.ruby.network.routers1.msg_bytes.Data::2 105696
system.ruby.network.routers1.msg_bytes.Response_Data::4 105984
system.ruby.network.routers1.msg_bytes.Writeback_Control::3 11744
system.ruby.network.routers2.percent_links_utilized 7.332987
system.ruby.network.routers2.msg_count.Control::2 1472
system.ruby.network.routers2.msg_count.Data::2 1468
system.ruby.network.routers2.msg_count.Response_Data::4 1472
system.ruby.network.routers2.msg_count.Writeback_Control::3 1468
system.ruby.network.routers2.msg_bytes.Control::2 11776
system.ruby.network.routers2.msg_bytes.Data::2 105696
system.ruby.network.routers2.msg_bytes.Response_Data::4 105984
system.ruby.network.routers2.msg_bytes.Writeback_Control::3 11744
system.ruby.network.msg_count.Control 4416
system.ruby.network.msg_count.Data 4404
system.ruby.network.msg_count.Response_Data 4416
system.ruby.network.msg_count.Writeback_Control 4404
system.ruby.network.msg_byte.Control 35328
system.ruby.network.msg_byte.Data 317088
system.ruby.network.msg_byte.Response_Data 317952
system.ruby.network.msg_byte.Writeback_Control 35232
system.ruby.network.routers0.throttle0.link_utilization 7.340969
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1472
system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1468
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 105984
system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 11744
system.ruby.network.routers0.throttle1.link_utilization 7.325006
system.ruby.network.routers0.throttle1.msg_count.Control::2 1472
system.ruby.network.routers0.throttle1.msg_count.Data::2 1468
system.ruby.network.routers0.throttle1.msg_bytes.Control::2 11776
system.ruby.network.routers0.throttle1.msg_bytes.Data::2 105696
system.ruby.network.routers1.throttle0.link_utilization 7.325006
system.ruby.network.routers1.throttle0.msg_count.Control::2 1472
system.ruby.network.routers1.throttle0.msg_count.Data::2 1468
system.ruby.network.routers1.throttle0.msg_bytes.Control::2 11776
system.ruby.network.routers1.throttle0.msg_bytes.Data::2 105696
system.ruby.network.routers1.throttle1.link_utilization 7.340969
system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1472
system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1468
system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 105984
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 11744
system.ruby.network.routers2.throttle0.link_utilization 7.340969
system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1472
system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1468
system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 105984
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 11744
system.ruby.network.routers2.throttle1.link_utilization 7.325006
system.ruby.network.routers2.throttle1.msg_count.Control::2 1472
system.ruby.network.routers2.throttle1.msg_count.Data::2 1468
system.ruby.network.routers2.throttle1.msg_bytes.Control::2 11776
system.ruby.network.routers2.throttle1.msg_bytes.Data::2 105696
system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1::samples 1470 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1 | 1470 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1::total 1470 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1::samples 1472 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1 | 1472 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1::total 1472 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2::samples 1466 # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2 | 1466 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2::total 1466 # delay histogram for vnet_2
system.ruby.LD.latency_hist_seqr::bucket_size 32
system.ruby.LD.latency_hist_seqr::max_bucket 319
system.ruby.LD.latency_hist_seqr::samples 1132
system.ruby.LD.latency_hist_seqr::mean 33.356007
system.ruby.LD.latency_hist_seqr::gmean 9.984943
system.ruby.LD.latency_hist_seqr::stdev 37.413851
system.ruby.LD.latency_hist_seqr | 465 41.08% 41.08% | 534 47.17% 88.25% | 104 9.19% 97.44% | 3 0.27% 97.70% | 10 0.88% 98.59% | 8 0.71% 99.29% | 4 0.35% 99.65% | 0 0.00% 99.65% | 0 0.00% 99.65% | 4 0.35% 100.00%
system.ruby.LD.latency_hist_seqr::total 1132
system.ruby.delayVCHist.vnet_2::samples 1468 # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2 | 1468 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2::total 1468 # delay histogram for vnet_2
system.ruby.LD.latency_hist_seqr::bucket_size 64
system.ruby.LD.latency_hist_seqr::max_bucket 639
system.ruby.LD.latency_hist_seqr::samples 1135
system.ruby.LD.latency_hist_seqr::mean 33.525991
system.ruby.LD.latency_hist_seqr::gmean 10.018050
system.ruby.LD.latency_hist_seqr::stdev 38.312060
system.ruby.LD.latency_hist_seqr | 999 88.02% 88.02% | 116 10.22% 98.24% | 13 1.15% 99.38% | 0 0.00% 99.38% | 6 0.53% 99.91% | 1 0.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.latency_hist_seqr::total 1135
system.ruby.LD.hit_latency_hist_seqr::bucket_size 1
system.ruby.LD.hit_latency_hist_seqr::max_bucket 9
system.ruby.LD.hit_latency_hist_seqr::samples 465
system.ruby.LD.hit_latency_hist_seqr::samples 466
system.ruby.LD.hit_latency_hist_seqr::mean 1
system.ruby.LD.hit_latency_hist_seqr::gmean 1
system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 465 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.hit_latency_hist_seqr::total 465
system.ruby.LD.miss_latency_hist_seqr::bucket_size 32
system.ruby.LD.miss_latency_hist_seqr::max_bucket 319
system.ruby.LD.miss_latency_hist_seqr::samples 667
system.ruby.LD.miss_latency_hist_seqr::mean 55.913043
system.ruby.LD.miss_latency_hist_seqr::gmean 49.663893
system.ruby.LD.miss_latency_hist_seqr::stdev 33.713440
system.ruby.LD.miss_latency_hist_seqr | 0 0.00% 0.00% | 534 80.06% 80.06% | 104 15.59% 95.65% | 3 0.45% 96.10% | 10 1.50% 97.60% | 8 1.20% 98.80% | 4 0.60% 99.40% | 0 0.00% 99.40% | 0 0.00% 99.40% | 4 0.60% 100.00%
system.ruby.LD.miss_latency_hist_seqr::total 667
system.ruby.ST.latency_hist_seqr::bucket_size 32
system.ruby.ST.latency_hist_seqr::max_bucket 319
system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 466 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.hit_latency_hist_seqr::total 466
system.ruby.LD.miss_latency_hist_seqr::bucket_size 64
system.ruby.LD.miss_latency_hist_seqr::max_bucket 639
system.ruby.LD.miss_latency_hist_seqr::samples 669
system.ruby.LD.miss_latency_hist_seqr::mean 56.182362
system.ruby.LD.miss_latency_hist_seqr::gmean 49.875907
system.ruby.LD.miss_latency_hist_seqr::stdev 35.208867
system.ruby.LD.miss_latency_hist_seqr | 533 79.67% 79.67% | 116 17.34% 97.01% | 13 1.94% 98.95% | 0 0.00% 98.95% | 6 0.90% 99.85% | 1 0.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.miss_latency_hist_seqr::total 669
system.ruby.ST.latency_hist_seqr::bucket_size 64
system.ruby.ST.latency_hist_seqr::max_bucket 639
system.ruby.ST.latency_hist_seqr::samples 901
system.ruby.ST.latency_hist_seqr::mean 12.753607
system.ruby.ST.latency_hist_seqr::gmean 2.500911
system.ruby.ST.latency_hist_seqr::stdev 24.939066
system.ruby.ST.latency_hist_seqr | 684 75.92% 75.92% | 184 20.42% 96.34% | 28 3.11% 99.45% | 1 0.11% 99.56% | 1 0.11% 99.67% | 2 0.22% 99.89% | 0 0.00% 99.89% | 0 0.00% 99.89% | 1 0.11% 100.00% | 0 0.00% 100.00%
system.ruby.ST.latency_hist_seqr::mean 13.069922
system.ruby.ST.latency_hist_seqr::gmean 2.509564
system.ruby.ST.latency_hist_seqr::stdev 28.093942
system.ruby.ST.latency_hist_seqr | 870 96.56% 96.56% | 27 3.00% 99.56% | 3 0.33% 99.89% | 0 0.00% 99.89% | 0 0.00% 99.89% | 0 0.00% 99.89% | 0 0.00% 99.89% | 1 0.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.latency_hist_seqr::total 901
system.ruby.ST.hit_latency_hist_seqr::bucket_size 1
system.ruby.ST.hit_latency_hist_seqr::max_bucket 9
@ -499,45 +499,45 @@ system.ruby.ST.hit_latency_hist_seqr::mean 1
system.ruby.ST.hit_latency_hist_seqr::gmean 1
system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 684 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.hit_latency_hist_seqr::total 684
system.ruby.ST.miss_latency_hist_seqr::bucket_size 32
system.ruby.ST.miss_latency_hist_seqr::max_bucket 319
system.ruby.ST.miss_latency_hist_seqr::bucket_size 64
system.ruby.ST.miss_latency_hist_seqr::max_bucket 639
system.ruby.ST.miss_latency_hist_seqr::samples 217
system.ruby.ST.miss_latency_hist_seqr::mean 49.801843
system.ruby.ST.miss_latency_hist_seqr::gmean 44.971096
system.ruby.ST.miss_latency_hist_seqr::stdev 27.840525
system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 184 84.79% 84.79% | 28 12.90% 97.70% | 1 0.46% 98.16% | 1 0.46% 98.62% | 2 0.92% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 1 0.46% 100.00% | 0 0.00% 100.00%
system.ruby.ST.miss_latency_hist_seqr::mean 51.115207
system.ruby.ST.miss_latency_hist_seqr::gmean 45.620625
system.ruby.ST.miss_latency_hist_seqr::stdev 37.056021
system.ruby.ST.miss_latency_hist_seqr | 186 85.71% 85.71% | 27 12.44% 98.16% | 3 1.38% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 1 0.46% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.miss_latency_hist_seqr::total 217
system.ruby.IFETCH.latency_hist_seqr::bucket_size 64
system.ruby.IFETCH.latency_hist_seqr::max_bucket 639
system.ruby.IFETCH.latency_hist_seqr::samples 5625
system.ruby.IFETCH.latency_hist_seqr::mean 7.715378
system.ruby.IFETCH.latency_hist_seqr::gmean 1.529642
system.ruby.IFETCH.latency_hist_seqr::stdev 23.186705
system.ruby.IFETCH.latency_hist_seqr | 5481 97.44% 97.44% | 115 2.04% 99.48% | 21 0.37% 99.86% | 1 0.02% 99.88% | 5 0.09% 99.96% | 2 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.latency_hist_seqr::total 5625
system.ruby.IFETCH.latency_hist_seqr::samples 5642
system.ruby.IFETCH.latency_hist_seqr::mean 7.572847
system.ruby.IFETCH.latency_hist_seqr::gmean 1.525495
system.ruby.IFETCH.latency_hist_seqr::stdev 22.420339
system.ruby.IFETCH.latency_hist_seqr | 5503 97.54% 97.54% | 110 1.95% 99.49% | 21 0.37% 99.86% | 4 0.07% 99.93% | 0 0.00% 99.93% | 4 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.latency_hist_seqr::total 5642
system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1
system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9
system.ruby.IFETCH.hit_latency_hist_seqr::samples 5039
system.ruby.IFETCH.hit_latency_hist_seqr::samples 5056
system.ruby.IFETCH.hit_latency_hist_seqr::mean 1
system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1
system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 5039 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.hit_latency_hist_seqr::total 5039
system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 5056 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.hit_latency_hist_seqr::total 5056
system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64
system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639
system.ruby.IFETCH.miss_latency_hist_seqr::samples 586
system.ruby.IFETCH.miss_latency_hist_seqr::mean 65.460751
system.ruby.IFETCH.miss_latency_hist_seqr::gmean 59.138692
system.ruby.IFETCH.miss_latency_hist_seqr::stdev 37.945521
system.ruby.IFETCH.miss_latency_hist_seqr | 442 75.43% 75.43% | 115 19.62% 95.05% | 21 3.58% 98.63% | 1 0.17% 98.81% | 5 0.85% 99.66% | 2 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.miss_latency_hist_seqr::mean 64.283276
system.ruby.IFETCH.miss_latency_hist_seqr::gmean 58.328027
system.ruby.IFETCH.miss_latency_hist_seqr::stdev 35.386051
system.ruby.IFETCH.miss_latency_hist_seqr | 447 76.28% 76.28% | 110 18.77% 95.05% | 21 3.58% 98.63% | 4 0.68% 99.32% | 0 0.00% 99.32% | 4 0.68% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.miss_latency_hist_seqr::total 586
system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64
system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639
system.ruby.Directory.miss_mach_latency_hist_seqr::samples 1470
system.ruby.Directory.miss_mach_latency_hist_seqr::mean 58.817007
system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 52.469450
system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 35.158300
system.ruby.Directory.miss_mach_latency_hist_seqr | 1160 78.91% 78.91% | 251 17.07% 95.99% | 42 2.86% 98.84% | 5 0.34% 99.18% | 10 0.68% 99.86% | 2 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.Directory.miss_mach_latency_hist_seqr::total 1470
system.ruby.Directory.miss_mach_latency_hist_seqr::samples 1472
system.ruby.Directory.miss_mach_latency_hist_seqr::mean 58.660326
system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 52.389786
system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 35.865583
system.ruby.Directory.miss_mach_latency_hist_seqr | 1166 79.21% 79.21% | 253 17.19% 96.40% | 37 2.51% 98.91% | 4 0.27% 99.18% | 6 0.41% 99.59% | 5 0.34% 99.93% | 0 0.00% 99.93% | 1 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.Directory.miss_mach_latency_hist_seqr::total 1472
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 1
@ -564,53 +564,53 @@ system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::gmean
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::stdev nan
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00%
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 667
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 55.913043
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 49.663893
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 33.713440
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 534 80.06% 80.06% | 104 15.59% 95.65% | 3 0.45% 96.10% | 10 1.50% 97.60% | 8 1.20% 98.80% | 4 0.60% 99.40% | 0 0.00% 99.40% | 0 0.00% 99.40% | 4 0.60% 100.00%
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 667
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 669
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 56.182362
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 49.875907
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 35.208867
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 533 79.67% 79.67% | 116 17.34% 97.01% | 13 1.94% 98.95% | 0 0.00% 98.95% | 6 0.90% 99.85% | 1 0.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 669
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 217
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 49.801843
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 44.971096
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 27.840525
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 184 84.79% 84.79% | 28 12.90% 97.70% | 1 0.46% 98.16% | 1 0.46% 98.62% | 2 0.92% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 1 0.46% 100.00% | 0 0.00% 100.00%
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 51.115207
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 45.620625
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 37.056021
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 186 85.71% 85.71% | 27 12.44% 98.16% | 3 1.38% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 1 0.46% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 217
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 586
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 65.460751
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 59.138692
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 37.945521
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 442 75.43% 75.43% | 115 19.62% 95.05% | 21 3.58% 98.63% | 1 0.17% 98.81% | 5 0.85% 99.66% | 2 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 64.283276
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 58.328027
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 35.386051
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 447 76.28% 76.28% | 110 18.77% 95.05% | 21 3.58% 98.63% | 4 0.68% 99.32% | 0 0.00% 99.32% | 4 0.68% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 586
system.ruby.Directory_Controller.GETX 1470 0.00% 0.00%
system.ruby.Directory_Controller.PUTX 1466 0.00% 0.00%
system.ruby.Directory_Controller.Memory_Data 1470 0.00% 0.00%
system.ruby.Directory_Controller.Memory_Ack 1466 0.00% 0.00%
system.ruby.Directory_Controller.I.GETX 1470 0.00% 0.00%
system.ruby.Directory_Controller.M.PUTX 1466 0.00% 0.00%
system.ruby.Directory_Controller.IM.Memory_Data 1470 0.00% 0.00%
system.ruby.Directory_Controller.MI.Memory_Ack 1466 0.00% 0.00%
system.ruby.L1Cache_Controller.Load 1132 0.00% 0.00%
system.ruby.L1Cache_Controller.Ifetch 5625 0.00% 0.00%
system.ruby.Directory_Controller.GETX 1472 0.00% 0.00%
system.ruby.Directory_Controller.PUTX 1468 0.00% 0.00%
system.ruby.Directory_Controller.Memory_Data 1472 0.00% 0.00%
system.ruby.Directory_Controller.Memory_Ack 1468 0.00% 0.00%
system.ruby.Directory_Controller.I.GETX 1472 0.00% 0.00%
system.ruby.Directory_Controller.M.PUTX 1468 0.00% 0.00%
system.ruby.Directory_Controller.IM.Memory_Data 1472 0.00% 0.00%
system.ruby.Directory_Controller.MI.Memory_Ack 1468 0.00% 0.00%
system.ruby.L1Cache_Controller.Load 1135 0.00% 0.00%
system.ruby.L1Cache_Controller.Ifetch 5642 0.00% 0.00%
system.ruby.L1Cache_Controller.Store 901 0.00% 0.00%
system.ruby.L1Cache_Controller.Data 1470 0.00% 0.00%
system.ruby.L1Cache_Controller.Replacement 1466 0.00% 0.00%
system.ruby.L1Cache_Controller.Writeback_Ack 1466 0.00% 0.00%
system.ruby.L1Cache_Controller.I.Load 667 0.00% 0.00%
system.ruby.L1Cache_Controller.Data 1472 0.00% 0.00%
system.ruby.L1Cache_Controller.Replacement 1468 0.00% 0.00%
system.ruby.L1Cache_Controller.Writeback_Ack 1468 0.00% 0.00%
system.ruby.L1Cache_Controller.I.Load 669 0.00% 0.00%
system.ruby.L1Cache_Controller.I.Ifetch 586 0.00% 0.00%
system.ruby.L1Cache_Controller.I.Store 217 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Load 465 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Ifetch 5039 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Load 466 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Ifetch 5056 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Store 684 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Replacement 1466 0.00% 0.00%
system.ruby.L1Cache_Controller.MI.Writeback_Ack 1466 0.00% 0.00%
system.ruby.L1Cache_Controller.IS.Data 1253 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Replacement 1468 0.00% 0.00%
system.ruby.L1Cache_Controller.MI.Writeback_Ack 1468 0.00% 0.00%
system.ruby.L1Cache_Controller.IS.Data 1255 0.00% 0.00%
system.ruby.L1Cache_Controller.IM.Data 217 0.00% 0.00%
---------- End Simulation Statistics ----------

7
tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini
View file

@ -88,7 +88,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@ -130,7 +129,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
@ -183,7 +181,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
@ -218,6 +215,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
point_of_coherency=false
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
@ -248,7 +246,7 @@ env=
errout=cerr
euid=100
eventq_index=0
executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello
executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/mips/linux/hello
gid=100
input=cin
kvmInSE=false
@ -283,6 +281,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4

1
tests/quick/se/00.hello/ref/mips/linux/simple-timing/simerr
View file

@ -1,2 +1 @@
warn: Sockets disabled, not accepting gdb connections
warn: mmap failing: arguments not page-aligned: start 0x0 offset 0x7efefeff

12
tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout
View file

@ -1,13 +1,15 @@
Redirecting stdout to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing/simout
Redirecting stderr to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 21 2016 14:17:41
gem5 started Jan 21 2016 14:18:13
gem5 executing on zizzer, pid 60580
command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing -re /z/atgutier/gem5/gem5-commit/tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing
gem5 compiled Mar 14 2016 22:04:10
gem5 started Mar 14 2016 22:06:34
gem5 executing on phenom, pid 29861
command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello World!
Exiting @ tick 33912500 because target called exit()
Exiting @ tick 33932500 because target called exit()

264
tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt
View file

@ -1,16 +1,16 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000034 # Number of seconds simulated
sim_ticks 33912500 # Number of ticks simulated
final_tick 33912500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 33932500 # Number of ticks simulated
final_tick 33932500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 109628 # Simulator instruction rate (inst/s)
host_op_rate 109584 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 660533411 # Simulator tick rate (ticks/s)
host_mem_usage 228304 # Number of bytes of host memory used
host_seconds 0.05 # Real time elapsed on the host
sim_insts 5624 # Number of instructions simulated
sim_ops 5624 # Number of ops (including micro ops) simulated
host_inst_rate 42153 # Simulator instruction rate (inst/s)
host_op_rate 42149 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 253513577 # Simulator tick rate (ticks/s)
host_mem_usage 224784 # Number of bytes of host memory used
host_seconds 0.13 # Real time elapsed on the host
sim_insts 5641 # Number of instructions simulated
sim_ops 5641 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 18752 # Number of bytes read from this memory
@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 18752 # Nu
system.physmem.num_reads::cpu.inst 293 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 137 # Number of read requests responded to by this memory
system.physmem.num_reads::total 430 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 552952451 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 258547733 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 811500184 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 552952451 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 552952451 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 552952451 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 258547733 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 811500184 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 552626538 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 258395344 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 811021882 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 552626538 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 552626538 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 552626538 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 258395344 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 811021882 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
@ -49,87 +49,87 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 7 # Number of system calls
system.cpu.numCycles 67825 # number of cpu cycles simulated
system.cpu.numCycles 67865 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 5624 # Number of instructions committed
system.cpu.committedOps 5624 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 4944 # Number of integer alu accesses
system.cpu.committedInsts 5641 # Number of instructions committed
system.cpu.committedOps 5641 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 4957 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses
system.cpu.num_func_calls 190 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 649 # number of instructions that are conditional controls
system.cpu.num_int_insts 4944 # number of integer instructions
system.cpu.num_func_calls 191 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 651 # number of instructions that are conditional controls
system.cpu.num_int_insts 4957 # number of integer instructions
system.cpu.num_fp_insts 2 # number of float instructions
system.cpu.num_int_register_reads 7054 # number of times the integer registers were read
system.cpu.num_int_register_writes 3281 # number of times the integer registers were written
system.cpu.num_int_register_reads 7072 # number of times the integer registers were read
system.cpu.num_int_register_writes 3291 # number of times the integer registers were written
system.cpu.num_fp_register_reads 3 # number of times the floating registers were read
system.cpu.num_fp_register_writes 1 # number of times the floating registers were written
system.cpu.num_mem_refs 2034 # number of memory refs
system.cpu.num_load_insts 1132 # Number of load instructions
system.cpu.num_mem_refs 2037 # number of memory refs
system.cpu.num_load_insts 1135 # Number of load instructions
system.cpu.num_store_insts 902 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 67825 # Number of busy cycles
system.cpu.num_busy_cycles 67865 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.Branches 883 # Number of branches fetched
system.cpu.op_class::No_OpClass 637 11.32% 11.32% # Class of executed instruction
system.cpu.op_class::IntAlu 2950 52.44% 63.77% # Class of executed instruction
system.cpu.op_class::IntMult 2 0.04% 63.80% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 63.80% # Class of executed instruction
system.cpu.op_class::FloatAdd 2 0.04% 63.84% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::MemRead 1132 20.12% 83.96% # Class of executed instruction
system.cpu.op_class::MemWrite 902 16.04% 100.00% # Class of executed instruction
system.cpu.Branches 886 # Number of branches fetched
system.cpu.op_class::No_OpClass 641 11.36% 11.36% # Class of executed instruction
system.cpu.op_class::IntAlu 2960 52.46% 63.82% # Class of executed instruction
system.cpu.op_class::IntMult 2 0.04% 63.86% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 63.86% # Class of executed instruction
system.cpu.op_class::FloatAdd 2 0.04% 63.90% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::MemRead 1135 20.12% 84.01% # Class of executed instruction
system.cpu.op_class::MemWrite 902 15.99% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 5625 # Class of executed instruction
system.cpu.op_class::total 5642 # Class of executed instruction
system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 86.067027 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 1896 # Total number of references to valid blocks.
system.cpu.dcache.tags.tagsinuse 86.030444 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 1899 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 137 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 13.839416 # Average number of references to valid blocks.
system.cpu.dcache.tags.avg_refs 13.861314 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 86.067027 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.021012 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.021012 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_blocks::cpu.data 86.030444 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.021004 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.021004 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 137 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 115 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.033447 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 4203 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 4203 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 1045 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1045 # number of ReadReq hits
system.cpu.dcache.tags.tag_accesses 4209 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 4209 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 851 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 851 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 1896 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 1896 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 1896 # number of overall hits
system.cpu.dcache.overall_hits::total 1896 # number of overall hits
system.cpu.dcache.demand_hits::cpu.data 1899 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 1899 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 1899 # number of overall hits
system.cpu.dcache.overall_hits::total 1899 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 87 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 87 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 50 # number of WriteReq misses
@ -146,22 +146,22 @@ system.cpu.dcache.demand_miss_latency::cpu.data 8494000
system.cpu.dcache.demand_miss_latency::total 8494000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 8494000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 8494000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 1132 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1132 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::cpu.data 1135 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1135 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 2033 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 2033 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 2033 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 2033 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076855 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.076855 # miss rate for ReadReq accesses
system.cpu.dcache.demand_accesses::cpu.data 2036 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 2036 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 2036 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 2036 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076652 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.076652 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.055494 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.055494 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.067388 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.067388 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.067388 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.067388 # miss rate for overall accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.067289 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.067289 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.067289 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.067289 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62000 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 62000 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency
@ -194,14 +194,14 @@ system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8357000
system.cpu.dcache.demand_mshr_miss_latency::total 8357000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8357000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 8357000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076855 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076855 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076652 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076652 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.067388 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.067388 # mshr miss rate for overall accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067289 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.067289 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067289 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.067289 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency
@ -212,26 +212,26 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000
system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 13 # number of replacements
system.cpu.icache.tags.tagsinuse 129.022312 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 5331 # Total number of references to valid blocks.
system.cpu.icache.tags.tagsinuse 128.953338 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 5348 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 295 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 18.071186 # Average number of references to valid blocks.
system.cpu.icache.tags.avg_refs 18.128814 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 129.022312 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.062999 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.062999 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_blocks::cpu.inst 128.953338 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.062965 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.062965 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 282 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 177 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.137695 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 11547 # Number of tag accesses
system.cpu.icache.tags.data_accesses 11547 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 5331 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 5331 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 5331 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 5331 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 5331 # number of overall hits
system.cpu.icache.overall_hits::total 5331 # number of overall hits
system.cpu.icache.tags.tag_accesses 11581 # Number of tag accesses
system.cpu.icache.tags.data_accesses 11581 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 5348 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 5348 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 5348 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 5348 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 5348 # number of overall hits
system.cpu.icache.overall_hits::total 5348 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 295 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 295 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 295 # number of demand (read+write) misses
@ -244,18 +244,18 @@ system.cpu.icache.demand_miss_latency::cpu.inst 18192500
system.cpu.icache.demand_miss_latency::total 18192500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 18192500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 18192500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 5626 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 5626 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 5626 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 5626 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 5626 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 5626 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052435 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.052435 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.052435 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.052435 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.052435 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.052435 # miss rate for overall accesses
system.cpu.icache.ReadReq_accesses::cpu.inst 5643 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 5643 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 5643 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 5643 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 5643 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 5643 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052277 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.052277 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.052277 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.052277 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.052277 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.052277 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61669.491525 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 61669.491525 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 61669.491525 # average overall miss latency
@ -284,12 +284,12 @@ system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17897500
system.cpu.icache.demand_mshr_miss_latency::total 17897500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17897500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 17897500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052435 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052435 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052435 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.052435 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052435 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.052435 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052277 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052277 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052277 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.052277 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052277 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.052277 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60669.491525 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60669.491525 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60669.491525 # average overall mshr miss latency
@ -298,16 +298,16 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60669.491525
system.cpu.icache.overall_avg_mshr_miss_latency::total 60669.491525 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 183.581605 # Cycle average of tags in use
system.cpu.l2cache.tags.tagsinuse 183.490494 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 15 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 380 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.039474 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.156658 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 53.424948 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003972 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.087016 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 53.403478 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003970 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001630 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.005602 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.005600 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 380 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 255 # Occupied blocks per task id

10
tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simout
View file

@ -1,9 +1,11 @@
Redirecting stdout to build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt/simout
Redirecting stderr to build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Mar 13 2016 22:43:13
gem5 started Mar 13 2016 22:49:02
gem5 executing on phenom, pid 19910
gem5 compiled Mar 14 2016 21:54:46
gem5 started Mar 14 2016 21:58:29
gem5 executing on phenom, pid 28223
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt
Global frequency set at 1000000000000 ticks per second
@ -12,4 +14,4 @@ info: Increasing stack size by one page.
info: Increasing stack size by one page.
Hello world!
Hello world!
Exiting @ tick 24832500 because target called exit()
Exiting @ tick 24794500 because target called exit()

1596
tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt
View file

File diff suppressed because it is too large Load diff

1
tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/config.ini
View file

@ -222,6 +222,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4

12
tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/simout
View file

@ -1,14 +1,16 @@
Redirecting stdout to build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple/simout
Redirecting stderr to build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 21 2016 13:49:21
gem5 started Jan 21 2016 13:50:15
gem5 executing on zizzer, pid 34054
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple
gem5 compiled Mar 14 2016 21:54:46
gem5 started Mar 14 2016 21:58:08
gem5 executing on phenom, pid 28209
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple
Global frequency set at 1000000000000 ticks per second
Beginning simulation!
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
Exiting @ tick 405501000 because target called exit()
Exiting @ tick 405365000 because target called exit()

345
tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/stats.txt
View file

@ -1,91 +1,91 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000406 # Number of seconds simulated
sim_ticks 405501000 # Number of ticks simulated
final_tick 405501000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_seconds 0.000405 # Number of seconds simulated
sim_ticks 405365000 # Number of ticks simulated
final_tick 405365000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 86197 # Simulator instruction rate (inst/s)
host_op_rate 86167 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 5423806428 # Simulator tick rate (ticks/s)
host_mem_usage 613516 # Number of bytes of host memory used
host_seconds 0.07 # Real time elapsed on the host
sim_insts 6440 # Number of instructions simulated
sim_ops 6440 # Number of ops (including micro ops) simulated
host_inst_rate 83628 # Simulator instruction rate (inst/s)
host_op_rate 83610 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 5251060650 # Simulator tick rate (ticks/s)
host_mem_usage 610048 # Number of bytes of host memory used
host_seconds 0.08 # Real time elapsed on the host
sim_insts 6453 # Number of instructions simulated
sim_ops 6453 # Number of ops (including micro ops) simulated
system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.mem_ctrl.bytes_read::cpu.inst 25800 # Number of bytes read from this memory
system.mem_ctrl.bytes_read::cpu.data 8828 # Number of bytes read from this memory
system.mem_ctrl.bytes_read::total 34628 # Number of bytes read from this memory
system.mem_ctrl.bytes_inst_read::cpu.inst 25800 # Number of instructions bytes read from this memory
system.mem_ctrl.bytes_inst_read::total 25800 # Number of instructions bytes read from this memory
system.mem_ctrl.bytes_read::cpu.inst 25852 # Number of bytes read from this memory
system.mem_ctrl.bytes_read::cpu.data 8844 # Number of bytes read from this memory
system.mem_ctrl.bytes_read::total 34696 # Number of bytes read from this memory
system.mem_ctrl.bytes_inst_read::cpu.inst 25852 # Number of instructions bytes read from this memory
system.mem_ctrl.bytes_inst_read::total 25852 # Number of instructions bytes read from this memory
system.mem_ctrl.bytes_written::cpu.data 6696 # Number of bytes written to this memory
system.mem_ctrl.bytes_written::total 6696 # Number of bytes written to this memory
system.mem_ctrl.num_reads::cpu.inst 6450 # Number of read requests responded to by this memory
system.mem_ctrl.num_reads::cpu.data 1188 # Number of read requests responded to by this memory
system.mem_ctrl.num_reads::total 7638 # Number of read requests responded to by this memory
system.mem_ctrl.num_reads::cpu.inst 6463 # Number of read requests responded to by this memory
system.mem_ctrl.num_reads::cpu.data 1190 # Number of read requests responded to by this memory
system.mem_ctrl.num_reads::total 7653 # Number of read requests responded to by this memory
system.mem_ctrl.num_writes::cpu.data 865 # Number of write requests responded to by this memory
system.mem_ctrl.num_writes::total 865 # Number of write requests responded to by this memory
system.mem_ctrl.bw_read::cpu.inst 63624997 # Total read bandwidth from this memory (bytes/s)
system.mem_ctrl.bw_read::cpu.data 21770600 # Total read bandwidth from this memory (bytes/s)
system.mem_ctrl.bw_read::total 85395597 # Total read bandwidth from this memory (bytes/s)
system.mem_ctrl.bw_inst_read::cpu.inst 63624997 # Instruction read bandwidth from this memory (bytes/s)
system.mem_ctrl.bw_inst_read::total 63624997 # Instruction read bandwidth from this memory (bytes/s)
system.mem_ctrl.bw_write::cpu.data 16512906 # Write bandwidth from this memory (bytes/s)
system.mem_ctrl.bw_write::total 16512906 # Write bandwidth from this memory (bytes/s)
system.mem_ctrl.bw_total::cpu.inst 63624997 # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrl.bw_total::cpu.data 38283506 # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrl.bw_total::total 101908503 # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrl.readReqs 7639 # Number of read requests accepted
system.mem_ctrl.bw_read::cpu.inst 63774623 # Total read bandwidth from this memory (bytes/s)
system.mem_ctrl.bw_read::cpu.data 21817374 # Total read bandwidth from this memory (bytes/s)
system.mem_ctrl.bw_read::total 85591997 # Total read bandwidth from this memory (bytes/s)
system.mem_ctrl.bw_inst_read::cpu.inst 63774623 # Instruction read bandwidth from this memory (bytes/s)
system.mem_ctrl.bw_inst_read::total 63774623 # Instruction read bandwidth from this memory (bytes/s)
system.mem_ctrl.bw_write::cpu.data 16518446 # Write bandwidth from this memory (bytes/s)
system.mem_ctrl.bw_write::total 16518446 # Write bandwidth from this memory (bytes/s)
system.mem_ctrl.bw_total::cpu.inst 63774623 # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrl.bw_total::cpu.data 38335821 # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrl.bw_total::total 102110444 # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrl.readReqs 7654 # Number of read requests accepted
system.mem_ctrl.writeReqs 865 # Number of write requests accepted
system.mem_ctrl.readBursts 7639 # Number of DRAM read bursts, including those serviced by the write queue
system.mem_ctrl.readBursts 7654 # Number of DRAM read bursts, including those serviced by the write queue
system.mem_ctrl.writeBursts 865 # Number of DRAM write bursts, including those merged in the write queue
system.mem_ctrl.bytesReadDRAM 477632 # Total number of bytes read from DRAM
system.mem_ctrl.bytesReadWrQ 11264 # Total number of bytes read from write queue
system.mem_ctrl.bytesReadDRAM 477504 # Total number of bytes read from DRAM
system.mem_ctrl.bytesReadWrQ 12352 # Total number of bytes read from write queue
system.mem_ctrl.bytesWritten 6144 # Total number of bytes written to DRAM
system.mem_ctrl.bytesReadSys 34632 # Total read bytes from the system interface side
system.mem_ctrl.bytesReadSys 34700 # Total read bytes from the system interface side
system.mem_ctrl.bytesWrittenSys 6696 # Total written bytes from the system interface side
system.mem_ctrl.servicedByWrQ 176 # Number of DRAM read bursts serviced by the write queue
system.mem_ctrl.servicedByWrQ 193 # Number of DRAM read bursts serviced by the write queue
system.mem_ctrl.mergedWrBursts 747 # Number of DRAM write bursts merged with an existing one
system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.mem_ctrl.perBankRdBursts::0 1736 # Per bank write bursts
system.mem_ctrl.perBankRdBursts::1 393 # Per bank write bursts
system.mem_ctrl.perBankRdBursts::2 768 # Per bank write bursts
system.mem_ctrl.perBankRdBursts::3 787 # Per bank write bursts
system.mem_ctrl.perBankRdBursts::4 776 # Per bank write bursts
system.mem_ctrl.perBankRdBursts::3 800 # Per bank write bursts
system.mem_ctrl.perBankRdBursts::4 763 # Per bank write bursts
system.mem_ctrl.perBankRdBursts::5 293 # Per bank write bursts
system.mem_ctrl.perBankRdBursts::6 6 # Per bank write bursts
system.mem_ctrl.perBankRdBursts::7 26 # Per bank write bursts
system.mem_ctrl.perBankRdBursts::8 0 # Per bank write bursts
system.mem_ctrl.perBankRdBursts::9 1 # Per bank write bursts
system.mem_ctrl.perBankRdBursts::10 257 # Per bank write bursts
system.mem_ctrl.perBankRdBursts::10 253 # Per bank write bursts
system.mem_ctrl.perBankRdBursts::11 578 # Per bank write bursts
system.mem_ctrl.perBankRdBursts::12 167 # Per bank write bursts
system.mem_ctrl.perBankRdBursts::13 1430 # Per bank write bursts
system.mem_ctrl.perBankRdBursts::14 89 # Per bank write bursts
system.mem_ctrl.perBankRdBursts::15 156 # Per bank write bursts
system.mem_ctrl.perBankRdBursts::15 158 # Per bank write bursts
system.mem_ctrl.perBankWrBursts::0 0 # Per bank write bursts
system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts
system.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts
system.mem_ctrl.perBankWrBursts::3 0 # Per bank write bursts
system.mem_ctrl.perBankWrBursts::4 27 # Per bank write bursts
system.mem_ctrl.perBankWrBursts::5 6 # Per bank write bursts
system.mem_ctrl.perBankWrBursts::4 18 # Per bank write bursts
system.mem_ctrl.perBankWrBursts::5 8 # Per bank write bursts
system.mem_ctrl.perBankWrBursts::6 0 # Per bank write bursts
system.mem_ctrl.perBankWrBursts::7 0 # Per bank write bursts
system.mem_ctrl.perBankWrBursts::8 0 # Per bank write bursts
system.mem_ctrl.perBankWrBursts::9 0 # Per bank write bursts
system.mem_ctrl.perBankWrBursts::10 5 # Per bank write bursts
system.mem_ctrl.perBankWrBursts::10 6 # Per bank write bursts
system.mem_ctrl.perBankWrBursts::11 0 # Per bank write bursts
system.mem_ctrl.perBankWrBursts::12 0 # Per bank write bursts
system.mem_ctrl.perBankWrBursts::13 14 # Per bank write bursts
system.mem_ctrl.perBankWrBursts::14 44 # Per bank write bursts
system.mem_ctrl.perBankWrBursts::13 21 # Per bank write bursts
system.mem_ctrl.perBankWrBursts::14 43 # Per bank write bursts
system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts
system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry
system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry
system.mem_ctrl.totGap 405425000 # Total gap between requests
system.mem_ctrl.totGap 405289000 # Total gap between requests
system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2)
system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2)
system.mem_ctrl.readPktSize::2 6620 # Read request sizes (log2)
system.mem_ctrl.readPktSize::3 1019 # Read request sizes (log2)
system.mem_ctrl.readPktSize::2 6633 # Read request sizes (log2)
system.mem_ctrl.readPktSize::3 1021 # Read request sizes (log2)
system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2)
system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2)
system.mem_ctrl.readPktSize::6 0 # Read request sizes (log2)
@ -96,7 +96,7 @@ system.mem_ctrl.writePktSize::3 809 # Wr
system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2)
system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2)
system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2)
system.mem_ctrl.rdQLenPdf::0 7463 # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::0 7461 # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see
@ -192,106 +192,105 @@ system.mem_ctrl.wrQLenPdf::60 0 # Wh
system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.mem_ctrl.bytesPerActivate::samples 775 # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::mean 623.649032 # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::gmean 407.696259 # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::stdev 407.140251 # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::0-127 158 20.39% 20.39% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::128-255 63 8.13% 28.52% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::256-383 48 6.19% 34.71% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::384-511 41 5.29% 40.00% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::512-639 47 6.06% 46.06% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::640-767 28 3.61% 49.68% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::768-895 28 3.61% 53.29% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::896-1023 33 4.26% 57.55% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::1024-1151 329 42.45% 100.00% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::total 775 # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::samples 762 # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::mean 634.288714 # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::gmean 419.900652 # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::stdev 405.302633 # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::0-127 146 19.16% 19.16% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::128-255 69 9.06% 28.22% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::256-383 39 5.12% 33.33% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::384-511 43 5.64% 38.98% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::512-639 44 5.77% 44.75% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::640-767 27 3.54% 48.29% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::768-895 31 4.07% 52.36% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::896-1023 30 3.94% 56.30% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::1024-1151 333 43.70% 100.00% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::total 762 # Bytes accessed per row activation
system.mem_ctrl.rdPerTurnAround::samples 6 # Reads before turning the bus around for writes
system.mem_ctrl.rdPerTurnAround::mean 1159.333333 # Reads before turning the bus around for writes
system.mem_ctrl.rdPerTurnAround::gmean 1053.861325 # Reads before turning the bus around for writes
system.mem_ctrl.rdPerTurnAround::stdev 505.634519 # Reads before turning the bus around for writes
system.mem_ctrl.rdPerTurnAround::512-575 1 16.67% 16.67% # Reads before turning the bus around for writes
system.mem_ctrl.rdPerTurnAround::576-639 1 16.67% 33.33% # Reads before turning the bus around for writes
system.mem_ctrl.rdPerTurnAround::1152-1215 1 16.67% 50.00% # Reads before turning the bus around for writes
system.mem_ctrl.rdPerTurnAround::1344-1407 1 16.67% 66.67% # Reads before turning the bus around for writes
system.mem_ctrl.rdPerTurnAround::1408-1471 1 16.67% 83.33% # Reads before turning the bus around for writes
system.mem_ctrl.rdPerTurnAround::1792-1855 1 16.67% 100.00% # Reads before turning the bus around for writes
system.mem_ctrl.rdPerTurnAround::mean 1203.833333 # Reads before turning the bus around for writes
system.mem_ctrl.rdPerTurnAround::gmean 1052.985580 # Reads before turning the bus around for writes
system.mem_ctrl.rdPerTurnAround::stdev 699.444184 # Reads before turning the bus around for writes
system.mem_ctrl.rdPerTurnAround::512-639 2 33.33% 33.33% # Reads before turning the bus around for writes
system.mem_ctrl.rdPerTurnAround::896-1023 1 16.67% 50.00% # Reads before turning the bus around for writes
system.mem_ctrl.rdPerTurnAround::1152-1279 1 16.67% 66.67% # Reads before turning the bus around for writes
system.mem_ctrl.rdPerTurnAround::1408-1535 1 16.67% 83.33% # Reads before turning the bus around for writes
system.mem_ctrl.rdPerTurnAround::2432-2559 1 16.67% 100.00% # Reads before turning the bus around for writes
system.mem_ctrl.rdPerTurnAround::total 6 # Reads before turning the bus around for writes
system.mem_ctrl.wrPerTurnAround::samples 6 # Writes before turning the bus around for reads
system.mem_ctrl.wrPerTurnAround::mean 16 # Writes before turning the bus around for reads
system.mem_ctrl.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads
system.mem_ctrl.wrPerTurnAround::16 6 100.00% 100.00% # Writes before turning the bus around for reads
system.mem_ctrl.wrPerTurnAround::total 6 # Writes before turning the bus around for reads
system.mem_ctrl.totQLat 26448250 # Total ticks spent queuing
system.mem_ctrl.totMemAccLat 166379500 # Total ticks spent from burst creation until serviced by the DRAM
system.mem_ctrl.totBusLat 37315000 # Total ticks spent in databus transfers
system.mem_ctrl.avgQLat 3543.92 # Average queueing delay per DRAM burst
system.mem_ctrl.totQLat 26088750 # Total ticks spent queuing
system.mem_ctrl.totMemAccLat 165982500 # Total ticks spent from burst creation until serviced by the DRAM
system.mem_ctrl.totBusLat 37305000 # Total ticks spent in databus transfers
system.mem_ctrl.avgQLat 3496.68 # Average queueing delay per DRAM burst
system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.mem_ctrl.avgMemAccLat 22293.92 # Average memory access latency per DRAM burst
system.mem_ctrl.avgRdBW 1177.88 # Average DRAM read bandwidth in MiByte/s
system.mem_ctrl.avgWrBW 15.15 # Average achieved write bandwidth in MiByte/s
system.mem_ctrl.avgRdBWSys 85.41 # Average system read bandwidth in MiByte/s
system.mem_ctrl.avgWrBWSys 16.51 # Average system write bandwidth in MiByte/s
system.mem_ctrl.avgMemAccLat 22246.68 # Average memory access latency per DRAM burst
system.mem_ctrl.avgRdBW 1177.96 # Average DRAM read bandwidth in MiByte/s
system.mem_ctrl.avgWrBW 15.16 # Average achieved write bandwidth in MiByte/s
system.mem_ctrl.avgRdBWSys 85.60 # Average system read bandwidth in MiByte/s
system.mem_ctrl.avgWrBWSys 16.52 # Average system write bandwidth in MiByte/s
system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.mem_ctrl.busUtil 9.32 # Data bus utilization in percentage
system.mem_ctrl.busUtilRead 9.20 # Data bus utilization in percentage for reads
system.mem_ctrl.busUtilWrite 0.12 # Data bus utilization in percentage for writes
system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing
system.mem_ctrl.avgWrQLen 23.37 # Average write queue length when enqueuing
system.mem_ctrl.readRowHits 6696 # Number of row buffer hits during reads
system.mem_ctrl.writeRowHits 87 # Number of row buffer hits during writes
system.mem_ctrl.readRowHitRate 89.72 # Row buffer hit rate for reads
system.mem_ctrl.writeRowHitRate 73.73 # Row buffer hit rate for writes
system.mem_ctrl.avgGap 47674.62 # Average gap between requests
system.mem_ctrl.pageHitRate 89.47 # Row buffer hit rate, read and write combined
system.mem_ctrl_0.actEnergy 3439800 # Energy for activate commands per rank (pJ)
system.mem_ctrl_0.preEnergy 1876875 # Energy for precharge commands per rank (pJ)
system.mem_ctrl_0.readEnergy 37268400 # Energy for read commands per rank (pJ)
system.mem_ctrl_0.writeEnergy 213840 # Energy for write commands per rank (pJ)
system.mem_ctrl.avgWrQLen 24.34 # Average write queue length when enqueuing
system.mem_ctrl.readRowHits 6706 # Number of row buffer hits during reads
system.mem_ctrl.writeRowHits 88 # Number of row buffer hits during writes
system.mem_ctrl.readRowHitRate 89.88 # Row buffer hit rate for reads
system.mem_ctrl.writeRowHitRate 74.58 # Row buffer hit rate for writes
system.mem_ctrl.avgGap 47574.72 # Average gap between requests
system.mem_ctrl.pageHitRate 89.64 # Row buffer hit rate, read and write combined
system.mem_ctrl_0.actEnergy 3333960 # Energy for activate commands per rank (pJ)
system.mem_ctrl_0.preEnergy 1819125 # Energy for precharge commands per rank (pJ)
system.mem_ctrl_0.readEnergy 37284000 # Energy for read commands per rank (pJ)
system.mem_ctrl_0.writeEnergy 168480 # Energy for write commands per rank (pJ)
system.mem_ctrl_0.refreshEnergy 26445120 # Energy for refresh commands per rank (pJ)
system.mem_ctrl_0.actBackEnergy 264293325 # Energy for active background per rank (pJ)
system.mem_ctrl_0.preBackEnergy 11250750 # Energy for precharge background per rank (pJ)
system.mem_ctrl_0.totalEnergy 344788110 # Total energy per rank (pJ)
system.mem_ctrl_0.averagePower 851.023979 # Core power per rank (mW)
system.mem_ctrl_0.memoryStateTime::IDLE 15542500 # Time in different power states
system.mem_ctrl_0.actBackEnergy 262765440 # Energy for active background per rank (pJ)
system.mem_ctrl_0.preBackEnergy 12591750 # Energy for precharge background per rank (pJ)
system.mem_ctrl_0.totalEnergy 344407875 # Total energy per rank (pJ)
system.mem_ctrl_0.averagePower 850.082840 # Core power per rank (mW)
system.mem_ctrl_0.memoryStateTime::IDLE 17896000 # Time in different power states
system.mem_ctrl_0.memoryStateTime::REF 13520000 # Time in different power states
system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.mem_ctrl_0.memoryStateTime::ACT 376096250 # Time in different power states
system.mem_ctrl_0.memoryStateTime::ACT 373743250 # Time in different power states
system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.mem_ctrl_1.actEnergy 2419200 # Energy for activate commands per rank (pJ)
system.mem_ctrl_1.preEnergy 1320000 # Energy for precharge commands per rank (pJ)
system.mem_ctrl_1.readEnergy 20888400 # Energy for read commands per rank (pJ)
system.mem_ctrl_1.writeEnergy 408240 # Energy for write commands per rank (pJ)
system.mem_ctrl_1.actEnergy 2426760 # Energy for activate commands per rank (pJ)
system.mem_ctrl_1.preEnergy 1324125 # Energy for precharge commands per rank (pJ)
system.mem_ctrl_1.readEnergy 20872800 # Energy for read commands per rank (pJ)
system.mem_ctrl_1.writeEnergy 453600 # Energy for write commands per rank (pJ)
system.mem_ctrl_1.refreshEnergy 26445120 # Energy for refresh commands per rank (pJ)
system.mem_ctrl_1.actBackEnergy 228585105 # Energy for active background per rank (pJ)
system.mem_ctrl_1.preBackEnergy 42573750 # Energy for precharge background per rank (pJ)
system.mem_ctrl_1.totalEnergy 322639815 # Total energy per rank (pJ)
system.mem_ctrl_1.averagePower 796.356403 # Core power per rank (mW)
system.mem_ctrl_1.memoryStateTime::IDLE 69100250 # Time in different power states
system.mem_ctrl_1.actBackEnergy 229562370 # Energy for active background per rank (pJ)
system.mem_ctrl_1.preBackEnergy 41716500 # Energy for precharge background per rank (pJ)
system.mem_ctrl_1.totalEnergy 322801275 # Total energy per rank (pJ)
system.mem_ctrl_1.averagePower 796.754927 # Core power per rank (mW)
system.mem_ctrl_1.memoryStateTime::IDLE 67586500 # Time in different power states
system.mem_ctrl_1.memoryStateTime::REF 13520000 # Time in different power states
system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.mem_ctrl_1.memoryStateTime::ACT 322538500 # Time in different power states
system.mem_ctrl_1.memoryStateTime::ACT 324052250 # Time in different power states
system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 1188 # DTB read hits
system.cpu.dtb.read_hits 1190 # DTB read hits
system.cpu.dtb.read_misses 7 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 1195 # DTB read accesses
system.cpu.dtb.read_accesses 1197 # DTB read accesses
system.cpu.dtb.write_hits 865 # DTB write hits
system.cpu.dtb.write_misses 3 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 868 # DTB write accesses
system.cpu.dtb.data_hits 2053 # DTB hits
system.cpu.dtb.data_hits 2055 # DTB hits
system.cpu.dtb.data_misses 10 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 2063 # DTB accesses
system.cpu.itb.fetch_hits 6451 # ITB hits
system.cpu.dtb.data_accesses 2065 # DTB accesses
system.cpu.itb.fetch_hits 6464 # ITB hits
system.cpu.itb.fetch_misses 17 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 6468 # ITB accesses
system.cpu.itb.fetch_accesses 6481 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@ -305,90 +304,90 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
system.cpu.numCycles 405501 # number of cpu cycles simulated
system.cpu.numCycles 405365 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 6440 # Number of instructions committed
system.cpu.committedOps 6440 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 6368 # Number of integer alu accesses
system.cpu.committedInsts 6453 # Number of instructions committed
system.cpu.committedOps 6453 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 6380 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
system.cpu.num_func_calls 251 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 754 # number of instructions that are conditional controls
system.cpu.num_int_insts 6368 # number of integer instructions
system.cpu.num_conditional_control_insts 759 # number of instructions that are conditional controls
system.cpu.num_int_insts 6380 # number of integer instructions
system.cpu.num_fp_insts 10 # number of float instructions
system.cpu.num_int_register_reads 8380 # number of times the integer registers were read
system.cpu.num_int_register_writes 4614 # number of times the integer registers were written
system.cpu.num_int_register_reads 8392 # number of times the integer registers were read
system.cpu.num_int_register_writes 4621 # number of times the integer registers were written
system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
system.cpu.num_mem_refs 2063 # number of memory refs
system.cpu.num_load_insts 1195 # Number of load instructions
system.cpu.num_mem_refs 2065 # number of memory refs
system.cpu.num_load_insts 1197 # Number of load instructions
system.cpu.num_store_insts 868 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 405501 # Number of busy cycles
system.cpu.num_busy_cycles 405365 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.Branches 1054 # Number of branches fetched
system.cpu.Branches 1060 # Number of branches fetched
system.cpu.op_class::No_OpClass 19 0.29% 0.29% # Class of executed instruction
system.cpu.op_class::IntAlu 4365 67.67% 67.97% # Class of executed instruction
system.cpu.op_class::IntMult 1 0.02% 67.98% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 67.98% # Class of executed instruction
system.cpu.op_class::FloatAdd 2 0.03% 68.02% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 68.02% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 68.02% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 68.02% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 68.02% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 68.02% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 68.02% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 68.02% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 68.02% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 68.02% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 68.02% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 68.02% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 68.02% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 68.02% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 68.02% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 68.02% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 68.02% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 68.02% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 68.02% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 68.02% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 68.02% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 68.02% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 68.02% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 68.02% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.02% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.02% # Class of executed instruction
system.cpu.op_class::MemRead 1195 18.53% 86.54% # Class of executed instruction
system.cpu.op_class::MemWrite 868 13.46% 100.00% # Class of executed instruction
system.cpu.op_class::IntAlu 4376 67.71% 68.00% # Class of executed instruction
system.cpu.op_class::IntMult 1 0.02% 68.02% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 68.02% # Class of executed instruction
system.cpu.op_class::FloatAdd 2 0.03% 68.05% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 68.05% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 68.05% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 68.05% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 68.05% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 68.05% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 68.05% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 68.05% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 68.05% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 68.05% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 68.05% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 68.05% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 68.05% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 68.05% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 68.05% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 68.05% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 68.05% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 68.05% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 68.05% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 68.05% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 68.05% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 68.05% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 68.05% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 68.05% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.05% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.05% # Class of executed instruction
system.cpu.op_class::MemRead 1197 18.52% 86.57% # Class of executed instruction
system.cpu.op_class::MemWrite 868 13.43% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 6450 # Class of executed instruction
system.membus.trans_dist::ReadReq 7639 # Transaction distribution
system.membus.trans_dist::ReadResp 7638 # Transaction distribution
system.cpu.op_class::total 6463 # Class of executed instruction
system.membus.trans_dist::ReadReq 7654 # Transaction distribution
system.membus.trans_dist::ReadResp 7653 # Transaction distribution
system.membus.trans_dist::WriteReq 865 # Transaction distribution
system.membus.trans_dist::WriteResp 865 # Transaction distribution
system.membus.pkt_count_system.cpu.icache_port::system.mem_ctrl.port 12901 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.mem_ctrl.port 4106 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 17007 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.mem_ctrl.port 25800 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.mem_ctrl.port 15524 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 41324 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.icache_port::system.mem_ctrl.port 12927 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.mem_ctrl.port 4110 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 17037 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.mem_ctrl.port 25852 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.mem_ctrl.port 15540 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 41392 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 8504 # Request fanout histogram
system.membus.snoop_fanout::mean 0.758584 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.427967 # Request fanout histogram
system.membus.snoop_fanout::samples 8519 # Request fanout histogram
system.membus.snoop_fanout::mean 0.758775 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.427852 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 2053 24.14% 24.14% # Request fanout histogram
system.membus.snoop_fanout::1 6451 75.86% 100.00% # Request fanout histogram
system.membus.snoop_fanout::0 2055 24.12% 24.12% # Request fanout histogram
system.membus.snoop_fanout::1 6464 75.88% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 8504 # Request fanout histogram
system.membus.reqLayer0.occupancy 9369000 # Layer occupancy (ticks)
system.membus.snoop_fanout::total 8519 # Request fanout histogram
system.membus.reqLayer0.occupancy 9384000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 2.3 # Layer utilization (%)
system.membus.respLayer0.occupancy 14662500 # Layer occupancy (ticks)
system.membus.respLayer0.occupancy 14690750 # Layer occupancy (ticks)
system.membus.respLayer0.utilization 3.6 # Layer utilization (%)
system.membus.respLayer1.occupancy 3576750 # Layer occupancy (ticks)
system.membus.respLayer1.occupancy 3574500 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.9 # Layer utilization (%)
---------- End Simulation Statistics ----------

5
tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/config.ini
View file

@ -94,7 +94,6 @@ clk_domain=system.clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@ -136,7 +135,6 @@ clk_domain=system.clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@ -220,6 +218,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
point_of_coherency=false
response_latency=1
snoop_filter=system.l2bus.snoop_filter
snoop_response_latency=1
@ -245,7 +244,6 @@ clk_domain=system.clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
@ -356,6 +354,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4

12
tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/simout
View file

@ -1,14 +1,16 @@
Redirecting stdout to build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level/simout
Redirecting stderr to build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 21 2016 13:49:21
gem5 started Jan 21 2016 13:50:14
gem5 executing on zizzer, pid 34037
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level
gem5 compiled Mar 14 2016 21:54:46
gem5 started Mar 14 2016 21:56:34
gem5 executing on phenom, pid 28126
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level
Global frequency set at 1000000000000 ticks per second
Beginning simulation!
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
Exiting @ tick 61610000 because target called exit()
Exiting @ tick 61470000 because target called exit()

552
tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt
View file

@ -1,16 +1,16 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000062 # Number of seconds simulated
sim_ticks 61610000 # Number of ticks simulated
final_tick 61610000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_seconds 0.000061 # Number of seconds simulated
sim_ticks 61470000 # Number of ticks simulated
final_tick 61470000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 98323 # Simulator instruction rate (inst/s)
host_op_rate 98283 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 939896452 # Simulator tick rate (ticks/s)
host_mem_usage 618136 # Number of bytes of host memory used
host_seconds 0.07 # Real time elapsed on the host
sim_insts 6440 # Number of instructions simulated
sim_ops 6440 # Number of ops (including micro ops) simulated
host_inst_rate 62593 # Simulator instruction rate (inst/s)
host_op_rate 62569 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 595804848 # Simulator tick rate (ticks/s)
host_mem_usage 614668 # Number of bytes of host memory used
host_seconds 0.10 # Real time elapsed on the host
sim_insts 6453 # Number of instructions simulated
sim_ops 6453 # Number of ops (including micro ops) simulated
system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.mem_ctrl.bytes_read::cpu.inst 17792 # Number of bytes read from this memory
@ -21,14 +21,14 @@ system.mem_ctrl.bytes_inst_read::total 17792 # Nu
system.mem_ctrl.num_reads::cpu.inst 278 # Number of read requests responded to by this memory
system.mem_ctrl.num_reads::cpu.data 168 # Number of read requests responded to by this memory
system.mem_ctrl.num_reads::total 446 # Number of read requests responded to by this memory
system.mem_ctrl.bw_read::cpu.inst 288784288 # Total read bandwidth from this memory (bytes/s)
system.mem_ctrl.bw_read::cpu.data 174517124 # Total read bandwidth from this memory (bytes/s)
system.mem_ctrl.bw_read::total 463301412 # Total read bandwidth from this memory (bytes/s)
system.mem_ctrl.bw_inst_read::cpu.inst 288784288 # Instruction read bandwidth from this memory (bytes/s)
system.mem_ctrl.bw_inst_read::total 288784288 # Instruction read bandwidth from this memory (bytes/s)
system.mem_ctrl.bw_total::cpu.inst 288784288 # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrl.bw_total::cpu.data 174517124 # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrl.bw_total::total 463301412 # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrl.bw_read::cpu.inst 289442004 # Total read bandwidth from this memory (bytes/s)
system.mem_ctrl.bw_read::cpu.data 174914592 # Total read bandwidth from this memory (bytes/s)
system.mem_ctrl.bw_read::total 464356597 # Total read bandwidth from this memory (bytes/s)
system.mem_ctrl.bw_inst_read::cpu.inst 289442004 # Instruction read bandwidth from this memory (bytes/s)
system.mem_ctrl.bw_inst_read::total 289442004 # Instruction read bandwidth from this memory (bytes/s)
system.mem_ctrl.bw_total::cpu.inst 289442004 # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrl.bw_total::cpu.data 174914592 # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrl.bw_total::total 464356597 # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrl.readReqs 446 # Number of read requests accepted
system.mem_ctrl.writeReqs 0 # Number of write requests accepted
system.mem_ctrl.readBursts 446 # Number of DRAM read bursts, including those serviced by the write queue
@ -75,7 +75,7 @@ system.mem_ctrl.perBankWrBursts::14 0 # Pe
system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts
system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry
system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry
system.mem_ctrl.totGap 61360000 # Total gap between requests
system.mem_ctrl.totGap 61220000 # Total gap between requests
system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2)
system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2)
system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2)
@ -187,88 +187,88 @@ system.mem_ctrl.wrQLenPdf::61 0 # Wh
system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.mem_ctrl.bytesPerActivate::samples 95 # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::mean 270.147368 # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::gmean 180.864884 # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::stdev 259.243949 # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::0-127 27 28.42% 28.42% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::128-255 31 32.63% 61.05% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::256-383 11 11.58% 72.63% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::384-511 8 8.42% 81.05% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::512-639 6 6.32% 87.37% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::mean 270.821053 # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::gmean 180.792132 # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::stdev 259.793616 # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::0-127 28 29.47% 29.47% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::128-255 29 30.53% 60.00% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::256-383 12 12.63% 72.63% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::384-511 9 9.47% 82.11% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::512-639 5 5.26% 87.37% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::640-767 6 6.32% 93.68% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::768-895 1 1.05% 94.74% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::1024-1151 5 5.26% 100.00% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::total 95 # Bytes accessed per row activation
system.mem_ctrl.totQLat 3464500 # Total ticks spent queuing
system.mem_ctrl.totMemAccLat 11827000 # Total ticks spent from burst creation until serviced by the DRAM
system.mem_ctrl.totQLat 3294500 # Total ticks spent queuing
system.mem_ctrl.totMemAccLat 11657000 # Total ticks spent from burst creation until serviced by the DRAM
system.mem_ctrl.totBusLat 2230000 # Total ticks spent in databus transfers
system.mem_ctrl.avgQLat 7767.94 # Average queueing delay per DRAM burst
system.mem_ctrl.avgQLat 7386.77 # Average queueing delay per DRAM burst
system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.mem_ctrl.avgMemAccLat 26517.94 # Average memory access latency per DRAM burst
system.mem_ctrl.avgRdBW 463.30 # Average DRAM read bandwidth in MiByte/s
system.mem_ctrl.avgMemAccLat 26136.77 # Average memory access latency per DRAM burst
system.mem_ctrl.avgRdBW 464.36 # Average DRAM read bandwidth in MiByte/s
system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.mem_ctrl.avgRdBWSys 463.30 # Average system read bandwidth in MiByte/s
system.mem_ctrl.avgRdBWSys 464.36 # Average system read bandwidth in MiByte/s
system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.mem_ctrl.busUtil 3.62 # Data bus utilization in percentage
system.mem_ctrl.busUtilRead 3.62 # Data bus utilization in percentage for reads
system.mem_ctrl.busUtil 3.63 # Data bus utilization in percentage
system.mem_ctrl.busUtilRead 3.63 # Data bus utilization in percentage for reads
system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing
system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing
system.mem_ctrl.readRowHits 340 # Number of row buffer hits during reads
system.mem_ctrl.readRowHits 341 # Number of row buffer hits during reads
system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes
system.mem_ctrl.readRowHitRate 76.23 # Row buffer hit rate for reads
system.mem_ctrl.readRowHitRate 76.46 # Row buffer hit rate for reads
system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes
system.mem_ctrl.avgGap 137578.48 # Average gap between requests
system.mem_ctrl.pageHitRate 76.23 # Row buffer hit rate, read and write combined
system.mem_ctrl_0.actEnergy 302400 # Energy for activate commands per rank (pJ)
system.mem_ctrl_0.preEnergy 165000 # Energy for precharge commands per rank (pJ)
system.mem_ctrl_0.readEnergy 1583400 # Energy for read commands per rank (pJ)
system.mem_ctrl.avgGap 137264.57 # Average gap between requests
system.mem_ctrl.pageHitRate 76.46 # Row buffer hit rate, read and write combined
system.mem_ctrl_0.actEnergy 309960 # Energy for activate commands per rank (pJ)
system.mem_ctrl_0.preEnergy 169125 # Energy for precharge commands per rank (pJ)
system.mem_ctrl_0.readEnergy 1591200 # Energy for read commands per rank (pJ)
system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.mem_ctrl_0.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ)
system.mem_ctrl_0.actBackEnergy 37159155 # Energy for active background per rank (pJ)
system.mem_ctrl_0.preBackEnergy 262500 # Energy for precharge background per rank (pJ)
system.mem_ctrl_0.totalEnergy 43032375 # Total energy per rank (pJ)
system.mem_ctrl_0.averagePower 785.782110 # Core power per rank (mW)
system.mem_ctrl_0.memoryStateTime::IDLE 256750 # Time in different power states
system.mem_ctrl_0.actBackEnergy 37059120 # Energy for active background per rank (pJ)
system.mem_ctrl_0.preBackEnergy 350250 # Energy for precharge background per rank (pJ)
system.mem_ctrl_0.totalEnergy 43039575 # Total energy per rank (pJ)
system.mem_ctrl_0.averagePower 785.913583 # Core power per rank (mW)
system.mem_ctrl_0.memoryStateTime::IDLE 388750 # Time in different power states
system.mem_ctrl_0.memoryStateTime::REF 1820000 # Time in different power states
system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.mem_ctrl_0.memoryStateTime::ACT 52700750 # Time in different power states
system.mem_ctrl_0.memoryStateTime::ACT 52568750 # Time in different power states
system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.mem_ctrl_1.actEnergy 393120 # Energy for activate commands per rank (pJ)
system.mem_ctrl_1.preEnergy 214500 # Energy for precharge commands per rank (pJ)
system.mem_ctrl_1.actEnergy 385560 # Energy for activate commands per rank (pJ)
system.mem_ctrl_1.preEnergy 210375 # Energy for precharge commands per rank (pJ)
system.mem_ctrl_1.readEnergy 1489800 # Energy for read commands per rank (pJ)
system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.mem_ctrl_1.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ)
system.mem_ctrl_1.actBackEnergy 35929665 # Energy for active background per rank (pJ)
system.mem_ctrl_1.preBackEnergy 1341000 # Energy for precharge background per rank (pJ)
system.mem_ctrl_1.totalEnergy 42928005 # Total energy per rank (pJ)
system.mem_ctrl_1.averagePower 783.876287 # Core power per rank (mW)
system.mem_ctrl_1.memoryStateTime::IDLE 2295000 # Time in different power states
system.mem_ctrl_1.actBackEnergy 35948475 # Energy for active background per rank (pJ)
system.mem_ctrl_1.preBackEnergy 1324500 # Energy for precharge background per rank (pJ)
system.mem_ctrl_1.totalEnergy 42918630 # Total energy per rank (pJ)
system.mem_ctrl_1.averagePower 783.705097 # Core power per rank (mW)
system.mem_ctrl_1.memoryStateTime::IDLE 2128500 # Time in different power states
system.mem_ctrl_1.memoryStateTime::REF 1820000 # Time in different power states
system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.mem_ctrl_1.memoryStateTime::ACT 51042000 # Time in different power states
system.mem_ctrl_1.memoryStateTime::ACT 51068500 # Time in different power states
system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 1188 # DTB read hits
system.cpu.dtb.read_hits 1190 # DTB read hits
system.cpu.dtb.read_misses 7 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 1195 # DTB read accesses
system.cpu.dtb.read_accesses 1197 # DTB read accesses
system.cpu.dtb.write_hits 865 # DTB write hits
system.cpu.dtb.write_misses 3 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 868 # DTB write accesses
system.cpu.dtb.data_hits 2053 # DTB hits
system.cpu.dtb.data_hits 2055 # DTB hits
system.cpu.dtb.data_misses 10 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 2063 # DTB accesses
system.cpu.itb.fetch_hits 6451 # ITB hits
system.cpu.dtb.data_accesses 2065 # DTB accesses
system.cpu.itb.fetch_hits 6464 # ITB hits
system.cpu.itb.fetch_misses 17 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 6468 # ITB accesses
system.cpu.itb.fetch_accesses 6481 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@ -282,87 +282,87 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
system.cpu.numCycles 61610 # number of cpu cycles simulated
system.cpu.numCycles 61470 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 6440 # Number of instructions committed
system.cpu.committedOps 6440 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 6368 # Number of integer alu accesses
system.cpu.committedInsts 6453 # Number of instructions committed
system.cpu.committedOps 6453 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 6380 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
system.cpu.num_func_calls 251 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 754 # number of instructions that are conditional controls
system.cpu.num_int_insts 6368 # number of integer instructions
system.cpu.num_conditional_control_insts 759 # number of instructions that are conditional controls
system.cpu.num_int_insts 6380 # number of integer instructions
system.cpu.num_fp_insts 10 # number of float instructions
system.cpu.num_int_register_reads 8380 # number of times the integer registers were read
system.cpu.num_int_register_writes 4614 # number of times the integer registers were written
system.cpu.num_int_register_reads 8392 # number of times the integer registers were read
system.cpu.num_int_register_writes 4621 # number of times the integer registers were written
system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
system.cpu.num_mem_refs 2063 # number of memory refs
system.cpu.num_load_insts 1195 # Number of load instructions
system.cpu.num_mem_refs 2065 # number of memory refs
system.cpu.num_load_insts 1197 # Number of load instructions
system.cpu.num_store_insts 868 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 61610 # Number of busy cycles
system.cpu.num_busy_cycles 61470 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.Branches 1054 # Number of branches fetched
system.cpu.Branches 1060 # Number of branches fetched
system.cpu.op_class::No_OpClass 19 0.29% 0.29% # Class of executed instruction
system.cpu.op_class::IntAlu 4365 67.67% 67.97% # Class of executed instruction
system.cpu.op_class::IntMult 1 0.02% 67.98% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 67.98% # Class of executed instruction
system.cpu.op_class::FloatAdd 2 0.03% 68.02% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 68.02% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 68.02% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 68.02% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 68.02% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 68.02% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 68.02% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 68.02% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 68.02% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 68.02% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 68.02% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 68.02% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 68.02% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 68.02% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 68.02% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 68.02% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 68.02% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 68.02% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 68.02% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 68.02% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 68.02% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 68.02% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 68.02% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 68.02% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.02% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.02% # Class of executed instruction
system.cpu.op_class::MemRead 1195 18.53% 86.54% # Class of executed instruction
system.cpu.op_class::MemWrite 868 13.46% 100.00% # Class of executed instruction
system.cpu.op_class::IntAlu 4376 67.71% 68.00% # Class of executed instruction
system.cpu.op_class::IntMult 1 0.02% 68.02% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 68.02% # Class of executed instruction
system.cpu.op_class::FloatAdd 2 0.03% 68.05% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 68.05% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 68.05% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 68.05% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 68.05% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 68.05% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 68.05% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 68.05% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 68.05% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 68.05% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 68.05% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 68.05% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 68.05% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 68.05% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 68.05% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 68.05% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 68.05% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 68.05% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 68.05% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 68.05% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 68.05% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 68.05% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 68.05% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 68.05% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.05% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.05% # Class of executed instruction
system.cpu.op_class::MemRead 1197 18.52% 86.57% # Class of executed instruction
system.cpu.op_class::MemWrite 868 13.43% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 6450 # Class of executed instruction
system.cpu.op_class::total 6463 # Class of executed instruction
system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 104.302306 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 1885 # Total number of references to valid blocks.
system.cpu.dcache.tags.tagsinuse 104.645861 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 1887 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 11.220238 # Average number of references to valid blocks.
system.cpu.dcache.tags.avg_refs 11.232143 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 104.302306 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.101858 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.101858 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_blocks::cpu.data 104.645861 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.102193 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.102193 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.164062 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 4274 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 4274 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 1093 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1093 # number of ReadReq hits
system.cpu.dcache.tags.tag_accesses 4278 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 4278 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 1095 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1095 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 792 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 1885 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 1885 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 1885 # number of overall hits
system.cpu.dcache.overall_hits::total 1885 # number of overall hits
system.cpu.dcache.demand_hits::cpu.data 1887 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 1887 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 1887 # number of overall hits
system.cpu.dcache.overall_hits::total 1887 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 95 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 95 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 73 # number of WriteReq misses
@ -371,38 +371,38 @@ system.cpu.dcache.demand_misses::cpu.data 168 # n
system.cpu.dcache.demand_misses::total 168 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 168 # number of overall misses
system.cpu.dcache.overall_misses::total 168 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 9733000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 9733000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 7588000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 7588000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 17321000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 17321000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 17321000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 17321000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 1188 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1188 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_miss_latency::cpu.data 10102000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 10102000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 7278000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 7278000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 17380000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 17380000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 17380000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 17380000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 1190 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1190 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 2053 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 2053 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 2053 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 2053 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.079966 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.079966 # miss rate for ReadReq accesses
system.cpu.dcache.demand_accesses::cpu.data 2055 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 2055 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 2055 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 2055 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.079832 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.079832 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084393 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.084393 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.081831 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.081831 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.081831 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.081831 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 102452.631579 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 102452.631579 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 103945.205479 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 103945.205479 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 103101.190476 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 103101.190476 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 103101.190476 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 103101.190476 # average overall miss latency
system.cpu.dcache.demand_miss_rate::cpu.data 0.081752 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.081752 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.081752 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.081752 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 106336.842105 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 106336.842105 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 99698.630137 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 99698.630137 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 103452.380952 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 103452.380952 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 103452.380952 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 103452.380952 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -419,82 +419,82 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 168
system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9543000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 9543000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7442000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 7442000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16985000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 16985000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16985000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 16985000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.079966 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.079966 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9912000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 9912000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7132000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 7132000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17044000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 17044000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17044000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 17044000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.079832 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.079832 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.081831 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.081831 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.081831 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.081831 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 100452.631579 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 100452.631579 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 101945.205479 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 101945.205479 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 101101.190476 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 101101.190476 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101101.190476 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 101101.190476 # average overall mshr miss latency
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.081752 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.081752 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.081752 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.081752 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 104336.842105 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 104336.842105 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 97698.630137 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 97698.630137 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 101452.380952 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 101452.380952 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101452.380952 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 101452.380952 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 62 # number of replacements
system.cpu.icache.tags.tagsinuse 113.926978 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 6170 # Total number of references to valid blocks.
system.cpu.icache.tags.tagsinuse 113.715440 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 6183 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 281 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 21.957295 # Average number of references to valid blocks.
system.cpu.icache.tags.avg_refs 22.003559 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 113.926978 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.445027 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.445027 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_blocks::cpu.inst 113.715440 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.444201 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.444201 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 219 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 167 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.855469 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 13183 # Number of tag accesses
system.cpu.icache.tags.data_accesses 13183 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 6170 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 6170 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 6170 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 6170 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 6170 # number of overall hits
system.cpu.icache.overall_hits::total 6170 # number of overall hits
system.cpu.icache.tags.tag_accesses 13209 # Number of tag accesses
system.cpu.icache.tags.data_accesses 13209 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 6183 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 6183 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 6183 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 6183 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 6183 # number of overall hits
system.cpu.icache.overall_hits::total 6183 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 281 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 281 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 281 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 281 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 281 # number of overall misses
system.cpu.icache.overall_misses::total 281 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 28181000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 28181000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 28181000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 28181000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 28181000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 28181000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 6451 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 6451 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 6451 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 6451 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 6451 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 6451 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.043559 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.043559 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.043559 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.043559 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.043559 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.043559 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 100288.256228 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 100288.256228 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 100288.256228 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 100288.256228 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 100288.256228 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 100288.256228 # average overall miss latency
system.cpu.icache.ReadReq_miss_latency::cpu.inst 27952000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 27952000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 27952000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 27952000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 27952000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 27952000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 6464 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 6464 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 6464 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 6464 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 6464 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 6464 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.043472 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.043472 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.043472 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.043472 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.043472 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.043472 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 99473.309609 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 99473.309609 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 99473.309609 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 99473.309609 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 99473.309609 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 99473.309609 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -509,24 +509,24 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 281
system.cpu.icache.demand_mshr_misses::total 281 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 281 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 281 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27619000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 27619000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27619000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 27619000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27619000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 27619000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043559 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.043559 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043559 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.043559 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043559 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.043559 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 98288.256228 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 98288.256228 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 98288.256228 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 98288.256228 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 98288.256228 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 98288.256228 # average overall mshr miss latency
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27390000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 27390000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27390000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 27390000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27390000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 27390000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043472 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.043472 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043472 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.043472 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043472 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.043472 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 97473.309609 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 97473.309609 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 97473.309609 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 97473.309609 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 97473.309609 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 97473.309609 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.l2bus.snoop_filter.tot_requests 511 # Total number of requests made to the snoop filter.
system.l2bus.snoop_filter.hit_single_requests 63 # Number of requests hitting in the snoop filter with a single holder of the requested data.
@ -564,16 +564,16 @@ system.l2bus.respLayer0.utilization 1.4 # La
system.l2bus.respLayer1.occupancy 504000 # Layer occupancy (ticks)
system.l2bus.respLayer1.utilization 0.8 # Layer utilization (%)
system.l2cache.tags.replacements 0 # number of replacements
system.l2cache.tags.tagsinuse 185.392407 # Cycle average of tags in use
system.l2cache.tags.tagsinuse 185.619069 # Cycle average of tags in use
system.l2cache.tags.total_refs 65 # Total number of references to valid blocks.
system.l2cache.tags.sampled_refs 373 # Sample count of references to valid blocks.
system.l2cache.tags.avg_refs 0.174263 # Average number of references to valid blocks.
system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.l2cache.tags.occ_blocks::cpu.inst 128.681337 # Average occupied blocks per requestor
system.l2cache.tags.occ_blocks::cpu.data 56.711070 # Average occupied blocks per requestor
system.l2cache.tags.occ_percent::cpu.inst 0.031416 # Average percentage of cache occupancy
system.l2cache.tags.occ_percent::cpu.data 0.013845 # Average percentage of cache occupancy
system.l2cache.tags.occ_percent::total 0.045262 # Average percentage of cache occupancy
system.l2cache.tags.occ_blocks::cpu.inst 128.455542 # Average occupied blocks per requestor
system.l2cache.tags.occ_blocks::cpu.data 57.163528 # Average occupied blocks per requestor
system.l2cache.tags.occ_percent::cpu.inst 0.031361 # Average percentage of cache occupancy
system.l2cache.tags.occ_percent::cpu.data 0.013956 # Average percentage of cache occupancy
system.l2cache.tags.occ_percent::total 0.045317 # Average percentage of cache occupancy
system.l2cache.tags.occ_task_id_blocks::1024 373 # Occupied blocks per task id
system.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id
system.l2cache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id
@ -597,17 +597,17 @@ system.l2cache.demand_misses::total 446 # nu
system.l2cache.overall_misses::cpu.inst 278 # number of overall misses
system.l2cache.overall_misses::cpu.data 168 # number of overall misses
system.l2cache.overall_misses::total 446 # number of overall misses
system.l2cache.ReadExReq_miss_latency::cpu.data 7223000 # number of ReadExReq miss cycles
system.l2cache.ReadExReq_miss_latency::total 7223000 # number of ReadExReq miss cycles
system.l2cache.ReadSharedReq_miss_latency::cpu.inst 26711000 # number of ReadSharedReq miss cycles
system.l2cache.ReadSharedReq_miss_latency::cpu.data 9258000 # number of ReadSharedReq miss cycles
system.l2cache.ReadSharedReq_miss_latency::total 35969000 # number of ReadSharedReq miss cycles
system.l2cache.demand_miss_latency::cpu.inst 26711000 # number of demand (read+write) miss cycles
system.l2cache.demand_miss_latency::cpu.data 16481000 # number of demand (read+write) miss cycles
system.l2cache.demand_miss_latency::total 43192000 # number of demand (read+write) miss cycles
system.l2cache.overall_miss_latency::cpu.inst 26711000 # number of overall miss cycles
system.l2cache.overall_miss_latency::cpu.data 16481000 # number of overall miss cycles
system.l2cache.overall_miss_latency::total 43192000 # number of overall miss cycles
system.l2cache.ReadExReq_miss_latency::cpu.data 6913000 # number of ReadExReq miss cycles
system.l2cache.ReadExReq_miss_latency::total 6913000 # number of ReadExReq miss cycles
system.l2cache.ReadSharedReq_miss_latency::cpu.inst 26482000 # number of ReadSharedReq miss cycles
system.l2cache.ReadSharedReq_miss_latency::cpu.data 9627000 # number of ReadSharedReq miss cycles
system.l2cache.ReadSharedReq_miss_latency::total 36109000 # number of ReadSharedReq miss cycles
system.l2cache.demand_miss_latency::cpu.inst 26482000 # number of demand (read+write) miss cycles
system.l2cache.demand_miss_latency::cpu.data 16540000 # number of demand (read+write) miss cycles
system.l2cache.demand_miss_latency::total 43022000 # number of demand (read+write) miss cycles
system.l2cache.overall_miss_latency::cpu.inst 26482000 # number of overall miss cycles
system.l2cache.overall_miss_latency::cpu.data 16540000 # number of overall miss cycles
system.l2cache.overall_miss_latency::total 43022000 # number of overall miss cycles
system.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses)
system.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses)
system.l2cache.ReadSharedReq_accesses::cpu.inst 281 # number of ReadSharedReq accesses(hits+misses)
@ -630,17 +630,17 @@ system.l2cache.demand_miss_rate::total 0.993318 # mi
system.l2cache.overall_miss_rate::cpu.inst 0.989324 # miss rate for overall accesses
system.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
system.l2cache.overall_miss_rate::total 0.993318 # miss rate for overall accesses
system.l2cache.ReadExReq_avg_miss_latency::cpu.data 98945.205479 # average ReadExReq miss latency
system.l2cache.ReadExReq_avg_miss_latency::total 98945.205479 # average ReadExReq miss latency
system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 96082.733813 # average ReadSharedReq miss latency
system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 97452.631579 # average ReadSharedReq miss latency
system.l2cache.ReadSharedReq_avg_miss_latency::total 96431.635389 # average ReadSharedReq miss latency
system.l2cache.demand_avg_miss_latency::cpu.inst 96082.733813 # average overall miss latency
system.l2cache.demand_avg_miss_latency::cpu.data 98101.190476 # average overall miss latency
system.l2cache.demand_avg_miss_latency::total 96843.049327 # average overall miss latency
system.l2cache.overall_avg_miss_latency::cpu.inst 96082.733813 # average overall miss latency
system.l2cache.overall_avg_miss_latency::cpu.data 98101.190476 # average overall miss latency
system.l2cache.overall_avg_miss_latency::total 96843.049327 # average overall miss latency
system.l2cache.ReadExReq_avg_miss_latency::cpu.data 94698.630137 # average ReadExReq miss latency
system.l2cache.ReadExReq_avg_miss_latency::total 94698.630137 # average ReadExReq miss latency
system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 95258.992806 # average ReadSharedReq miss latency
system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 101336.842105 # average ReadSharedReq miss latency
system.l2cache.ReadSharedReq_avg_miss_latency::total 96806.970509 # average ReadSharedReq miss latency
system.l2cache.demand_avg_miss_latency::cpu.inst 95258.992806 # average overall miss latency
system.l2cache.demand_avg_miss_latency::cpu.data 98452.380952 # average overall miss latency
system.l2cache.demand_avg_miss_latency::total 96461.883408 # average overall miss latency
system.l2cache.overall_avg_miss_latency::cpu.inst 95258.992806 # average overall miss latency
system.l2cache.overall_avg_miss_latency::cpu.data 98452.380952 # average overall miss latency
system.l2cache.overall_avg_miss_latency::total 96461.883408 # average overall miss latency
system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -660,17 +660,17 @@ system.l2cache.demand_mshr_misses::total 446 # nu
system.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses
system.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
system.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses
system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5763000 # number of ReadExReq MSHR miss cycles
system.l2cache.ReadExReq_mshr_miss_latency::total 5763000 # number of ReadExReq MSHR miss cycles
system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 21151000 # number of ReadSharedReq MSHR miss cycles
system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7358000 # number of ReadSharedReq MSHR miss cycles
system.l2cache.ReadSharedReq_mshr_miss_latency::total 28509000 # number of ReadSharedReq MSHR miss cycles
system.l2cache.demand_mshr_miss_latency::cpu.inst 21151000 # number of demand (read+write) MSHR miss cycles
system.l2cache.demand_mshr_miss_latency::cpu.data 13121000 # number of demand (read+write) MSHR miss cycles
system.l2cache.demand_mshr_miss_latency::total 34272000 # number of demand (read+write) MSHR miss cycles
system.l2cache.overall_mshr_miss_latency::cpu.inst 21151000 # number of overall MSHR miss cycles
system.l2cache.overall_mshr_miss_latency::cpu.data 13121000 # number of overall MSHR miss cycles
system.l2cache.overall_mshr_miss_latency::total 34272000 # number of overall MSHR miss cycles
system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5453000 # number of ReadExReq MSHR miss cycles
system.l2cache.ReadExReq_mshr_miss_latency::total 5453000 # number of ReadExReq MSHR miss cycles
system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 20922000 # number of ReadSharedReq MSHR miss cycles
system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7727000 # number of ReadSharedReq MSHR miss cycles
system.l2cache.ReadSharedReq_mshr_miss_latency::total 28649000 # number of ReadSharedReq MSHR miss cycles
system.l2cache.demand_mshr_miss_latency::cpu.inst 20922000 # number of demand (read+write) MSHR miss cycles
system.l2cache.demand_mshr_miss_latency::cpu.data 13180000 # number of demand (read+write) MSHR miss cycles
system.l2cache.demand_mshr_miss_latency::total 34102000 # number of demand (read+write) MSHR miss cycles
system.l2cache.overall_mshr_miss_latency::cpu.inst 20922000 # number of overall MSHR miss cycles
system.l2cache.overall_mshr_miss_latency::cpu.data 13180000 # number of overall MSHR miss cycles
system.l2cache.overall_mshr_miss_latency::total 34102000 # number of overall MSHR miss cycles
system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.989324 # mshr miss rate for ReadSharedReq accesses
@ -682,17 +682,17 @@ system.l2cache.demand_mshr_miss_rate::total 0.993318 #
system.l2cache.overall_mshr_miss_rate::cpu.inst 0.989324 # mshr miss rate for overall accesses
system.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.l2cache.overall_mshr_miss_rate::total 0.993318 # mshr miss rate for overall accesses
system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78945.205479 # average ReadExReq mshr miss latency
system.l2cache.ReadExReq_avg_mshr_miss_latency::total 78945.205479 # average ReadExReq mshr miss latency
system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 76082.733813 # average ReadSharedReq mshr miss latency
system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77452.631579 # average ReadSharedReq mshr miss latency
system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76431.635389 # average ReadSharedReq mshr miss latency
system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76082.733813 # average overall mshr miss latency
system.l2cache.demand_avg_mshr_miss_latency::cpu.data 78101.190476 # average overall mshr miss latency
system.l2cache.demand_avg_mshr_miss_latency::total 76843.049327 # average overall mshr miss latency
system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76082.733813 # average overall mshr miss latency
system.l2cache.overall_avg_mshr_miss_latency::cpu.data 78101.190476 # average overall mshr miss latency
system.l2cache.overall_avg_mshr_miss_latency::total 76843.049327 # average overall mshr miss latency
system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 74698.630137 # average ReadExReq mshr miss latency
system.l2cache.ReadExReq_avg_mshr_miss_latency::total 74698.630137 # average ReadExReq mshr miss latency
system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 75258.992806 # average ReadSharedReq mshr miss latency
system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 81336.842105 # average ReadSharedReq mshr miss latency
system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76806.970509 # average ReadSharedReq mshr miss latency
system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 75258.992806 # average overall mshr miss latency
system.l2cache.demand_avg_mshr_miss_latency::cpu.data 78452.380952 # average overall mshr miss latency
system.l2cache.demand_avg_mshr_miss_latency::total 76461.883408 # average overall mshr miss latency
system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 75258.992806 # average overall mshr miss latency
system.l2cache.overall_avg_mshr_miss_latency::cpu.data 78452.380952 # average overall mshr miss latency
system.l2cache.overall_avg_mshr_miss_latency::total 76461.883408 # average overall mshr miss latency
system.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.membus.trans_dist::ReadResp 373 # Transaction distribution
system.membus.trans_dist::ReadExReq 73 # Transaction distribution

1
tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/config.ini
View file

@ -224,6 +224,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4

1
tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/simerr
View file

@ -1,3 +1,2 @@
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: mmap failing: arguments not page-aligned: start 0x0 offset 0x7efefeff

12
tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/simout
View file

@ -1,14 +1,16 @@
Redirecting stdout to build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple/simout
Redirecting stderr to build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 21 2016 14:17:41
gem5 started Jan 21 2016 14:18:13
gem5 executing on zizzer, pid 60583
command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple -re /z/atgutier/gem5/gem5-commit/tests/run.py build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple
gem5 compiled Mar 14 2016 22:04:10
gem5 started Mar 14 2016 22:06:34
gem5 executing on phenom, pid 29862
command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple
Global frequency set at 1000000000000 ticks per second
Beginning simulation!
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello World!
Exiting @ tick 367783000 because target called exit()
Exiting @ tick 368887000 because target called exit()

292
tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/stats.txt
View file

@ -1,48 +1,48 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000368 # Number of seconds simulated
sim_ticks 367783000 # Number of ticks simulated
final_tick 367783000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_seconds 0.000369 # Number of seconds simulated
sim_ticks 368887000 # Number of ticks simulated
final_tick 368887000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 91194 # Simulator instruction rate (inst/s)
host_op_rate 91153 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 5958550453 # Simulator tick rate (ticks/s)
host_mem_usage 611392 # Number of bytes of host memory used
host_seconds 0.06 # Real time elapsed on the host
sim_insts 5624 # Number of instructions simulated
sim_ops 5624 # Number of ops (including micro ops) simulated
host_inst_rate 25687 # Simulator instruction rate (inst/s)
host_op_rate 25686 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1679592961 # Simulator tick rate (ticks/s)
host_mem_usage 607900 # Number of bytes of host memory used
host_seconds 0.22 # Real time elapsed on the host
sim_insts 5641 # Number of instructions simulated
sim_ops 5641 # Number of ops (including micro ops) simulated
system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.mem_ctrl.bytes_read::cpu.inst 22500 # Number of bytes read from this memory
system.mem_ctrl.bytes_read::cpu.data 4289 # Number of bytes read from this memory
system.mem_ctrl.bytes_read::total 26789 # Number of bytes read from this memory
system.mem_ctrl.bytes_inst_read::cpu.inst 22500 # Number of instructions bytes read from this memory
system.mem_ctrl.bytes_inst_read::total 22500 # Number of instructions bytes read from this memory
system.mem_ctrl.bytes_read::cpu.inst 22568 # Number of bytes read from this memory
system.mem_ctrl.bytes_read::cpu.data 4301 # Number of bytes read from this memory
system.mem_ctrl.bytes_read::total 26869 # Number of bytes read from this memory
system.mem_ctrl.bytes_inst_read::cpu.inst 22568 # Number of instructions bytes read from this memory
system.mem_ctrl.bytes_inst_read::total 22568 # Number of instructions bytes read from this memory
system.mem_ctrl.bytes_written::cpu.data 3601 # Number of bytes written to this memory
system.mem_ctrl.bytes_written::total 3601 # Number of bytes written to this memory
system.mem_ctrl.num_reads::cpu.inst 5625 # Number of read requests responded to by this memory
system.mem_ctrl.num_reads::cpu.data 1132 # Number of read requests responded to by this memory
system.mem_ctrl.num_reads::total 6757 # Number of read requests responded to by this memory
system.mem_ctrl.num_reads::cpu.inst 5642 # Number of read requests responded to by this memory
system.mem_ctrl.num_reads::cpu.data 1135 # Number of read requests responded to by this memory
system.mem_ctrl.num_reads::total 6777 # Number of read requests responded to by this memory
system.mem_ctrl.num_writes::cpu.data 901 # Number of write requests responded to by this memory
system.mem_ctrl.num_writes::total 901 # Number of write requests responded to by this memory
system.mem_ctrl.bw_read::cpu.inst 61177379 # Total read bandwidth from this memory (bytes/s)
system.mem_ctrl.bw_read::cpu.data 11661768 # Total read bandwidth from this memory (bytes/s)
system.mem_ctrl.bw_read::total 72839147 # Total read bandwidth from this memory (bytes/s)
system.mem_ctrl.bw_inst_read::cpu.inst 61177379 # Instruction read bandwidth from this memory (bytes/s)
system.mem_ctrl.bw_inst_read::total 61177379 # Instruction read bandwidth from this memory (bytes/s)
system.mem_ctrl.bw_write::cpu.data 9791100 # Write bandwidth from this memory (bytes/s)
system.mem_ctrl.bw_write::total 9791100 # Write bandwidth from this memory (bytes/s)
system.mem_ctrl.bw_total::cpu.inst 61177379 # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrl.bw_total::cpu.data 21452868 # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrl.bw_total::total 82630247 # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrl.readReqs 6758 # Number of read requests accepted
system.mem_ctrl.bw_read::cpu.inst 61178627 # Total read bandwidth from this memory (bytes/s)
system.mem_ctrl.bw_read::cpu.data 11659397 # Total read bandwidth from this memory (bytes/s)
system.mem_ctrl.bw_read::total 72838024 # Total read bandwidth from this memory (bytes/s)
system.mem_ctrl.bw_inst_read::cpu.inst 61178627 # Instruction read bandwidth from this memory (bytes/s)
system.mem_ctrl.bw_inst_read::total 61178627 # Instruction read bandwidth from this memory (bytes/s)
system.mem_ctrl.bw_write::cpu.data 9761797 # Write bandwidth from this memory (bytes/s)
system.mem_ctrl.bw_write::total 9761797 # Write bandwidth from this memory (bytes/s)
system.mem_ctrl.bw_total::cpu.inst 61178627 # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrl.bw_total::cpu.data 21421194 # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrl.bw_total::total 82599821 # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrl.readReqs 6778 # Number of read requests accepted
system.mem_ctrl.writeReqs 901 # Number of write requests accepted
system.mem_ctrl.readBursts 6758 # Number of DRAM read bursts, including those serviced by the write queue
system.mem_ctrl.readBursts 6778 # Number of DRAM read bursts, including those serviced by the write queue
system.mem_ctrl.writeBursts 901 # Number of DRAM write bursts, including those merged in the write queue
system.mem_ctrl.bytesReadDRAM 426368 # Total number of bytes read from DRAM
system.mem_ctrl.bytesReadDRAM 427648 # Total number of bytes read from DRAM
system.mem_ctrl.bytesReadWrQ 6144 # Total number of bytes read from write queue
system.mem_ctrl.bytesWritten 4096 # Total number of bytes written to DRAM
system.mem_ctrl.bytesReadSys 26793 # Total read bytes from the system interface side
system.mem_ctrl.bytesReadSys 26873 # Total read bytes from the system interface side
system.mem_ctrl.bytesWrittenSys 3601 # Total written bytes from the system interface side
system.mem_ctrl.servicedByWrQ 96 # Number of DRAM read bursts serviced by the write queue
system.mem_ctrl.mergedWrBursts 807 # Number of DRAM write bursts merged with an existing one
@ -56,12 +56,12 @@ system.mem_ctrl.perBankRdBursts::5 18 # Pe
system.mem_ctrl.perBankRdBursts::6 105 # Per bank write bursts
system.mem_ctrl.perBankRdBursts::7 518 # Per bank write bursts
system.mem_ctrl.perBankRdBursts::8 543 # Per bank write bursts
system.mem_ctrl.perBankRdBursts::9 1211 # Per bank write bursts
system.mem_ctrl.perBankRdBursts::9 1212 # Per bank write bursts
system.mem_ctrl.perBankRdBursts::10 899 # Per bank write bursts
system.mem_ctrl.perBankRdBursts::11 346 # Per bank write bursts
system.mem_ctrl.perBankRdBursts::12 677 # Per bank write bursts
system.mem_ctrl.perBankRdBursts::13 396 # Per bank write bursts
system.mem_ctrl.perBankRdBursts::14 1409 # Per bank write bursts
system.mem_ctrl.perBankRdBursts::13 398 # Per bank write bursts
system.mem_ctrl.perBankRdBursts::14 1426 # Per bank write bursts
system.mem_ctrl.perBankRdBursts::15 50 # Per bank write bursts
system.mem_ctrl.perBankWrBursts::0 0 # Per bank write bursts
system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts
@ -81,10 +81,10 @@ system.mem_ctrl.perBankWrBursts::14 19 # Pe
system.mem_ctrl.perBankWrBursts::15 2 # Per bank write bursts
system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry
system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry
system.mem_ctrl.totGap 367707000 # Total gap between requests
system.mem_ctrl.totGap 368811000 # Total gap between requests
system.mem_ctrl.readPktSize::0 79 # Read request sizes (log2)
system.mem_ctrl.readPktSize::1 1 # Read request sizes (log2)
system.mem_ctrl.readPktSize::2 6678 # Read request sizes (log2)
system.mem_ctrl.readPktSize::2 6698 # Read request sizes (log2)
system.mem_ctrl.readPktSize::3 0 # Read request sizes (log2)
system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2)
system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2)
@ -96,7 +96,7 @@ system.mem_ctrl.writePktSize::3 0 # Wr
system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2)
system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2)
system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2)
system.mem_ctrl.rdQLenPdf::0 6662 # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::0 6682 # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see
@ -192,27 +192,27 @@ system.mem_ctrl.wrQLenPdf::60 0 # Wh
system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.mem_ctrl.bytesPerActivate::samples 842 # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::mean 509.263658 # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::gmean 293.556275 # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::stdev 414.582189 # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::0-127 268 31.83% 31.83% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::128-255 81 9.62% 41.45% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::256-383 48 5.70% 47.15% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::384-511 49 5.82% 52.97% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::512-639 36 4.28% 57.24% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::640-767 49 5.82% 63.06% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::768-895 19 2.26% 65.32% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::896-1023 21 2.49% 67.81% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::1024-1151 271 32.19% 100.00% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::total 842 # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::samples 849 # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::mean 506.270907 # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::gmean 291.216794 # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::stdev 415.367861 # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::0-127 272 32.04% 32.04% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::128-255 76 8.95% 40.99% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::256-383 61 7.18% 48.17% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::384-511 46 5.42% 53.59% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::512-639 36 4.24% 57.83% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::640-767 42 4.95% 62.78% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::768-895 24 2.83% 65.61% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::896-1023 15 1.77% 67.37% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::1024-1151 277 32.63% 100.00% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::total 849 # Bytes accessed per row activation
system.mem_ctrl.rdPerTurnAround::samples 4 # Reads before turning the bus around for writes
system.mem_ctrl.rdPerTurnAround::mean 1344.750000 # Reads before turning the bus around for writes
system.mem_ctrl.rdPerTurnAround::gmean 1258.849963 # Reads before turning the bus around for writes
system.mem_ctrl.rdPerTurnAround::stdev 502.036104 # Reads before turning the bus around for writes
system.mem_ctrl.rdPerTurnAround::mean 1349.750000 # Reads before turning the bus around for writes
system.mem_ctrl.rdPerTurnAround::gmean 1262.645152 # Reads before turning the bus around for writes
system.mem_ctrl.rdPerTurnAround::stdev 506.185325 # Reads before turning the bus around for writes
system.mem_ctrl.rdPerTurnAround::640-703 1 25.00% 25.00% # Reads before turning the bus around for writes
system.mem_ctrl.rdPerTurnAround::1216-1279 1 25.00% 50.00% # Reads before turning the bus around for writes
system.mem_ctrl.rdPerTurnAround::1600-1663 1 25.00% 75.00% # Reads before turning the bus around for writes
system.mem_ctrl.rdPerTurnAround::1664-1727 1 25.00% 75.00% # Reads before turning the bus around for writes
system.mem_ctrl.rdPerTurnAround::1792-1855 1 25.00% 100.00% # Reads before turning the bus around for writes
system.mem_ctrl.rdPerTurnAround::total 4 # Reads before turning the bus around for writes
system.mem_ctrl.wrPerTurnAround::samples 4 # Writes before turning the bus around for reads
@ -220,55 +220,55 @@ system.mem_ctrl.wrPerTurnAround::mean 16 # Wr
system.mem_ctrl.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads
system.mem_ctrl.wrPerTurnAround::16 4 100.00% 100.00% # Writes before turning the bus around for reads
system.mem_ctrl.wrPerTurnAround::total 4 # Writes before turning the bus around for reads
system.mem_ctrl.totQLat 27926000 # Total ticks spent queuing
system.mem_ctrl.totMemAccLat 152838500 # Total ticks spent from burst creation until serviced by the DRAM
system.mem_ctrl.totBusLat 33310000 # Total ticks spent in databus transfers
system.mem_ctrl.avgQLat 4191.83 # Average queueing delay per DRAM burst
system.mem_ctrl.totQLat 28067250 # Total ticks spent queuing
system.mem_ctrl.totMemAccLat 153354750 # Total ticks spent from burst creation until serviced by the DRAM
system.mem_ctrl.totBusLat 33410000 # Total ticks spent in databus transfers
system.mem_ctrl.avgQLat 4200.43 # Average queueing delay per DRAM burst
system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.mem_ctrl.avgMemAccLat 22941.83 # Average memory access latency per DRAM burst
system.mem_ctrl.avgMemAccLat 22950.43 # Average memory access latency per DRAM burst
system.mem_ctrl.avgRdBW 1159.29 # Average DRAM read bandwidth in MiByte/s
system.mem_ctrl.avgWrBW 11.14 # Average achieved write bandwidth in MiByte/s
system.mem_ctrl.avgWrBW 11.10 # Average achieved write bandwidth in MiByte/s
system.mem_ctrl.avgRdBWSys 72.85 # Average system read bandwidth in MiByte/s
system.mem_ctrl.avgWrBWSys 9.79 # Average system write bandwidth in MiByte/s
system.mem_ctrl.avgWrBWSys 9.76 # Average system write bandwidth in MiByte/s
system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.mem_ctrl.busUtil 9.14 # Data bus utilization in percentage
system.mem_ctrl.busUtilRead 9.06 # Data bus utilization in percentage for reads
system.mem_ctrl.busUtilWrite 0.09 # Data bus utilization in percentage for writes
system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing
system.mem_ctrl.avgWrQLen 23.24 # Average write queue length when enqueuing
system.mem_ctrl.readRowHits 5822 # Number of row buffer hits during reads
system.mem_ctrl.avgWrQLen 23.19 # Average write queue length when enqueuing
system.mem_ctrl.readRowHits 5834 # Number of row buffer hits during reads
system.mem_ctrl.writeRowHits 58 # Number of row buffer hits during writes
system.mem_ctrl.readRowHitRate 87.39 # Row buffer hit rate for reads
system.mem_ctrl.readRowHitRate 87.31 # Row buffer hit rate for reads
system.mem_ctrl.writeRowHitRate 61.70 # Row buffer hit rate for writes
system.mem_ctrl.avgGap 48009.79 # Average gap between requests
system.mem_ctrl.pageHitRate 87.03 # Row buffer hit rate, read and write combined
system.mem_ctrl.avgGap 48028.52 # Average gap between requests
system.mem_ctrl.pageHitRate 86.95 # Row buffer hit rate, read and write combined
system.mem_ctrl_0.actEnergy 1058400 # Energy for activate commands per rank (pJ)
system.mem_ctrl_0.preEnergy 577500 # Energy for precharge commands per rank (pJ)
system.mem_ctrl_0.readEnergy 8821800 # Energy for read commands per rank (pJ)
system.mem_ctrl_0.readEnergy 8806200 # Energy for read commands per rank (pJ)
system.mem_ctrl_0.writeEnergy 38880 # Energy for write commands per rank (pJ)
system.mem_ctrl_0.refreshEnergy 23902320 # Energy for refresh commands per rank (pJ)
system.mem_ctrl_0.actBackEnergy 136778625 # Energy for active background per rank (pJ)
system.mem_ctrl_0.preBackEnergy 99747000 # Energy for precharge background per rank (pJ)
system.mem_ctrl_0.totalEnergy 270924525 # Total energy per rank (pJ)
system.mem_ctrl_0.averagePower 739.798888 # Core power per rank (mW)
system.mem_ctrl_0.memoryStateTime::IDLE 164402500 # Time in different power states
system.mem_ctrl_0.actBackEnergy 143993115 # Energy for active background per rank (pJ)
system.mem_ctrl_0.preBackEnergy 93418500 # Energy for precharge background per rank (pJ)
system.mem_ctrl_0.totalEnergy 271794915 # Total energy per rank (pJ)
system.mem_ctrl_0.averagePower 742.175615 # Core power per rank (mW)
system.mem_ctrl_0.memoryStateTime::IDLE 153996500 # Time in different power states
system.mem_ctrl_0.memoryStateTime::REF 12220000 # Time in different power states
system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.mem_ctrl_0.memoryStateTime::ACT 189605000 # Time in different power states
system.mem_ctrl_0.memoryStateTime::ACT 200230500 # Time in different power states
system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.mem_ctrl_1.actEnergy 5299560 # Energy for activate commands per rank (pJ)
system.mem_ctrl_1.preEnergy 2891625 # Energy for precharge commands per rank (pJ)
system.mem_ctrl_1.actEnergy 5344920 # Energy for activate commands per rank (pJ)
system.mem_ctrl_1.preEnergy 2916375 # Energy for precharge commands per rank (pJ)
system.mem_ctrl_1.readEnergy 42907800 # Energy for read commands per rank (pJ)
system.mem_ctrl_1.writeEnergy 375840 # Energy for write commands per rank (pJ)
system.mem_ctrl_1.refreshEnergy 23902320 # Energy for refresh commands per rank (pJ)
system.mem_ctrl_1.actBackEnergy 246879540 # Energy for active background per rank (pJ)
system.mem_ctrl_1.preBackEnergy 3167250 # Energy for precharge background per rank (pJ)
system.mem_ctrl_1.totalEnergy 325423935 # Total energy per rank (pJ)
system.mem_ctrl_1.averagePower 888.617467 # Core power per rank (mW)
system.mem_ctrl_1.memoryStateTime::IDLE 3404750 # Time in different power states
system.mem_ctrl_1.actBackEnergy 246623040 # Energy for active background per rank (pJ)
system.mem_ctrl_1.preBackEnergy 3392250 # Energy for precharge background per rank (pJ)
system.mem_ctrl_1.totalEnergy 325462545 # Total energy per rank (pJ)
system.mem_ctrl_1.averagePower 888.722897 # Core power per rank (mW)
system.mem_ctrl_1.memoryStateTime::IDLE 3452250 # Time in different power states
system.mem_ctrl_1.memoryStateTime::REF 12220000 # Time in different power states
system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.mem_ctrl_1.memoryStateTime::ACT 350602750 # Time in different power states
system.mem_ctrl_1.memoryStateTime::ACT 350555250 # Time in different power states
system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
@ -289,90 +289,90 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 7 # Number of system calls
system.cpu.numCycles 367783 # number of cpu cycles simulated
system.cpu.numCycles 368887 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 5624 # Number of instructions committed
system.cpu.committedOps 5624 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 4944 # Number of integer alu accesses
system.cpu.committedInsts 5641 # Number of instructions committed
system.cpu.committedOps 5641 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 4957 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses
system.cpu.num_func_calls 190 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 649 # number of instructions that are conditional controls
system.cpu.num_int_insts 4944 # number of integer instructions
system.cpu.num_func_calls 191 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 651 # number of instructions that are conditional controls
system.cpu.num_int_insts 4957 # number of integer instructions
system.cpu.num_fp_insts 2 # number of float instructions
system.cpu.num_int_register_reads 7054 # number of times the integer registers were read
system.cpu.num_int_register_writes 3281 # number of times the integer registers were written
system.cpu.num_int_register_reads 7072 # number of times the integer registers were read
system.cpu.num_int_register_writes 3291 # number of times the integer registers were written
system.cpu.num_fp_register_reads 3 # number of times the floating registers were read
system.cpu.num_fp_register_writes 1 # number of times the floating registers were written
system.cpu.num_mem_refs 2034 # number of memory refs
system.cpu.num_load_insts 1132 # Number of load instructions
system.cpu.num_mem_refs 2037 # number of memory refs
system.cpu.num_load_insts 1135 # Number of load instructions
system.cpu.num_store_insts 902 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 367783 # Number of busy cycles
system.cpu.num_busy_cycles 368887 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.Branches 883 # Number of branches fetched
system.cpu.op_class::No_OpClass 637 11.32% 11.32% # Class of executed instruction
system.cpu.op_class::IntAlu 2950 52.44% 63.77% # Class of executed instruction
system.cpu.op_class::IntMult 2 0.04% 63.80% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 63.80% # Class of executed instruction
system.cpu.op_class::FloatAdd 2 0.04% 63.84% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::MemRead 1132 20.12% 83.96% # Class of executed instruction
system.cpu.op_class::MemWrite 902 16.04% 100.00% # Class of executed instruction
system.cpu.Branches 886 # Number of branches fetched
system.cpu.op_class::No_OpClass 641 11.36% 11.36% # Class of executed instruction
system.cpu.op_class::IntAlu 2960 52.46% 63.82% # Class of executed instruction
system.cpu.op_class::IntMult 2 0.04% 63.86% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 63.86% # Class of executed instruction
system.cpu.op_class::FloatAdd 2 0.04% 63.90% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::MemRead 1135 20.12% 84.01% # Class of executed instruction
system.cpu.op_class::MemWrite 902 15.99% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 5625 # Class of executed instruction
system.membus.trans_dist::ReadReq 6758 # Transaction distribution
system.membus.trans_dist::ReadResp 6757 # Transaction distribution
system.cpu.op_class::total 5642 # Class of executed instruction
system.membus.trans_dist::ReadReq 6778 # Transaction distribution
system.membus.trans_dist::ReadResp 6777 # Transaction distribution
system.membus.trans_dist::WriteReq 901 # Transaction distribution
system.membus.trans_dist::WriteResp 901 # Transaction distribution
system.membus.pkt_count_system.cpu.icache_port::system.mem_ctrl.port 11251 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.mem_ctrl.port 4066 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 15317 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.mem_ctrl.port 22500 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.mem_ctrl.port 7890 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 30390 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.icache_port::system.mem_ctrl.port 11285 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.mem_ctrl.port 4072 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 15357 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.mem_ctrl.port 22568 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.mem_ctrl.port 7902 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 30470 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 7659 # Request fanout histogram
system.membus.snoop_fanout::mean 0.734561 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.441596 # Request fanout histogram
system.membus.snoop_fanout::samples 7679 # Request fanout histogram
system.membus.snoop_fanout::mean 0.734861 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.441436 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 2033 26.54% 26.54% # Request fanout histogram
system.membus.snoop_fanout::1 5626 73.46% 100.00% # Request fanout histogram
system.membus.snoop_fanout::0 2036 26.51% 26.51% # Request fanout histogram
system.membus.snoop_fanout::1 5643 73.49% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 7659 # Request fanout histogram
system.membus.reqLayer0.occupancy 8560000 # Layer occupancy (ticks)
system.membus.snoop_fanout::total 7679 # Request fanout histogram
system.membus.reqLayer0.occupancy 8580000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 2.3 # Layer utilization (%)
system.membus.respLayer0.occupancy 12820000 # Layer occupancy (ticks)
system.membus.respLayer0.occupancy 12857500 # Layer occupancy (ticks)
system.membus.respLayer0.utilization 3.5 # Layer utilization (%)
system.membus.respLayer1.occupancy 3545250 # Layer occupancy (ticks)
system.membus.respLayer1.occupancy 3555500 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 1.0 # Layer utilization (%)
---------- End Simulation Statistics ----------

5
tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/config.ini
View file

@ -94,7 +94,6 @@ clk_domain=system.clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@ -136,7 +135,6 @@ clk_domain=system.clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@ -222,6 +220,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
point_of_coherency=false
response_latency=1
snoop_filter=system.l2bus.snoop_filter
snoop_response_latency=1
@ -247,7 +246,6 @@ clk_domain=system.clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
@ -358,6 +356,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4

1
tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/simerr
View file

@ -1,3 +1,2 @@
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: mmap failing: arguments not page-aligned: start 0x0 offset 0x7efefeff

10
tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/simout
View file

@ -1,10 +1,12 @@
Redirecting stdout to build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level/simout
Redirecting stderr to build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 21 2016 14:17:41
gem5 started Jan 21 2016 14:18:14
gem5 executing on zizzer, pid 60586
command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level -re /z/atgutier/gem5/gem5-commit/tests/run.py build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level
gem5 compiled Mar 14 2016 22:04:10
gem5 started Mar 14 2016 22:06:34
gem5 executing on phenom, pid 29863
command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level
Global frequency set at 1000000000000 ticks per second
Beginning simulation!

346
tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt
View file

@ -4,13 +4,13 @@ sim_seconds 0.000059 # Nu
sim_ticks 58892000 # Number of ticks simulated
final_tick 58892000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 88343 # Simulator instruction rate (inst/s)
host_op_rate 88311 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 924415589 # Simulator tick rate (ticks/s)
host_mem_usage 616028 # Number of bytes of host memory used
host_seconds 0.06 # Real time elapsed on the host
sim_insts 5624 # Number of instructions simulated
sim_ops 5624 # Number of ops (including micro ops) simulated
host_inst_rate 44023 # Simulator instruction rate (inst/s)
host_op_rate 44007 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 459268108 # Simulator tick rate (ticks/s)
host_mem_usage 612532 # Number of bytes of host memory used
host_seconds 0.13 # Real time elapsed on the host
sim_insts 5641 # Number of instructions simulated
sim_ops 5641 # Number of ops (including micro ops) simulated
system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.mem_ctrl.bytes_read::cpu.inst 18752 # Number of bytes read from this memory
@ -199,12 +199,12 @@ system.mem_ctrl.bytesPerActivate::640-767 4 3.54% 96.46% # B
system.mem_ctrl.bytesPerActivate::768-895 1 0.88% 97.35% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::1024-1151 3 2.65% 100.00% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::total 113 # Bytes accessed per row activation
system.mem_ctrl.totQLat 3878500 # Total ticks spent queuing
system.mem_ctrl.totMemAccLat 11941000 # Total ticks spent from burst creation until serviced by the DRAM
system.mem_ctrl.totQLat 3838500 # Total ticks spent queuing
system.mem_ctrl.totMemAccLat 11901000 # Total ticks spent from burst creation until serviced by the DRAM
system.mem_ctrl.totBusLat 2150000 # Total ticks spent in databus transfers
system.mem_ctrl.avgQLat 9019.77 # Average queueing delay per DRAM burst
system.mem_ctrl.avgQLat 8926.74 # Average queueing delay per DRAM burst
system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.mem_ctrl.avgMemAccLat 27769.77 # Average memory access latency per DRAM burst
system.mem_ctrl.avgMemAccLat 27676.74 # Average memory access latency per DRAM burst
system.mem_ctrl.avgRdBW 467.30 # Average DRAM read bandwidth in MiByte/s
system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.mem_ctrl.avgRdBWSys 467.30 # Average system read bandwidth in MiByte/s
@ -271,84 +271,84 @@ system.cpu.workload.num_syscalls 7 # Nu
system.cpu.numCycles 58892 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 5624 # Number of instructions committed
system.cpu.committedOps 5624 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 4944 # Number of integer alu accesses
system.cpu.committedInsts 5641 # Number of instructions committed
system.cpu.committedOps 5641 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 4957 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses
system.cpu.num_func_calls 190 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 649 # number of instructions that are conditional controls
system.cpu.num_int_insts 4944 # number of integer instructions
system.cpu.num_func_calls 191 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 651 # number of instructions that are conditional controls
system.cpu.num_int_insts 4957 # number of integer instructions
system.cpu.num_fp_insts 2 # number of float instructions
system.cpu.num_int_register_reads 7054 # number of times the integer registers were read
system.cpu.num_int_register_writes 3281 # number of times the integer registers were written
system.cpu.num_int_register_reads 7072 # number of times the integer registers were read
system.cpu.num_int_register_writes 3291 # number of times the integer registers were written
system.cpu.num_fp_register_reads 3 # number of times the floating registers were read
system.cpu.num_fp_register_writes 1 # number of times the floating registers were written
system.cpu.num_mem_refs 2034 # number of memory refs
system.cpu.num_load_insts 1132 # Number of load instructions
system.cpu.num_mem_refs 2037 # number of memory refs
system.cpu.num_load_insts 1135 # Number of load instructions
system.cpu.num_store_insts 902 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 58892 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.Branches 883 # Number of branches fetched
system.cpu.op_class::No_OpClass 637 11.32% 11.32% # Class of executed instruction
system.cpu.op_class::IntAlu 2950 52.44% 63.77% # Class of executed instruction
system.cpu.op_class::IntMult 2 0.04% 63.80% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 63.80% # Class of executed instruction
system.cpu.op_class::FloatAdd 2 0.04% 63.84% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction
system.cpu.op_class::MemRead 1132 20.12% 83.96% # Class of executed instruction
system.cpu.op_class::MemWrite 902 16.04% 100.00% # Class of executed instruction
system.cpu.Branches 886 # Number of branches fetched
system.cpu.op_class::No_OpClass 641 11.36% 11.36% # Class of executed instruction
system.cpu.op_class::IntAlu 2960 52.46% 63.82% # Class of executed instruction
system.cpu.op_class::IntMult 2 0.04% 63.86% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 63.86% # Class of executed instruction
system.cpu.op_class::FloatAdd 2 0.04% 63.90% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.90% # Class of executed instruction
system.cpu.op_class::MemRead 1135 20.12% 84.01% # Class of executed instruction
system.cpu.op_class::MemWrite 902 15.99% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 5625 # Class of executed instruction
system.cpu.op_class::total 5642 # Class of executed instruction
system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 86.277492 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 1896 # Total number of references to valid blocks.
system.cpu.dcache.tags.tagsinuse 86.268662 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 1899 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 137 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 13.839416 # Average number of references to valid blocks.
system.cpu.dcache.tags.avg_refs 13.861314 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 86.277492 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.084255 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.084255 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_blocks::cpu.data 86.268662 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.084247 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.084247 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 137 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.133789 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 4203 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 4203 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 1045 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1045 # number of ReadReq hits
system.cpu.dcache.tags.tag_accesses 4209 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 4209 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 851 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 851 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 1896 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 1896 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 1896 # number of overall hits
system.cpu.dcache.overall_hits::total 1896 # number of overall hits
system.cpu.dcache.demand_hits::cpu.data 1899 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 1899 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 1899 # number of overall hits
system.cpu.dcache.overall_hits::total 1899 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 87 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 87 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 50 # number of WriteReq misses
@ -365,22 +365,22 @@ system.cpu.dcache.demand_miss_latency::cpu.data 14174000
system.cpu.dcache.demand_miss_latency::total 14174000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 14174000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 14174000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 1132 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1132 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::cpu.data 1135 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1135 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 2033 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 2033 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 2033 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 2033 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076855 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.076855 # miss rate for ReadReq accesses
system.cpu.dcache.demand_accesses::cpu.data 2036 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 2036 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 2036 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 2036 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076652 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.076652 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.055494 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.055494 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.067388 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.067388 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.067388 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.067388 # miss rate for overall accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.067289 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.067289 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.067289 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.067289 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 102413.793103 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 102413.793103 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 105280 # average WriteReq miss latency
@ -413,14 +413,14 @@ system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13900000
system.cpu.dcache.demand_mshr_miss_latency::total 13900000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13900000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 13900000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076855 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076855 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076652 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076652 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.067388 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.067388 # mshr miss rate for overall accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067289 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.067289 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067289 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.067289 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 100413.793103 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 100413.793103 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 103280 # average WriteReq mshr miss latency
@ -431,56 +431,56 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101459.854015
system.cpu.dcache.overall_avg_mshr_miss_latency::total 101459.854015 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 94 # number of replacements
system.cpu.icache.tags.tagsinuse 110.157629 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 5329 # Total number of references to valid blocks.
system.cpu.icache.tags.tagsinuse 110.145403 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 5346 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 297 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 17.942761 # Average number of references to valid blocks.
system.cpu.icache.tags.avg_refs 18 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 110.157629 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.430303 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.430303 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_blocks::cpu.inst 110.145403 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.430255 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.430255 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 203 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 139 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.792969 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 11549 # Number of tag accesses
system.cpu.icache.tags.data_accesses 11549 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 5329 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 5329 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 5329 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 5329 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 5329 # number of overall hits
system.cpu.icache.overall_hits::total 5329 # number of overall hits
system.cpu.icache.tags.tag_accesses 11583 # Number of tag accesses
system.cpu.icache.tags.data_accesses 11583 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 5346 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 5346 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 5346 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 5346 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 5346 # number of overall hits
system.cpu.icache.overall_hits::total 5346 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 297 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 297 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 297 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 297 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 297 # number of overall misses
system.cpu.icache.overall_misses::total 297 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 30270000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 30270000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 30270000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 30270000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 30270000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 30270000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 5626 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 5626 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 5626 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 5626 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 5626 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 5626 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052791 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.052791 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.052791 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.052791 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.052791 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.052791 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 101919.191919 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 101919.191919 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 101919.191919 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 101919.191919 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 101919.191919 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 101919.191919 # average overall miss latency
system.cpu.icache.ReadReq_miss_latency::cpu.inst 30230000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 30230000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 30230000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 30230000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 30230000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 30230000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 5643 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 5643 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 5643 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 5643 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 5643 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 5643 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052632 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.052632 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.052632 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.052632 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.052632 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.052632 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 101784.511785 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 101784.511785 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 101784.511785 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 101784.511785 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 101784.511785 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 101784.511785 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -495,24 +495,24 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 297
system.cpu.icache.demand_mshr_misses::total 297 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 297 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 297 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 29676000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 29676000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 29676000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 29676000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 29676000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 29676000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052791 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052791 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052791 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.052791 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052791 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.052791 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 99919.191919 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 99919.191919 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 99919.191919 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 99919.191919 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 99919.191919 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 99919.191919 # average overall mshr miss latency
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 29636000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 29636000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 29636000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 29636000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 29636000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 29636000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052632 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052632 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052632 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.052632 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052632 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.052632 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 99784.511785 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 99784.511785 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 99784.511785 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 99784.511785 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 99784.511785 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 99784.511785 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.l2bus.snoop_filter.tot_requests 528 # Total number of requests made to the snoop filter.
system.l2bus.snoop_filter.hit_single_requests 94 # Number of requests hitting in the snoop filter with a single holder of the requested data.
@ -550,16 +550,16 @@ system.l2bus.respLayer0.utilization 1.5 # La
system.l2bus.respLayer1.occupancy 411000 # Layer occupancy (ticks)
system.l2bus.respLayer1.utilization 0.7 # Layer utilization (%)
system.l2cache.tags.replacements 0 # number of replacements
system.l2cache.tags.tagsinuse 183.881600 # Cycle average of tags in use
system.l2cache.tags.tagsinuse 183.861903 # Cycle average of tags in use
system.l2cache.tags.total_refs 98 # Total number of references to valid blocks.
system.l2cache.tags.sampled_refs 380 # Sample count of references to valid blocks.
system.l2cache.tags.avg_refs 0.257895 # Average number of references to valid blocks.
system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.l2cache.tags.occ_blocks::cpu.inst 130.357827 # Average occupied blocks per requestor
system.l2cache.tags.occ_blocks::cpu.data 53.523773 # Average occupied blocks per requestor
system.l2cache.tags.occ_percent::cpu.inst 0.031826 # Average percentage of cache occupancy
system.l2cache.tags.occ_percent::cpu.data 0.013067 # Average percentage of cache occupancy
system.l2cache.tags.occ_percent::total 0.044893 # Average percentage of cache occupancy
system.l2cache.tags.occ_blocks::cpu.inst 130.345601 # Average occupied blocks per requestor
system.l2cache.tags.occ_blocks::cpu.data 53.516302 # Average occupied blocks per requestor
system.l2cache.tags.occ_percent::cpu.inst 0.031823 # Average percentage of cache occupancy
system.l2cache.tags.occ_percent::cpu.data 0.013066 # Average percentage of cache occupancy
system.l2cache.tags.occ_percent::total 0.044888 # Average percentage of cache occupancy
system.l2cache.tags.occ_task_id_blocks::1024 380 # Occupied blocks per task id
system.l2cache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id
system.l2cache.tags.age_task_id_blocks_1024::1 303 # Occupied blocks per task id
@ -585,15 +585,15 @@ system.l2cache.overall_misses::cpu.data 137 # nu
system.l2cache.overall_misses::total 430 # number of overall misses
system.l2cache.ReadExReq_miss_latency::cpu.data 5014000 # number of ReadExReq miss cycles
system.l2cache.ReadExReq_miss_latency::total 5014000 # number of ReadExReq miss cycles
system.l2cache.ReadSharedReq_miss_latency::cpu.inst 28701000 # number of ReadSharedReq miss cycles
system.l2cache.ReadSharedReq_miss_latency::cpu.inst 28661000 # number of ReadSharedReq miss cycles
system.l2cache.ReadSharedReq_miss_latency::cpu.data 8475000 # number of ReadSharedReq miss cycles
system.l2cache.ReadSharedReq_miss_latency::total 37176000 # number of ReadSharedReq miss cycles
system.l2cache.demand_miss_latency::cpu.inst 28701000 # number of demand (read+write) miss cycles
system.l2cache.ReadSharedReq_miss_latency::total 37136000 # number of ReadSharedReq miss cycles
system.l2cache.demand_miss_latency::cpu.inst 28661000 # number of demand (read+write) miss cycles
system.l2cache.demand_miss_latency::cpu.data 13489000 # number of demand (read+write) miss cycles
system.l2cache.demand_miss_latency::total 42190000 # number of demand (read+write) miss cycles
system.l2cache.overall_miss_latency::cpu.inst 28701000 # number of overall miss cycles
system.l2cache.demand_miss_latency::total 42150000 # number of demand (read+write) miss cycles
system.l2cache.overall_miss_latency::cpu.inst 28661000 # number of overall miss cycles
system.l2cache.overall_miss_latency::cpu.data 13489000 # number of overall miss cycles
system.l2cache.overall_miss_latency::total 42190000 # number of overall miss cycles
system.l2cache.overall_miss_latency::total 42150000 # number of overall miss cycles
system.l2cache.ReadExReq_accesses::cpu.data 50 # number of ReadExReq accesses(hits+misses)
system.l2cache.ReadExReq_accesses::total 50 # number of ReadExReq accesses(hits+misses)
system.l2cache.ReadSharedReq_accesses::cpu.inst 297 # number of ReadSharedReq accesses(hits+misses)
@ -618,15 +618,15 @@ system.l2cache.overall_miss_rate::cpu.data 1 #
system.l2cache.overall_miss_rate::total 0.990783 # miss rate for overall accesses
system.l2cache.ReadExReq_avg_miss_latency::cpu.data 100280 # average ReadExReq miss latency
system.l2cache.ReadExReq_avg_miss_latency::total 100280 # average ReadExReq miss latency
system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 97955.631399 # average ReadSharedReq miss latency
system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 97819.112628 # average ReadSharedReq miss latency
system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 97413.793103 # average ReadSharedReq miss latency
system.l2cache.ReadSharedReq_avg_miss_latency::total 97831.578947 # average ReadSharedReq miss latency
system.l2cache.demand_avg_miss_latency::cpu.inst 97955.631399 # average overall miss latency
system.l2cache.ReadSharedReq_avg_miss_latency::total 97726.315789 # average ReadSharedReq miss latency
system.l2cache.demand_avg_miss_latency::cpu.inst 97819.112628 # average overall miss latency
system.l2cache.demand_avg_miss_latency::cpu.data 98459.854015 # average overall miss latency
system.l2cache.demand_avg_miss_latency::total 98116.279070 # average overall miss latency
system.l2cache.overall_avg_miss_latency::cpu.inst 97955.631399 # average overall miss latency
system.l2cache.demand_avg_miss_latency::total 98023.255814 # average overall miss latency
system.l2cache.overall_avg_miss_latency::cpu.inst 97819.112628 # average overall miss latency
system.l2cache.overall_avg_miss_latency::cpu.data 98459.854015 # average overall miss latency
system.l2cache.overall_avg_miss_latency::total 98116.279070 # average overall miss latency
system.l2cache.overall_avg_miss_latency::total 98023.255814 # average overall miss latency
system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -648,15 +648,15 @@ system.l2cache.overall_mshr_misses::cpu.data 137
system.l2cache.overall_mshr_misses::total 430 # number of overall MSHR misses
system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4014000 # number of ReadExReq MSHR miss cycles
system.l2cache.ReadExReq_mshr_miss_latency::total 4014000 # number of ReadExReq MSHR miss cycles
system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 22841000 # number of ReadSharedReq MSHR miss cycles
system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 22801000 # number of ReadSharedReq MSHR miss cycles
system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6735000 # number of ReadSharedReq MSHR miss cycles
system.l2cache.ReadSharedReq_mshr_miss_latency::total 29576000 # number of ReadSharedReq MSHR miss cycles
system.l2cache.demand_mshr_miss_latency::cpu.inst 22841000 # number of demand (read+write) MSHR miss cycles
system.l2cache.ReadSharedReq_mshr_miss_latency::total 29536000 # number of ReadSharedReq MSHR miss cycles
system.l2cache.demand_mshr_miss_latency::cpu.inst 22801000 # number of demand (read+write) MSHR miss cycles
system.l2cache.demand_mshr_miss_latency::cpu.data 10749000 # number of demand (read+write) MSHR miss cycles
system.l2cache.demand_mshr_miss_latency::total 33590000 # number of demand (read+write) MSHR miss cycles
system.l2cache.overall_mshr_miss_latency::cpu.inst 22841000 # number of overall MSHR miss cycles
system.l2cache.demand_mshr_miss_latency::total 33550000 # number of demand (read+write) MSHR miss cycles
system.l2cache.overall_mshr_miss_latency::cpu.inst 22801000 # number of overall MSHR miss cycles
system.l2cache.overall_mshr_miss_latency::cpu.data 10749000 # number of overall MSHR miss cycles
system.l2cache.overall_mshr_miss_latency::total 33590000 # number of overall MSHR miss cycles
system.l2cache.overall_mshr_miss_latency::total 33550000 # number of overall MSHR miss cycles
system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.986532 # mshr miss rate for ReadSharedReq accesses
@ -670,15 +670,15 @@ system.l2cache.overall_mshr_miss_rate::cpu.data 1
system.l2cache.overall_mshr_miss_rate::total 0.990783 # mshr miss rate for overall accesses
system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80280 # average ReadExReq mshr miss latency
system.l2cache.ReadExReq_avg_mshr_miss_latency::total 80280 # average ReadExReq mshr miss latency
system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 77955.631399 # average ReadSharedReq mshr miss latency
system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 77819.112628 # average ReadSharedReq mshr miss latency
system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77413.793103 # average ReadSharedReq mshr miss latency
system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77831.578947 # average ReadSharedReq mshr miss latency
system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77955.631399 # average overall mshr miss latency
system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77726.315789 # average ReadSharedReq mshr miss latency
system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77819.112628 # average overall mshr miss latency
system.l2cache.demand_avg_mshr_miss_latency::cpu.data 78459.854015 # average overall mshr miss latency
system.l2cache.demand_avg_mshr_miss_latency::total 78116.279070 # average overall mshr miss latency
system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77955.631399 # average overall mshr miss latency
system.l2cache.demand_avg_mshr_miss_latency::total 78023.255814 # average overall mshr miss latency
system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77819.112628 # average overall mshr miss latency
system.l2cache.overall_avg_mshr_miss_latency::cpu.data 78459.854015 # average overall mshr miss latency
system.l2cache.overall_avg_mshr_miss_latency::total 78116.279070 # average overall mshr miss latency
system.l2cache.overall_avg_mshr_miss_latency::total 78023.255814 # average overall mshr miss latency
system.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.membus.trans_dist::ReadResp 380 # Transaction distribution
system.membus.trans_dist::ReadExReq 50 # Transaction distribution