Commit graph

278 commits

Author SHA1 Message Date
Kevin Lim
bc05f5982e Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/test-regress

--HG--
extra : convert_revision : d420ee86454b72b0e5d3a98bac3b496f172c1788
2006-12-12 17:55:50 -05:00
Kevin Lim
c7ad7b44eb Allow for multiple redirects to happen on a single cycle (only the one for the oldest instruction is passed on to commit).
This fixes a minor bug when multiple FU completions come back out of order (due to the order in which the FUs are freed up), and the oldest redirect isn't recorded properly.  The eon benchmark should run now.

src/cpu/o3/iew_impl.hh:
    Allow for multiple redirects to happen on a single cycle (only the one for the oldest instruction is passed on to commit).

--HG--
extra : convert_revision : b7d202dee1754539ed814f0fac59adb8c6328ee1
2006-12-12 17:35:46 -05:00
Steve Reinhardt
6c8c86f2f9 Rename the StaticInst-based (read|set)(Int|Float)Reg methods to (read|set)(Int|Float)RegOperand to distinguish from non-StaticInst version.
--HG--
extra : convert_revision : b33ce0ebe2fee86cc791c00a35d8c6e395e1380c
2006-12-12 09:58:40 -08:00
Kevin Lim
34924ce3b8 Fix up in case a req hasn't yet been generated for this instruction (if there was a fault prior to translation).
--HG--
extra : convert_revision : 43f4ea5e6a234cc6071006eab72135c11b8523c8
2006-12-11 23:51:21 -05:00
Kevin Lim
1868c9fd7f Fix for fetch to use the icache's block size to generate proper access size.
--HG--
extra : convert_revision : 0f292233ac05b584f527c32f80e3ca3d40a6a2c1
2006-12-11 23:47:30 -05:00
Gabe Black
97cdd5198b Compilation fixes
--HG--
extra : convert_revision : 974e91a960251a35d5ebb76c7e6c7ac330339896
2006-12-07 18:49:10 -05:00
Gabe Black
0f8fd5fd68 Fix for squashing during a serializing instruction.
--HG--
extra : convert_revision : 04f9131258bfb7cca1654e00273edb29bde2366b
2006-12-07 18:47:33 -05:00
Kevin Lim
b618e733bd Fix for MIPS_SE/m5.fast compile.
--HG--
extra : convert_revision : dbb893250974ac6db7b6c1ba67263fd35098ca43
2006-12-06 14:23:31 -05:00
Gabe Black
50b8cce355 Use the renamed register index, rather than the flattened one.
--HG--
extra : convert_revision : 599650c408667bb1b8db20a6847b9e697f7b49e4
2006-12-06 11:40:41 -05:00
Gabe Black
f04fcf58f1 Got rid of some typedefs and moved the tlbs into the base o3 cpu.
--HG--
extra : convert_revision : dcd1d2a64fd91aded15c8c763a78b4eebf421870
2006-12-06 11:39:49 -05:00
Gabe Black
07a4e2cd36 Use the setSyscallReturn defined in arch rather than duplicating it here.
--HG--
extra : convert_revision : 862ece59aa253b52b6744a0a76738d5ee19561b3
2006-12-06 11:38:39 -05:00
Gabe Black
ef942ceecb Moved the RegIdx arrays to the base dyninst.
--HG--
extra : convert_revision : d705cde25c2cf1add20669e99d086add49141518
2006-12-06 11:37:39 -05:00
Gabe Black
6826ee53db Got rid of some typedefs, moved the tlbs to the base o3 cpu, and called the architecture defined setSyscallReturn function instead of a duplicate copy.
src/cpu/o3/alpha/cpu.hh:
    Got rid of some typedefs, and moved the tlbs to the base o3 cpu.
src/cpu/o3/alpha/thread_context.hh:
src/cpu/o3/cpu.cc:
    Moved the tlbs to the base o3 cpu.

--HG--
extra : convert_revision : 1805613aa230b8974a226ee3d2584c85f7a578aa
2006-12-06 11:36:40 -05:00
Gabe Black
2dcf00bc8b Merge zizzer:/bk/newmem
into  zower.eecs.umich.edu:/eecshome/m5/newmem

src/cpu/o3/commit_impl.hh:
    Hand Merge

--HG--
extra : convert_revision : 6984db90d5b5ec71c31f1c345f5a77eed540059e
2006-12-06 06:05:28 -05:00
Gabe Black
be29adf51c Added a DPRINTF to print out the actual value pulled from memory.
--HG--
extra : convert_revision : 18780f753a7e98f8de3047dd6781b944b0826b4e
2006-12-06 06:02:13 -05:00
Gabe Black
75b93179ab Flattening and syscallReturn fixes
src/cpu/o3/thread_context_impl.hh:
    Use flattened indices
src/cpu/simple_thread.hh:
    Use flattened indices, and pass a thread context to setSyscallReturn rather than a register file.
src/cpu/thread_context.hh:
    The SyscallReturn class is no longer in arch/syscallreturn.hh

--HG--
extra : convert_revision : ed84bb8ac5ef0774526ecd0d7270b0c60cd3708e
2006-12-06 06:00:04 -05:00
Gabe Black
1886795368 Don't panic, but this needs to be fixed.
--HG--
extra : convert_revision : 7a4aed238d437dbb2cc5946b3045d53697070a27
2006-12-06 05:58:07 -05:00
Gabe Black
1d7d7df315 Make syscalls flatten their register indices, and also call into the ISA's setSyscallReturn function rather than having a duplicated one.
--HG--
extra : convert_revision : 1e83ef629a7fd143f2e35e68abaa56f81d6b9d9e
2006-12-06 05:56:34 -05:00
Gabe Black
156cf0db51 Change rename to rename the flattened register index instead of the architectural one.
--HG--
extra : convert_revision : 757866ad7a3c8be7382e1ffa71c60bc00c861f6f
2006-12-06 05:55:23 -05:00
Gabe Black
6456cb535c Added in endianness conversion on memory accesses as the data goes out. This will break the checker!
--HG--
extra : convert_revision : b8191cab09ab8f3ced05693293f058382319ed8e
2006-12-06 05:54:16 -05:00
Gabe Black
20340b5e26 Change how optional delay slot instructions are detected and squashed.
--HG--
extra : convert_revision : ffd019d4adc2fbbc0a663d8dc6ef73edce12511b
2006-12-06 05:51:18 -05:00
Gabe Black
8a21635eff Get rid of some typedefs which were hardly used, and move some stuff back here that shouldn't be in the architecture specific DynInst classes.
--HG--
extra : convert_revision : dad0d7191acf773c16dc3ed9dd911f5e8bfc08b3
2006-12-06 05:48:59 -05:00
Kevin Lim
c0f21b09c8 Fixes for MIPS_SE compiling. Regressions seem to work, but Korey should make sure these changes (commit especially) work okay.
src/cpu/o3/commit_impl.hh:
src/cpu/o3/fetch_impl.hh:
    Fixes for MIPS_SE compile.

--HG--
extra : convert_revision : fde9616f8e72b397c5ca965774172372cff53790
2006-12-02 13:33:46 -05:00
Gabe Black
5bdf4400b2 Merge zizzer:/bk/sparcfs
into  zower.eecs.umich.edu:/eecshome/m5/newmemmid

src/arch/sparc/isa_traits.hh:
src/arch/sparc/miscregfile.hh:
    hand merge

--HG--
extra : convert_revision : 34f50dc5e6e22096cb2c08b5888f2b0fcd418f3e
2006-11-29 17:34:20 -05:00
Kevin Lim
c96160cef5 Change the connecting of the physPort and virtPort to the memory object below the CPU to happen every time activateContext is called. The overhead is probably a little higher than necessary, but allows these connections to properly be made when there are CPUs that are inactive until they are switched in.
Right now this introduces a minor memory leak as old physPorts and virtPorts are not deleted when new ones are created.  A flyspray task has been created for this issue.  It can not be resolved until we determine how the bus will handle giving out ID's to functional ports that may be deleted.

src/cpu/o3/cpu.cc:
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
    Change the setup of the physPort and virtPort to instead happen every time the CPU has a context activated.  This is a little high overhead, but keeps it working correctly when the CPU does not have a physical memory attached to it until it switches in (like the case of switch CPUs).
src/cpu/o3/thread_context.hh:
    Change function from being called at init() to just being called whenever the memory ports need to be connected.
src/cpu/o3/thread_context_impl.hh:
    Update this to not delete the port if it's the same as the virtPort.
src/cpu/thread_context.hh:
    Change function from being called at init() to whenever the memory ports need to be connected.
src/cpu/thread_state.cc:
    Instead of initializing the ports, simply connect them, deleting any old ports that might exist.  This allows these functions to be called multiple times.
src/cpu/thread_state.hh:
    Ports are no longer initialized, but rather connected at context activation time.

--HG--
extra : convert_revision : e399ce5dfbd6ad658c953a7c9c7b69b89a70219e
2006-11-29 16:07:55 -05:00
Gabe Black
f2daf210f1 Initial changes to get O3 working with SPARC
src/arch/sparc/process.cc:
    MachineBytes doesn't exist any more.
src/arch/sparc/regfile.cc:
    Add in the miscRegFile for good measure.
src/cpu/o3/isa_specific.hh:
    Add in a section for SPARC
src/cpu/o3/sparc/cpu.cc:
src/cpu/o3/sparc/cpu.hh:
src/cpu/o3/sparc/cpu_builder.cc:
src/cpu/o3/sparc/cpu_impl.hh:
src/cpu/o3/sparc/dyn_inst.cc:
src/cpu/o3/sparc/dyn_inst.hh:
src/cpu/o3/sparc/dyn_inst_impl.hh:
src/cpu/o3/sparc/impl.hh:
src/cpu/o3/sparc/params.hh:
src/cpu/o3/sparc/thread_context.cc:
src/cpu/o3/sparc/thread_context.hh:
    Sparc version of this file.

--HG--
extra : convert_revision : 34bb5218f802d0a1328132a518cdd769fb59b6a4
2006-11-24 22:06:33 -05:00
Kevin Lim
a2113fd3dc Update Virtual and Physical ports.
src/cpu/o3/alpha/cpu_impl.hh:
    Handle the PhysicalPort and VirtualPort in the ThreadState.
src/cpu/o3/cpu.cc:
    Initialize the thread context.
src/cpu/o3/thread_context.hh:
    Add new function to initialize thread context.
src/cpu/o3/thread_context_impl.hh:
    Use code now put into function.
src/cpu/simple_thread.cc:
    Move code to ThreadState and use the new helper function.
src/cpu/simple_thread.hh:
    Remove init() in this derived class; use init() from ThreadState base class.
src/cpu/thread_state.cc:
    Move setting up of Physical and Virtual ports here.  Change getMemFuncPort() to connectToMemFunc(), which connects a port to a functional port of the memory object below the CPU.
src/cpu/thread_state.hh:
    Update functions.

--HG--
extra : convert_revision : ff254715ef0b259dc80d08f13543b63e4024ca8d
2006-11-19 17:43:03 -05:00
Ron Dreslinski
7babf6b3a8 Make cpu's capable of having a phase shift
--HG--
extra : convert_revision : 7f082ba5c1cd2445aec731950c31a877aac23a75
2006-11-14 01:10:36 -05:00
Ron Dreslinski
a962fc4f56 Make CPU models signal to update the snoop ranges
--HG--
extra : convert_revision : 717b62510f28a69af99453309fbbb458359eeb2a
2006-11-13 18:51:16 -05:00
Kevin Lim
41a9196f60 More interrupt reworking.
--HG--
extra : convert_revision : 40dfbb72c4e418c54e909c54dad5fe6ef7017cb4
2006-11-13 02:49:03 -05:00
Kevin Lim
4c21fab575 Change warn to DPRINTF.
--HG--
extra : convert_revision : 746bdf92334d220158eb0eb6bf113b4dcedbb354
2006-11-13 00:26:38 -05:00
Kevin Lim
8a0cbbe27b Fix for regression failure.
src/cpu/o3/fetch_impl.hh:
    Fetch needs to make sure it isn't waiting on an Icache access.

--HG--
extra : convert_revision : b53eb58b9e5a00bdb394134586d1f84f84d1c6e1
2006-11-12 23:30:09 -05:00
Kevin Lim
3052632b68 Merge ktlim@zamp:./local/clean/tmp/test-regress
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-busfix

--HG--
extra : convert_revision : b98236507bb8996ce605b48b5a5a6a7aac297dc5
2006-11-12 21:57:58 -05:00
Kevin Lim
437436a2f7 Fix for non-FS compile.
--HG--
extra : convert_revision : 661b412b0ae670181b89cb7dbc5e9d813804aa7a
2006-11-12 21:49:51 -05:00
Kevin Lim
12e26c68c3 Updates to support new interrupt processing and removal of PcPAL.
src/arch/alpha/interrupts.hh:
    No need for this now that the ThreadContext is being used to set these IPRs in interrupts.
    Also split up the interrupt checking from the updating of the IPL and interrupt summary.
src/arch/alpha/tlb.cc:
    Check the PC for whether or not it's in PAL mode, not the addr.
src/cpu/o3/alpha/cpu.hh:
    Split up getting the interrupt from actually processing the interrupt.
src/cpu/o3/alpha/cpu_impl.hh:
    Splut up the processing of interrupts.
src/cpu/o3/commit_impl.hh:
    Update for ISA-oriented interrupt changes.
src/cpu/o3/fetch_impl.hh:
    Fix broken if statement from PcPAL updates, and properly populate the request fields.

    Also more debugging output.
src/cpu/ozone/cpu_impl.hh:
    Updates for ISA-oriented interrupt stuff.
src/cpu/ozone/front_end_impl.hh:
    Populate request fields properly.
src/cpu/simple/base.cc:
    Update for interrupt stuff.

--HG--
extra : convert_revision : 9bac3f9ffed4948ee788699b2fa8419bc1ca647c
2006-11-12 20:15:30 -05:00
Nathan Binkert
b16e559177 Get rid of the ParamContext for pseudo instructions and move
the parameters to the BaseCPU object.

--HG--
extra : convert_revision : 557292cffb40918133647b0c9ac653ee5112df2e
2006-11-11 17:22:10 -08:00
Gabe Black
cc77304676 The Lock_Flag_DepTag went away earlier, and using TheISA gives the false impression that this code is ISA independent.
--HG--
extra : convert_revision : 67d9e51702efbe5f5244268e3753328a6cf1a1d5
2006-11-11 07:16:24 -05:00
Kevin Lim
b5e68fb546 Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem

--HG--
extra : convert_revision : 0c2db1e1b5fdb91c1ac5705ab872a6bfb575a67a
2006-11-10 12:44:15 -05:00
Kevin Lim
f593c8a8e2 Change up some warnings to DPRINTFs.
--HG--
extra : convert_revision : b3e9fa094d68f608865dedfc9f3f4125a20fd748
2006-11-10 12:25:08 -05:00
Kevin Lim
6591ebb098 Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-busfix

--HG--
extra : convert_revision : dafe2d4a032b277c219ea13faf20567c20c1f2f4
2006-11-09 15:06:00 -05:00
Kevin Lim
0b0d5a282a Draining fixes.
src/cpu/o3/cpu.cc:
    Handle draining properly when CPU isn't actually being used.
src/cpu/simple/atomic.cc:
    Be sure to set status properly when draining.
src/mem/bus.cc:
    Fix for draining.

--HG--
extra : convert_revision : d9796e6693e974f022159029fc9743c49a970c8f
2006-11-09 11:33:44 -05:00
Gabe Black
f720029e97 Merge zizzer.eecs.umich.edu:/bk/newmem/
into  zeep.eecs.umich.edu:/home/gblack/m5/newmemmemops

--HG--
extra : convert_revision : dc165840841bdd88e40111b98d1be493441703f0
2006-11-08 16:18:10 -05:00
Gabe Black
67b9a2ebd8 Move the check to see if you're in user mode into the isa directory.
--HG--
extra : convert_revision : b5b7cdf4a5e5e54228c592093516bf18d0f7dbe6
2006-11-08 13:55:48 -05:00
Gabe Black
c693c6ba9f Put kernel_stats back into arch.
--HG--
rename : src/kern/alpha/idle_event.cc => src/arch/alpha/idle_event.cc
rename : src/kern/alpha/idle_event.hh => src/arch/alpha/idle_event.hh
rename : src/kern/alpha/kernel_stats.cc => src/arch/alpha/kernel_stats.cc
rename : src/kern/alpha/kernel_stats.hh => src/arch/alpha/kernel_stats.hh
rename : src/kern/sparc/kernel_stats.hh => src/arch/sparc/kernel_stats.hh
rename : src/kern/base_kernel_stats.cc => src/kern/kernel_stats.cc
rename : src/kern/base_kernel_stats.hh => src/kern/kernel_stats.hh
extra : convert_revision : 42bd3e36b407edbd19b912c9218f4e5923a15966
2006-11-07 22:34:34 -05:00
Kevin Lim
d9f159a3b9 Initialize mem dep unit properly.
src/cpu/o3/mem_dep_unit_impl.hh:
    Initialize mem dep unit properly, add debug output.

--HG--
extra : convert_revision : 3c56dedfa57de1edc4b1c8f8d9bc94e18002eff2
2006-11-07 13:53:06 -05:00
Gabe Black
3826b6927c Got rid of a stray blank line.
--HG--
extra : convert_revision : 7b58f75e5efc3c9ead2434f87605cbabcb23d90a
2006-11-07 05:41:51 -05:00
Gabe Black
4bfb8547bb Moved the switched version of kernel_stats.hh back to kern, and moved the base kernel_stats to base_kernel_stats
--HG--
extra : convert_revision : 2a010d2eb7ea2586ff063b99b8bcde6eb1e8e017
2006-11-07 05:36:54 -05:00
Gabe Black
02abca6b9e Merge zizzer.eecs.umich.edu:/bk/newmem/
into  zeep.eecs.umich.edu:/home/gblack/m5/newmemmemops

src/SConscript:
    SCCS merged

--HG--
extra : convert_revision : f130c8a2d33f58d857e5d5a02bb9698c1bceb23b
2006-11-06 19:52:32 -05:00
Gabe Black
85a6079db7 Remote GDB support has been changed to use inheritance. Alpha should work, but isn't tested. Other architectures will not.
--HG--
extra : convert_revision : fc7e1e73e2f3b1a4ab9905a1eb98c5f07c6c8707
2006-11-06 18:29:58 -05:00
Kevin Lim
067c9c5531 Initialize pointer to NULL.
src/cpu/o3/lsq_unit_impl.hh:
    Be sure to initialize pointer to NULL.

--HG--
extra : convert_revision : 917d5119e4bd8eae10959ed07069d8c694315c7a
2006-11-05 20:29:38 -05:00
Gabe Black
118b9dc1f9 Got rid of "inPalMode". Some places are still effectively checking if they are in PAL mode, however.
--HG--
extra : convert_revision : b52d9642efc474eaf97437fa2df879efefa0062b
2006-11-03 04:25:33 -05:00
Gabe Black
c8fc116c76 Add a new file which describes an ISA's interrupt handling mechanism. It records when interrupts are requested, and returns an interrupt to execute if the
--HG--
extra : convert_revision : c535000a6a170caefd441687b60f940513d29739
2006-11-03 02:25:39 -05:00
Kevin Lim
e71ccde663 Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-busfix

--HG--
extra : convert_revision : a9a41e2c292bd95aa148e1cf4d9a77c0622a462b
2006-11-02 15:20:47 -05:00
Kevin Lim
ccaf80cc46 Use ISA specific makeExtMI.
src/arch/alpha/utility.hh:
    For now makeExtMI will be specific to the ISA.

--HG--
extra : convert_revision : 89959c6499efcc3df9301ad8ea039580764a1496
2006-11-02 13:11:38 -05:00
Gabe Black
b565660c42 Merge zizzer.eecs.umich.edu:/bk/newmem/
into  zeep.eecs.umich.edu:/home/gblack/m5/newmemmemops

--HG--
extra : convert_revision : c2f7398a0d14dd11108579bb243ada7420285a22
2006-11-01 19:00:59 -05:00
Gabe Black
2b11b47357 Adjustments for the AlphaTLB changing to AlphaISA::TLB and changing register file functions to not take faults
--HG--
extra : convert_revision : 1cef0734462ee2e4db12482462c2ab3c134d3675
2006-11-01 16:44:45 -05:00
Kevin Lim
bfd5eb2b08 Remove mem parameter. Now the translating port asks the CPU's dcache's peer for its MemObject instead of having to have a paramter for the MemObject.
configs/example/fs.py:
configs/example/se.py:
src/cpu/simple/base.cc:
src/cpu/simple/base.hh:
src/cpu/simple/timing.cc:
src/cpu/simple_thread.cc:
src/cpu/simple_thread.hh:
src/cpu/thread_state.cc:
src/cpu/thread_state.hh:
tests/configs/o3-timing-mp.py:
tests/configs/o3-timing.py:
tests/configs/simple-atomic-mp.py:
tests/configs/simple-atomic.py:
tests/configs/simple-timing-mp.py:
tests/configs/simple-timing.py:
tests/configs/tsunami-simple-atomic-dual.py:
tests/configs/tsunami-simple-atomic.py:
tests/configs/tsunami-simple-timing-dual.py:
tests/configs/tsunami-simple-timing.py:
    No need for mem parameter any more.
src/cpu/checker/cpu.cc:
    Use new constructor for simple thread (no more MemObject parameter).
src/cpu/checker/cpu.hh:
    Remove MemObject parameter.
src/cpu/memtest/memtest.hh:
    Ports now take in their MemObject owner.
src/cpu/o3/alpha/cpu_builder.cc:
    Remove mem parameter.
src/cpu/o3/alpha/cpu_impl.hh:
    Remove memory parameter and clean up handling of TranslatingPort.
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/mips/cpu_builder.cc:
src/cpu/o3/mips/cpu_impl.hh:
src/cpu/o3/params.hh:
src/cpu/o3/thread_state.hh:
src/cpu/ozone/cpu.hh:
src/cpu/ozone/cpu_builder.cc:
src/cpu/ozone/cpu_impl.hh:
src/cpu/ozone/front_end.hh:
src/cpu/ozone/front_end_impl.hh:
src/cpu/ozone/lw_lsq.hh:
src/cpu/ozone/lw_lsq_impl.hh:
src/cpu/ozone/simple_params.hh:
src/cpu/ozone/thread_state.hh:
src/cpu/simple/atomic.cc:
    Remove memory parameter.

--HG--
extra : convert_revision : 43cb44a33b31320d44b69679dcf646c0380d07d3
2006-10-31 14:33:56 -05:00
Gabe Black
3c19c5f0f2 Missed a few instances of this function.
--HG--
extra : convert_revision : 581f97dafc2b30bd5067f6ff7f9cdbabc6890622
2006-10-31 04:12:52 -05:00
Gabe Black
038217049a Move IntrFlag into the MiscRegFile and get rid of specialized accessor functions.
--HG--
extra : convert_revision : e0d12a150b01d05de9bc02bcbc7c22797975a5b9
2006-10-31 03:37:01 -05:00
Kevin Lim
ce4531c079 Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem

--HG--
extra : convert_revision : 161c35ade82f2471e605d948dca56cfa216693fd
2006-10-23 14:32:35 -04:00
Kevin Lim
4ccccfef71 Fix fetch to stop fetching upon encountering a fault in SE mode. Also change warning to a DPRINTF.
--HG--
extra : convert_revision : 819bade049d7ffd97d316051c99146ece5e3a651
2006-10-23 14:10:37 -04:00
Kevin Lim
1926faac06 Add in support for LL/SC in the O3 CPU. Needs to be fully tested.
src/cpu/base_dyn_inst.hh:
    Extend BaseDynInst a little bit so it can be use as a TC as well (specifically for ll/sc code).
src/cpu/base_dyn_inst_impl.hh:
    Add variable to track if the result of the instruction should be recorded.
src/cpu/o3/alpha/cpu_impl.hh:
    Clear lock flag upon hwrei.
src/cpu/o3/lsq_unit.hh:
    Use ISA specified handling of locked reads.
src/cpu/o3/lsq_unit_impl.hh:
    Use ISA specified handling of locked writes.

--HG--
extra : convert_revision : 1f5c789c35deb4b016573c02af4aab60d726c0e5
2006-10-23 14:00:07 -04:00
Gabe Black
0b5cf4ba6e Merge zizzer.eecs.umich.edu:/bk/newmem
into  zeep.eecs.umich.edu:/home/gblack/m5/newmem

--HG--
extra : convert_revision : 2711fec2bf72801999b060e65f0bf744c18734fb
2006-10-20 16:39:47 -04:00
Nathan Binkert
a4c6f0d69e Use PacketPtr everywhere
--HG--
extra : convert_revision : d9eb83ab77ffd2d725961f295b1733137e187711
2006-10-20 00:10:12 -07:00
Nathan Binkert
7245d4530d refactor code for the packet, get rid of packet_impl.hh
and call it packet_access.hh and fix the #includes so
things compile right.

--HG--
extra : convert_revision : d3626c9715b9f7e51bb3ab8d97e971fad4e0b724
2006-10-19 23:38:45 -07:00
Ron Dreslinski
210e73f2a2 Small changes:
?? doesn't compile in warn statements
Should have been false, where I had a true.

src/cpu/o3/lsq_impl.hh:
    Apparently you can't have ?? in a warn statement (Something about trigraphs)
src/mem/cache/cache_impl.hh:
    Forgot to signal atomic mode in snoopProbe

--HG--
extra : convert_revision : c75cb76e193e852284564993440c8ea39e6de426
2006-10-19 20:18:17 -04:00
Ron Dreslinski
9cf063eb8e Merge zizzer:/bk/newmem
into  zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest

--HG--
extra : convert_revision : c6611b32537918f5bf183788227ddf69a9a9a069
2006-10-19 19:00:43 -04:00
Lisa Hsu
c2c48645c9 only do this assert after you know you're not switched out or idle.
--HG--
extra : convert_revision : 0cd0d31db44fe7e8e44bde90e1756873faca422f
2006-10-18 17:59:11 -04:00
Ron Dreslinski
9c582c7e14 Fixes for uni-coherence in timing mode for FS.
Still a bug in atomic uni-coherence in FS.

src/cpu/o3/fetch_impl.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
    Make CPU models handle coherence requests
src/mem/cache/base_cache.cc:
    Properly signal coherence CSHRs
src/mem/cache/coherence/uni_coherence.cc:
    Only deallocate once

--HG--
extra : convert_revision : c4533de421c371c5532ee505e3ecd451511f5c99
2006-10-17 18:50:19 -04:00
Gabe Black
519d11bab3 Merge zizzer.eecs.umich.edu:/bk/newmem
into  zeep.eecs.umich.edu:/home/gblack/m5/newmem

--HG--
extra : convert_revision : 898976bbd322e55bc234035456df8090c6dcf72d
2006-10-16 15:56:53 -04:00
Kevin Lim
a50e83c134 Fix assertion. I haven't tested it fully (I can't reproduce Lisa's error) but I believe it should fix what she's running into (which was definitely a bug).
src/cpu/o3/fetch_impl.hh:
    Move assertion to area where it should really always be true.  Sometimes you might recvRetry and not necessarily be blocked (if there was a squash).

--HG--
extra : convert_revision : 76ad35357e7f4c44fa544ffed071096a62053018
2006-10-13 17:35:23 -04:00
Gabe Black
866cfaf9dc Merge zizzer.eecs.umich.edu:/bk/newmem
into  zeep.eecs.umich.edu:/home/gblack/m5/newmem

--HG--
extra : convert_revision : 30b2475ba034550376455e1bc0e52e19a200fd5a
2006-10-12 10:58:45 -04:00
Kevin Lim
bdde892d66 Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem

src/cpu/memtest/memtest.cc:
src/cpu/memtest/memtest.hh:
src/cpu/simple/timing.hh:
tests/configs/o3-timing-mp.py:
    Hand merge.

--HG--
extra : convert_revision : a58cc439eb5e8f900d175ed8b5a85b6c8723e558
2006-10-09 22:59:56 -04:00
Kevin Lim
a9ae6c8656 Comment out code that messed up SMT (but will be needed eventually).
src/cpu/o3/cpu.cc:
    Comment out reseting CPU structures for now.  This can be updated to work in the future.

--HG--
extra : convert_revision : bc1a86e2fe47da5acb14ba8b64568b0355431f1c
2006-10-09 22:49:58 -04:00
Kevin Lim
92bf23bed6 Be sure to delete packet and sender state if the cache is blocked.
src/cpu/o3/lsq_unit.hh:
    Be sure to delete data if the cache is blocked.

--HG--
extra : convert_revision : fafbcfb8937e85555823942e69e798e557a600e5
2006-10-09 19:14:14 -04:00
Kevin Lim
af7315c7dc Fix caches plus sampling switch over.
src/cpu/o3/cpu.cc:
    Fix up caches plus sampling switch over.

--HG--
extra : convert_revision : 49d0c16d4c5e8d5ba83749d568a4efe3b42e3a97
2006-10-09 19:13:06 -04:00
Kevin Lim
d95b23b81f Fix outstanding bug (FS#158).
src/cpu/o3/cpu.cc:
    Extra debugging, fix a bug brought up on bug tracker.

--HG--
extra : convert_revision : 23f8b166ba0d0af54e15b651ed28f59a1bc9d2f2
2006-10-09 11:01:19 -04:00
Ron Dreslinski
bc732b59fd Have cpus send snoop ranges
--HG--
extra : convert_revision : 2a1fba141e409ee1d7a0b69b5b21d236e3d4ce68
2006-10-09 01:04:37 -04:00
Ron Dreslinski
5cb1840b31 Fixes for functional path.
If the cpu needs to update any state when it gets a functional write (LSQ??)
then that code needs to be written.

src/cpu/o3/fetch_impl.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/ozone/front_end_impl.hh:
src/cpu/ozone/lw_lsq_impl.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
    CPU's can recieve functional accesses, they need to determine if they need to do anything with them.
src/mem/bus.cc:
src/mem/bus.hh:
    Make the fuctional path do the correct tye of snoop

--HG--
extra : convert_revision : 70d09f954b907a8aa9b8137579cd2b06e02ae2ff
2006-10-08 20:30:42 -04:00
Steve Reinhardt
5df93cc1cd Replace tests of LOCKED/UNCACHEABLE flags with isLocked()/isUncacheable().
--HG--
extra : convert_revision : f22ce3221d270ecf8631d3dcaed05753accd5461
2006-10-08 14:48:24 -07:00
Kevin Lim
d48ea81ba2 Updates to O3 CPU. It should now work in FS mode, although sampling still has a bug.
src/cpu/o3/commit_impl.hh:
    Fixes for compile and sampling.
src/cpu/o3/cpu.cc:
    Deallocate and activate threads properly.  Also hopefully fix being able to use caches while switching over.
src/cpu/o3/cpu.hh:
    Fixes for deallocating and activating threads.
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/lsq_unit.hh:
    Handle getting back a BadAddress result from the access.
src/cpu/o3/iew_impl.hh:
    More debug output.
src/cpu/o3/lsq_unit_impl.hh:
    Fixup store conditional handling (still a bit of a hack, but works now).

    Also handle getting back a BadAddress result from the access.
src/cpu/o3/thread_context_impl.hh:
    Deallocate context now records if the context should be fully removed.

--HG--
extra : convert_revision : 55f81660602d0e25367ce1f5b0b9cfc62abe7bf9
2006-10-08 00:53:41 -04:00
Gabe Black
e8ced44aea Merge zizzer.eecs.umich.edu:/bk/newmem
into  zeep.eecs.umich.edu:/home/gblack/m5/newmem

src/cpu/ozone/cpu_impl.hh:
    Hand merged

--HG--
extra : convert_revision : f8a5b0205bcb78c8f5e109f456fe7bca80a7abac
2006-10-02 14:32:02 -04:00
Kevin Lim
568fa11084 Updates to fix merge issues and bring almost everything up to working speed. Ozone CPU remains untested, but everything else compiles and runs.
src/arch/alpha/isa_traits.hh:
    This got changed to the wrong version by accident.
src/cpu/base.cc:
    Fix up progress event to not schedule itself if the interval is set to 0.
src/cpu/base.hh:
    Fix up the CPU Progress Event to not print itself if it's set to 0.  Also remove stats_reset_inst (something I added to m5 but isn't necessary here).
src/cpu/base_dyn_inst.hh:
src/cpu/checker/cpu.hh:
    Remove float variable of instResult; it's always held within the double part now.
src/cpu/checker/cpu_impl.hh:
    Use thread and not cpuXC.
src/cpu/o3/alpha/cpu_builder.cc:
src/cpu/o3/checker_builder.cc:
src/cpu/ozone/checker_builder.cc:
src/cpu/ozone/cpu_builder.cc:
src/python/m5/objects/BaseCPU.py:
    Remove stats_reset_inst.
src/cpu/o3/commit_impl.hh:
src/cpu/ozone/lw_back_end_impl.hh:
    Get TC, not XCProxy.
src/cpu/o3/cpu.cc:
    Switch out updates from the version of m5 I have.  Also remove serialize code that got added twice.
src/cpu/o3/iew_impl.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/thread_state.hh:
    Remove code that was added twice.
src/cpu/o3/lsq_unit.hh:
    Add back in stats that got lost in the merge.
src/cpu/o3/lsq_unit_impl.hh:
    Use proper method to get flags.  Also wake CPU if we're coming back from a cache miss.
src/cpu/o3/thread_context_impl.hh:
src/cpu/o3/thread_state.hh:
    Support profiling.
src/cpu/ozone/cpu.hh:
    Update to use proper typename.
src/cpu/ozone/cpu_impl.hh:
src/cpu/ozone/dyn_inst_impl.hh:
    Updates for newmem.
src/cpu/ozone/lw_lsq_impl.hh:
    Get flags correctly.
src/cpu/ozone/thread_state.hh:
    Reorder constructor initialization, use tc.
src/sim/pseudo_inst.cc:
    Allow for loading of symbol file.  Be sure to use ThreadContext and not ExecContext.

--HG--
extra : convert_revision : c5657f84155807475ab4a1e20d944bb6f0d79d94
2006-10-02 11:58:09 -04:00
Kevin Lim
4ed184eade Merge ktlim@zamp:./local/clean/o3-merge/m5
into  zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem

configs/boot/micro_memlat.rcS:
configs/boot/micro_tlblat.rcS:
src/arch/alpha/ev5.cc:
src/arch/alpha/isa/decoder.isa:
src/arch/alpha/isa_traits.hh:
src/cpu/base.cc:
src/cpu/base.hh:
src/cpu/base_dyn_inst.hh:
src/cpu/checker/cpu.hh:
src/cpu/checker/cpu_impl.hh:
src/cpu/o3/alpha/cpu_impl.hh:
src/cpu/o3/alpha/params.hh:
src/cpu/o3/checker_builder.cc:
src/cpu/o3/commit_impl.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/iew.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue.hh:
src/cpu/o3/lsq.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/o3/lsq_unit.hh:
src/cpu/o3/lsq_unit_impl.hh:
src/cpu/o3/regfile.hh:
src/cpu/o3/rename_impl.hh:
src/cpu/o3/thread_state.hh:
src/cpu/ozone/checker_builder.cc:
src/cpu/ozone/cpu.hh:
src/cpu/ozone/cpu_impl.hh:
src/cpu/ozone/front_end.hh:
src/cpu/ozone/front_end_impl.hh:
src/cpu/ozone/lw_back_end.hh:
src/cpu/ozone/lw_back_end_impl.hh:
src/cpu/ozone/lw_lsq.hh:
src/cpu/ozone/lw_lsq_impl.hh:
src/cpu/ozone/thread_state.hh:
src/cpu/simple/base.cc:
src/cpu/simple_thread.cc:
src/cpu/simple_thread.hh:
src/cpu/thread_state.hh:
src/dev/ide_disk.cc:
src/python/m5/objects/O3CPU.py:
src/python/m5/objects/Root.py:
src/python/m5/objects/System.py:
src/sim/pseudo_inst.cc:
src/sim/pseudo_inst.hh:
src/sim/system.hh:
util/m5/m5.c:
    Hand merge.

--HG--
rename : arch/alpha/ev5.cc => src/arch/alpha/ev5.cc
rename : arch/alpha/freebsd/system.cc => src/arch/alpha/freebsd/system.cc
rename : arch/alpha/isa/decoder.isa => src/arch/alpha/isa/decoder.isa
rename : arch/alpha/isa/mem.isa => src/arch/alpha/isa/mem.isa
rename : arch/alpha/isa_traits.hh => src/arch/alpha/isa_traits.hh
rename : arch/alpha/linux/system.cc => src/arch/alpha/linux/system.cc
rename : arch/alpha/system.cc => src/arch/alpha/system.cc
rename : arch/alpha/tru64/system.cc => src/arch/alpha/tru64/system.cc
rename : cpu/base.cc => src/cpu/base.cc
rename : cpu/base.hh => src/cpu/base.hh
rename : cpu/base_dyn_inst.hh => src/cpu/base_dyn_inst.hh
rename : cpu/checker/cpu.hh => src/cpu/checker/cpu.hh
rename : cpu/checker/cpu.cc => src/cpu/checker/cpu_impl.hh
rename : cpu/o3/alpha_cpu_builder.cc => src/cpu/o3/alpha/cpu_builder.cc
rename : cpu/checker/o3_cpu_builder.cc => src/cpu/o3/checker_builder.cc
rename : cpu/o3/commit_impl.hh => src/cpu/o3/commit_impl.hh
rename : cpu/o3/cpu.cc => src/cpu/o3/cpu.cc
rename : cpu/o3/fetch_impl.hh => src/cpu/o3/fetch_impl.hh
rename : cpu/o3/iew.hh => src/cpu/o3/iew.hh
rename : cpu/o3/iew_impl.hh => src/cpu/o3/iew_impl.hh
rename : cpu/o3/inst_queue.hh => src/cpu/o3/inst_queue.hh
rename : cpu/o3/inst_queue_impl.hh => src/cpu/o3/inst_queue_impl.hh
rename : cpu/o3/lsq_impl.hh => src/cpu/o3/lsq_impl.hh
rename : cpu/o3/lsq_unit.hh => src/cpu/o3/lsq_unit.hh
rename : cpu/o3/lsq_unit_impl.hh => src/cpu/o3/lsq_unit_impl.hh
rename : cpu/o3/mem_dep_unit_impl.hh => src/cpu/o3/mem_dep_unit_impl.hh
rename : cpu/o3/rename.hh => src/cpu/o3/rename.hh
rename : cpu/o3/rename_impl.hh => src/cpu/o3/rename_impl.hh
rename : cpu/o3/thread_state.hh => src/cpu/o3/thread_state.hh
rename : cpu/o3/tournament_pred.cc => src/cpu/o3/tournament_pred.cc
rename : cpu/o3/tournament_pred.hh => src/cpu/o3/tournament_pred.hh
rename : cpu/checker/cpu_builder.cc => src/cpu/ozone/checker_builder.cc
rename : cpu/ozone/cpu.hh => src/cpu/ozone/cpu.hh
rename : cpu/ozone/cpu_builder.cc => src/cpu/ozone/cpu_builder.cc
rename : cpu/ozone/cpu_impl.hh => src/cpu/ozone/cpu_impl.hh
rename : cpu/ozone/front_end.hh => src/cpu/ozone/front_end.hh
rename : cpu/ozone/front_end_impl.hh => src/cpu/ozone/front_end_impl.hh
rename : cpu/ozone/inorder_back_end_impl.hh => src/cpu/ozone/inorder_back_end_impl.hh
rename : cpu/ozone/inst_queue_impl.hh => src/cpu/ozone/inst_queue_impl.hh
rename : cpu/ozone/lw_back_end.hh => src/cpu/ozone/lw_back_end.hh
rename : cpu/ozone/lw_back_end_impl.hh => src/cpu/ozone/lw_back_end_impl.hh
rename : cpu/ozone/lw_lsq.hh => src/cpu/ozone/lw_lsq.hh
rename : cpu/ozone/lw_lsq_impl.hh => src/cpu/ozone/lw_lsq_impl.hh
rename : cpu/ozone/simple_params.hh => src/cpu/ozone/simple_params.hh
rename : cpu/ozone/thread_state.hh => src/cpu/ozone/thread_state.hh
rename : cpu/simple/cpu.cc => src/cpu/simple/base.cc
rename : cpu/cpu_exec_context.cc => src/cpu/simple_thread.cc
rename : cpu/thread_state.hh => src/cpu/thread_state.hh
rename : dev/ide_disk.hh => src/dev/ide_disk.hh
rename : python/m5/objects/BaseCPU.py => src/python/m5/objects/BaseCPU.py
rename : python/m5/objects/AlphaFullCPU.py => src/python/m5/objects/O3CPU.py
rename : python/m5/objects/OzoneCPU.py => src/python/m5/objects/OzoneCPU.py
rename : python/m5/objects/Root.py => src/python/m5/objects/Root.py
rename : python/m5/objects/System.py => src/python/m5/objects/System.py
rename : sim/eventq.hh => src/sim/eventq.hh
rename : sim/pseudo_inst.cc => src/sim/pseudo_inst.cc
rename : sim/pseudo_inst.hh => src/sim/pseudo_inst.hh
rename : sim/serialize.cc => src/sim/serialize.cc
rename : sim/stat_control.cc => src/sim/stat_control.cc
rename : sim/stat_control.hh => src/sim/stat_control.hh
rename : sim/system.hh => src/sim/system.hh
extra : convert_revision : 135d90e43f6cea89f9460ba4e23f4b0b85886e7d
2006-09-30 23:43:23 -04:00
Gabe Black
76708a9a6c Changed makeExtMI to take a ThreadContext instead of a pc.
--HG--
extra : convert_revision : e5b200e4e053702fc703f44149d18ce48ac4eaa6
2006-09-30 02:55:21 -04:00
Gabe Black
8abab05c83 Merge zizzer.eecs.umich.edu:/bk/newmem
into  ewok.(none):/home/gblack/m5/newmem

--HG--
extra : convert_revision : 91aacb435c223e8c37f6ba0a458b0dee55edcaf2
2006-09-15 00:59:39 -04:00
Gabe Black
c32ef326d2 Fix up the parameters to getInstRecord
--HG--
extra : convert_revision : 0fac43035a2510d3a3f596d3d8f57193045570f6
2006-09-03 02:10:05 -04:00
Korey Sewell
82862e0e15 add ISA_HAS_DELAY_SLOT directive instead of "#if THE_ISA == ALPHA_ISA" throughout CPU models
src/arch/alpha/isa_traits.hh:
src/arch/mips/isa_traits.hh:
src/arch/sparc/isa_traits.hh:
    define 'ISA_HAS_DELAY_SLOT'
src/cpu/base_dyn_inst.hh:
src/cpu/o3/bpred_unit_impl.hh:
src/cpu/o3/commit_impl.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue_impl.hh:
src/cpu/o3/rename_impl.hh:
src/cpu/simple/base.cc:
    use ISA_HAS_DELAY_SLOT instead of THE_ISA == ALPHA_ISA

--HG--
extra : convert_revision : 24c7460d9391e8d443c9fe08e17c331ae8e9c36a
2006-08-31 20:51:30 -04:00
Ron Dreslinski
ec0a18ffb9 Fixes for Kevins O3 model to work with the blocking caches.
src/cpu/o3/fetch_impl.hh:
    Fix ordering so dereference works
src/cpu/o3/lsq_impl.hh:
    Check to make sure we didn't squash already
src/cpu/o3/lsq_unit.hh:
    Fix for counting squashed retrys in the WB count
src/cpu/o3/lsq_unit_impl.hh:
    Make sure to set retryID for stores, and clear it appropriately

--HG--
extra : convert_revision : 689765a1baea7b36f13eb177d65e97b52b6da09f
2006-08-16 15:56:22 -04:00
Gabe Black
74e80fc6c7 Some touchup to the reorganized includes and "using" directives.
--HG--
extra : convert_revision : 956c80d6d826b08e52c0892a480a0a9b74b96b9d
2006-08-15 05:49:52 -04:00
Gabe Black
74546aac01 Cleaned up include files and got rid of many using directives in header files.
--HG--
extra : convert_revision : 6b11e039cbc061dab75195fa1aebe6ca2cdc6f91
2006-08-15 05:07:15 -04:00
Gabe Black
fc8b4f5253 Started to add support for O3 for sparc.
--HG--
extra : convert_revision : 3f94bda14024a09b9fbd7a5d13284d4987349ddf
2006-08-11 20:29:15 -04:00
Gabe Black
800e6ecc07 Pushed most of constants.hh back into isa_traits.hh and regfile.hh and created a seperate file for the syscallreturn class.
--HG--
extra : convert_revision : 9507ea1c09fda959f00aec9ec8ffb887ec8dd0f9
2006-08-11 19:43:10 -04:00
Korey Sewell
95561dc138 MIPS ISA runs 'hello world' in O3CPU ...
src/arch/mips/isa/base.isa:
    special case syscall disasembly... maybe give own instruction class?
src/arch/mips/isa/decoder.isa:
    add 'IsSerializeAfter' flag for syscall
src/cpu/o3/commit.hh:
    Add skidBuffer to commit
src/cpu/o3/commit_impl.hh:
    Use skidbuffer in MIPS ISA
src/cpu/o3/fetch_impl.hh:
    Print name out when there is a fault
src/cpu/o3/mips/cpu_impl.hh:
    change comment

--HG--
extra : convert_revision : d032549e07102bdd50aa09f044fce8de6f0239b5
2006-07-26 18:47:06 -04:00
Korey Sewell
19ca97af79 This changeset gets the MIPS ISA pretty much working in the O3CPU. It builds, runs, and gets very very close to completing the hello world
succesfully but there are some minor quirks to iron out. Who would've known a DELAY SLOT introduces that much complexity?! arrgh!

Anyways, a lot of this stuff had to do with my project at MIPS and me needing to know how I was going to get this working for the MIPS
ISA. So I figured I would try to touch it up and throw it in here (I hate to introduce non-completely working components... )

src/arch/alpha/isa/mem.isa:
    spacing
src/arch/mips/faults.cc:
src/arch/mips/faults.hh:
    Gabe really authored this
src/arch/mips/isa/decoder.isa:
    add StoreConditional Flag to instruction
src/arch/mips/isa/formats/basic.isa:
    Steven really did this file
src/arch/mips/isa/formats/branch.isa:
    fix bug for uncond/cond control
src/arch/mips/isa/formats/mem.isa:
    Adjust O3CPU memory access to use new memory model interface.
src/arch/mips/isa/formats/util.isa:
    update LoadStoreBase template
src/arch/mips/isa_traits.cc:
    update SERIALIZE partially
src/arch/mips/process.cc:
src/arch/mips/process.hh:
    no need for this for NOW. ASID/Virtual addressing handles it
src/arch/mips/regfile/misc_regfile.hh:
    add in clear() function and comments for future usage of special misc. regs
src/cpu/base_dyn_inst.hh:
    add in nextNPC variable and supporting functions.

    add isCondDelaySlot function

    Update predTaken and mispredicted functions
src/cpu/base_dyn_inst_impl.hh:
    init nextNPC
src/cpu/o3/SConscript:
    add MIPS files to compile
src/cpu/o3/alpha/thread_context.hh:
    no need for my name on this file
src/cpu/o3/bpred_unit_impl.hh:
    Update RAS appropriately for MIPS
src/cpu/o3/comm.hh:
    add some extra communication variables to aid in handling the
    delay slots
src/cpu/o3/commit.hh:
    minor name fix for nextNPC functions.
src/cpu/o3/commit_impl.hh:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue_impl.hh:
src/cpu/o3/rename_impl.hh:
    Fix necessary variables and functions for squashes with delay slots
src/cpu/o3/cpu.cc:
    Update function interface ...

    adjust removeInstsNotInROB function to recognize delay slots insts
src/cpu/o3/cpu.hh:
    update removeInstsNotInROB
src/cpu/o3/decode.hh:
    declare necessary variables for handling delay slot
src/cpu/o3/dyn_inst.hh:
    Add in MipsDynInst
src/cpu/o3/fetch.hh:
src/cpu/o3/iew.hh:
src/cpu/o3/rename.hh:
    declare necessary variables and adjust functions for handling delay slot
src/cpu/o3/inst_queue.hh:
src/cpu/simple/base.cc:
    no need for my name here
src/cpu/o3/isa_specific.hh:
    add in MIPS files
src/cpu/o3/scoreboard.hh:
    dont include alpha specific isa traits!
src/cpu/o3/thread_context.hh:
    no need for my name here, i just rearranged where the file goes
src/cpu/static_inst.hh:
    add isCondDelaySlot function
src/cpu/o3/mips/cpu.cc:
src/cpu/o3/mips/cpu.hh:
src/cpu/o3/mips/cpu_builder.cc:
src/cpu/o3/mips/cpu_impl.hh:
src/cpu/o3/mips/dyn_inst.cc:
src/cpu/o3/mips/dyn_inst.hh:
src/cpu/o3/mips/dyn_inst_impl.hh:
src/cpu/o3/mips/impl.hh:
src/cpu/o3/mips/params.hh:
src/cpu/o3/mips/thread_context.cc:
src/cpu/o3/mips/thread_context.hh:
    MIPS file for O3CPU...mirrors ALPHA definition

--HG--
extra : convert_revision : 9bb199b4085903e49ffd5a4c8ac44d11460d988c
2006-07-23 13:39:42 -04:00
Kevin Lim
85515c4976 O3CPU fixes.
src/cpu/o3/lsq_unit.hh:
    LSQ needs to decrement the WB counter if the load is going to be replayed.
src/cpu/o3/lsq_unit_impl.hh:
    LSQ needs to decrement the WB counter if the load is squashed.

--HG--
extra : convert_revision : 20a10baf0d6ab46065e561ddba231251865ebdbd
2006-07-19 15:28:02 -04:00
Kevin Lim
0cedb23d3c Some minor compiling fixes.
src/cpu/o3/iew.hh:
    Non-debug compile fixes.
src/cpu/simple/atomic.cc:
src/cpu/simple/atomic.hh:
    Merge fix.

--HG--
extra : convert_revision : 38081925d2b74d8f64acdb65dba94b2bf465b16a
2006-07-19 15:26:48 -04:00
Kevin Lim
31ac8e7337 Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge

configs/test/fs.py:
configs/test/test.py:
    SCCS merged

--HG--
extra : convert_revision : 7b2dbcd5881fac01dec38001c4131e73b5be52b5
2006-07-14 17:54:43 -04:00
Korey Sewell
07186de5a1 forgot tid
--HG--
extra : convert_revision : 272ef8f9cd0802770edc4dcef2c26dc44de71e47
2006-07-14 13:22:35 -04:00
Korey Sewell
b2c51d064b For now, halt context is the same as deallocating.
suspend context will now take the thread off the activeThread list.

src/arch/mips/isa_traits.cc:
    add in copy MiscRegs unimplemented function

--HG--
extra : convert_revision : 3ed5320b3786f84d4bb242e3a32b6f415339c3ba
2006-07-14 13:06:37 -04:00
Kevin Lim
1e4acb8e01 Move Dcache port creation from LSQUnit to LSQ in order to support Ron's recent changes, and using the O3CPU in SMT mode.
src/cpu/o3/lsq.hh:
    Update to have LSQ work with only one dcache port for all LSQ Units.  LSQ has the dcache port, and the LSQ Units must tell the LSQ if the cache has become blocked.
src/cpu/o3/lsq_impl.hh:
    Updates to have the LSQ work with only one dcache port for all LSQUnits.
src/cpu/o3/lsq_unit.hh:
src/cpu/o3/lsq_unit_impl.hh:
    Update for LSQ to create dcache port instead of LSQUnits.  Now LSQUnits are given the dcache port from the LSQ, and also must check the LSQ if the cache is blocked prior to accessing the cache.

--HG--
extra : convert_revision : 2708adbf323f4e7647dc0c1e31ef5bb4596b89f8
2006-07-13 13:12:51 -04:00
Kevin Lim
2af213022c Fix for bug when squashing and the fetching. Now fetch checks if the cache data is valid.
--HG--
extra : convert_revision : 07b8eda3e90bbbb3ed470c8cc3cf1b63371ab529
2006-07-13 13:09:29 -04:00
Kevin Lim
a0a952d5ff Update for changes to draining.
--HG--
extra : convert_revision : 5038dd8be72827f40cf89318db0b2bb4f9bbd864
2006-07-13 13:08:58 -04:00
Kevin Lim
6dfaf06edf Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge

configs/test/test.py:
    Hand merge.

--HG--
extra : convert_revision : e3fce9cf50a65a9400cd3ec887b13e4765274ec2
2006-07-12 17:21:25 -04:00
Kevin Lim
e758c1fc04 Serialization changes to make O3CPU consistent with the other models.
src/cpu/o3/commit_impl.hh:
    Always set instruction.  This is necessary for serialization as the instruction is also serialized.
src/cpu/o3/cpu.cc:
    Change serialization so it matches other CPU's output.  Also fix up some indexing.

--HG--
extra : convert_revision : 52f6e183132d177bed6e29dd7cf0c10aed6d8534
2006-07-12 17:18:34 -04:00
Kevin Lim
bbfe1db6b3 Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem

src/cpu/o3/fetch_impl.hh:
    Hand merge.

--HG--
extra : convert_revision : 820dab2bc921cbadecaca51cd069327f984f5c74
2006-07-12 15:25:34 -04:00
Kevin Lim
6d120b7912 Track the PC of the cache data stored in fetch so it doesn't access memory multiple times if information is already in fetch.
--HG--
extra : convert_revision : 00b160b255e998cf99286bcc21894110c7642624
2006-07-12 15:24:27 -04:00
Ron Dreslinski
6bcc65c1f8 Fix ordering issue with squashed Icache Fetches and Static data in packet.
Now hello world works with 2 levels of cache with O3 CPU(multiple outstanding requests).

src/cpu/o3/fetch_impl.hh:
    Fix ordering issue with squashed Icache Fetches and Static data in packet.

--HG--
extra : convert_revision : a6adb87540b007ead0b4982cb3f31da8199fb5ca
2006-07-11 15:42:31 -04:00
Kevin Lim
5dbd7a3f76 Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge

--HG--
extra : convert_revision : 0e4c7684879b8552908e0b64a00b4824de807244
2006-07-10 15:41:35 -04:00
Kevin Lim
f60d8217e3 Some minor cleanups.
src/cpu/SConscript:
    Change the error message to be slightly nicer.
src/cpu/o3/commit.hh:
    Remove old code.
src/cpu/o3/commit_impl.hh:
    Remove old unused code.

--HG--
extra : convert_revision : 48aa430e1f3554007dd5e4f3d9e89b5e4f124390
2006-07-10 15:41:28 -04:00
Kevin Lim
fcaafdc48c Add parameters for backwards and forwards sizes for time buffers.
src/base/timebuf.hh:
    Add a function to return the size of the time buffer.

--HG--
extra : convert_revision : 8ffacd8b9013eb76264df065244e00dc1460efd4
2006-07-10 15:40:28 -04:00
Korey Sewell
cdf27a0a86 Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
into  zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-o3

--HG--
extra : convert_revision : 9098d989832e2a5818b80771e3c02170c5c8cd5b
2006-07-07 19:02:12 -04:00
Kevin Lim
8ade33d324 Support Ron's changes for hooking up ports.
src/cpu/checker/cpu.hh:
    Now that BaseCPU is a MemObject, the checker must define this function.
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/iew.hh:
src/cpu/o3/lsq.hh:
src/cpu/o3/lsq_unit.hh:
    Implement getPort function so the connector can connect the ports properly.
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/lsq_unit_impl.hh:
    The connector handles connecting the ports now.
src/python/m5/objects/O3CPU.py:
    Add ports to the parameters.

--HG--
extra : convert_revision : 0b1a216b9a5d0574e62165d7c6c242498104d918
2006-07-07 17:33:24 -04:00
Kevin Lim
744e0055b7 Fix for bug when draining and a memory access is outstanding.
--HG--
extra : convert_revision : 1af782cf023ae74c2a3ff9f7aefcea880bc87936
2006-07-07 16:48:44 -04:00
Korey Sewell
74d4d67138 Minor fix for SMT Hello Worlds to finish correctly.
Still, there is a problem with the LSQ and indexing out of range in the buffer.
I havent nailed down the fix yet, but it's coming ...

src/cpu/o3/commit_impl.hh:
    add space to DPRINT
src/cpu/o3/cpu.cc:
    add newline to DPRINT
src/cpu/o3/rob.hh:
src/cpu/o3/rob_impl.hh:
    Each thread needs it's own squashedSeqNum for the case where they are both squashing at the same time and they dont
    write over each other's squash number.

--HG--
extra : convert_revision : 2155421a8b5b20e4544eea3d3c53d3e715465fa6
2006-07-07 15:58:03 -04:00
Kevin Lim
018ba50f2c Switch out fixes for CPUs.
src/cpu/o3/cpu.cc:
    Fix up keeping proper state when switched out and drained.
src/cpu/simple/timing.cc:
src/cpu/simple/timing.hh:
    Keep track of the event we use to schedule fetch initially and upon resume.  We may have to cancel the event if the CPU is switched out.

--HG--
extra : convert_revision : 60a2a1bd2cdc67bd53ca4a67aa77166c826a4c8c
2006-07-07 15:38:15 -04:00
Korey Sewell
161e8bf874 Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
into  zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-o3

--HG--
extra : convert_revision : 90717b492139428e0c48be35a6bda45960c61086
2006-07-07 04:07:00 -04:00
Korey Sewell
c355df5bfe Fix so that O3CPU doesnt segfault on exit.
Major thing was to not execute commit if there are no active threads in CPU.

src/cpu/o3/alpha/thread_context.hh:
    call deallocate instead of deallocateContext
src/cpu/o3/commit_impl.hh:
    dont run commit stage if there are no instructions
src/cpu/o3/cpu.cc:
    add deallocate event, deactivateThread function, and edit deallocateContext.
src/cpu/o3/cpu.hh:
    add deallocate event and add optional delay to deallocateContext
src/cpu/o3/thread_context.hh:
    optional delay for deallocate
src/cpu/o3/thread_context_impl.hh:
    edit DPRINTFs to say Thread Context instead of Alpha TC
src/cpu/thread_context.hh:
    optional delay
src/sim/syscall_emul.hh:
    name stuff

--HG--
extra : convert_revision : f4033e1f66b3043d30ad98dcc70d8b193dea70b6
2006-07-07 04:06:26 -04:00
Kevin Lim
fff7531677 Support serializing and unserializing in the O3 CPU. Also a few small fixes for draining/switching CPUs.
src/cpu/o3/commit_impl.hh:
    Fix to clear drainPending variable on call to resume.
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
    Support serializing and unserializing in the O3 CPU.
src/cpu/o3/lsq_impl.hh:
    Be sure to say we have no stores to write back if the active thread list is empty.
src/cpu/simple_thread.cc:
src/cpu/simple_thread.hh:
    Slightly change how SimpleThread is used to copy from other ThreadContexts.

--HG--
extra : convert_revision : 92a5109b3783a989d5b451036061ef82c56d3121
2006-07-06 23:13:38 -04:00
Kevin Lim
fbe3e22474 Fix the O3CPU to support the multi-pass method for checking if the system has fully drained.
src/cpu/o3/commit.hh:
src/cpu/o3/commit_impl.hh:
src/cpu/o3/decode.hh:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/iew.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/rename.hh:
src/cpu/o3/rename_impl.hh:
    Return a value so that the CPU can instantly return from draining if the pipeline is already drained.
src/cpu/o3/cpu.cc:
    Use values returned from pipeline stages so that the CPU can instantly return from draining if the pipeline is already drained.

--HG--
extra : convert_revision : d8ef6b811644ea67c8b40c4719273fa224105811
2006-07-06 17:57:20 -04:00
Kevin Lim
e7ccc94ea3 Various serialization changes to make it possible for the O3CPU to checkpoint.
src/arch/alpha/regfile.hh:
    Define serialize/unserialize functions on MiscRegFile itself.
src/cpu/o3/regfile.hh:
    Remove old commented code.
src/cpu/simple_thread.cc:
src/cpu/simple_thread.hh:
    Push common serialization code to ThreadState level.  Also allow the SimpleThread to be used for checkpointing by other models.
src/cpu/thread_state.cc:
src/cpu/thread_state.hh:
    Move common serialization code into ThreadState.

--HG--
extra : convert_revision : ef64ef515355437439af967eda2e610e8c1b658b
2006-07-06 17:53:26 -04:00
Kevin Lim
05eef5ee15 Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge

--HG--
extra : convert_revision : 00f8eecf99c771ae8943ed1d3a652bfbcfe1c6bc
2006-07-06 13:59:13 -04:00
Kevin Lim
30c516d51c Support for draining, and the new method of switching out. Now switching out happens after the pipeline has been drained, deferring the three way handshake to the normal drain mechanism. The calls of switchOut() and takeOverFrom() both take action immediately.
src/cpu/o3/commit.hh:
src/cpu/o3/commit_impl.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/decode.hh:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/iew.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/rename.hh:
src/cpu/o3/rename_impl.hh:
    Support for draining, new method of switching out.

--HG--
extra : convert_revision : 05bf8b271ec85b3e2c675c3bed6c42aeba21f465
2006-07-06 13:59:02 -04:00
Korey Sewell
e60f998e29 Had to add this because for some reason gcc wasnt recognizing "THE_ISA == ALPHA_ISA"... wierd but OK
--HG--
extra : convert_revision : f847d6c01212e32200a319c16596b8e1c1d15c7d
2006-07-06 12:29:34 -04:00
Korey Sewell
a35898c18d Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
into  zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-o3

--HG--
extra : convert_revision : 2f08ea52ef54118d42aa590c0d86aa0cc7988713
2006-07-06 12:19:29 -04:00
Korey Sewell
03fa13b27c Use O3DynInst in cpu_models.py and in static_inst_exec_sigs.hh instead of a specific ISA dyn. inst.
src/cpu/cpu_models.py:
    Use O3DynInst
src/cpu/o3/dyn_inst.hh:
    declare O3DynInst here based off of ISA ... this must be updated for each ISA.
src/cpu/static_inst.hh:
    take out O3 forward declarations here and include header file to keep this file clean

--HG--
extra : convert_revision : 0d65463479c3cfc2d1154935b1032dae32c5efd0
2006-07-06 12:18:55 -04:00
Korey Sewell
215041215b more steps toward O3 SMT
src/arch/mips/isa/formats/fp.isa:
    Adjust for newmem
src/cpu/cpu_models.py:
    Use O3DynInst instead of convoluted way
src/cpu/o3/alpha/impl.hh:
    take out O3DynInst typedef here ...
src/cpu/o3/cpu.cc:
    open up the SMT functions in the O3CPU
src/cpu/static_inst.hh:
    Add O3DynInst
src/cpu/o3/dyn_inst.hh:
    Use to get ISA-specific O3DynInst

--HG--
extra : convert_revision : 3713187ead93e336e80889e23a1f1d2f36d664fe
2006-07-06 11:25:44 -04:00
Kevin Lim
d598061dd6 Remove sampler and serializer. Now they are handled through C++ interacting with Python.
src/SConscript:
src/cpu/base.cc:
src/cpu/base.hh:
src/cpu/checker/cpu.hh:
src/cpu/checker/cpu_impl.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/fetch.hh:
src/cpu/ozone/cpu.hh:
src/cpu/ozone/cpu_impl.hh:
src/cpu/simple/base.cc:
src/cpu/simple/base.hh:
src/sim/pseudo_inst.cc:
    Remove sampler.
src/sim/sim_object.cc:
    Remove serializer.

--HG--
extra : convert_revision : ce7616189440f3dc70040148da6d07309a386008
2006-07-05 21:14:36 -04:00
Kevin Lim
ea9697250c Fix up some merge problems.
src/base/traceflags.py:
    Remove BaseCPU traceflag.
src/cpu/o3/alpha/params.hh:
    Move non-Alpha specific parameters out of this params class.
src/cpu/o3/params.hh:
    Move non-Alpha specific params into this params class.

--HG--
extra : convert_revision : e5b652adb47a240376733400e6054c66c50bd514
2006-07-05 16:54:24 -04:00
Kevin Lim
b973fae85d Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge

src/base/traceflags.py:
src/cpu/SConscript:
    Hand merge.
src/cpu/o3/alpha/params.hh:
    Hand merge.  This needs to get changed.

--HG--
rename : src/cpu/o3/alpha_cpu_builder.cc => src/cpu/o3/alpha/cpu_builder.cc
rename : src/cpu/o3/alpha_params.hh => src/cpu/o3/alpha/params.hh
rename : src/python/m5/objects/AlphaO3CPU.py => src/python/m5/objects/O3CPU.py
extra : convert_revision : 581f338f5bce35288f7d15d95cbd0ac3a9135e6a
2006-07-05 16:08:18 -04:00
Kevin Lim
b84103811d Add some different parameters. The main change is that the writeback count is now limited so that it doesn't overflow the buffer.
src/cpu/o3/alpha_cpu_builder.cc:
src/cpu/o3/alpha_params.hh:
    Add in dispatchWidth, wbWidth, wbDepth parameters.  wbDepth is the number of cycles of wbWidth instructions that can be buffered.
src/cpu/o3/iew.hh:
    Include separate parameter for dispatch width.
    Also limit the number of outstanding writebacks so the writeback buffer isn't overflowed.  The IQ must make sure with the IEW stage that it can issue instructions prior to issuing.
src/cpu/o3/iew_impl.hh:
    Include separate parameter for dispatch width.
    Also limit the number of outstanding writebacks so the writeback buffer isn't overflowed.
src/cpu/o3/inst_queue_impl.hh:
    IQ needs to check with the IEW to make sure it can issue instructions, and increments the IEW wb counter each time there is an outstanding instruction that will writeback.
src/cpu/o3/lsq_unit_impl.hh:
    Be sure to decrement the writeback counter if there's a squashed load that returned.
src/python/m5/objects/AlphaO3CPU.py:
    Change the parameters to include dispatch width, writeback width, and writeback depth.

--HG--
extra : convert_revision : 31c8cc495273e3c481b79055562fc40f71291fc4
2006-07-05 15:51:36 -04:00
Korey Sewell
f4c5609988 Fix for FS O3CPU compile ... missing forward class declaration/header file after files got split for ISA-independence
src/cpu/o3/alpha/thread_context.hh:
    Use 'this' when accessing cpu
src/cpu/o3/cpu.hh:
    add numActiveThreds function
src/cpu/o3/thread_context.hh:
    forward class declarations
src/cpu/o3/thread_context_impl.hh:
    add quiesce event header file
src/cpu/thread_context.hh:
    add exit() function to thread context (read comments in file)
src/sim/syscall_emul.cc:
    adjust exitFunc syscall

--HG--
extra : convert_revision : 323dc871e2b4f4ee5036be388ceb6634cd85a83e
2006-07-03 12:19:35 -04:00
Korey Sewell
cf58578ba1 typo ... change 'single_thread' to 'round_robin_policy'
--HG--
extra : convert_revision : a4a5cb90557f786d42c6178bc6e268312c5ecbee
2006-07-02 23:27:13 -04:00
Korey Sewell
c8b3d8a1ed Fix default SMT configuration in O3CPU (i.e. fetch policy, workloads/numThreads)
Edit Test3 for newmem

src/base/traceflags.py:
    Add O3CPU flag
src/cpu/base.cc:
    for some reason adding a BaseCPU flag doesnt work so just go back to old way...
src/cpu/o3/alpha/cpu_builder.cc:
    Determine number threads by workload size instead of solely by parameter.

    Default SMT fetch policy to RoundRobin if it's not specified in Config file
src/cpu/o3/commit.hh:
    only use nextNPC for !ALPHA
src/cpu/o3/commit_impl.hh:
    add FetchTrapPending as condition for commit
src/cpu/o3/cpu.cc:
    panic if active threads is more than Impl::MaxThreads
src/cpu/o3/fetch.hh:
src/cpu/o3/inst_queue.hh:
src/cpu/o3/inst_queue_impl.hh:
src/cpu/o3/rob.hh:
src/cpu/o3/rob_impl.hh:
    name stuff
src/cpu/o3/fetch_impl.hh:
    fatal if try to use SMT branch count, that's unimplemented right now
src/python/m5/config.py:
    make it clearer that a parameter is not valid within a configuration class

--HG--
extra : convert_revision : 55069847304e40e257f9225f0dc3894ce6491b34
2006-07-02 23:11:24 -04:00
Korey Sewell
62961a2916 fix cpu builder to build the correct name...
add activateThread event and functions

src/cpu/o3/alpha/cpu_builder.cc:
    Have CPU builder build a DerivO3CPU not a DerivAlphaO3CPU
src/cpu/o3/cpu.cc:
    add activateThread Event

    add activateThread function

    adjust activateContext to schedule a thread to activate within the
    CPU instead of activating thread right away. This will lead to stages
    trying to use threads that  arent ready yet and wasting execution time & possibly
    performance.
src/cpu/o3/cpu.hh:
    add activateThread Event

    add activateThread function

    add schedule/descheculed activate thread event

--HG--
extra : convert_revision : 236d30dc160910507ad36f7f527ab185ed38dc04
2006-07-01 18:52:02 -04:00
Korey Sewell
51261196bd now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory
src/cpu/o3/alpha/cpu.cc:
src/cpu/o3/alpha/cpu_impl.hh:
src/cpu/o3/alpha/impl.hh:
    filenames
src/cpu/o3/alpha/thread_context.hh:
    public
src/cpu/o3/base_dyn_inst.cc:
src/cpu/o3/bpred_unit.cc:
src/cpu/o3/commit.cc:
src/cpu/o3/cpu.cc:
src/cpu/o3/decode.cc:
src/cpu/o3/fetch.cc:
src/cpu/o3/iew.cc:
src/cpu/o3/inst_queue.cc:
src/cpu/o3/lsq.cc:
src/cpu/o3/lsq_unit.cc:
src/cpu/o3/mem_dep_unit.cc:
src/cpu/o3/rename.cc:
src/cpu/o3/rob.cc:
    use O3CPUImpl ... not Alpha
src/cpu/o3/checker_builder.cc:
    filename

--HG--
extra : convert_revision : 6eb739909699ade1e2a9d63637b182413ceebc69
2006-06-30 20:49:31 -04:00
Korey Sewell
d9ef772e8d Make O3CPU model independent of the ISA
Use O3CPU when building instead of AlphaO3CPU.

I could use some better python magic in the cpu_models.py file!

AUTHORS:
    add middle initial
SConstruct:
    change from AlphaO3CPU to O3CPU
src/cpu/SConscript:
    edits to build O3CPU instead of AlphaO3CPU
src/cpu/cpu_models.py:
    change substitution template to use proper CPU EXEC CONTEXT For O3CPU Model...

    Actually, some Python expertise could be used here. The 'env' variable is not
    passed to this file, so I had to parse through the ARGV to find the ISA...
src/cpu/o3/base_dyn_inst.cc:
src/cpu/o3/bpred_unit.cc:
src/cpu/o3/commit.cc:
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/decode.cc:
src/cpu/o3/fetch.cc:
src/cpu/o3/iew.cc:
src/cpu/o3/inst_queue.cc:
src/cpu/o3/lsq.cc:
src/cpu/o3/lsq_unit.cc:
src/cpu/o3/mem_dep_unit.cc:
src/cpu/o3/rename.cc:
src/cpu/o3/rob.cc:
    use isa_specific.hh
src/sim/process.cc:
    only initi NextNPC if not ALPHA
src/cpu/o3/alpha/cpu.cc:
    alphao3cpu impl
src/cpu/o3/alpha/cpu.hh:
    move AlphaTC to it's own file
src/cpu/o3/alpha/cpu_impl.hh:
    Move AlphaTC to it's own file ...
src/cpu/o3/alpha/dyn_inst.cc:
src/cpu/o3/alpha/dyn_inst.hh:
src/cpu/o3/alpha/dyn_inst_impl.hh:
    include paths
src/cpu/o3/alpha/impl.hh:
    include paths, set default MaxThreads to 2 instead of 4
src/cpu/o3/alpha/params.hh:
    set Alpha Specific Params here
src/python/m5/objects/O3CPU.py:
    add O3CPU class
src/cpu/o3/SConscript:
    include isa-specific build files
src/cpu/o3/alpha/thread_context.cc:
    NEW HOME of AlphaTC
src/cpu/o3/alpha/thread_context.hh:
    new home of AlphaTC
src/cpu/o3/isa_specific.hh:
    includes ISA specific files
src/cpu/o3/params.hh:
    base o3 params
src/cpu/o3/thread_context.hh:
    base o3 thread context
src/cpu/o3/thread_context_impl.hh:
    base o3 thead context impl

--HG--
rename : src/cpu/o3/alpha_cpu.cc => src/cpu/o3/alpha/cpu.cc
rename : src/cpu/o3/alpha_cpu.hh => src/cpu/o3/alpha/cpu.hh
rename : src/cpu/o3/alpha_cpu_builder.cc => src/cpu/o3/alpha/cpu_builder.cc
rename : src/cpu/o3/alpha_cpu_impl.hh => src/cpu/o3/alpha/cpu_impl.hh
rename : src/cpu/o3/alpha_dyn_inst.cc => src/cpu/o3/alpha/dyn_inst.cc
rename : src/cpu/o3/alpha_dyn_inst.hh => src/cpu/o3/alpha/dyn_inst.hh
rename : src/cpu/o3/alpha_dyn_inst_impl.hh => src/cpu/o3/alpha/dyn_inst_impl.hh
rename : src/cpu/o3/alpha_impl.hh => src/cpu/o3/alpha/impl.hh
rename : src/cpu/o3/alpha_params.hh => src/cpu/o3/alpha/params.hh
rename : src/python/m5/objects/AlphaO3CPU.py => src/python/m5/objects/O3CPU.py
extra : convert_revision : d377d6417452ac337bc502f28b2fde907d6b340e
2006-06-30 19:52:08 -04:00
Ali Saidi
07cd37c48b Make full CPU handle SE faults
--HG--
extra : convert_revision : e336623ac3329ec0ee2430548c6a9650e2a69d6a
2006-06-27 14:59:38 -04:00
Kevin Lim
63bdaeedfa Checker related updates.
src/cpu/o3/cpu.cc:
    Updates to make sure the checker is compiled in if enabled and also to include it only when it's used.

--HG--
extra : convert_revision : c48ead5b2665dc858acd87c2ee99d39d80594a69
2006-06-22 23:43:45 -04:00
Kevin Lim
e6c04b1584 Change ThreadState constructor ordering to match the rest of the ThreadStates.
--HG--
extra : convert_revision : 63d98aa8b6a694c285d95a2a57e1b3aaef4cee3b
2006-06-22 18:10:17 -04:00
Kevin Lim
6e95bcd333 Misc fixes.
src/cpu/o3/alpha_dyn_inst_impl.hh:
    Consolidate these calls into one.
src/cpu/o3/commit_impl.hh:
    Include checker only if it's being used.
src/cpu/o3/fetch_impl.hh:
    Do not deallocate request if it's a squashed response that was received.
src/cpu/o3/lsq_unit.hh:
    Add in comment.
src/cpu/o3/lsq_unit_impl.hh:
    Only include checker if it's being used.

--HG--
extra : convert_revision : aae0bf1e19baae90f1e61d41191548612bbb3be6
2006-06-22 18:09:31 -04:00
Kevin Lim
14b9cda9f6 Minor updates.
src/cpu/o3/alpha_cpu.hh:
    Fix #define in header.
util/rundiff:
    Fix file comments to be more correct.
util/tracediff:
    Update comments to be more correct.

--HG--
extra : convert_revision : a28030ce8979de3d9361191c6af23743460dc53e
2006-06-17 22:55:00 -04:00
Kevin Lim
f3d74759ca Split off instantiation into separate CC files for each of the models. This makes it easier to be able to specify only certain CPU models.
src/cpu/SConscript:
    Split off instantiations into separate CC files.  This makes it easier to split them per CPU model.
src/cpu/base_dyn_inst_impl.hh:
    Move instantations out of impl.hh file and into a cc file.
src/cpu/checker/cpu_impl.hh:
    Move instantiations over to .cc files inside each CPU's directory.  Makes it easier to only use what's actually included.
src/cpu/o3/bpred_unit.cc:
    Pull Ozone instantiations out of this .cc file; put them into the ozone's CC file.
src/cpu/o3/checker_builder.cc:
    Instantiate Checker for O3 CPU.
src/cpu/ozone/checker_builder.cc:
    Instantiate Checker for Ozone CPU.

--HG--
rename : src/cpu/base_dyn_inst.cc => src/cpu/base_dyn_inst_impl.hh
rename : src/cpu/checker/cpu.cc => src/cpu/checker/cpu_impl.hh
rename : src/cpu/checker/o3_builder.cc => src/cpu/o3/checker_builder.cc
rename : src/cpu/checker/ozone_builder.cc => src/cpu/ozone/checker_builder.cc
extra : convert_revision : 4e5f928b165379c06d31071c544ea46cf0b8fa71
2006-06-17 21:39:25 -04:00
Kevin Lim
4e07f6ca52 Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge

--HG--
extra : convert_revision : 488b9a9965dd86ca73dc9e510e5b3122cbd357f9
2006-06-16 17:53:33 -04:00
Kevin Lim
0bbd909f02 Reorganization to move FuncUnit, FUDesc, and OpDesc out of the encumbered directory and into the normal cpu directory.
src/SConscript:
    Split off FuncUnits from old FUPool so I'm not including encumbered code.  This was all written by Steve Raasch so it's safe to include in the main tree.
src/cpu/o3/fu_pool.cc:
    Include the func unit file that's not in the encumbered directory.

--HG--
extra : convert_revision : 9801c606961dd2d62dba190d13a76069992bf241
2006-06-16 17:52:15 -04:00
Kevin Lim
f4d0f92855 Miscellaneous minor fixes.
src/cpu/checker/cpu.cc:
    Add in comment.
src/cpu/cpuevent.hh:
    Fix up comment.
src/cpu/o3/bpred_unit.cc:
    Comment out Ozone instantiations.
src/cpu/o3/dep_graph.hh:
    Include destructor.

--HG--
extra : convert_revision : 549454ed11bc2fa49a0627f7fb8f96d00a9be303
2006-06-16 17:15:18 -04:00
Kevin Lim
baba18ab92 Two updates that got combined into one ChangeSet accidentally. They're both pretty simple so they shouldn't cause any trouble.
First: Rename FullCPU and its variants in the o3 directory to O3CPU to differentiate from the old model, and also to specify it's an out of order model.

Second: Include build options for selecting the Checker to be used.  These options make sure if the Checker is being used there is a CPU that supports it also being compiled.

SConstruct:
    Add in option USE_CHECKER to allow for not compiling in checker code.  The checker is enabled through this option instead of through the CPU_MODELS list.  However it's still necessary to treat the Checker like a CPU model, so it is appended onto the CPU_MODELS list if enabled.
configs/test/test.py:
    Name change for DetailedCPU to DetailedO3CPU.  Also include option for max tick.
src/base/traceflags.py:
    Add in O3CPU trace flag.
src/cpu/SConscript:
    Rename AlphaFullCPU to AlphaO3CPU.

    Only include checker sources if they're necessary.  Also add a list of CPUs that support the Checker, and only allow the Checker to be compiled in if one of those CPUs are also being included.
src/cpu/base_dyn_inst.cc:
src/cpu/base_dyn_inst.hh:
    Rename typedef to ImplCPU instead of FullCPU, to differentiate from the old FullCPU.
src/cpu/cpu_models.py:
src/cpu/o3/alpha_cpu.cc:
src/cpu/o3/alpha_cpu.hh:
src/cpu/o3/alpha_cpu_builder.cc:
src/cpu/o3/alpha_cpu_impl.hh:
    Rename AlphaFullCPU to AlphaO3CPU to differentiate from old FullCPU model.
src/cpu/o3/alpha_dyn_inst.hh:
src/cpu/o3/alpha_dyn_inst_impl.hh:
src/cpu/o3/alpha_impl.hh:
src/cpu/o3/alpha_params.hh:
src/cpu/o3/commit.hh:
src/cpu/o3/cpu.hh:
src/cpu/o3/decode.hh:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/iew.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue.hh:
src/cpu/o3/lsq.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/o3/lsq_unit.hh:
src/cpu/o3/regfile.hh:
src/cpu/o3/rename.hh:
src/cpu/o3/rename_impl.hh:
src/cpu/o3/rob.hh:
src/cpu/o3/rob_impl.hh:
src/cpu/o3/thread_state.hh:
src/python/m5/objects/AlphaO3CPU.py:
    Rename FullCPU to O3CPU to differentiate from old FullCPU model.
src/cpu/o3/commit_impl.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/lsq_unit_impl.hh:
    Rename FullCPU to O3CPU to differentiate from old FullCPU model.
    Also #ifdef the checker code so it doesn't need to be included if it's not selected.

--HG--
rename : src/cpu/checker/o3_cpu_builder.cc => src/cpu/checker/o3_builder.cc
rename : src/cpu/checker/cpu_builder.cc => src/cpu/checker/ozone_builder.cc
rename : src/python/m5/objects/AlphaFullCPU.py => src/python/m5/objects/AlphaO3CPU.py
extra : convert_revision : 86619baf257b8b7c8955efd447eba56e0d7acd6a
2006-06-16 17:08:47 -04:00
Kevin Lim
720e6c4145 Checker updates.
src/cpu/checker/cpu.cc:
src/cpu/checker/cpu.hh:
    Updates for checker.  Output more informative messages on error.  Rename some functions.  Add in option to warn (and not exit) on load results being incorrect.
src/cpu/checker/cpu_builder.cc:
src/cpu/checker/o3_cpu_builder.cc:
    Add in parameter to warn (and not exit) on load result errors.
src/cpu/o3/commit_impl.hh:
src/cpu/o3/lsq_unit_impl.hh:
    Renamed checker functin.

--HG--
extra : convert_revision : d7aa28b8462691d20600f97a7213e2acd91c5665
2006-06-16 13:10:47 -04:00
Korey Sewell
51a5b82637 Initial changes to allowed DetailedCPU to work with other architectures (i.e. Sparc & MIPS)
Still need to add some code to fetch & commit stages

src/cpu/o3/commit.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
    Add nextNPC read & set functions
src/cpu/o3/fetch.hh:
src/cpu/o3/fetch_impl.hh:
    Add nextNPC

--HG--
extra : convert_revision : 120677547d54091411399156bd066ce5baf785f7
2006-06-15 22:01:28 -04:00
Kevin Lim
5d11e8bff6 Minor code cleanup of BaseDynInst.
src/cpu/base_dyn_inst.cc:
src/cpu/base_dyn_inst.hh:
    Minor code cleanup by putting several bools into a bitset instead.
src/cpu/o3/commit_impl.hh:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue_impl.hh:
src/cpu/o3/lsq_unit.hh:
src/cpu/o3/lsq_unit_impl.hh:
src/cpu/o3/rename_impl.hh:
src/cpu/o3/rob_impl.hh:
    Changed around some things in BaseDynInst.

--HG--
extra : convert_revision : 1db363d69a863cc8744cc9f9ec542ade8472eb42
2006-06-14 13:12:41 -04:00