Fix default SMT configuration in O3CPU (i.e. fetch policy, workloads/numThreads)
Edit Test3 for newmem src/base/traceflags.py: Add O3CPU flag src/cpu/base.cc: for some reason adding a BaseCPU flag doesnt work so just go back to old way... src/cpu/o3/alpha/cpu_builder.cc: Determine number threads by workload size instead of solely by parameter. Default SMT fetch policy to RoundRobin if it's not specified in Config file src/cpu/o3/commit.hh: only use nextNPC for !ALPHA src/cpu/o3/commit_impl.hh: add FetchTrapPending as condition for commit src/cpu/o3/cpu.cc: panic if active threads is more than Impl::MaxThreads src/cpu/o3/fetch.hh: src/cpu/o3/inst_queue.hh: src/cpu/o3/inst_queue_impl.hh: src/cpu/o3/rob.hh: src/cpu/o3/rob_impl.hh: name stuff src/cpu/o3/fetch_impl.hh: fatal if try to use SMT branch count, that's unimplemented right now src/python/m5/config.py: make it clearer that a parameter is not valid within a configuration class --HG-- extra : convert_revision : 55069847304e40e257f9225f0dc3894ce6491b34
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@ -121,6 +121,7 @@ baseFlags = [
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'FE',
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'IBE',
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'BE',
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'O3CPU',
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'OzoneLSQ',
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'PCEvent',
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'PCIA',
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@ -68,12 +68,12 @@ BaseCPU::BaseCPU(Params *p)
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number_of_threads(p->numberOfThreads), system(p->system)
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#endif
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{
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DPRINTF(BaseCPU, "BaseCPU: Creating object, mem address %#x.\n", this);
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DPRINTF(FullCPU, "BaseCPU: Creating object, mem address %#x.\n", this);
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// add self to global list of CPUs
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cpuList.push_back(this);
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DPRINTF(BaseCPU, "BaseCPU: CPU added to cpuList, mem address %#x.\n",
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DPRINTF(FullCPU, "BaseCPU: CPU added to cpuList, mem address %#x.\n",
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this);
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if (number_of_threads > maxThreadsPerCPU)
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@ -274,12 +274,12 @@ CREATE_SIM_OBJECT(DerivO3CPU)
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// In non-full-system mode, we infer the number of threads from
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// the workload if it's not explicitly specified.
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int actual_num_threads =
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numThreads.isValid() ? numThreads : workload.size();
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(numThreads.isValid() && numThreads >= workload.size()) ?
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numThreads : workload.size();
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if (workload.size() == 0) {
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fatal("Must specify at least one workload!");
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}
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#endif
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AlphaSimpleParams *params = new AlphaSimpleParams;
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@ -371,7 +371,16 @@ CREATE_SIM_OBJECT(DerivO3CPU)
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params->numROBEntries = numROBEntries;
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params->smtNumFetchingThreads = smtNumFetchingThreads;
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params->smtFetchPolicy = smtFetchPolicy;
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// Default smtFetchPolicy to "RoundRobin", if necessary.
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std::string round_robin_policy = "RoundRobin";
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std::string single_thread = "SingleThread";
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if (actual_num_threads > 1 && single_thread.compare(smtFetchPolicy) == 0)
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params->smtFetchPolicy = single_thread;
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else
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params->smtFetchPolicy = smtFetchPolicy;
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params->smtIQPolicy = smtIQPolicy;
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params->smtLSQPolicy = smtLSQPolicy;
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params->smtLSQThreshold = smtLSQThreshold;
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@ -406,8 +406,10 @@ class DefaultCommit
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/** The next PC of each thread. */
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Addr nextPC[Impl::MaxThreads];
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#if THE_ISA != ALPHA_ISA
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/** The next NPC of each thread. */
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Addr nextNPC[Impl::MaxThreads];
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#endif
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/** The sequence number of the youngest valid instruction in the ROB. */
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InstSeqNum youngestSeqNum[Impl::MaxThreads];
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@ -1221,7 +1221,8 @@ DefaultCommit<Impl>::roundRobin()
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unsigned tid = *pri_iter;
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if (commitStatus[tid] == Running ||
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commitStatus[tid] == Idle) {
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commitStatus[tid] == Idle ||
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commitStatus[tid] == FetchTrapPending) {
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if (rob->isHeadReady(tid)) {
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priority_list.erase(pri_iter);
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@ -127,7 +127,7 @@ FullO3CPU<Impl>::FullO3CPU(Params *params)
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regFile(params->numPhysIntRegs, params->numPhysFloatRegs),
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freeList(params->numberOfThreads,//number of activeThreads
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freeList(params->numberOfThreads,
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TheISA::NumIntRegs, params->numPhysIntRegs,
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TheISA::NumFloatRegs, params->numPhysFloatRegs),
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@ -135,7 +135,7 @@ FullO3CPU<Impl>::FullO3CPU(Params *params)
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params->smtROBPolicy, params->smtROBThreshold,
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params->numberOfThreads),
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scoreboard(params->numberOfThreads,//number of activeThreads
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scoreboard(params->numberOfThreads,
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TheISA::NumIntRegs, params->numPhysIntRegs,
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TheISA::NumFloatRegs, params->numPhysFloatRegs,
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TheISA::NumMiscRegs * number_of_threads,
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@ -221,6 +221,12 @@ FullO3CPU<Impl>::FullO3CPU(Params *params)
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#if !FULL_SYSTEM
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int active_threads = params->workload.size();
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if (active_threads > Impl::MaxThreads) {
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panic("Workload Size too large. Increase the 'MaxThreads'"
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"constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) or "
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"edit your workload size.");
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}
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#else
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int active_threads = 1;
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#endif
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@ -114,8 +114,6 @@ DefaultFetch<Impl>::DefaultFetch(Params *params)
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if (numThreads > Impl::MaxThreads)
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fatal("numThreads is not a valid value\n");
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DPRINTF(Fetch, "Fetch constructor called\n");
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// Set fetch stage's status to inactive.
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_status = Inactive;
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@ -128,6 +126,8 @@ DefaultFetch<Impl>::DefaultFetch(Params *params)
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// Figure out fetch policy
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if (policy == "singlethread") {
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fetchPolicy = SingleThread;
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if (numThreads > 1)
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panic("Invalid Fetch Policy for a SMT workload.");
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} else if (policy == "roundrobin") {
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fetchPolicy = RoundRobin;
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DPRINTF(Fetch, "Fetch policy set to Round Robin\n");
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@ -559,7 +559,7 @@ DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid
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return false;
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}
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DPRINTF(Fetch, "Doing cache access.\n");
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DPRINTF(Fetch, "[tid:%i]: Doing cache access.\n", tid);
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lastIcacheStall[tid] = curTick;
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@ -724,12 +724,15 @@ DefaultFetch<Impl>::tick()
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// Reset the number of the instruction we're fetching.
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numInst = 0;
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#if FULL_SYSTEM
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if (fromCommit->commitInfo[0].interruptPending) {
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interruptPending = true;
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}
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if (fromCommit->commitInfo[0].clearInterrupt) {
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interruptPending = false;
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}
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#endif
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for (threadFetched = 0; threadFetched < numFetchingThreads;
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threadFetched++) {
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@ -903,6 +906,8 @@ DefaultFetch<Impl>::fetch(bool &status_change)
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return;
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}
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DPRINTF(Fetch, "Attempting to fetch from [tid:%i]\n", tid);
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// The current PC.
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Addr &fetch_PC = PC[tid];
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@ -1279,6 +1284,6 @@ int
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DefaultFetch<Impl>::branchCount()
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{
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list<unsigned>::iterator threads = (*activeThreads).begin();
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warn("Branch Count Fetch policy unimplemented\n");
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panic("Branch Count Fetch policy unimplemented\n");
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return *threads;
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}
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@ -26,6 +26,7 @@
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Kevin Lim
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* Korey Sewell
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*/
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#ifndef __CPU_O3_INST_QUEUE_HH__
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@ -26,6 +26,7 @@
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Kevin Lim
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* Korey Sewell
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*/
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#include <limits>
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@ -125,7 +126,7 @@ InstructionQueue<Impl>::InstructionQueue(Params *params)
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maxEntries[i] = part_amt;
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}
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DPRINTF(Fetch, "IQ sharing policy set to Partitioned:"
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DPRINTF(IQ, "IQ sharing policy set to Partitioned:"
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"%i entries per thread.\n",part_amt);
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} else if (policy == "threshold") {
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@ -140,7 +141,7 @@ InstructionQueue<Impl>::InstructionQueue(Params *params)
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maxEntries[i] = thresholdIQ;
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}
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DPRINTF(Fetch, "IQ sharing policy set to Threshold:"
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DPRINTF(IQ, "IQ sharing policy set to Threshold:"
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"%i entries per thread.\n",thresholdIQ);
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} else {
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assert(0 && "Invalid IQ Sharing Policy.Options Are:{Dynamic,"
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@ -26,6 +26,7 @@
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Kevin Lim
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* Korey Sewell
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*/
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#ifndef __CPU_O3_ROB_HH__
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@ -26,6 +26,7 @@
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Kevin Lim
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* Korey Sewell
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*/
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#include "config/full_system.hh"
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@ -274,7 +274,7 @@ class MetaSimObject(type):
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cls._values[attr] = value
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else:
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raise AttributeError, \
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"Class %s has no parameter %s" % (cls.__name__, attr)
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"Class %s has no parameter \'%s\'" % (cls.__name__, attr)
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def __getattr__(cls, attr):
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if cls._values.has_key(attr):
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