Make CPU models signal to update the snoop ranges

--HG--
extra : convert_revision : 717b62510f28a69af99453309fbbb458359eeb2a
This commit is contained in:
Ron Dreslinski 2006-11-13 18:51:16 -05:00
parent 023fccff0e
commit a962fc4f56
10 changed files with 56 additions and 8 deletions

View file

@ -81,8 +81,13 @@ MemTest::CpuPort::recvFunctional(PacketPtr pkt)
void
MemTest::CpuPort::recvStatusChange(Status status)
{
if (status == RangeChange)
if (status == RangeChange) {
if (!snoopRangeSent) {
snoopRangeSent = true;
sendStatusChange(Port::RangeChange);
}
return;
}
panic("MemTest doesn't expect recvStatusChange callback!");
}
@ -145,6 +150,9 @@ MemTest::MemTest(const string &name,
// thread = new SimpleThread(NULL, 0, NULL, 0, mainMem);
curTick = 0;
cachePort.snoopRangeSent = false;
funcPort.snoopRangeSent = true;
// Needs to be masked off once we know the block size.
traceBlockAddr = _traceAddr;
baseAddr1 = 0x100000;

View file

@ -100,6 +100,8 @@ class MemTest : public MemObject
: Port(_name, _memtest), memtest(_memtest)
{ }
bool snoopRangeSent;
protected:
virtual bool recvTiming(PacketPtr pkt);
@ -120,6 +122,8 @@ class MemTest : public MemObject
CpuPort cachePort;
CpuPort funcPort;
bool snoopRangeSent;
class MemTestSenderState : public Packet::SenderState
{
public:

View file

@ -83,6 +83,8 @@ class DefaultFetch
: Port(_fetch->name() + "-iport"), fetch(_fetch)
{ }
bool snoopRangeSent;
protected:
/** Atomic version of receive. Panics. */
virtual Tick recvAtomic(PacketPtr pkt);

View file

@ -70,8 +70,13 @@ template<class Impl>
void
DefaultFetch<Impl>::IcachePort::recvStatusChange(Status status)
{
if (status == RangeChange)
if (status == RangeChange) {
if (!snoopRangeSent) {
snoopRangeSent = true;
sendStatusChange(Port::RangeChange);
}
return;
}
panic("DefaultFetch doesn't expect recvStatusChange callback!");
}
@ -287,6 +292,8 @@ DefaultFetch<Impl>::setCPU(O3CPU *cpu_ptr)
// Name is finally available, so create the port.
icachePort = new IcachePort(this);
icachePort->snoopRangeSent = false;
#if USE_CHECKER
if (cpu->checker) {
cpu->checker->setIcachePort(icachePort);

View file

@ -298,6 +298,8 @@ class LSQ {
: lsq(_lsq)
{ }
bool snoopRangeSent;
protected:
/** Atomic version of receive. Panics. */
virtual Tick recvAtomic(PacketPtr pkt);

View file

@ -53,9 +53,13 @@ template <class Impl>
void
LSQ<Impl>::DcachePort::recvStatusChange(Status status)
{
if (status == RangeChange)
if (status == RangeChange) {
if (!snoopRangeSent) {
snoopRangeSent = true;
sendStatusChange(Port::RangeChange);
}
return;
}
panic("O3CPU doesn't expect recvStatusChange callback!");
}
@ -97,6 +101,8 @@ LSQ<Impl>::LSQ(Params *params)
{
DPRINTF(LSQ, "Creating LSQ object.\n");
dcachePort.snoopRangeSent = false;
//**********************************************/
//************ Handle SMT Parameters ***********/
//**********************************************/

View file

@ -107,8 +107,13 @@ AtomicSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt)
void
AtomicSimpleCPU::CpuPort::recvStatusChange(Status status)
{
if (status == RangeChange)
if (status == RangeChange) {
if (!snoopRangeSent) {
snoopRangeSent = true;
sendStatusChange(Port::RangeChange);
}
return;
}
panic("AtomicSimpleCPU doesn't expect recvStatusChange callback!");
}
@ -127,6 +132,9 @@ AtomicSimpleCPU::AtomicSimpleCPU(Params *p)
{
_status = Idle;
icachePort.snoopRangeSent = false;
dcachePort.snoopRangeSent = false;
ifetch_req = new Request();
ifetch_req->setThreadContext(p->cpu_id, 0); // Add thread ID if we add MT
ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast);

View file

@ -90,6 +90,8 @@ class AtomicSimpleCPU : public BaseSimpleCPU
: Port(_name, _cpu), cpu(_cpu)
{ }
bool snoopRangeSent;
protected:
virtual bool recvTiming(PacketPtr pkt);

View file

@ -82,8 +82,13 @@ TimingSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt)
void
TimingSimpleCPU::CpuPort::recvStatusChange(Status status)
{
if (status == RangeChange)
if (status == RangeChange) {
if (!snoopRangeSent) {
snoopRangeSent = true;
sendStatusChange(Port::RangeChange);
}
return;
}
panic("TimingSimpleCPU doesn't expect recvStatusChange callback!");
}
@ -101,6 +106,10 @@ TimingSimpleCPU::TimingSimpleCPU(Params *p)
cpu_id(p->cpu_id)
{
_status = Idle;
icachePort.snoopRangeSent = false;
dcachePort.snoopRangeSent = false;
ifetch_pkt = dcache_pkt = NULL;
drainEvent = NULL;
fetchEvent = NULL;

View file

@ -82,6 +82,8 @@ class TimingSimpleCPU : public BaseSimpleCPU
: Port(_name, _cpu), cpu(_cpu), lat(_lat)
{ }
bool snoopRangeSent;
protected:
virtual Tick recvAtomic(PacketPtr pkt);
@ -166,8 +168,6 @@ class TimingSimpleCPU : public BaseSimpleCPU
PacketPtr ifetch_pkt;
PacketPtr dcache_pkt;
int cpu_id;
Tick previousTick;