Make CPU models signal to update the snoop ranges
--HG-- extra : convert_revision : 717b62510f28a69af99453309fbbb458359eeb2a
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023fccff0e
commit
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10 changed files with 56 additions and 8 deletions
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@ -81,8 +81,13 @@ MemTest::CpuPort::recvFunctional(PacketPtr pkt)
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void
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MemTest::CpuPort::recvStatusChange(Status status)
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{
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if (status == RangeChange)
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if (status == RangeChange) {
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if (!snoopRangeSent) {
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snoopRangeSent = true;
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sendStatusChange(Port::RangeChange);
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}
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return;
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}
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panic("MemTest doesn't expect recvStatusChange callback!");
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}
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@ -145,6 +150,9 @@ MemTest::MemTest(const string &name,
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// thread = new SimpleThread(NULL, 0, NULL, 0, mainMem);
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curTick = 0;
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cachePort.snoopRangeSent = false;
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funcPort.snoopRangeSent = true;
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// Needs to be masked off once we know the block size.
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traceBlockAddr = _traceAddr;
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baseAddr1 = 0x100000;
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@ -100,6 +100,8 @@ class MemTest : public MemObject
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: Port(_name, _memtest), memtest(_memtest)
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{ }
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bool snoopRangeSent;
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protected:
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virtual bool recvTiming(PacketPtr pkt);
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@ -120,6 +122,8 @@ class MemTest : public MemObject
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CpuPort cachePort;
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CpuPort funcPort;
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bool snoopRangeSent;
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class MemTestSenderState : public Packet::SenderState
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{
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public:
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@ -83,6 +83,8 @@ class DefaultFetch
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: Port(_fetch->name() + "-iport"), fetch(_fetch)
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{ }
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bool snoopRangeSent;
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protected:
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/** Atomic version of receive. Panics. */
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virtual Tick recvAtomic(PacketPtr pkt);
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@ -70,8 +70,13 @@ template<class Impl>
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void
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DefaultFetch<Impl>::IcachePort::recvStatusChange(Status status)
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{
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if (status == RangeChange)
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if (status == RangeChange) {
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if (!snoopRangeSent) {
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snoopRangeSent = true;
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sendStatusChange(Port::RangeChange);
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}
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return;
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}
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panic("DefaultFetch doesn't expect recvStatusChange callback!");
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}
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@ -287,6 +292,8 @@ DefaultFetch<Impl>::setCPU(O3CPU *cpu_ptr)
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// Name is finally available, so create the port.
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icachePort = new IcachePort(this);
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icachePort->snoopRangeSent = false;
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#if USE_CHECKER
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if (cpu->checker) {
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cpu->checker->setIcachePort(icachePort);
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@ -298,6 +298,8 @@ class LSQ {
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: lsq(_lsq)
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{ }
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bool snoopRangeSent;
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protected:
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/** Atomic version of receive. Panics. */
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virtual Tick recvAtomic(PacketPtr pkt);
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@ -53,9 +53,13 @@ template <class Impl>
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void
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LSQ<Impl>::DcachePort::recvStatusChange(Status status)
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{
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if (status == RangeChange)
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if (status == RangeChange) {
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if (!snoopRangeSent) {
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snoopRangeSent = true;
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sendStatusChange(Port::RangeChange);
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}
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return;
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}
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panic("O3CPU doesn't expect recvStatusChange callback!");
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}
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@ -97,6 +101,8 @@ LSQ<Impl>::LSQ(Params *params)
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{
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DPRINTF(LSQ, "Creating LSQ object.\n");
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dcachePort.snoopRangeSent = false;
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//**********************************************/
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//************ Handle SMT Parameters ***********/
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//**********************************************/
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@ -107,8 +107,13 @@ AtomicSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt)
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void
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AtomicSimpleCPU::CpuPort::recvStatusChange(Status status)
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{
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if (status == RangeChange)
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if (status == RangeChange) {
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if (!snoopRangeSent) {
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snoopRangeSent = true;
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sendStatusChange(Port::RangeChange);
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}
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return;
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}
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panic("AtomicSimpleCPU doesn't expect recvStatusChange callback!");
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}
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@ -127,6 +132,9 @@ AtomicSimpleCPU::AtomicSimpleCPU(Params *p)
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{
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_status = Idle;
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icachePort.snoopRangeSent = false;
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dcachePort.snoopRangeSent = false;
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ifetch_req = new Request();
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ifetch_req->setThreadContext(p->cpu_id, 0); // Add thread ID if we add MT
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ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast);
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@ -90,6 +90,8 @@ class AtomicSimpleCPU : public BaseSimpleCPU
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: Port(_name, _cpu), cpu(_cpu)
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{ }
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bool snoopRangeSent;
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protected:
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virtual bool recvTiming(PacketPtr pkt);
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@ -82,8 +82,13 @@ TimingSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt)
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void
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TimingSimpleCPU::CpuPort::recvStatusChange(Status status)
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{
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if (status == RangeChange)
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if (status == RangeChange) {
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if (!snoopRangeSent) {
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snoopRangeSent = true;
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sendStatusChange(Port::RangeChange);
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}
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return;
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}
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panic("TimingSimpleCPU doesn't expect recvStatusChange callback!");
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}
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@ -101,6 +106,10 @@ TimingSimpleCPU::TimingSimpleCPU(Params *p)
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cpu_id(p->cpu_id)
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{
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_status = Idle;
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icachePort.snoopRangeSent = false;
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dcachePort.snoopRangeSent = false;
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ifetch_pkt = dcache_pkt = NULL;
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drainEvent = NULL;
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fetchEvent = NULL;
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@ -82,6 +82,8 @@ class TimingSimpleCPU : public BaseSimpleCPU
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: Port(_name, _cpu), cpu(_cpu), lat(_lat)
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{ }
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bool snoopRangeSent;
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protected:
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virtual Tick recvAtomic(PacketPtr pkt);
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@ -166,8 +168,6 @@ class TimingSimpleCPU : public BaseSimpleCPU
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PacketPtr ifetch_pkt;
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PacketPtr dcache_pkt;
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int cpu_id;
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Tick previousTick;
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