Support Ron's changes for hooking up ports.

src/cpu/checker/cpu.hh:
    Now that BaseCPU is a MemObject, the checker must define this function.
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/iew.hh:
src/cpu/o3/lsq.hh:
src/cpu/o3/lsq_unit.hh:
    Implement getPort function so the connector can connect the ports properly.
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/lsq_unit_impl.hh:
    The connector handles connecting the ports now.
src/python/m5/objects/O3CPU.py:
    Add ports to the parameters.

--HG--
extra : convert_revision : 0b1a216b9a5d0574e62165d7c6c242498104d918

src/cpu/checker/cpu.hh

@@ -127,6 +127,12 @@ class CheckerCPU : public BaseCPU
 
     Port *dcachePort;
 
+    virtual Port *getPort(const std::string &name, int idx)
+    {
+        panic("Not supported on checker!");
+        return NULL;
+    }
+
   public:
     // Primary thread being run.
     SimpleThread *thread;

src/cpu/o3/cpu.cc

@@ -360,6 +360,18 @@ FullO3CPU<Impl>::fullCPURegStats()
 
 }
 
+template <class Impl>
+Port *
+FullO3CPU<Impl>::getPort(const std::string &if_name, int idx)
+{
+    if (if_name == "dcache_port")
+        return iew.getDcachePort();
+    else if (if_name == "icache_port")
+        return fetch.getIcachePort();
+    else
+        panic("No Such Port\n");
+}
+
 template <class Impl>
 void
 FullO3CPU<Impl>::tick()

src/cpu/o3/cpu.hh

@@ -208,6 +208,9 @@ class FullO3CPU : public BaseO3CPU
     /** Registers statistics. */
     void fullCPURegStats();
 
+    /** Returns a specific port. */
+    Port *getPort(const std::string &if_name, int idx);
+
     /** Ticks CPU, calling tick() on each stage, and checking the overall
      *  activity to see if the CPU should deschedule itself.
      */

src/cpu/o3/fetch.hh

@@ -162,6 +162,9 @@ class DefaultFetch
     /** Registers statistics. */
     void regStats();
 
+    /** Returns the icache port. */
+    Port *getIcachePort() { return icachePort; }
+
     /** Sets CPU pointer. */
     void setCPU(O3CPU *cpu_ptr);
 

src/cpu/o3/fetch_impl.hh

@@ -280,10 +280,6 @@ DefaultFetch<Impl>::setCPU(O3CPU *cpu_ptr)
     // Name is finally available, so create the port.
     icachePort = new IcachePort(this);
 
-    Port *mem_dport = mem->getPort("");
-    icachePort->setPeer(mem_dport);
-    mem_dport->setPeer(icachePort);
-
 #if USE_CHECKER
     if (cpu->checker) {
         cpu->checker->setIcachePort(icachePort);

src/cpu/o3/iew.hh

@@ -125,6 +125,9 @@ class DefaultIEW
     /** Initializes stage; sends back the number of free IQ and LSQ entries. */
     void initStage();
 
+    /** Returns the dcache port. */
+    Port *getDcachePort() { return ldstQueue.getDcachePort(); }
+
     /** Sets CPU pointer for IEW, IQ, and LSQ. */
     void setCPU(O3CPU *cpu_ptr);
 

src/cpu/o3/lsq.hh

@@ -65,6 +65,13 @@ class LSQ {
     /** Registers statistics of each LSQ unit. */
     void regStats();
 
+    /** Returns dcache port.
+     *  @todo: Dcache port needs to be moved up to this level for SMT
+     *  to work.  For now it just returns the port from one of the
+     *  threads.
+     */
+    Port *getDcachePort() { return thread[0].getDcachePort(); }
+
     /** Sets the pointer to the list of active threads. */
     void setActiveThreads(std::list<unsigned> *at_ptr);
     /** Sets the CPU pointer. */

src/cpu/o3/lsq_unit.hh

@@ -77,6 +77,11 @@ class LSQUnit {
     /** Returns the name of the LSQ unit. */
     std::string name() const;
 
+    /** Returns the dcache port.
+     *  @todo: Remove this once the port moves up to the LSQ level.
+     */
+    Port *getDcachePort() { return dcachePort; }
+
     /** Registers statistics. */
     void regStats();
 

src/cpu/o3/lsq_unit_impl.hh

@@ -182,10 +182,6 @@ LSQUnit<Impl>::setCPU(O3CPU *cpu_ptr)
     cpu = cpu_ptr;
     dcachePort = new DcachePort(cpu, this);
 
-    Port *mem_dport = mem->getPort("");
-    dcachePort->setPeer(mem_dport);
-    mem_dport->setPeer(dcachePort);
-
 #if USE_CHECKER
     if (cpu->checker) {
         cpu->checker->setDcachePort(dcachePort);

src/python/m5/objects/O3CPU.py

@@ -10,6 +10,8 @@ class DerivO3CPU(BaseCPU):
     checker = Param.BaseCPU(NULL, "checker")
 
     cachePorts = Param.Unsigned("Cache Ports")
+    icache_port = Port("Instruction Port")
+    dcache_port = Port("Data Port")
 
     decodeToFetchDelay = Param.Unsigned("Decode to fetch delay")
     renameToFetchDelay = Param.Unsigned("Rename to fetch delay")