Got rid of some typedefs, moved the tlbs to the base o3 cpu, and called the architecture defined setSyscallReturn function instead of a duplicate copy.
src/cpu/o3/alpha/cpu.hh:
Got rid of some typedefs, and moved the tlbs to the base o3 cpu.
src/cpu/o3/alpha/thread_context.hh:
src/cpu/o3/cpu.cc:
Moved the tlbs to the base o3 cpu.
--HG--
extra : convert_revision : 1805613aa230b8974a226ee3d2584c85f7a578aa
This commit is contained in:
Gabe Black
parent
0ed6c52c1e
commit
6826ee53db
5 changed files with 35 additions and 69 deletions
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@ -37,12 +37,6 @@
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#include "cpu/o3/cpu.hh"
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#include "sim/byteswap.hh"
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namespace TheISA
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{
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class ITB;
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class DTB;
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}
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class EndQuiesceEvent;
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namespace Kernel {
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class Statistics;
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@ -61,14 +55,6 @@ class TranslatingPort;
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template <class Impl>
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class AlphaO3CPU : public FullO3CPU<Impl>
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{
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protected:
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typedef TheISA::IntReg IntReg;
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typedef TheISA::FloatReg FloatReg;
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typedef TheISA::FloatRegBits FloatRegBits;
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typedef TheISA::MiscReg MiscReg;
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typedef TheISA::RegFile RegFile;
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typedef TheISA::MiscRegFile MiscRegFile;
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public:
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typedef O3ThreadState<Impl> ImplState;
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typedef O3ThreadState<Impl> Thread;
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@ -77,13 +63,6 @@ class AlphaO3CPU : public FullO3CPU<Impl>
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/** Constructs an AlphaO3CPU with the given parameters. */
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AlphaO3CPU(Params *params);
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#if FULL_SYSTEM
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/** ITB pointer. */
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AlphaISA::ITB *itb;
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/** DTB pointer. */
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AlphaISA::DTB *dtb;
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#endif
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/** Registers statistics. */
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void regStats();
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@ -91,19 +70,19 @@ class AlphaO3CPU : public FullO3CPU<Impl>
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/** Translates instruction requestion. */
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Fault translateInstReq(RequestPtr &req, Thread *thread)
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{
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return itb->translate(req, thread->getTC());
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return this->itb->translate(req, thread->getTC());
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}
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/** Translates data read request. */
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Fault translateDataReadReq(RequestPtr &req, Thread *thread)
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{
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return dtb->translate(req, thread->getTC(), false);
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return this->dtb->translate(req, thread->getTC(), false);
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}
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/** Translates data write request. */
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Fault translateDataWriteReq(RequestPtr &req, Thread *thread)
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{
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return dtb->translate(req, thread->getTC(), true);
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return this->dtb->translate(req, thread->getTC(), true);
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}
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#else
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@ -127,20 +106,22 @@ class AlphaO3CPU : public FullO3CPU<Impl>
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#endif
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/** Reads a miscellaneous register. */
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MiscReg readMiscReg(int misc_reg, unsigned tid);
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TheISA::MiscReg readMiscReg(int misc_reg, unsigned tid);
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/** Reads a misc. register, including any side effects the read
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* might have as defined by the architecture.
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*/
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MiscReg readMiscRegWithEffect(int misc_reg, unsigned tid);
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TheISA::MiscReg readMiscRegWithEffect(int misc_reg, unsigned tid);
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/** Sets a miscellaneous register. */
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void setMiscReg(int misc_reg, const MiscReg &val, unsigned tid);
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void setMiscReg(int misc_reg, const TheISA::MiscReg &val,
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unsigned tid);
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/** Sets a misc. register, including any side effects the write
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* might have as defined by the architecture.
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*/
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void setMiscRegWithEffect(int misc_reg, const MiscReg &val, unsigned tid);
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void setMiscRegWithEffect(int misc_reg, const TheISA::MiscReg &val,
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unsigned tid);
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/** Initiates a squash of all in-flight instructions for a given
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* thread. The source of the squash is an external update of
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@ -175,10 +156,10 @@ class AlphaO3CPU : public FullO3CPU<Impl>
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*/
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void syscall(int64_t callnum, int tid);
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/** Gets a syscall argument. */
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IntReg getSyscallArg(int i, int tid);
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TheISA::IntReg getSyscallArg(int i, int tid);
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/** Used to shift args for indirect syscall. */
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void setSyscallArg(int i, IntReg val, int tid);
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void setSyscallArg(int i, TheISA::IntReg val, int tid);
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/** Sets the return value of a syscall. */
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void setSyscallReturn(SyscallReturn return_value, int tid);
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@ -55,12 +55,7 @@
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#endif
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template <class Impl>
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AlphaO3CPU<Impl>::AlphaO3CPU(Params *params)
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#if FULL_SYSTEM
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: FullO3CPU<Impl>(params), itb(params->itb), dtb(params->dtb)
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#else
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: FullO3CPU<Impl>(params)
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#endif
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AlphaO3CPU<Impl>::AlphaO3CPU(Params *params) : FullO3CPU<Impl>(params)
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{
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DPRINTF(O3CPU, "Creating AlphaO3CPU object.\n");
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@ -173,15 +168,16 @@ AlphaO3CPU<Impl>::readMiscRegWithEffect(int misc_reg, unsigned tid)
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template <class Impl>
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void
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AlphaO3CPU<Impl>::setMiscReg(int misc_reg, const MiscReg &val, unsigned tid)
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AlphaO3CPU<Impl>::setMiscReg(int misc_reg, const TheISA::MiscReg &val,
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unsigned tid)
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{
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this->regFile.setMiscReg(misc_reg, val, tid);
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}
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template <class Impl>
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void
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AlphaO3CPU<Impl>::setMiscRegWithEffect(int misc_reg, const MiscReg &val,
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unsigned tid)
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AlphaO3CPU<Impl>::setMiscRegWithEffect(int misc_reg,
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const TheISA::MiscReg &val, unsigned tid)
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{
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this->regFile.setMiscRegWithEffect(misc_reg, val, tid);
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}
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@ -315,7 +311,7 @@ AlphaO3CPU<Impl>::getSyscallArg(int i, int tid)
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template <class Impl>
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void
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AlphaO3CPU<Impl>::setSyscallArg(int i, IntReg val, int tid)
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AlphaO3CPU<Impl>::setSyscallArg(int i, TheISA::IntReg val, int tid)
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{
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this->setArchIntReg(AlphaISA::ArgumentReg0 + i, val, tid);
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}
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@ -324,17 +320,6 @@ template <class Impl>
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void
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AlphaO3CPU<Impl>::setSyscallReturn(SyscallReturn return_value, int tid)
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{
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// check for error condition. Alpha syscall convention is to
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// indicate success/failure in reg a3 (r19) and put the
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// return value itself in the standard return value reg (v0).
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if (return_value.successful()) {
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// no error
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this->setArchIntReg(TheISA::SyscallSuccessReg, 0, tid);
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this->setArchIntReg(TheISA::ReturnValueReg, return_value.value(), tid);
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} else {
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// got an error, return details
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this->setArchIntReg(TheISA::SyscallSuccessReg, (IntReg) -1, tid);
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this->setArchIntReg(TheISA::ReturnValueReg, -return_value.value(), tid);
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}
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TheISA::setSyscallReturn(return_value, this->tcBase(tid));
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}
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#endif
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@ -36,12 +36,6 @@ class AlphaTC : public O3ThreadContext<Impl>
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{
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public:
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#if FULL_SYSTEM
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/** Returns a pointer to the ITB. */
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virtual AlphaISA::ITB *getITBPtr() { return this->cpu->itb; }
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/** Returns a pointer to the DTB. */
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virtual AlphaISA::DTB *getDTBPtr() { return this->cpu->dtb; }
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/** Returns pointer to the quiesce event. */
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virtual EndQuiesceEvent *getQuiesceEvent()
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{
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@ -149,6 +149,10 @@ FullO3CPU<Impl>::DeallocateContextEvent::description()
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template <class Impl>
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FullO3CPU<Impl>::FullO3CPU(Params *params)
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: BaseO3CPU(params),
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#if FULL_SYSTEM
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itb(params->itb),
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dtb(params->dtb),
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#endif
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tickEvent(this),
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removeInstsThisCycle(false),
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fetch(params),
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@ -91,9 +91,6 @@ template <class Impl>
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class FullO3CPU : public BaseO3CPU
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{
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public:
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typedef TheISA::FloatReg FloatReg;
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typedef TheISA::FloatRegBits FloatRegBits;
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// Typedefs from the Impl here.
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typedef typename Impl::CPUPol CPUPolicy;
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typedef typename Impl::Params Params;
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@ -114,6 +111,11 @@ class FullO3CPU : public BaseO3CPU
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SwitchedOut
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};
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#if FULL_SYSTEM
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TheISA::ITB * itb;
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TheISA::DTB * dtb;
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#endif
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/** Overall CPU status. */
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Status _status;
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@ -382,23 +384,23 @@ class FullO3CPU : public BaseO3CPU
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/** Register accessors. Index refers to the physical register index. */
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uint64_t readIntReg(int reg_idx);
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FloatReg readFloatReg(int reg_idx);
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TheISA::FloatReg readFloatReg(int reg_idx);
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FloatReg readFloatReg(int reg_idx, int width);
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TheISA::FloatReg readFloatReg(int reg_idx, int width);
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FloatRegBits readFloatRegBits(int reg_idx);
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TheISA::FloatRegBits readFloatRegBits(int reg_idx);
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FloatRegBits readFloatRegBits(int reg_idx, int width);
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TheISA::FloatRegBits readFloatRegBits(int reg_idx, int width);
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void setIntReg(int reg_idx, uint64_t val);
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void setFloatReg(int reg_idx, FloatReg val);
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void setFloatReg(int reg_idx, TheISA::FloatReg val);
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void setFloatReg(int reg_idx, FloatReg val, int width);
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void setFloatReg(int reg_idx, TheISA::FloatReg val, int width);
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void setFloatRegBits(int reg_idx, FloatRegBits val);
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void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val);
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void setFloatRegBits(int reg_idx, FloatRegBits val, int width);
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void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val, int width);
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uint64_t readArchIntReg(int reg_idx, unsigned tid);
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