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Change how optional delay slot instructions are detected and squashed.

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--HG--
extra : convert_revision : ffd019d4adc2fbbc0a663d8dc6ef73edce12511b
This commit is contained in:
Gabe Black 2006-12-06 05:51:18 -05:00
parent 8a21635eff
commit 20340b5e26
3 changed files with 22 additions and 29 deletions
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2
src/cpu/o3/comm.hh
View file

@ -87,7 +87,7 @@ struct DefaultIEWDefaultCommit {
bool squash[Impl::MaxThreads];
bool branchMispredict[Impl::MaxThreads];
bool branchTaken[Impl::MaxThreads];
bool condDelaySlotBranch[Impl::MaxThreads];
bool squashDelaySlot[Impl::MaxThreads];
uint64_t mispredPC[Impl::MaxThreads];
uint64_t nextPC[Impl::MaxThreads];
InstSeqNum squashedSeqNum[Impl::MaxThreads];

27
src/cpu/o3/commit_impl.hh
View file

@ -728,27 +728,12 @@ DefaultCommit<Impl>::commit()
InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
#if ISA_HAS_DELAY_SLOT
InstSeqNum bdelay_done_seq_num;
bool squash_bdelay_slot;
InstSeqNum bdelay_done_seq_num = squashed_inst;
bool squash_bdelay_slot = fromIEW->squashDelaySlot[tid];
if (!squash_bdelay_slot)
bdelay_done_seq_num++;
if (fromIEW->branchMispredict[tid]) {
if (fromIEW->branchTaken[tid] &&
fromIEW->condDelaySlotBranch[tid]) {
DPRINTF(Commit, "[tid:%i]: Cond. delay slot branch"
"mispredicted as taken. Squashing after previous "
"inst, [sn:%i]\n",
tid, squashed_inst);
bdelay_done_seq_num = squashed_inst;
squash_bdelay_slot = true;
} else {
DPRINTF(Commit, "[tid:%i]: Branch Mispredict. Squashing "
"after delay slot [sn:%i]\n", tid, squashed_inst+1);
bdelay_done_seq_num = squashed_inst + 1;
squash_bdelay_slot = false;
}
} else {
bdelay_done_seq_num = squashed_inst;
}
#endif
if (fromIEW->includeSquashInst[tid] == true) {
@ -1116,7 +1101,7 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
// Update the commit rename map
for (int i = 0; i < head_inst->numDestRegs(); i++) {
renameMap[tid]->setEntry(head_inst->destRegIdx(i),
renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i),
head_inst->renamedDestRegIdx(i));
}

22
src/cpu/o3/iew_impl.hh
View file

@ -481,18 +481,26 @@ DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, unsigned tid)
toCommit->branchMispredict[tid] = true;
#if ISA_HAS_DELAY_SLOT
bool branch_taken = inst->readNextNPC() !=
(inst->readNextPC() + sizeof(TheISA::MachInst));
bool branch_taken =
(inst->readNextNPC() != (inst->readPC() + 2 * sizeof(TheISA::MachInst)) &&
inst->readNextNPC() != (inst->readPC() + 3 * sizeof(TheISA::MachInst)));
DPRINTF(Sparc, "Branch taken = %s [sn:%i]\n",
branch_taken ? "true": "false", inst->seqNum);
toCommit->branchTaken[tid] = branch_taken;
toCommit->condDelaySlotBranch[tid] = inst->isCondDelaySlot();
if (inst->isCondDelaySlot() && branch_taken) {
bool squashDelaySlot =
(inst->readNextPC() != inst->readPC() + sizeof(TheISA::MachInst));
DPRINTF(Sparc, "Squash delay slot = %s [sn:%i]\n",
squashDelaySlot ? "true": "false", inst->seqNum);
toCommit->squashDelaySlot[tid] = squashDelaySlot;
//If we're squashing the delay slot, we need to pick back up at NextPC.
//Otherwise, NextPC isn't being squashed, so we should pick back up at
//NextNPC.
if (squashDelaySlot)
toCommit->nextPC[tid] = inst->readNextPC();
} else {
else
toCommit->nextPC[tid] = inst->readNextNPC();
}
#else
toCommit->branchTaken[tid] = inst->readNextPC() !=
(inst->readPC() + sizeof(TheISA::MachInst));