gem5/src/cpu/o3
Ron Dreslinski 210e73f2a2 Small changes:
?? doesn't compile in warn statements
Should have been false, where I had a true.

src/cpu/o3/lsq_impl.hh:
    Apparently you can't have ?? in a warn statement (Something about trigraphs)
src/mem/cache/cache_impl.hh:
    Forgot to signal atomic mode in snoopProbe

--HG--
extra : convert_revision : c75cb76e193e852284564993440c8ea39e6de426
2006-10-19 20:18:17 -04:00
..
alpha Updates to fix merge issues and bring almost everything up to working speed. Ozone CPU remains untested, but everything else compiles and runs. 2006-10-02 11:58:09 -04:00
mips Cleaned up include files and got rid of many using directives in header files. 2006-08-15 05:07:15 -04:00
2bit_local_pred.cc Merge ktlim@zamp:/z/ktlim2/clean/m5-o3 2006-06-04 16:07:54 -04:00
2bit_local_pred.hh Cleaned up include files and got rid of many using directives in header files. 2006-08-15 05:07:15 -04:00
base_dyn_inst.cc now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory 2006-06-30 20:49:31 -04:00
bpred_unit.cc now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory 2006-06-30 20:49:31 -04:00
bpred_unit.hh Cleaned up include files and got rid of many using directives in header files. 2006-08-15 05:07:15 -04:00
bpred_unit_impl.hh add ISA_HAS_DELAY_SLOT directive instead of "#if THE_ISA == ALPHA_ISA" throughout CPU models 2006-08-31 20:51:30 -04:00
btb.cc Cleaned up include files and got rid of many using directives in header files. 2006-08-15 05:07:15 -04:00
btb.hh Cleaned up include files and got rid of many using directives in header files. 2006-08-15 05:07:15 -04:00
checker_builder.cc Updates to fix merge issues and bring almost everything up to working speed. Ozone CPU remains untested, but everything else compiles and runs. 2006-10-02 11:58:09 -04:00
comm.hh Cleaned up include files and got rid of many using directives in header files. 2006-08-15 05:07:15 -04:00
commit.cc now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory 2006-06-30 20:49:31 -04:00
commit.hh Cleaned up include files and got rid of many using directives in header files. 2006-08-15 05:07:15 -04:00
commit_impl.hh Updates to O3 CPU. It should now work in FS mode, although sampling still has a bug. 2006-10-08 00:53:41 -04:00
cpu.cc only do this assert after you know you're not switched out or idle. 2006-10-18 17:59:11 -04:00
cpu.hh Updates to O3 CPU. It should now work in FS mode, although sampling still has a bug. 2006-10-08 00:53:41 -04:00
cpu_policy.hh Merge ktlim@zamp:/z/ktlim2/clean/m5-o3 2006-06-04 16:07:54 -04:00
decode.cc now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory 2006-06-30 20:49:31 -04:00
decode.hh This changeset gets the MIPS ISA pretty much working in the O3CPU. It builds, runs, and gets very very close to completing the hello world 2006-07-23 13:39:42 -04:00
decode_impl.hh add ISA_HAS_DELAY_SLOT directive instead of "#if THE_ISA == ALPHA_ISA" throughout CPU models 2006-08-31 20:51:30 -04:00
dep_graph.hh Miscellaneous minor fixes. 2006-06-16 17:15:18 -04:00
dyn_inst.hh Started to add support for O3 for sparc. 2006-08-11 20:29:15 -04:00
fetch.cc now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory 2006-06-30 20:49:31 -04:00
fetch.hh Have cpus send snoop ranges 2006-10-09 01:04:37 -04:00
fetch_impl.hh Fixes for uni-coherence in timing mode for FS. 2006-10-17 18:50:19 -04:00
free_list.cc Merge ktlim@zizzer:/bk/newmem 2006-06-02 18:19:50 -04:00
free_list.hh Merge ktlim@zizzer:/bk/newmem 2006-06-02 18:19:50 -04:00
fu_pool.cc Reorganization to move FuncUnit, FUDesc, and OpDesc out of the encumbered directory and into the normal cpu directory. 2006-06-16 17:52:15 -04:00
fu_pool.hh Update copyright. 2006-06-07 16:02:55 -04:00
iew.cc now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory 2006-06-30 20:49:31 -04:00
iew.hh Merge ktlim@zamp:./local/clean/o3-merge/m5 2006-09-30 23:43:23 -04:00
iew_impl.hh Updates to O3 CPU. It should now work in FS mode, although sampling still has a bug. 2006-10-08 00:53:41 -04:00
inst_queue.cc now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory 2006-06-30 20:49:31 -04:00
inst_queue.hh Merge ktlim@zamp:./local/clean/o3-merge/m5 2006-09-30 23:43:23 -04:00
inst_queue_impl.hh Merge ktlim@zamp:./local/clean/o3-merge/m5 2006-09-30 23:43:23 -04:00
isa_specific.hh This changeset gets the MIPS ISA pretty much working in the O3CPU. It builds, runs, and gets very very close to completing the hello world 2006-07-23 13:39:42 -04:00
lsq.cc now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory 2006-06-30 20:49:31 -04:00
lsq.hh Have cpus send snoop ranges 2006-10-09 01:04:37 -04:00
lsq_impl.hh Small changes: 2006-10-19 20:18:17 -04:00
lsq_unit.cc now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory 2006-06-30 20:49:31 -04:00
lsq_unit.hh Merge ktlim@zizzer:/bk/newmem 2006-10-09 22:59:56 -04:00
lsq_unit_impl.hh Merge ktlim@zizzer:/bk/newmem 2006-10-09 22:59:56 -04:00
mem_dep_unit.cc now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory 2006-06-30 20:49:31 -04:00
mem_dep_unit.hh Merge ktlim@zamp:/z/ktlim2/clean/m5-o3 2006-06-04 16:07:54 -04:00
mem_dep_unit_impl.hh Merge ktlim@zamp:./local/clean/o3-merge/m5 2006-09-30 23:43:23 -04:00
params.hh Add parameters for backwards and forwards sizes for time buffers. 2006-07-10 15:40:28 -04:00
ras.cc Merge ktlim@zizzer:/bk/newmem 2006-06-02 18:19:50 -04:00
ras.hh Cleaned up include files and got rid of many using directives in header files. 2006-08-15 05:07:15 -04:00
regfile.hh Cleaned up include files and got rid of many using directives in header files. 2006-08-15 05:07:15 -04:00
rename.cc now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory 2006-06-30 20:49:31 -04:00
rename.hh Merge ktlim@zamp:./local/clean/o3-merge/m5 2006-09-30 23:43:23 -04:00
rename_impl.hh Merge ktlim@zamp:./local/clean/o3-merge/m5 2006-09-30 23:43:23 -04:00
rename_map.cc Merge ktlim@zizzer:/bk/newmem 2006-06-02 18:19:50 -04:00
rename_map.hh Cleaned up include files and got rid of many using directives in header files. 2006-08-15 05:07:15 -04:00
rob.cc now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory 2006-06-30 20:49:31 -04:00
rob.hh Minor fix for SMT Hello Worlds to finish correctly. 2006-07-07 15:58:03 -04:00
rob_impl.hh Cleaned up include files and got rid of many using directives in header files. 2006-08-15 05:07:15 -04:00
sat_counter.cc Merge ktlim@zizzer:/bk/newmem 2006-06-02 18:19:50 -04:00
sat_counter.hh Merge ktlim@zizzer:/bk/newmem 2006-06-02 18:19:50 -04:00
SConscript Started to add support for O3 for sparc. 2006-08-11 20:29:15 -04:00
scoreboard.cc Update copyright. 2006-06-07 16:02:55 -04:00
scoreboard.hh Cleaned up include files and got rid of many using directives in header files. 2006-08-15 05:07:15 -04:00
store_set.cc Fixes to get new CPU model working for simple test case. The CPU does not yet support retrying accesses. 2006-06-05 18:14:39 -04:00
store_set.hh Cleaned up include files and got rid of many using directives in header files. 2006-08-15 05:07:15 -04:00
thread_context.hh This changeset gets the MIPS ISA pretty much working in the O3CPU. It builds, runs, and gets very very close to completing the hello world 2006-07-23 13:39:42 -04:00
thread_context_impl.hh Updates to O3 CPU. It should now work in FS mode, although sampling still has a bug. 2006-10-08 00:53:41 -04:00
thread_state.hh Updates to fix merge issues and bring almost everything up to working speed. Ozone CPU remains untested, but everything else compiles and runs. 2006-10-02 11:58:09 -04:00
tournament_pred.cc Merge ktlim@zamp:./local/clean/o3-merge/m5 2006-09-30 23:43:23 -04:00
tournament_pred.hh Merge ktlim@zamp:./local/clean/o3-merge/m5 2006-09-30 23:43:23 -04:00