Got rid of some typedefs and moved the tlbs into the base o3 cpu.

--HG--
extra : convert_revision : dcd1d2a64fd91aded15c8c763a78b4eebf421870

src/cpu/o3/sparc/cpu.hh

@@ -37,12 +37,6 @@
 #include "cpu/o3/cpu.hh"
 #include "sim/byteswap.hh"
 
-namespace TheISA
-{
-    class ITB;
-    class DTB;
-}
-
 class EndQuiesceEvent;
 namespace Kernel {
     class Statistics;
@@ -61,14 +55,6 @@ class TranslatingPort;
 template <class Impl>
 class SparcO3CPU : public FullO3CPU<Impl>
 {
-  protected:
-    typedef TheISA::IntReg IntReg;
-    typedef TheISA::FloatReg FloatReg;
-    typedef TheISA::FloatRegBits FloatRegBits;
-    typedef TheISA::MiscReg MiscReg;
-    typedef TheISA::RegFile RegFile;
-    typedef TheISA::MiscRegFile MiscRegFile;
-
   public:
     typedef O3ThreadState<Impl> ImplState;
     typedef O3ThreadState<Impl> Thread;
@@ -77,13 +63,6 @@ class SparcO3CPU : public FullO3CPU<Impl>
     /** Constructs an AlphaO3CPU with the given parameters. */
     SparcO3CPU(Params *params);
 
-#if FULL_SYSTEM
-    /** ITB pointer. */
-    SparcISA::ITB *itb;
-    /** DTB pointer. */
-    SparcISA::DTB *dtb;
-#endif
-
     /** Registers statistics. */
     void regStats();
 
@@ -91,19 +70,19 @@ class SparcO3CPU : public FullO3CPU<Impl>
     /** Translates instruction requestion. */
     Fault translateInstReq(RequestPtr &req, Thread *thread)
     {
-        return itb->translate(req, thread->getTC());
+        return this->itb->translate(req, thread->getTC());
     }
 
     /** Translates data read request. */
     Fault translateDataReadReq(RequestPtr &req, Thread *thread)
     {
-        return dtb->translate(req, thread->getTC(), false);
+        return this->dtb->translate(req, thread->getTC(), false);
     }
 
     /** Translates data write request. */
     Fault translateDataWriteReq(RequestPtr &req, Thread *thread)
     {
-        return dtb->translate(req, thread->getTC(), true);
+        return this->dtb->translate(req, thread->getTC(), true);
     }
 
 #else
@@ -127,20 +106,21 @@ class SparcO3CPU : public FullO3CPU<Impl>
 
 #endif
     /** Reads a miscellaneous register. */
-    MiscReg readMiscReg(int misc_reg, unsigned tid);
+    TheISA::MiscReg readMiscReg(int misc_reg, unsigned tid);
 
     /** Reads a misc. register, including any side effects the read
      * might have as defined by the architecture.
      */
-    MiscReg readMiscRegWithEffect(int misc_reg, unsigned tid);
+    TheISA::MiscReg readMiscRegWithEffect(int misc_reg, unsigned tid);
 
     /** Sets a miscellaneous register. */
-    void setMiscReg(int misc_reg, const MiscReg &val, unsigned tid);
+    void setMiscReg(int misc_reg, const TheISA::MiscReg &val, unsigned tid);
 
     /** Sets a misc. register, including any side effects the write
      * might have as defined by the architecture.
      */
-    void setMiscRegWithEffect(int misc_reg, const MiscReg &val, unsigned tid);
+    void setMiscRegWithEffect(int misc_reg, const TheISA::MiscReg &val,
+            unsigned tid);
 
     /** Initiates a squash of all in-flight instructions for a given
      * thread.  The source of the squash is an external update of
@@ -148,24 +128,6 @@ class SparcO3CPU : public FullO3CPU<Impl>
      */
     void squashFromTC(unsigned tid);
 
-#if FULL_SYSTEM
-    /** Posts an interrupt. */
-    void post_interrupt(int int_num, int index);
-    /** HW return from error interrupt. */
-    Fault hwrei(unsigned tid);
-
-    bool simPalCheck(int palFunc, unsigned tid);
-
-    /** Returns the Fault for any valid interrupt. */
-    Fault getInterrupts();
-
-    /** Processes any an interrupt fault. */
-    void processInterrupts(Fault interrupt);
-
-    /** Halts the CPU. */
-    void halt() { panic("Halt not implemented!\n"); }
-#endif
-
     /** Traps to handle given fault. */
     void trap(Fault fault, unsigned tid);
 
@@ -175,10 +137,10 @@ class SparcO3CPU : public FullO3CPU<Impl>
      */
     void syscall(int64_t callnum, int tid);
     /** Gets a syscall argument. */
-    IntReg getSyscallArg(int i, int tid);
+    TheISA::IntReg getSyscallArg(int i, int tid);
 
     /** Used to shift args for indirect syscall. */
-    void setSyscallArg(int i, IntReg val, int tid);
+    void setSyscallArg(int i, TheISA::IntReg val, int tid);
 
     /** Sets the return value of a syscall. */
     void setSyscallReturn(SyscallReturn return_value, int tid);
@@ -204,4 +166,4 @@ class SparcO3CPU : public FullO3CPU<Impl>
     bool lockFlag;
 };
 
-#endif // __CPU_O3_ALPHA_CPU_HH__
+#endif // __CPU_O3_SPARC_CPU_HH__

src/cpu/o3/sparc/cpu_impl.hh

@@ -55,12 +55,7 @@
 #endif
 
 template <class Impl>
-SparcO3CPU<Impl>::SparcO3CPU(Params *params)
-#if FULL_SYSTEM
-    : FullO3CPU<Impl>(params), itb(params->itb), dtb(params->dtb)
-#else
-    : FullO3CPU<Impl>(params)
-#endif
+SparcO3CPU<Impl>::SparcO3CPU(Params *params) : FullO3CPU<Impl>(params)
 {
     DPRINTF(O3CPU, "Creating SparcO3CPU object.\n");
 
@@ -172,15 +167,16 @@ SparcO3CPU<Impl>::readMiscRegWithEffect(int misc_reg, unsigned tid)
 
 template <class Impl>
 void
-SparcO3CPU<Impl>::setMiscReg(int misc_reg, const MiscReg &val, unsigned tid)
+SparcO3CPU<Impl>::setMiscReg(int misc_reg,
+        const SparcISA::MiscReg &val, unsigned tid)
 {
     this->regFile.setMiscReg(misc_reg, val, tid);
 }
 
 template <class Impl>
 void
-SparcO3CPU<Impl>::setMiscRegWithEffect(int misc_reg, const MiscReg &val,
-                                       unsigned tid)
+SparcO3CPU<Impl>::setMiscRegWithEffect(int misc_reg,
+        const SparcISA::MiscReg &val, unsigned tid)
 {
     this->regFile.setMiscRegWithEffect(misc_reg, val, tid);
 }
@@ -285,16 +281,16 @@ template <class Impl>
 TheISA::IntReg
 SparcO3CPU<Impl>::getSyscallArg(int i, int tid)
 {
-    IntReg idx = TheISA::flattenIntIndex(this->tcBase(tid),
+    TheISA::IntReg idx = TheISA::flattenIntIndex(this->tcBase(tid),
             SparcISA::ArgumentReg0 + i);
     return this->readArchIntReg(idx, tid);
 }
 
 template <class Impl>
 void
-SparcO3CPU<Impl>::setSyscallArg(int i, IntReg val, int tid)
+SparcO3CPU<Impl>::setSyscallArg(int i, TheISA::IntReg val, int tid)
 {
-    IntReg idx = TheISA::flattenIntIndex(this->tcBase(tid),
+    TheISA::IntReg idx = TheISA::flattenIntIndex(this->tcBase(tid),
             SparcISA::ArgumentReg0 + i);
     this->setArchIntReg(idx, val, tid);
 }

src/cpu/o3/sparc/thread_context.hh

@@ -36,12 +36,6 @@ class SparcTC : public O3ThreadContext<Impl>
 {
   public:
 #if FULL_SYSTEM
-    /** Returns a pointer to the ITB. */
-    virtual SparcISA::ITB *getITBPtr() { return this->cpu->itb; }
-
-    /** Returns a pointer to the DTB. */
-    virtual SparcISA::DTB *getDTBPtr() { return this->cpu->dtb; }
-
     /** Returns pointer to the quiesce event. */
     virtual EndQuiesceEvent *getQuiesceEvent()
     {

src/cpu/o3/thread_context.hh

@@ -66,6 +66,14 @@ class O3ThreadContext : public ThreadContext
     /** Pointer to the thread state that this TC corrseponds to. */
     O3ThreadState<Impl> *thread;
 
+#if FULL_SYSTEM
+    /** Returns a pointer to the ITB. */
+    virtual AlphaISA::ITB *getITBPtr() { return cpu->itb; }
+
+    /** Returns a pointer to the DTB. */
+    virtual AlphaISA::DTB *getDTBPtr() { return cpu->dtb; }
+#endif
+
     /** Returns a pointer to this CPU. */
     virtual BaseCPU *getCpuPtr() { return cpu; }