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gem5/src/cpu/o3
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Kevin Lim bc05f5982e Merge ktlim@zizzer:/bk/newmem 
into  zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/test-regress

--HG--
extra : convert_revision : d420ee86454b72b0e5d3a98bac3b496f172c1788
2006-12-12 17:55:50 -05:00
..
alpha Rename the StaticInst-based (read|set)(Int|Float)Reg methods to (read|set)(Int|Float)RegOperand to distinguish from non-StaticInst version. 2006-12-12 09:58:40 -08:00
mips Rename the StaticInst-based (read|set)(Int|Float)Reg methods to (read|set)(Int|Float)RegOperand to distinguish from non-StaticInst version. 2006-12-12 09:58:40 -08:00
2bit_local_pred.cc Merge ktlim@zamp:/z/ktlim2/clean/m5-o3 2006-06-04 16:07:54 -04:00
2bit_local_pred.hh Cleaned up include files and got rid of many using directives in header files. 2006-08-15 05:07:15 -04:00
base_dyn_inst.cc now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory 2006-06-30 20:49:31 -04:00
bpred_unit.cc now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory 2006-06-30 20:49:31 -04:00
bpred_unit.hh Cleaned up include files and got rid of many using directives in header files. 2006-08-15 05:07:15 -04:00
bpred_unit_impl.hh add ISA_HAS_DELAY_SLOT directive instead of "#if THE_ISA == ALPHA_ISA" throughout CPU models 2006-08-31 20:51:30 -04:00
btb.cc Cleaned up include files and got rid of many using directives in header files. 2006-08-15 05:07:15 -04:00
btb.hh Cleaned up include files and got rid of many using directives in header files. 2006-08-15 05:07:15 -04:00
checker_builder.cc Adjustments for the AlphaTLB changing to AlphaISA::TLB and changing register file functions to not take faults 2006-11-01 16:44:45 -05:00
comm.hh Cleaned up include files and got rid of many using directives in header files. 2006-08-15 05:07:15 -04:00
commit.cc now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory 2006-06-30 20:49:31 -04:00
commit.hh More interrupt reworking. 2006-11-13 02:49:03 -05:00
commit_impl.hh Fix for MIPS_SE/m5.fast compile. 2006-12-06 14:23:31 -05:00
cpu.cc Change the connecting of the physPort and virtPort to the memory object below the CPU to happen every time activateContext is called. The overhead is probably a little higher than necessary, but allows these connections to properly be made when there are CPUs that are inactive until they are switched in. 2006-11-29 16:07:55 -05:00
cpu.hh Remove mem parameter. Now the translating port asks the CPU's dcache's peer for its MemObject instead of having to have a paramter for the MemObject. 2006-10-31 14:33:56 -05:00
cpu_policy.hh Merge ktlim@zamp:/z/ktlim2/clean/m5-o3 2006-06-04 16:07:54 -04:00
decode.cc now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory 2006-06-30 20:49:31 -04:00
decode.hh This changeset gets the MIPS ISA pretty much working in the O3CPU. It builds, runs, and gets very very close to completing the hello world 2006-07-23 13:39:42 -04:00
decode_impl.hh add ISA_HAS_DELAY_SLOT directive instead of "#if THE_ISA == ALPHA_ISA" throughout CPU models 2006-08-31 20:51:30 -04:00
dep_graph.hh Miscellaneous minor fixes. 2006-06-16 17:15:18 -04:00
dyn_inst.hh Started to add support for O3 for sparc. 2006-08-11 20:29:15 -04:00
fetch.cc now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory 2006-06-30 20:49:31 -04:00
fetch.hh Make CPU models signal to update the snoop ranges 2006-11-13 18:51:16 -05:00
fetch_impl.hh Fix for fetch to use the icache's block size to generate proper access size. 2006-12-11 23:47:30 -05:00
free_list.cc Merge ktlim@zizzer:/bk/newmem 2006-06-02 18:19:50 -04:00
free_list.hh Merge ktlim@zizzer:/bk/newmem 2006-06-02 18:19:50 -04:00
fu_pool.cc Reorganization to move FuncUnit, FUDesc, and OpDesc out of the encumbered directory and into the normal cpu directory. 2006-06-16 17:52:15 -04:00
fu_pool.hh Update copyright. 2006-06-07 16:02:55 -04:00
iew.cc now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory 2006-06-30 20:49:31 -04:00
iew.hh Merge ktlim@zamp:./local/clean/o3-merge/m5 2006-09-30 23:43:23 -04:00
iew_impl.hh Allow for multiple redirects to happen on a single cycle (only the one for the oldest instruction is passed on to commit). 2006-12-12 17:35:46 -05:00
inst_queue.cc now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory 2006-06-30 20:49:31 -04:00
inst_queue.hh Merge ktlim@zamp:./local/clean/o3-merge/m5 2006-09-30 23:43:23 -04:00
inst_queue_impl.hh Merge ktlim@zamp:./local/clean/o3-merge/m5 2006-09-30 23:43:23 -04:00
isa_specific.hh This changeset gets the MIPS ISA pretty much working in the O3CPU. It builds, runs, and gets very very close to completing the hello world 2006-07-23 13:39:42 -04:00
lsq.cc now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory 2006-06-30 20:49:31 -04:00
lsq.hh Make CPU models signal to update the snoop ranges 2006-11-13 18:51:16 -05:00
lsq_impl.hh Make CPU models signal to update the snoop ranges 2006-11-13 18:51:16 -05:00
lsq_unit.cc now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory 2006-06-30 20:49:31 -04:00
lsq_unit.hh Merge ktlim@zizzer:/bk/newmem 2006-10-23 14:32:35 -04:00
lsq_unit_impl.hh Fix up in case a req hasn't yet been generated for this instruction (if there was a fault prior to translation). 2006-12-11 23:51:21 -05:00
mem_dep_unit.cc now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory 2006-06-30 20:49:31 -04:00
mem_dep_unit.hh Initialize mem dep unit properly. 2006-11-07 13:53:06 -05:00
mem_dep_unit_impl.hh Initialize mem dep unit properly. 2006-11-07 13:53:06 -05:00
params.hh Remove mem parameter. Now the translating port asks the CPU's dcache's peer for its MemObject instead of having to have a paramter for the MemObject. 2006-10-31 14:33:56 -05:00
ras.cc Merge ktlim@zizzer:/bk/newmem 2006-06-02 18:19:50 -04:00
ras.hh Cleaned up include files and got rid of many using directives in header files. 2006-08-15 05:07:15 -04:00
regfile.hh Put kernel_stats back into arch. 2006-11-07 22:34:34 -05:00
rename.cc now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory 2006-06-30 20:49:31 -04:00
rename.hh Merge ktlim@zamp:./local/clean/o3-merge/m5 2006-09-30 23:43:23 -04:00
rename_impl.hh Merge ktlim@zamp:./local/clean/o3-merge/m5 2006-09-30 23:43:23 -04:00
rename_map.cc Merge ktlim@zizzer:/bk/newmem 2006-06-02 18:19:50 -04:00
rename_map.hh Cleaned up include files and got rid of many using directives in header files. 2006-08-15 05:07:15 -04:00
rob.cc now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory 2006-06-30 20:49:31 -04:00
rob.hh Minor fix for SMT Hello Worlds to finish correctly. 2006-07-07 15:58:03 -04:00
rob_impl.hh Cleaned up include files and got rid of many using directives in header files. 2006-08-15 05:07:15 -04:00
sat_counter.cc Merge ktlim@zizzer:/bk/newmem 2006-06-02 18:19:50 -04:00
sat_counter.hh Merge ktlim@zizzer:/bk/newmem 2006-06-02 18:19:50 -04:00
SConscript Started to add support for O3 for sparc. 2006-08-11 20:29:15 -04:00
scoreboard.cc Update copyright. 2006-06-07 16:02:55 -04:00
scoreboard.hh Cleaned up include files and got rid of many using directives in header files. 2006-08-15 05:07:15 -04:00
store_set.cc Fixes to get new CPU model working for simple test case. The CPU does not yet support retrying accesses. 2006-06-05 18:14:39 -04:00
store_set.hh Cleaned up include files and got rid of many using directives in header files. 2006-08-15 05:07:15 -04:00
thread_context.hh Change the connecting of the physPort and virtPort to the memory object below the CPU to happen every time activateContext is called. The overhead is probably a little higher than necessary, but allows these connections to properly be made when there are CPUs that are inactive until they are switched in. 2006-11-29 16:07:55 -05:00
thread_context_impl.hh Change the connecting of the physPort and virtPort to the memory object below the CPU to happen every time activateContext is called. The overhead is probably a little higher than necessary, but allows these connections to properly be made when there are CPUs that are inactive until they are switched in. 2006-11-29 16:07:55 -05:00
thread_state.hh Remove mem parameter. Now the translating port asks the CPU's dcache's peer for its MemObject instead of having to have a paramter for the MemObject. 2006-10-31 14:33:56 -05:00
tournament_pred.cc Merge ktlim@zamp:./local/clean/o3-merge/m5 2006-09-30 23:43:23 -04:00
tournament_pred.hh Merge ktlim@zamp:./local/clean/o3-merge/m5 2006-09-30 23:43:23 -04:00