Remove sampler and serializer. Now they are handled through C++ interacting with Python.

src/SConscript:
src/cpu/base.cc:
src/cpu/base.hh:
src/cpu/checker/cpu.hh:
src/cpu/checker/cpu_impl.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/fetch.hh:
src/cpu/ozone/cpu.hh:
src/cpu/ozone/cpu_impl.hh:
src/cpu/simple/base.cc:
src/cpu/simple/base.hh:
src/sim/pseudo_inst.cc:
    Remove sampler.
src/sim/sim_object.cc:
    Remove serializer.

--HG--
extra : convert_revision : ce7616189440f3dc70040148da6d07309a386008

src/SConscript

@@ -89,7 +89,6 @@ base_sources = Split('''
 	cpu/pc_event.cc
         cpu/quiesce_event.cc
 	cpu/static_inst.cc
-        cpu/sampler/sampler.cc
         cpu/simple_thread.cc
         cpu/thread_state.cc
 

src/cpu/base.cc

@@ -41,7 +41,6 @@
 #include "cpu/cpuevent.hh"
 #include "cpu/thread_context.hh"
 #include "cpu/profile.hh"
-#include "cpu/sampler/sampler.hh"
 #include "sim/param.hh"
 #include "sim/process.hh"
 #include "sim/sim_events.hh"

src/cpu/base.hh

@@ -36,7 +36,6 @@
 
 #include "base/statistics.hh"
 #include "config/full_system.hh"
-#include "cpu/sampler/sampler.hh"
 #include "sim/eventq.hh"
 #include "sim/sim_object.hh"
 #include "arch/isa_traits.hh"

src/cpu/checker/cpu.hh

@@ -66,7 +66,6 @@ class ThreadContext;
 class MemInterface;
 class Checkpoint;
 class Request;
-class Sampler;
 
 /**
  * CheckerCPU class.  Dynamically verifies instructions as they are
@@ -374,7 +373,7 @@ class Checker : public CheckerCPU
         : CheckerCPU(p)
     { }
 
-    void switchOut(Sampler *s);
+    void switchOut();
     void takeOverFrom(BaseCPU *oldCPU);
 
     void verify(DynInstPtr &inst);

src/cpu/checker/cpu_impl.hh

@@ -293,7 +293,7 @@ Checker<DynInstPtr>::verify(DynInstPtr &completed_inst)
 
 template <class DynInstPtr>
 void
-Checker<DynInstPtr>::switchOut(Sampler *s)
+Checker<DynInstPtr>::switchOut()
 {
     instList.clear();
 }

src/cpu/o3/cpu.cc

@@ -714,9 +714,8 @@ FullO3CPU<Impl>::haltContext(int tid)
 
 template <class Impl>
 void
-FullO3CPU<Impl>::switchOut(Sampler *_sampler)
+FullO3CPU<Impl>::switchOut()
 {
-    sampler = _sampler;
     switchCount = 0;
     fetch.switchOut();
     decode.switchOut();
@@ -745,12 +744,11 @@ FullO3CPU<Impl>::signalSwitched()
 
 #if USE_CHECKER
         if (checker)
-            checker->switchOut(sampler);
+            checker->switchOut();
 #endif
 
         if (tickEvent.scheduled())
             tickEvent.squash();
-        sampler->signalSwitched();
         _status = SwitchedOut;
     }
     assert(switchCount <= 5);

src/cpu/o3/cpu.hh

@@ -271,7 +271,7 @@ class FullO3CPU : public BaseO3CPU
     virtual void syscall(int tid) { panic("Unimplemented!"); }
 
     /** Switches out this CPU. */
-    void switchOut(Sampler *sampler);
+    void switchOut();
 
     /** Signals to this CPU that a stage has completed switching out. */
     void signalSwitched();
@@ -550,9 +550,6 @@ class FullO3CPU : public BaseO3CPU
     /** Pointer to memory. */
     MemObject *mem;
 
-    /** Pointer to the sampler */
-    Sampler *sampler;
-
     /** Counter of how many stages have completed switching out. */
     int switchCount;
 

src/cpu/o3/fetch.hh

@@ -40,8 +40,6 @@
 #include "mem/port.hh"
 #include "sim/eventq.hh"
 
-class Sampler;
-
 /**
  * DefaultFetch class handles both single threaded and SMT fetch. Its
  * width is specified by the parameters; each cycle it tries to fetch

src/cpu/ozone/cpu.hh

@@ -55,7 +55,6 @@ class AlphaDTB;
 class PhysicalMemory;
 class MemoryController;
 
-class Sampler;
 class RemoteGDB;
 class GDBListener;
 
@@ -356,12 +355,10 @@ class OzoneCPU : public BaseCPU
 
     int cpuId;
 
-    void switchOut(Sampler *sampler);
+    void switchOut();
     void signalSwitched();
     void takeOverFrom(BaseCPU *oldCPU);
 
-    Sampler *sampler;
-
     int switchCount;
 
 #if FULL_SYSTEM

src/cpu/ozone/cpu_impl.hh

@@ -244,9 +244,8 @@ OzoneCPU<Impl>::~OzoneCPU()
 
 template <class Impl>
 void
-OzoneCPU<Impl>::switchOut(Sampler *_sampler)
+OzoneCPU<Impl>::switchOut()
 {
-    sampler = _sampler;
     switchCount = 0;
     // Front end needs state from back end, so switch out the back end first.
     backEnd->switchOut();
@@ -262,13 +261,12 @@ OzoneCPU<Impl>::signalSwitched()
         frontEnd->doSwitchOut();
 #if USE_CHECKER
         if (checker)
-            checker->switchOut(sampler);
+            checker->switchOut();
 #endif
 
         _status = SwitchedOut;
         if (tickEvent.scheduled())
             tickEvent.squash();
-        sampler->signalSwitched();
     }
     assert(switchCount <= 2);
 }

src/cpu/simple/base.cc

@@ -41,7 +41,6 @@
 #include "cpu/base.hh"
 #include "cpu/exetrace.hh"
 #include "cpu/profile.hh"
-#include "cpu/sampler/sampler.hh"
 #include "cpu/simple/base.hh"
 #include "cpu/simple_thread.hh"
 #include "cpu/smt.hh"

src/cpu/simple/base.hh

@@ -38,7 +38,6 @@
 #include "cpu/base.hh"
 #include "cpu/simple_thread.hh"
 #include "cpu/pc_event.hh"
-#include "cpu/sampler/sampler.hh"
 #include "cpu/static_inst.hh"
 #include "mem/packet.hh"
 #include "mem/port.hh"
@@ -128,11 +127,6 @@ class BaseSimpleCPU : public BaseCPU
     // Static data storage
     TheISA::IntReg dataReg;
 
-    // Pointer to the sampler that is telling us to switchover.
-    // Used to signal the completion of the pipe drain and schedule
-    // the next switchover
-    Sampler *sampler;
-
     StaticInstPtr curStaticInst;
 
     void checkForInterrupts();

src/sim/pseudo_inst.cc

@@ -52,8 +52,6 @@
 
 using namespace std;
 
-extern Sampler *SampCPU;
-
 using namespace Stats;
 using namespace TheISA;
 
@@ -280,7 +278,5 @@ namespace AlphaPseudo
 
     void switchcpu(ThreadContext *tc)
     {
-        if (SampCPU)
-            SampCPU->switchCPUs();
     }
 }

src/sim/sim_object.cc

@@ -37,7 +37,6 @@
 #include "base/misc.hh"
 #include "base/trace.hh"
 #include "base/stats/events.hh"
-#include "base/serializer.hh"
 #include "sim/host.hh"
 #include "sim/sim_object.hh"
 #include "sim/stats.hh"