Gabe Black
7b62e9ad71
ARM: Make macroops panic if executed directly.
...
The macroop should never be executed, only it's microops will.
2010-06-02 12:58:03 -05:00
Ali Saidi
8fadf2691d
ARM: GCC < 4.3 has some issues with attribute no return on some functions. Fix so it works for older gccs.
2010-06-02 12:58:03 -05:00
Gabe Black
f18040a205
ARM: Split out the "basic" templates and format.
...
--HG--
rename : src/arch/arm/isa/formats/basic.isa => src/arch/arm/isa/templates/basic.isa
2010-06-02 12:58:03 -05:00
Gabe Black
c175f1b993
ARM: Remove unnecessary cruft from includes.isa.
2010-06-02 12:58:03 -05:00
Gabe Black
e29ec7d2ed
ARM: Move the inst2string function out of the isa_desc.
...
Delete the now empty formats/util.isa.
2010-06-02 12:58:03 -05:00
Gabe Black
ae135228fc
ARM: Get rid of the unused ArmGenericCodeSubs.
2010-06-02 12:58:03 -05:00
Gabe Black
8c012e9571
ARM: Make the predecoder print out the ExtMachInst it gathered when traced.
2010-06-02 12:58:03 -05:00
Gabe Black
458bd025d4
ARM: Remove special naming for the new version of multiply.
2010-06-02 12:58:03 -05:00
Gabe Black
2196f75a25
ARM: Hook the new multiply instructions into all the decoders.
2010-06-02 12:58:03 -05:00
Gabe Black
33da368e99
ARM: Implement all integer multiply instructions.
2010-06-02 12:58:03 -05:00
Gabe Black
50229be27f
ARM: Add templates for multiply instructions.
2010-06-02 12:58:03 -05:00
Gabe Black
3430b34cff
ARM: Add base classes for multiply instructions.
2010-06-02 12:58:03 -05:00
Gabe Black
c7d2f43641
ARM: Decode plain binary immediate thumb data processing instructions.
2010-06-02 12:58:03 -05:00
Gabe Black
dcf218155d
ARM: Define a new "movt" data processing instruction.
2010-06-02 12:58:03 -05:00
Gabe Black
b615ed1470
ARM: Hook the new branch instructions into the 32 bit thumb decoder.
2010-06-02 12:58:03 -05:00
Gabe Black
274badd201
ARM: Hook the new branch instructions into the 16 bit thumb decoder.
2010-06-02 12:58:03 -05:00
Gabe Black
b6b2f8891a
ARM: Eliminate the old style branch instructions.
2010-06-02 12:58:03 -05:00
Gabe Black
d082705b01
ARM: Hook the new branch instructions into the ARM decoder.
2010-06-02 12:58:02 -05:00
Gabe Black
9869343636
ARM: Implement branch instructions external to the decoder.
2010-06-02 12:58:02 -05:00
Gabe Black
a6c1c8debb
ARM: Add new templates for branch instructions.
2010-06-02 12:58:02 -05:00
Gabe Black
ef3972eaae
ARM: Implement new base classes for branches.
2010-06-02 12:58:02 -05:00
Gabe Black
769f3406fe
ARM: Replace the interworking branch base class with a special operand.
2010-06-02 12:58:02 -05:00
Gabe Black
b6e7029dd5
ARM: Fix PC operand handling.
2010-06-02 12:58:02 -05:00
Gabe Black
7eb3ea2798
ARM: Remove the special naming from the new version of data processing instructions.
2010-06-02 12:58:02 -05:00
Gabe Black
4f08b52af2
ARM: Get rid of unnecessary flag calculating functions.
2010-06-02 12:58:02 -05:00
Gabe Black
bf903ec9a1
ARM: Get rid of the unused Jump format.
2010-06-02 12:58:02 -05:00
Gabe Black
36ca0658a4
ARM: Get rid of obsoleted predicated inst formats, etc.
2010-06-02 12:58:02 -05:00
Gabe Black
7939b48265
ARM: Implement disassembly for the new data processing classes.
2010-06-02 12:58:02 -05:00
Gabe Black
b66e3aec43
ARM: Hook the external data processing instructions into the Thumb decoder.
2010-06-02 12:58:02 -05:00
Gabe Black
beb759912b
ARM: Move the modified_imm function from all ARM instructions to just data processing ones.
2010-06-02 12:58:02 -05:00
Gabe Black
8136cb3605
ARM: Hook the new external data processing instructions to the ARM decoder.
2010-06-02 12:58:02 -05:00
Gabe Black
bf45d44cbe
ARM: Implement data processing instructions external to the decoder.
2010-06-02 12:58:02 -05:00
Gabe Black
c02f9cdddf
ARM: Add new base classes for data processing instructions.
2010-06-02 12:58:02 -05:00
Gabe Black
1e7b317a98
ARM: Hook up 32 bit thumb load/store multiple.
2010-06-02 12:58:02 -05:00
Gabe Black
64d6b6ebfd
ARM: Hook up 16 bit thumb load/store multiple.
2010-06-02 12:58:02 -05:00
Gabe Black
51bde086d5
ARM: Reimplement load/store multiple external to the decoder.
...
--HG--
rename : src/arch/arm/isa/formats/macromem.isa => src/arch/arm/isa/insts/macromem.isa
rename : src/arch/arm/isa/formats/macromem.isa => src/arch/arm/isa/templates/macromem.isa
2010-06-02 12:58:02 -05:00
Gabe Black
93a3714816
ARM: Move the templates for predicated instructions into a separate file.
...
This allows the templates to all be available at the same time before any of
the formats, etc. This breaks an artificial circular dependence.
--HG--
rename : src/arch/arm/isa/formats/pred.isa => src/arch/arm/isa/templates/pred.isa
2010-06-02 12:58:01 -05:00
Gabe Black
04300e33d4
ARM: Remove the special naming for the new memory instructions.
...
These are the only memory instructions now.
2010-06-02 12:58:01 -05:00
Gabe Black
deb6e8f805
ARM: Eliminate the old memory formats which are no longer used.
2010-06-02 12:58:01 -05:00
Gabe Black
1905024766
ARM: Eliminate decoding for the very deprecated FPA instructions.
2010-06-02 12:58:01 -05:00
Gabe Black
55465844dc
ARM: Make the addressing mode 3 loads/stores use the externally defined instructions.
2010-06-02 12:58:01 -05:00
Gabe Black
36b6ca2ce3
ARM: Pull double memory instructions out of the decoder.
2010-06-02 12:58:01 -05:00
Gabe Black
79b288f7b5
ARM: Force the condition code for 16 bit thumb instructions to be unconditional.
...
Before, because 16 bit thumb instructions didn't set the upper 16 bits of the
ExtMachInst, that field would be interpretted as "equals".
2010-06-02 12:58:01 -05:00
Gabe Black
a86491fbf2
ARM: Decode 16 bit thumb PC relative memory instructions.
2010-06-02 12:58:01 -05:00
Gabe Black
dc8af1b211
ARM: Decode 16 bit thumb immediate addressed memory instructions.
2010-06-02 12:58:01 -05:00
Gabe Black
4bbd73649d
ARM: Decode 16 bit thumb register addressed memory instructions.
2010-06-02 12:58:01 -05:00
Gabe Black
462cf6f49b
ARM: Make single stores decode to the new external store instructions.
2010-06-02 12:58:01 -05:00
Gabe Black
3b0f3b1ee2
ARM: Add a .w to the disassembly of 32 bit thumb instructions.
...
This isn't technically correct since the .w should only be added if there are
32 and 16 bit encodings, but always having it always is better than never
having it.
2010-06-02 12:58:01 -05:00
Gabe Black
fde3c8f41d
ARM: Make 32 bit thumb use the new, external load instructions.
2010-06-02 12:58:01 -05:00
Gabe Black
3b93015304
ARM: Define the store instructions from outside the decoder.
...
--HG--
rename : src/arch/arm/isa/insts/ldr.isa => src/arch/arm/isa/insts/str.isa
2010-06-02 12:58:01 -05:00
Gabe Black
81fdced83f
ARM: Define the load instructions from outside the decoder.
2010-06-02 12:58:01 -05:00
Gabe Black
321d3a6e8c
ARM: Implement a new set of base classes for non macro memory instructions.
2010-06-02 12:58:01 -05:00
Gabe Black
8933857af7
ARM: Create a "decoder" directory for the files implementing the decoder.
...
--HG--
rename : src/arch/arm/isa/armdecode.isa => src/arch/arm/isa/decoder/arm.isa
rename : src/arch/arm/isa/decoder.isa => src/arch/arm/isa/decoder/decoder.isa
rename : src/arch/arm/isa/thumbdecode.isa => src/arch/arm/isa/decoder/thumb.isa
rename : src/arch/arm/isa/vfpdecode.isa => src/arch/arm/isa/decoder/vfp.isa
2010-06-02 12:58:01 -05:00
Gabe Black
4ebd44dc4f
ARM: Flesh out the 32 bit thumb store single instructions.
2010-06-02 12:58:01 -05:00
Gabe Black
386424ccb5
ARM: Implement the 32 bit thumb load word instructions.
2010-06-02 12:58:01 -05:00
Gabe Black
292b8a3c91
ARM: Add an operand for accessing the current PC.
2010-06-02 12:58:00 -05:00
Gabe Black
003346077f
ARM: Flesh out 32 bit thumb load word decoding.
2010-06-02 12:58:00 -05:00
Gabe Black
0d4c4cacab
ARM: Implement some 32 bit thumb data processing immediate instructions.
2010-06-02 12:58:00 -05:00
Gabe Black
bd8812cf99
ARM: Replace the "never" condition with the "unconditional" condition.
2010-06-02 12:58:00 -05:00
Gabe Black
af91d27271
ARM: Add a base class for 32 bit thumb data processing immediate instructions.
2010-06-02 12:58:00 -05:00
Gabe Black
bfe1a194dd
ARM: Add a function to decode 32 bit thumb immediate values.
2010-06-02 12:58:00 -05:00
Gabe Black
0116655674
ARM: Expand the decoding for 32 bit thumb data processing immediate instructions.
2010-06-02 12:58:00 -05:00
Gabe Black
cef2e8ecee
ARM: Stub out the 32 bit Thumb portion of the decoder.
2010-06-02 12:58:00 -05:00
Gabe Black
659f8d021f
ARM: Add bitfields for 32 bit thumb.
2010-06-02 12:58:00 -05:00
Gabe Black
bc6ae010c9
ARM: Decode VFP instructions.
2010-06-02 12:58:00 -05:00
Gabe Black
7b8525287d
ARM: Stub out the 16 bit thumb decoder.
2010-06-02 12:58:00 -05:00
Gabe Black
aaa619ea23
ARM: Add thumb bitfields to the ExtMachInst and the isa definition.
2010-06-02 12:58:00 -05:00
Gabe Black
a1838f2c79
ARM: Make the decoder handle thumb instructions separately.
...
--HG--
rename : src/arch/arm/isa/decoder.isa => src/arch/arm/isa/armdecode.isa
rename : src/arch/arm/isa/decoder.isa => src/arch/arm/isa/thumbdecode.isa
2010-06-02 12:58:00 -05:00
Gabe Black
0dffd8ce79
ARM: Add a thumb bit bitfield.
2010-06-02 12:58:00 -05:00
Gabe Black
96be7e16c1
ARM: Make the predecoder handle Thumb instructions.
2010-06-02 12:58:00 -05:00
Gabe Black
f49cdb4f5d
ARM: Make sure ExtMachInst is used consistently instead of regular MachInst.
2010-06-02 12:58:00 -05:00
Gabe Black
330d9d4dbc
ARM: Add a bitfield for setting the regular, inst bits of an ExtMachInst.
2010-06-02 12:58:00 -05:00
Gabe Black
a59d219989
ARM: Add a bit to the ExtMachInst to select thumb mode.
2010-06-02 12:58:00 -05:00
Gabe Black
4ddeceba96
ARM: Allow ARM processes to start in Thumb mode.
2010-06-02 12:58:00 -05:00
Gabe Black
ebb273bb7b
ARM: Add a new base class for instructions that can do an interworking branch.
2010-06-02 12:57:59 -05:00
Gabe Black
9ef82c0bc4
ARM: Track the current ISA mode using the PC.
2010-06-02 12:57:59 -05:00
Gabe Black
1c0d9806e5
ARM: Fix custom writer/reader code for non indexed operands.
2010-06-02 12:57:59 -05:00
Gabe Black
4b87bc887a
ARM: Remove IsControl from operands that don't imply control transfers.
...
Also remove IsInteger from CondCodes.
2010-06-02 12:57:59 -05:00
Nathan Binkert
bb589d463b
x86: put back code that I accidentally deleted
2010-05-25 20:15:44 -07:00
Nathan Binkert
13d64906c2
copyright: Change HP copyright on x86 code to be more friendly
2010-05-23 22:44:15 -07:00
Gabe Black
c5c559b6ab
SPARC: Implement the version of movcc that uses the fp condition codes.
2010-05-14 14:22:51 -07:00
Gabe Black
c4497dbf03
X86: Make the cvti2f microop sign extend its integer source correctly.
...
The code was using the wrong bit as the sign bit. Other similar bits of code
seem to be correct.
2010-05-12 00:51:35 -07:00
Gabe Black
cc76842f83
X86: Actual change that fixes div. How did that happen?
2010-05-12 00:49:12 -07:00
Gabe Black
2ee7a89209
X86: Update the base aux vector X86 processes install.
2010-05-03 00:44:08 -07:00
Gabe Black
7524fdda6a
X86: Sometimes CPUID depends on ecx, so pass that in.
2010-05-02 00:40:17 -07:00
Gabe Black
51a3d65e25
X86: Finally fix a division corner case.
...
When doing an unsigned 64 bit division with a divisor that has its most
significant bit set, the division code would spill a bit off of the end of a
uint64_t trying to shift the dividend into position. This change adds code
that handles that case specially by purposefully letting it spill and then
going ahead assuming there was a 65th one bit.
2010-05-02 00:39:29 -07:00
Nathan Binkert
e99828b06a
tick: rename Clock namespace to SimClock
2010-04-15 16:24:12 -07:00
Steve Reinhardt
4d77ea7a57
cpu: fix exec tracing memory corruption bug
...
Accessing traceData (to call setAddress() and/or setData())
after initiating a timing translation was causing crashes,
since a failed translation could delete the traceData
object before returning.
It turns out that there was never a need to access traceData
after initiating the translation, as the traced data was
always available earlier; this ordering was merely
historical. Furthermore, traceData->setAddress() and
traceData->setData() were being called both from the CPU
model and the ISA definition, often redundantly.
This patch standardizes all setAddress and setData calls
for memory instructions to be in the CPU models and not
in the ISA definition. It also moves those calls above
the translation calls to eliminate the crashes.
2010-03-23 08:50:57 -07:00
Nathan Binkert
1068ca85d0
scons: import ply to work around scons sys.path weirdness
2010-03-10 15:39:34 -08:00
Nathan Binkert
f0b4259e98
cpu_models: get rid of cpu_models.py and move the stuff into SCons
2010-02-26 18:14:48 -08:00
Nathan Binkert
ac106767c8
isa_parser: Make SCons import the isa_parser
...
this is instead of forking a new interpreter
2010-02-26 18:14:48 -08:00
Nathan Binkert
629e8df196
isa_parser: move the operand map stuff into the ISAParser class.
2010-02-26 18:14:48 -08:00
Nathan Binkert
4db57edade
isa_parser: move more support functions into the ISAParser class
2010-02-26 18:14:48 -08:00
Nathan Binkert
5ad139375e
isa_parser: move more stuff into the ISAParser class
2010-02-26 18:14:48 -08:00
Nathan Binkert
4ef6e129d6
isa_parser: move the formatMap and exportContext into the ISAParser class
2010-02-26 18:14:48 -08:00
Nathan Binkert
4e105f6fe1
isa_parser: Make stack objects class members instead of globals
2010-02-26 18:14:48 -08:00
Nathan Binkert
b4178b1ae7
isa_parser: add a debug variable that changes how errors are reported.
...
This allows us to get tracebacks in certain cases where they're more
useful than our error message.
2010-02-26 18:14:48 -08:00
Nathan Binkert
40a05f04fb
isa_parser: Use an exception to flag error
...
This allows the error to propagate more easily
2010-02-26 18:14:48 -08:00
Nathan Binkert
f82a92925c
isa_parser: Move more stuff into the ISAParser class
2010-02-26 18:14:48 -08:00
Nathan Binkert
f7a627338c
isa_parser: move code around to prepare for putting more stuff in the class
2010-02-26 18:14:48 -08:00
Nathan Binkert
eb4ce01056
isa_parser: simple fixes, formatting and style
2010-02-26 18:14:48 -08:00
Timothy M. Jones
29e8bcead5
O3PCU: Split loads and stores that cross cache line boundaries.
...
When each load or store is sent to the LSQ, we check whether it will cross a
cache line boundary and, if so, split it in two. This creates two TLB
translations and two memory requests. Care has to be taken if the first
packet of a split load is sent but the second blocks the cache. Similarly,
for a store, if the first packet cannot be sent, we must store the second
one somewhere to retry later.
This modifies the LSQSenderState class to record both packets in a split
load or store.
Finally, a new const variable, HasUnalignedMemAcc, is added to each ISA
to indicate whether unaligned memory accesses are allowed. This is used
throughout the changed code so that compiler can optimise away code dealing
with split requests for ISAs that don't need them.
2010-02-12 19:53:20 +00:00
Timothy M. Jones
dd60902152
Power ISA: Add an alignment fault to Power ISA and check alignment in TLB.
2010-02-12 19:53:19 +00:00
Nathan Binkert
8a3fbbd8d9
compile: compile on 32 bit hardware
2009-11-05 17:21:26 -08:00
Nathan Binkert
52ccfde2cd
isa_parser: allow negative integer literals
2009-11-05 17:21:25 -08:00
Lisa Hsu
d6da172517
util: do checkpoint aggregation more cleanly, fix last changeset.
...
1) Move alpha-specific code out of page_table.cc:serialize().
2) Begin serializing M5_pid and unserializing it, but adding an function to do optional paramIn so that old checkpoints don't need to be fixed up.
3) Fix up alpha startup code so that the unserialized M5_pid value is properly written to DTB_IPR_ASN.
4) Fix the memory unserialize that I forgot somehow in the last changeset.
5) Add in an agg_se.py to handle aggregated checkpoints. --bench foo-bar plus positional arguments foo bar are the only changes in usage from se.py.
Note this aggregation stuff has only been tested for Alpha and nothing else, though it should take a very minimal amount of work to get it to work with another ISA.
2010-01-19 22:03:44 -08:00
Matt DeVuyst
18dc80e07b
MIPS: Beef up process initialization.
2009-12-31 15:30:51 -05:00
Gabe Black
ecaa7070e6
MIPS: Implement the SE mode version of rdhwr.
2009-12-31 15:30:51 -05:00
Gabe Black
c70f3c93af
MIPS: Fix decoding of the rdhwr instruction.
2009-12-31 15:30:51 -05:00
Gabe Black
134937b594
MIPS: Implement the set_thread_area system call.
2009-12-31 15:30:50 -05:00
Gabe Black
d3ed32b989
MIPS: Create an artificial control register to hold the thread pointer.
...
In Linux, the set_thread_area system call stores the address of the thread
local storage area into a field of the current thread_info structure. Later,
to access that value, the program uses the rdhwr instruction to read a
"hardware register" with index 29. The 64 bit MIPS manual, volume II, says
that index 29 is reserved for a future ABI extension and should cause a
"Reserved Instruction Exception". In Linux (and potentially other ISAs) that
exception is trapped and emulated to return the value stored by
set_thread_area as if that were actually stored by a physical register.
The tp_value address (as named in the Linux kernel) is ironically stored as a
control register so that it goes with a particular ThreadContext. Syscall
emulation will use that to emulate storing to the OS's thread info structure,
and rdhwr will emulate faulting and returning that value from software by
returning the value itself, as if it was in hardware. In other words, we fake
faking the register in SE mode. In an FS mode implementation it should
work as specified in the manual.
2009-12-31 15:30:50 -05:00
Gabe Black
cc07dcf026
MIPS: Extract CPU pointer from the thread context in scheduleCP0 setMiscReg.
...
The MIPS ISA object expects to be constructed with a CPU pointer it uses to
look at other thread contexts and allow them to be manipulated with control
registers. Unfortunately, that differs from all the other ISA classes and
would complicate their implementation.
This change makes the event constructor use a CPU pointer pulled out of the
thread context passed to setMiscReg instead.
2009-12-31 15:30:50 -05:00
Gabe Black
1261f1d8db
MIPS: Add missing syscall slots.
...
These are all after the existing ones, suggesting they were added after the
original list was created.
2009-12-21 14:59:40 -08:00
Soumyaroop Roy
1bd0f772f1
Alpha: Implement MVI and remaining BWX instructions.
2009-12-20 15:03:23 -06:00
Gabe Black
c7ca1d3c8a
X86: Add a common named flag for signed media operations.
2009-12-19 01:48:31 -08:00
Gabe Black
2554511533
X86: Create a common flag with a name to indicate high multiplies.
2009-12-19 01:48:07 -08:00
Gabe Black
e474079ddc
X86: Create a common flag with a name to indicate scalar media instructions.
2009-12-19 01:47:30 -08:00
Ali Saidi
422f0d9f10
ARM: Begin implementing CP15
2009-11-17 18:02:09 -06:00
Ali Saidi
0916c376a9
ARM: Differentiate between LDM exception return and LDM user regs.
2009-11-17 18:02:08 -06:00
Ali Saidi
1470dae8e9
ARM: Boilerplate full-system code.
...
--HG--
rename : src/arch/sparc/interrupts.hh => src/arch/arm/interrupts.hh
rename : src/arch/sparc/kernel_stats.hh => src/arch/arm/kernel_stats.hh
rename : src/arch/sparc/stacktrace.cc => src/arch/arm/stacktrace.cc
rename : src/arch/sparc/system.cc => src/arch/arm/system.cc
rename : src/arch/sparc/system.hh => src/arch/arm/system.hh
rename : src/dev/sparc/T1000.py => src/dev/arm/Versatile.py
rename : src/dev/sparc/t1000.cc => src/dev/arm/versatile.cc
rename : src/dev/sparc/t1000.hh => src/dev/arm/versatile.hh
2009-11-17 18:02:08 -06:00
Ali Saidi
171e7f7b24
imported patch isa_fixes2.diff
2009-11-16 11:37:03 -06:00
Gabe Black
9127ee5ac8
ARM: Make the exception return form of ldm restore CPSR.
2009-11-15 00:23:14 -08:00
Gabe Black
903fb8c73d
ARM: Create a new type of load uop that restores spsr into cpsr.
2009-11-15 00:15:42 -08:00
Gabe Black
b41725f723
ARM: Check in the actual change from the last commit.
...
The last commit was somehow empty. This was what was supposed to go in it.
2009-11-14 21:03:10 -08:00
Gabe Black
c4042985d7
ARM: Fix up the implmentation of the msr instruction.
2009-11-14 19:22:30 -08:00
Gabe Black
e2ab64543b
ARM: Define a mask to differentiate purely CPSR bits from CondCodes bits.
2009-11-14 19:22:30 -08:00
Gabe Black
425ebf6bd7
ARM: Add a bitfield to indicate if an immediate should be used.
2009-11-14 19:22:30 -08:00
Gabe Black
e543f16247
ARM: Write some functions to write to the CPSR and SPSR for instructions.
2009-11-14 19:22:30 -08:00
Gabe Black
812e390693
ARM: Fix up the implmentation of the mrs instruction.
2009-11-14 19:22:29 -08:00
Gabe Black
1df0025e28
ARM: More accurately describe the effects of using the control operands.
2009-11-14 19:22:29 -08:00
Gabe Black
50b9149c75
ARM: Hook up the moded versions of the SPSR.
...
These registers can be accessed directly, or through MISCREG_SPSR which will
act as whichever SPSR is appropriate for the current mode.
2009-11-14 19:22:29 -08:00
Ali Saidi
48bc573f5f
ARM: Move around decoder to properly decode CP15
2009-11-14 11:25:00 -06:00
Vince Weaver
8f6744c19c
X86: add ULL to 1's being shifted in 64-bit values
...
Some of the micro-ops weren't casting 1 to ULL before shifting,
which can cause problems. On the perl makerand input this
caused some values to be negative that shouldn't have been.
The casts are done as ULL(1) instead of 1ULL to match others
in the m5 code base.
2009-11-11 17:49:09 -05:00
Gabe Black
5524af83ef
ARM: Fix some bugs in the ISA desc and fill out some instructions.
2009-11-10 23:44:05 -08:00
Gabe Black
850eb54a7c
Merge with the head.
2009-11-10 21:12:53 -08:00
Gabe Black
b8120f6c38
Mem: Eliminate the NO_FAULT request flag.
2009-11-10 21:10:18 -08:00
Gabe Black
2e28da5583
ARM: Implement fault classes.
...
Implement some fault classes using the curriously recurring template pattern,
similar to SPARCs.
2009-11-10 20:34:38 -08:00
Gabe Black
4779020e13
ARM: Fix the integer register indexes.
...
The PC indexes in the various register sets was defined in the section for
unaliased registers which was throwing off the indexing. This moves those
where they belong. Also, to make detecting accesses to the PC easier and
because it's in the same place in all modes, the intRegForceUser function
now passes it through as index 15.
2009-11-10 20:19:55 -08:00
Vince Weaver
53e27c0277
X86: Fix bugs in movd implementation.
...
Unfortunately my implementation of the movd instruction had two bugs.
In one case, when moving a 32-bit value into an xmm register, the
lower half of the xmm register was not zero extended.
The other case is that xmm was used instead of xmmlm as the source
for a register move. My test case didn't notice this at first
as it moved xmm0 to eax, which both have the same register
number.
2009-11-10 11:29:30 -05:00
Vince Weaver
e81cc233a6
X86: Remove double-cast in Cvtf2i micro-op
...
This double cast led to rounding errors which caused
some benchmarks to get the wrong values, most notably lucas
which failed spectacularly due to CVTTSD2SI returning an
off-by-one value. equake was also broken.
2009-11-10 11:18:23 -05:00
Gabe Black
bbbfdee2ed
X86: Don't panic on faults on prefetches in SE mode.
2009-11-08 22:49:58 -08:00
Gabe Black
44e912c6bd
X86: Explain what really didn't work with unmapped addresses in SE mode.
2009-11-08 22:49:57 -08:00
Gabe Black
53086dfefe
X86: Make x86 use PREFETCH instead of PF_EXCLUSIVE.
2009-11-08 22:49:57 -08:00
Nathan Binkert
b1a1f9aec8
automerge
2009-11-08 20:15:54 -08:00
Gabe Black
8a4af3668d
ARM: Support forcing load/store multiple to use user registers.
2009-11-08 15:49:03 -08:00
Gabe Black
bb903b6514
ARM: Simplify the load/store multiple generation code.
...
Specifically, get rid of the big switch statement so more cases can be
handled. Enumerating all the possible settings doesn't scale well. Also do
some minor style clean up.
2009-11-08 15:16:59 -08:00
Nathan Binkert
708faa7677
compile: wrap 64bit numbers with ULL() so 32bit compiles work
...
In the isa_parser, we need to check case statements.
2009-11-08 13:31:59 -08:00
Gabe Black
48525f581c
ARM: Split the condition codes out of the CPSR.
...
This allows those bits to be renamed while allowing the other fields to
control the behavior of the processor.
2009-11-08 02:08:40 -08:00
Gabe Black
d188821d37
ARM: Add in more bits for the mon mode.
2009-11-08 02:01:02 -08:00
Gabe Black
3a3e846151
ARM: Get rid of NumInternalProcRegs.
...
That constant is a carry over from Alpha and doesn't do anything in ARM.
2009-11-08 02:00:55 -08:00