Commit graph

357 commits

Author SHA1 Message Date
Gabe Black
f721a4d9ad Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
into  zizzer.eecs.umich.edu:/z/m5/Bitkeeper/multiarch

arch/alpha/faults.hh:
    ur
    Using cleaned up fault class deiffinitions

--HG--
extra : convert_revision : a600950d539be2be73358f072aa5426456bf3d2d
2006-02-19 03:20:05 -05:00
Gabe Black
ed25d32617 Remade some changes which were undone
cpu/base.hh:
cpu/static_inst.hh:
    Changed include of targetarch/isa_traits.hh back to arch/isa_traits.hh
cpu/exec_context.hh:
    Changed Fault back to Fault *

--HG--
extra : convert_revision : 410f2e2472f8aa5bf92619a5defdf85f689a5597
2006-02-19 03:04:44 -05:00
Gabe Black
0e4a80df1a Merge gblack@m5.eecs.umich.edu:/bk/multiarch
into  ewok.(none):/home/gblack/m5/multiarch

--HG--
extra : convert_revision : 090b30a7f70294e1aeb13ba0bc15da4061bdf348
2006-02-19 02:34:52 -05:00
Gabe Black
463aa6d49d Changes to untemplate StaticInst and StaticInstPtr, change the isa to a namespace instead of a class, an improvement to the architecture specific header file selection system, and fixed up a few include paths.
arch/alpha/alpha_linux_process.cc:
    Added using directive for AlphaISA namespace
arch/alpha/alpha_memory.hh:
arch/alpha/isa/branch.isa:
cpu/pc_event.hh:
    Added typedefs for Addr
arch/alpha/alpha_tru64_process.cc:
arch/alpha/arguments.cc:
    Added using directive for AlphaISA
arch/alpha/ev5.hh:
    Added an include of arch/alpha/isa_traits.hh, and a using directive for the AlphaISA namespace.
arch/alpha/faults.hh:
    Added a typedef for the Addr type, and changed the formatting of the faults slightly.
arch/alpha/isa/main.isa:
    Untemplatized StaticInst, added a using for namespace AlphaISA to show up in decoder.cc and the exec.ccs, relocated makeNop to decoder.hh
arch/alpha/isa/mem.isa:
    Untemplatized StaticInst and StaticInstPtr
arch/alpha/isa/pal.isa:
cpu/base_dyn_inst.cc:
    Untemplatized StaticInstPtr
arch/alpha/isa_traits.hh:
    Changed variables to be externs instead of static since they are part of a namespace and not a class.
arch/alpha/stacktrace.cc:
    Untemplatized StaticInstPtr, and added a using directive for AlphaISA.
arch/alpha/stacktrace.hh:
    Added some typedefs for Addr and MachInst, and untemplatized StaticInstPtr
arch/alpha/vtophys.cc:
    Added a using directive for AlphaISA
arch/alpha/vtophys.hh:
    Added the AlphaISA namespace specifier where needed
arch/isa_parser.py:
    Changed the placement of the definition of the decodeInst function to be outside the namespaceInst namespace.
base/loader/object_file.hh:
cpu/o3/bpred_unit.hh:
    Added a typedef for Addr
base/loader/symtab.hh:
    Added a typedef for Addr, and added a TheISA to Addr in another typedef
base/remote_gdb.cc:
    Added a using namespace TheISA, and untemplatized StaticInstPtr
base/remote_gdb.hh:
    Added typedefs for Addr and MachInst
cpu/base.cc:
    Added TheISA specifier to some variables exported from the isa.
cpu/base.hh:
    Added a typedef for Addr, and TheISA to some variables from the ISA
cpu/base_dyn_inst.hh:
    Untemplatized StaticInstPtr, and added TheISA specifier to some variables from the ISA.
cpu/exec_context.hh:
    Added some typedefs for types from the isa, and added TheISA specifier to some variables from the isa
cpu/exetrace.hh:
    Added typedefs for some types from the ISA, and untemplatized StaticInstPtr
cpu/memtest/memtest.cc:
cpu/o3/btb.cc:
dev/baddev.cc:
dev/ide_ctrl.cc:
dev/ide_disk.cc:
dev/isa_fake.cc:
dev/ns_gige.cc:
dev/pciconfigall.cc:
dev/platform.cc:
dev/sinic.cc:
dev/uart8250.cc:
kern/freebsd/freebsd_system.cc:
kern/linux/linux_system.cc:
kern/system_events.cc:
kern/tru64/dump_mbuf.cc:
kern/tru64/tru64_events.cc:
sim/process.cc:
sim/pseudo_inst.cc:
sim/system.cc:
    Added using namespace TheISA
cpu/memtest/memtest.hh:
cpu/trace/opt_cpu.hh:
cpu/trace/reader/itx_reader.hh:
dev/ide_disk.hh:
dev/pcidev.hh:
dev/platform.hh:
dev/tsunami.hh:
sim/system.hh:
sim/vptr.hh:
    Added typedef for Addr
cpu/o3/2bit_local_pred.hh:
    Changed the include to use arch/isa_traits.hh instead of arch/alpha/isa_traits.hh. Added typedef for Addr
cpu/o3/alpha_cpu.hh:
    Added typedefs for Addr and IntReg
cpu/o3/alpha_cpu_impl.hh:
    Added this-> to setNextPC to fix a problem since it didn't depend on template parameters any more. Removed "typename" where it was no longer needed.
cpu/o3/alpha_dyn_inst.hh:
    Cleaned up some typedefs, and untemplatized StaticInst
cpu/o3/alpha_dyn_inst_impl.hh:
    untemplatized StaticInstPtr
cpu/o3/alpha_impl.hh:
    Fixed up a typedef of MachInst
cpu/o3/bpred_unit_impl.hh:
    Added a using TheISA::MachInst to a function
cpu/o3/btb.hh:
    Changed an include from arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef for Addr
cpu/o3/commit.hh:
    Removed a typedef of Impl::ISA as ISA, since TheISA takes care of this now.
cpu/o3/cpu.cc:
    Cleaned up namespace issues
cpu/o3/cpu.hh:
    Cleaned up namespace usage
cpu/o3/decode.hh:
    Removed typedef of ISA, and changed it to TheISA
cpu/o3/fetch.hh:
    Fized up typedefs, and changed ISA to TheISA
cpu/o3/free_list.hh:
    Changed include of arch/alpha/isa_traits.hh to arch/isa_traits.hh
cpu/o3/iew.hh:
    Removed typedef of ISA
cpu/o3/iew_impl.hh:
    Added TheISA namespace specifier to MachInst
cpu/o3/ras.hh:
    Changed include from arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef for Addr.
cpu/o3/regfile.hh:
    Changed ISA to TheISA, and added some typedefs for Addr, IntReg, FloatReg, and MiscRegFile
cpu/o3/rename.hh:
    Changed ISA to TheISA, and added a typedef for RegIndex
cpu/o3/rename_map.hh:
    Added an include for arch/isa_traits.hh, and a typedef for RegIndex
cpu/o3/rob.hh:
    Added a typedef for RegIndex
cpu/o3/store_set.hh:
cpu/o3/tournament_pred.hh:
    Changed an include of arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef of Addr
cpu/ozone/cpu.hh:
    Changed ISA into TheISA, and untemplatized StaticInst
cpu/pc_event.cc:
    Added namespace specifier TheISA to Addr types
cpu/profile.hh:
kern/kernel_stats.hh:
    Added typedef for Addr, and untemplatized StaticInstPtr
cpu/simple/cpu.cc:
    Changed using directive from LittleEndianGuest to AlphaISA, which will contain both namespaces. Added TheISA where needed, and untemplatized StaticInst
cpu/simple/cpu.hh:
    Added a typedef for MachInst, and untemplatized StaticInst
cpu/static_inst.cc:
    Untemplatized StaticInst
cpu/static_inst.hh:
    Untemplatized StaticInst by using the TheISA namespace
dev/alpha_console.cc:
    Added using namespace AlphaISA
dev/simple_disk.hh:
    Added typedef for Addr and fixed up some formatting
dev/sinicreg.hh:
    Added TheISA namespace specifier where needed
dev/tsunami.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
    Added using namespace TheISA. It might be better for it to be AlphaISA
dev/tsunami_cchip.cc:
    Added typedef for TheISA. It might be better for it to be AlphaISA
kern/linux/aligned.hh:
sim/pseudo_inst.hh:
    Added TheISA namespace specifier to Addr
kern/linux/linux_threadinfo.hh:
    Added typedef for Addr, and TheISA namespace specifier to StackPointerReg
kern/tru64/mbuf.hh:
    Added TheISA to Addr type in structs
sim/process.hh:
    Added typedefs of Addr, RegFile, and MachInst
sim/syscall_emul.cc:
    Added using namespace TheISA, and a cast of VMPageSize to the int type
sim/syscall_emul.hh:
    Added typecast for Addr, and TheISA namespace specifier for where needed

--HG--
extra : convert_revision : 91d4f6ca33a73b21c1f1771d74bfdea3b80eff45
2006-02-19 02:34:37 -05:00
Korey Sewell
bd17580928 changes from mergedmem
arch/mips/isa/formats/branch.isa:
    add branch_likely member functions
cpu/base.hh:
cpu/exec_context.hh:
cpu/static_inst.hh:
    change from mergedmem

--HG--
extra : convert_revision : d6ad6943e2ef09eac91a466fc5c9bd8e66bf319a
2006-02-18 14:38:23 -05:00
Kevin Lim
d6a330ebb9 Remove fake fault.
Switch fault pointers to const pointers to prevent them from accidentally being changed.
Fix some coding style.

arch/alpha/ev5.cc:
cpu/o3/commit_impl.hh:
kern/kernel_stats.hh:
    Remove fake fault.
arch/alpha/faults.cc:
    Remove fake fault, fix to have normal m5 line length limit, and change pointers to be const pointers so that the default faults aren't changed accidentally.
arch/alpha/faults.hh:
    Fix to have normal m5 line length limit, change pointers to const pointers.
sim/faults.cc:
sim/faults.hh:
    Remove fake fault, change pointers to const pointers.

--HG--
extra : convert_revision : 01d4600e0d4bdc1d177b32edebc78f86a1bbfe2e
2006-02-16 14:55:15 -05:00
Gabe Black
10c79efe55 Changed the fault enum into a class, and fixed everything up to work with it. Next, the faults need to be pulled out of all the other code so that they are only used to communicate between the CPU and the ISA.
SConscript:
    The new faults.cc file in sim allocates the system wide faults. When these faults are generated through a function interface in the ISA, this file may go away.
arch/alpha/alpha_memory.cc:
    Changed Fault to Fault * and took the underscores out of fault names.
arch/alpha/alpha_memory.hh:
    Changed Fault to Fault *. Also, added an include for the alpha faults.
arch/alpha/ev5.cc:
    Changed the fault_addr array into a fault_addr function. Once all of the faults can be expected to have the same type, fault_addr can go away completely and the info it provided will come from the fault itself. Also, Fault was changed to Fault *, and underscores were taken out of fault names.
arch/alpha/isa/decoder.isa:
    Changed Fault to Fault * and took the underscores out fault names.
arch/alpha/isa/fp.isa:
    Changed Fault to Fault *, and took the underscores out of fault names.
arch/alpha/isa/main.isa:
    Changed Fault to Fault *, removed underscores from fault names, and made an include of the alpha faults show up in all the generated files.
arch/alpha/isa/mem.isa:
    Changed Fault to Fault * and removed underscores from fault names.
arch/alpha/isa/unimp.isa:
arch/alpha/isa/unknown.isa:
cpu/exec_context.hh:
cpu/ozone/cpu.hh:
cpu/simple/cpu.cc:
dev/alpha_console.cc:
dev/ide_ctrl.cc:
dev/isa_fake.cc:
dev/pciconfigall.cc:
dev/pcidev.cc:
dev/pcidev.hh:
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
    Changed Fault to Fault *, and removed underscores from fault names.
arch/alpha/isa_traits.hh:
    Changed the include of arch/alpha/faults.hh to sim/faults.hh, since the alpha faults weren't needed.
cpu/base_dyn_inst.cc:
    Changed Fault to Fault *, and removed underscores from fault names. This file probably shouldn't use the Unimplemented Opcode fault.
cpu/base_dyn_inst.hh:
    Changed Fault to Fault * and took the underscores out of the fault names.
cpu/exec_context.cc:
cpu/o3/alpha_dyn_inst.hh:
cpu/o3/alpha_dyn_inst_impl.hh:
cpu/o3/fetch.hh:
dev/alpha_console.hh:
dev/baddev.hh:
dev/ide_ctrl.hh:
dev/isa_fake.hh:
dev/ns_gige.hh:
dev/pciconfigall.hh:
dev/sinic.hh:
dev/tsunami_cchip.hh:
dev/tsunami_io.hh:
dev/tsunami_pchip.hh:
dev/uart.hh:
dev/uart8250.hh:
    Changed Fault to Fault *.
cpu/o3/alpha_cpu.hh:
    Changed Fault to Fault *, removed underscores from fault names.
cpu/o3/alpha_cpu_impl.hh:
    Changed Fault to Fault *, removed underscores from fault names, and changed the fault_addr array to the fault_addr function. Once all faults are from the ISA, this function will probably go away.
cpu/o3/commit_impl.hh:
cpu/o3/fetch_impl.hh:
dev/baddev.cc:
    Changed Fault to Fault *, and removed underscores from the fault names.
cpu/o3/regfile.hh:
    Added an include for the alpha specific faults which will hopefully go away once the ipr stuff is moved, changed Fault to Fault *, and removed the underscores from fault names.
cpu/simple/cpu.hh:
    Changed Fault to Fault *
dev/ns_gige.cc:
    Changed Fault to Fault *, and removdd underscores from fault names.
dev/sinic.cc:
    Changed Fault to Fault *, and removed the underscores from fault names.
dev/uart8250.cc:
    Chanted Fault to Fault *, and removed underscores from fault names.
kern/kernel_stats.cc:
    Removed underscores from fault names, and from NumFaults.
kern/kernel_stats.hh:
    Changed the predeclaration of Fault from an enum to a class, and changd the "fault" function to work with the classes instead of the enum. Once there are no system wide faults anymore, this code will simplify back to something like it was originally.
sim/faults.cc:
    This allocates the system wide faults.
sim/faults.hh:
    This declares the system wide faults.
sim/syscall_emul.cc:
sim/syscall_emul.hh:
    Removed the underscores from fault names.

--HG--
rename : arch/alpha/faults.cc => sim/faults.cc
rename : arch/alpha/faults.hh => sim/faults.hh
extra : convert_revision : 253d39258237333ae8ec4d8047367cb3ea68569d
2006-02-16 01:22:51 -05:00
Ron Dreslinski
d142788172 More compilation fixes.
Should we add a proxy_port that does the v->p address translation?
Should the proxy port return a fault on translation errors, if we add one?

arch/alpha/alpha_linux_process.cc:
    Syscalls use a memPort through the CPU now instead of a xc functional memory.
cpu/base.hh:
    Add a pointer to the memPort syscalls will use.  Should this be a proxy_port that does address translation?
cpu/exec_context.cc:
cpu/exec_context.hh:
    Remove functional memory from the exec context
cpu/simple/cpu.cc:
    Set the memPort to be used as the syscall port as the dcache port
sim/syscall_emul.cc:
sim/syscall_emul.hh:
    Syscalls use a memPort through the CPU now instead of a xc functional memory.
    Also, fix the fact that readStringFunctional doesn't return a fault... should proxy_port handle this because it is doing the translation?

--HG--
extra : convert_revision : 1f65318c6594301a75dc4dc0c99fdd436b094a7f
2006-02-15 22:05:23 -05:00
Steve Reinhardt
b8a2d1e5c7 More progress toward compiling... partly by
fixing things, partly by ignoring CPU models
that don't currently compile.

SConscript:
    Split sources for fast, simple, and o3 CPU models into
    separate source lists.  For now none of these are included
    in the base source list, so you won't get any CPU models
    at all... but we still can't compile the other stuff so
    it's not an issue.

    Also get rid of obsolete encumbered/mem file.
base/loader/aout_object.cc:
base/loader/aout_object.hh:
base/loader/ecoff_object.cc:
base/loader/ecoff_object.hh:
base/loader/elf_object.cc:
base/loader/elf_object.hh:
base/loader/object_file.hh:
cpu/exec_context.cc:
sim/process.cc:
sim/system.cc:
sim/system.hh:
    FunctionalMemory -> Memory
cpu/pc_event.hh:
    Get rid of unused badpc.
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
    Move Port functions into .cc file.
mem/port.hh:
    Make recvAddressRangesQuery panic by default instead
    of being abstract... do CPUs need to implement this?
mem/request.hh:
    Add prefetch flags.
sim/syscall_emul.hh:
    Start to fix...

--HG--
extra : convert_revision : ece53b3855f20916caaa381598ac37e8c7adfba7
2006-02-15 17:52:49 -05:00
Ron Dreslinski
90def9ea9e Changes to start making the tree use the new memory system. Trying to compile decoder.cc but fails still.
SConscript:
    Place the memory objects back in the right place
arch/alpha/isa_desc:
    Fix includes to point to the new memory requests
cpu/exec_context.hh:
    Exec context now points to memory object, fix the include paths.
    Convert to prot_read/prot_write functions instead of read and write.
    Convert to new CpuRequestPtr instead of MemReqPtr.
mem/request.hh:
    Add back in support for Request Flags (needed by decoder to tag request) Removed the flags that were associated with packets/coherence.
sim/process.hh:
    Converted to point to new memory objects

--HG--
extra : convert_revision : a0b95380915d63b53194e2a26336d6adb1a0086b
2006-02-15 14:53:02 -05:00
Gabe Black
2c5e03550a Removed isa_traits.hh from targetarch, moved vptr.hh from arch/alpha to sim, fixed an include to have the new location, and removed an ambiguating function declaration in byteswap.hh.
SConscript:
    Moved isa_fullsys_traits.hh out of targetarch, since the only place it's included, and the only place the comments in the file say it should be included, is in the alpha isa_traits.hh
    targetarch/isa_traits.hh is now included through arch/isa_traits.hh
    vptr.hh was removed from targetarch, and moved to sim
arch/alpha/pseudo_inst.cc:
    Moved vptr.hh from targetarch to sim
base/loader/object_file.hh:
base/loader/symtab.hh:
cpu/base.hh:
dev/ide_disk.cc:
    Changed the include of isa_traits.hh from targetarch to arch
cpu/static_inst.hh:
dev/platform.hh:
dev/simple_disk.hh:
kern/tru64/dump_mbuf.cc:
kern/tru64/mbuf.hh:
kern/tru64/tru64_events.cc:
kern/tru64/tru64_system.cc:
kern/tru64/tru64_system.hh:
sim/process.hh:
sim/syscall_emul.hh:
    Changed the include of isa_traits.hh from targetarch to arch.
kern/linux/linux_threadinfo.hh:
    Changed the include of vptr.hh from targetarch to sim.
sim/byteswap.hh:
    Removed the line declaring swap_byte(long), since it ambiguates with swap_byte(int32_t)
sim/vptr.hh:
    Fixed the assert in the equals operator.
    Changed the AlphaISA namespace reference to TheISA.
    Changed arch/alpha/vtophys.hh to targetarch/vtophys.hh, since this file is now for all architectures.
    Added an include of arch/isa_traits.hh so that TheISA would be defined.

--HG--
extra : convert_revision : e3c6ac17ed0277cfeba1d35cd63eba66eba5996f
2006-02-12 12:40:58 -05:00
Ali Saidi
fb7899aa68 fix problems on darwin/*BSD for syscall emulation mode
arch/alpha/alpha_linux_process.cc:
arch/alpha/alpha_tru64_process.cc:
    fixup for bsd hosts. Some headers are included by default which means that
    more variables need TGT_ prefixes and there isn't a stat call (everything
    is a stat64 call) so we have to work around that a bit
base/intmath.hh:
base/socket.cc:
    this is no longer needed with mac os 10.4
cpu/inst_seq.hh:
    just use a uint64_t instead of long long
cpu/o3/inst_queue_impl.hh:
    I much cleaner way to get max int
sim/syscall_emul.hh:
    fix stat64 problems on *BSD

--HG--
extra : convert_revision : 9eef5f896e083ae1774e818a9765dd83e0305942
2006-02-10 14:21:32 -05:00
Gabe Black
82f2ae56ed Alot of changes to push towards ISA independence. Highlights are renaming of the isa_desc files, movement of byte_swap.hh into sim, and the creation of arch/isa_traits.hh
SConscript:
    Moved some files out of targetarch. The either no longer need to be there, never needed to be there, or should be referred to directly in arch/alpha due to there strictly alpha content.
arch/alpha/isa_traits.hh:
    Added alpha's endianness to it's isa_traits.hh
arch/mips/isa_traits.hh:
    Added MIPS endianness to it's isa_traits.hh
arch/sparc/isa_traits.hh:
    Added SPARCs endianess to it's isa_traits.hh
build/SConstruct:
    Added MIPS as a valid architecture
cpu/exec_context.hh:
    Included arch/isa_traits.hh to bring in the endianness of the system.
cpu/o3/alpha_cpu.hh:
    Included arch/isa_traits.hh to bring in the systems endianness, and removed the hardcoding of little endianness
cpu/o3/fetch_impl.hh:
kern/freebsd/freebsd_system.cc:
    Included arch/isa_traits.hh to bring in the systems endianness, and removed the hardcoding to little endianness.
sim/system.cc:
    Included arch/isa_traits.hh to bring in the systems endianness, and removed the hardcoding to little endian.

--HG--
extra : convert_revision : b1ab34b7569db531cd1c74f273b24222e63f9007
2006-02-08 01:03:55 -05:00
Kevin Lim
989292a0fa Update for new memory system. Uses the ports to access memory now. Also supports the response path of the new memory system, as well as retrying accesses.
cpu/simple/cpu.cc:
    Update for new memory system.  Supports using ports to access the memory system.  The IcacheMissStall/DcacheMissStall statuses have been changed to reflect the cache returning a response after a variable latency (due to hit/miss).  They are now DcacheWaitResponse/IcacheWaitResponse.  Also supports retrying accesses.

    For now the body of the copy functions are commented out.
cpu/simple/cpu.hh:
    Update for new memory system.

--HG--
extra : convert_revision : 5a80247537d98ed690f7b6119094d9f59b4c7d73
2006-02-03 15:21:06 -05:00
Gabe Black
2939a7089a byte_swap.hh was removed from arch/alpha/, and replaced by sim/byteswap.hh. The new file uses LittleEndianGuest and BigEndianGuest namespaces to allow selecting the appropriate functions.
arch/alpha/alpha_linux_process.cc:
arch/alpha/alpha_tru64_process.cc:
    Added the endianness namespace. This may change.
cpu/exec_context.hh:
    Changed the include path for byteswap, and forced LittleEndianness for lack of a better solution.
cpu/o3/alpha_cpu.hh:
    Forced LittleEndianness, for lack of a better solution.
cpu/o3/alpha_cpu_impl.hh:
    Cleared away some commented out code.
cpu/o3/fetch_impl.hh:
    Changed the include patch for byteswap, and forced LittleEndianness for lack of a better solution.
cpu/simple/cpu.cc:
    Added an include for byteswap.hh, and fixed the SimpleCPU to LittleEndian. This cpu only does alpha, so that's fine.
dev/disk_image.cc:
    Changed the include path of byteswap.hh
kern/freebsd/freebsd_system.cc:
kern/linux/linux_system.cc:
    Added an include for byteswap.hh, and forced LittleEndianness for lack of a better solution.
sim/system.cc:
    Forced LittleEndianness for lack of a better solution.

--HG--
extra : convert_revision : b95d3e1265a825e04bd77622a3ac09fbac6bd206
2006-02-03 00:16:44 -05:00
Ron Dreslinski
4c40848dcc Remove non-needed functions, fix return values of completion handler.
--HG--
extra : convert_revision : 7c0cb6b13ba68650d54cdc35779517e8c4b5e3ff
2006-01-31 15:03:04 -05:00
Ron Dreslinski
0d74f27313 More changes toward making simpleCpu use new port interface.
cpu/simple/cpu.cc:
    Initialize the ports, also add Request and Packet instead of MemReq.  Initial work at ICache read in place.
cpu/simple/cpu.hh:
    Need to call the completion handler when we see a recieve.

--HG--
extra : convert_revision : a52caee6f0ceb5d9ee1e5acca63a202f5ea71359
2006-01-31 15:00:09 -05:00
Ron Dreslinski
6c7fdb1be7 More include files, removing definition of SendResult whioch isn't needed anymore
cpu/simple/cpu.hh:
    Some needed includes
mem/port.hh:
    Now we removed the sendResult and replaced with void,tick,bool don't need it defined anymore

--HG--
extra : convert_revision : aea08ec299c41b9f9a5b0da7649cef0459315139
2006-01-31 14:42:42 -05:00
Ron Dreslinski
2f644efafa Fixed some void functions with returns, first stab at cpu ports.
cpu/simple/cpu.hh:
    Adding port definitions to simple cpu, still needs work.
mem/bus.hh:
    no return for void functions

--HG--
extra : convert_revision : 42e5bc16af187d3a46eb25a15b600a8a11b88cc5
2006-01-31 14:39:41 -05:00
Steve Reinhardt
0e79d188e1 Hacks to avoid compiling in old FullCPU model.
Needed in the interim until we port the old model over
to the new interface.  Long term we should have a cleaner
solution for controlling which models get compiled in.

SConscript:
    Move old FullCPU source file list to separate full_cpu_sources
    list so we can choose to not include it in compile.
arch/isa_parser.py:
    Hack to avoid generating FullCPU execute files.
    Need a better way to control this.
cpu/exetrace.cc:
    Don't include old FullCPU-specific headers (apparently
    unnecessary anyway--or if not they should be).

--HG--
extra : convert_revision : 00d5a91a9e4d71507404b8c7f4c6e7c7b7ba3853
2006-01-29 17:35:53 -05:00
Steve Reinhardt
03a2aca9a9 Changes for Process object initialization in merged-memory environment.
System object now exists for both fullsys and syscall emulation, as the
latter needs it so that Process objects can find the shared PhysicalMemory
for initialization.
Changes are incomplete: still need to fix up Process (& EioProcess) memory
initialization and syscall emulation code for new mem interface.

arch/alpha/alpha_linux_process.cc:
arch/alpha/alpha_linux_process.hh:
arch/alpha/alpha_tru64_process.cc:
arch/alpha/alpha_tru64_process.hh:
cpu/base.cc:
cpu/base.hh:
    Take System argument in constructor.
cpu/exec_context.cc:
    Take System argument in constructor.
    Merge two constructors into a single one.
cpu/exec_context.hh:
    Take System argument in constructor.
    Merge two constructors into a single one.
    Replace dummy translation with lookup in Process object's page table.
python/m5/objects/Process.py:
    Add System parameter to Process object (& subobjects).
python/m5/objects/System.py:
    Segregate full-system only Process parameters (most of them!).
sim/process.cc:
    Take System argument in constructor.
    Move initialization to startup() callback to occur after system & cpus
    are initialized.
    Generate ProxyMemory object to pass to loader for transparent
    virtual page allocation.
sim/process.hh:
    Take System argument in constructor.
    Move initialization to startup() callback to occur after system & cpus
    are initialized.
sim/system.cc:
sim/system.hh:
    Enable System object for non-full-system too.
    Basically involved putting most of the existing code
    inside '#ifdef FULL_SYSTEM'.
    Key thing needed for syscall emulation at this point is
    the PhysicalMemory object (for Process initialization).

--HG--
extra : convert_revision : f0f34b47bd4f77b502191affd3d03b4d6d9bcdd8
2006-01-28 00:08:22 -05:00
Steve Reinhardt
0cdcb08d90 Change base/intmath.{cc,hh} to follow m5 style.
arch/alpha/alpha_tru64_process.cc:
base/intmath.hh:
base/statistics.cc:
base/str.cc:
cpu/o3/btb.cc:
sim/process.cc:
sim/syscall_emul.hh:
    Rename intmath.hh functions to follow m5 style
    (RoundUp -> roundUp, etc.).
base/intmath.cc:
    Rename intmath.hh functions to follow m5 style
    (RoundUp -> roundUp, etc.).
    Also reindent code in m5 style.

--HG--
extra : convert_revision : 57b853002bc3c9911e122599d9062b41a06d8e6a
2005-12-23 13:32:31 -05:00
Ron Dreslinski
ffc32970f6 Two small fixes for mem_req's and Probe path with MOSI/MOESI
cpu/simple/cpu.cc:
    Properly set the Instruction Read bit in the Memory Request

--HG--
extra : convert_revision : e1a4756f32718fd8ef3ac3db16625bd6d8f07cc5
2005-12-01 18:47:36 -05:00
Nathan Binkert
64fc410ecb switch all profiling stuff to the kernelSymtab since allSymtab
is going away

--HG--
extra : convert_revision : 405ec55615474d0812ed780f26fd4df98e5ec6f5
2005-11-20 18:33:59 -05:00
Nathan Binkert
b62e7d24ec clear the function profile on a stats reset
cpu/profile.hh:
    Add a placeholder for a reset callback

--HG--
extra : convert_revision : 7fa13e5d04daf1cf93eb35c8fdaf67a40ce3ef73
2005-11-20 18:33:17 -05:00
Nathan Binkert
9e8151f392 use Counter to avoid overflowing an int
cpu/profile.hh:
    use Counter for the profile count to avoid overflow

--HG--
extra : convert_revision : bb603b7d139d1736dced26ef0ce1f93ddea30de7
2005-11-20 18:32:22 -05:00
Nathan Binkert
6e6422ab22 For SimpleCPU profiling code, only update the exec context's
profileNode if we got a new one

cpu/simple/cpu.cc:
    Only update the exec context's profileNode if we got a new one

--HG--
extra : convert_revision : a16a7410070b0d811032dc4b86b1368df913b2be
2005-11-20 17:55:11 -05:00
Nathan Binkert
0dcb288365 Cleanup the StackTrace interfaces and profile interfaces so they
are more efficient and reduce the number of new/delete calls

arch/alpha/stacktrace.cc:
    - Change the StackTrace code so that the class can more easily be
    cleaned out and reused to avoid extra allocations.
    - Allow trace() to accept a static instruction pointer so it can
    determine if the instruction is worth tracing.  This is moved from
    the CPU.
    - provide constants for special meaning PCs (user, console, unknown),
    instead of magic numbers
    - switch to using kernelSymtab instead of allSymtab which will be
    going away
    - if the stack adjustment doesn't make any sense, exit and push
    unknown so we don't get into an infinite loop or record garbage.
    - check to see if we've made too many iterations through the stack
    and panic to avoid an infinite loop
arch/alpha/stacktrace.hh:
    - Change the StackTrace code so that the class can more easily be
    cleaned out and reused to avoid extra allocations.
    - Allow trace() to accept a static instruction pointer so it can
    determine if the instruction is worth tracing.  This is moved from
    the CPU.
    - provide constants for special meaning PCs (user, console, unknown),
    instead of magic numbers
cpu/base.cc:
    only clear the profile if we have one
    include profile.hh here since base.hh doesn't do it anymore
cpu/base.hh:
    no need to include cpu/profile.hh here
cpu/profile.cc:
    use ProfileNode pointers instead of objects in the ChildList
    Consume a vector of addresses since that's really all we
    care about.
cpu/profile.hh:
    Keep pointers to ProfileNodes to reduce the size of these structures
    keep a StackTrace around so that we may reuse it.
    provide consume functions that use the new StackTrace trace interface
    one consume function is inline and tries to fastpath the no trace
    condition, it calls the outlined consume function if a trace is generated.
cpu/simple/cpu.cc:
    include cpu/profile.hh here since base.hh no longer does
    use the new FunctionProfile::consume interface
    (which contains the tracing functions)

--HG--
extra : convert_revision : 5a1d9265289a75f67a497b322926be1f8c2d8eb3
2005-11-20 17:44:58 -05:00
Steve Reinhardt
d727c2b6cf Fix Lisa's CPU trace system check for syscall emulation.
cpu/exetrace.cc:
    CPU system name check doesn't work under syscall emulation, so don't
    compile it in.

--HG--
extra : convert_revision : 2c128bf759877222107652fd86323be6dc71a34c
2005-11-10 20:30:04 -05:00
Lisa Hsu
3532a661c5 just commit what i need for dumping traces compatible with intel's casper
--HG--
extra : convert_revision : a0c4a68a576fa771fd553eaedd6a07255a04dca2
2005-11-09 16:42:36 -05:00
Nathan Binkert
a81c03737a Add new function profiling stuff, wrap the pc_sample stuff into it.
SConscript:
    Get rid of the pc_sample stuff and move to the new profiling stuff
base/traceflags.py:
    DPRINTF Stack stuff
cpu/base.cc:
cpu/base.hh:
cpu/exec_context.cc:
cpu/exec_context.hh:
cpu/simple/cpu.cc:
    Add profiling stuff
kern/kernel_stats.hh:
    Use a smart pointer
sim/system.cc:
sim/system.hh:
    Create a new symbol table that has all of the symbols for a
    particular system
util/stats/categories.py:
    change around the categories, add categories for function
    profiling stuff
util/stats/profile.py:
    No profile parsing and display code to deal with function
    profiling stuff, graph, dot, and text outputs.

--HG--
extra : convert_revision : b3de0cdc8bd468e42647966e2640ae009bda9eb8
2005-10-18 19:07:42 -04:00
Lisa Hsu
7b04cd9561 add a flag that supercedes all other InstExec flags to print a trace in the Intel sim compatible format.
--HG--
extra : convert_revision : 19569e5645f2d68fb68a0352753c08c2a24bfdc4
2005-10-09 18:20:54 -04:00
Steve Reinhardt
e90332ff7a Minor cleanup of memtest.
cpu/memtest/memtest.cc:
    Call random() consistently (not sometimes rand() and sometimes random()).
    Don't bother to call random() for copy-only parameters unless we're
    actually doing a copy.

--HG--
extra : convert_revision : 50ef72594ad53ba531584b3c9dde61ac036a4e38
2005-10-03 09:13:56 -04:00
Steve Reinhardt
d60de7122d Add functions to System object to set up function-based events,
including automatically fixing up addresses to deal with
optionally executed Alpha gp update prolog.

SConscript:
    Remove freebsd_events.cc and linux_events.cc.
base/remote_gdb.cc:
cpu/pc_event.cc:
kern/system_events.cc:
kern/system_events.hh:
    PCEvents now schedule themselves in constructor.
cpu/pc_event.hh:
    PCEvents now schedule themselves in the constructor.
    Get rid of constructor versions that don't take an address and
    all the schedule() methods that are now unnecessary.
kern/freebsd/freebsd_system.cc:
kern/freebsd/freebsd_system.hh:
    Use new System methods to schedule function-based events.
    Move FreeBSD-specific function event classes into FreebsdSystem.
kern/linux/linux_system.cc:
kern/linux/linux_system.hh:
    Use new System methods to schedule function-based events.
    Move Linux-specific function event classes into LinuxSystem.
kern/tru64/tru64_events.hh:
    PCEvents now schedule themselves in constructor.
    Add DebugPrintfrEvent to encapsulate raw setting as new type
    (to work better with new System function-event method.)
kern/tru64/tru64_system.cc:
    Use new System methods to schedule function-based events.
kern/tru64/tru64_system.hh:
    Add DebugPrintfrEvent to encapsulate raw setting as new type
    (to work better with new System function-event method.)
sim/system.cc:
sim/system.hh:
    Add functions to set up function-based events, including
    automatically fixing up addresses to deal with optionally
    executed Alpha gp update prolog.

--HG--
extra : convert_revision : c2cf09144297b6602afe755a34a0a2227023783f
2005-09-24 14:20:29 -04:00
Steve Reinhardt
c4793184bd Build options are set via a build_options file in the
build directory instead of being inferred from the name
of the build directory.
Options are passed to C++ via config/*.hh files instead of
via the command line.  Build option flags are now always
defined to 0 or 1, so checks must use '#if' rather than
'#ifdef'.

SConscript:
    MySQL detection moved to SConstruct.
    Add config/*.hh files (via ConfigFile builder).
arch/alpha/alpha_memory.cc:
arch/alpha/ev5.cc:
arch/alpha/ev5.hh:
arch/alpha/isa_traits.hh:
base/fast_alloc.hh:
base/statistics.cc:
base/statistics.hh:
base/stats/events.cc:
base/stats/events.hh:
cpu/base.cc:
cpu/base.hh:
cpu/base_dyn_inst.cc:
cpu/base_dyn_inst.hh:
cpu/exec_context.cc:
cpu/exec_context.hh:
cpu/o3/alpha_cpu.hh:
cpu/o3/alpha_cpu_builder.cc:
cpu/o3/alpha_cpu_impl.hh:
cpu/o3/alpha_dyn_inst.hh:
cpu/o3/alpha_dyn_inst_impl.hh:
cpu/o3/alpha_params.hh:
cpu/o3/commit_impl.hh:
cpu/o3/cpu.cc:
cpu/o3/cpu.hh:
cpu/o3/fetch_impl.hh:
cpu/o3/iew.hh:
cpu/o3/iew_impl.hh:
cpu/o3/regfile.hh:
cpu/o3/rename_impl.hh:
cpu/o3/rob_impl.hh:
cpu/ozone/cpu.hh:
cpu/pc_event.cc:
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
sim/process.cc:
sim/process.hh:
    Convert compile flags from def/undef to 0/1.
    Set via #include config/*.hh instead of command line.
arch/alpha/isa_desc:
    Convert compile flags from def/undef to 0/1.
    Set via #include config/*.hh instead of command line.
    Revamp fenv.h support... most of the ugliness is hidden
    in base/fenv.hh now.
base/mysql.hh:
    Fix typo in #ifndef guard.
build/SConstruct:
    Build options are set via a build_options file in the
    build directory instead of being inferred from the name
    of the build directory.
    Options are passed to C++ via config/*.hh files instead of
    via the command line.
python/SConscript:
    Generate m5_build_env directly from scons options
    instead of indirectly via CPPDEFINES.
python/m5/convert.py:
    Allow '0' and '1' for booleans.
    Rewrite toBool to use dict.
base/fenv.hh:
    Revamp <fenv.h> support to make it a compile option
    (so we can test w/o it even if it's present) and to
    make isa_desc cleaner.

--HG--
extra : convert_revision : 8f97dc11185bef5e1865b3269c7341df8525c9ad
2005-08-30 13:18:54 -04:00
Miguel Serrano
b64eae5e52 Changes for getting FreeBSD to run.
SConscript:
    Added more files to compile: dev/pcifake.cc, dev/isa_fake.cc, kern/freebsd/freebsd_system.cc, kern/freebsd/freebsd_events.cc.
arch/alpha/isa_traits.hh:
    Added constant for argument register 2 as it is needed by FreebsdSystem::doCalibrateClocks().
cpu/exec_context.hh:
cpu/o3/alpha_cpu.hh:
    Replaced htoa()s with gtoh() and htog().
cpu/o3/fetch_impl.hh:
cpu/simple/cpu.cc:
    Replaced htoa() with gtoh().
dev/disk_image.cc:
    Replaced htoa()s with letoh()s.
dev/ide_ctrl.cc:
    Got rid of magic numbers.
    Added IdeChannel and IdeRegType type names where necessary.
dev/ide_ctrl.hh:
    Got rid of unnecessary macros.
    Changed RegType_t to IdeRegType.
    Changed bmi_regs to allow accessing registers by name instead of just by array index.
    Added IdeChannel enum type to use in place of bool variables which were used to specify IDE channel.
dev/ide_disk.cc:
    Rewrote IdeDisk::read and IdeDisk::write functions to specify registers by name instead of indexing through an array.
dev/ide_disk.hh:
    Updated command register struct.
dev/ns_gige.cc:
dev/ns_gige.hh:
    Made ReadConfig and WriteConfig begin with a lower-case letter.
    writeConfig() now takes a pointer to data as a parameter instead of a copy of data.
dev/pciconfigall.cc:
    writeConfig() now takes a pointer to data as a parameter instead of a copy of data.
dev/pcidev.cc:
    Cleaned up readConfig() and writeConfig() functions.
dev/pcidev.hh:
    Added macros to make code that works with the BARs (base adress registers) more readable. writeConfig() now takes a pointer to data.
dev/pcireg.h:
    Changed PCIConfig struct to make accessing elements more straight forward. Removed type 1 (for PCI-to-PCI bridges) PCI configuration space struct since it is not used.
dev/rtcreg.h:
    Added macros for bit fields in RTC status registers A & B.
dev/sinic.cc:
    Function name change: WriteConfig --> writeConfig.
    writeConfig() now takes a pointer to data instead of a copy of data.
    The accessing of elements of PCIConfig structure is updated.
dev/sinic.hh:
    Function name change: WriteConfig --> writeConfig.
    writeConfig() now takes a pointer to data instead of a copy of data.
dev/tsunami_io.cc:
    Added implementation of new RTC and PIT classes.
dev/tsunami_io.hh:
    Added classes for RTC and PIT modules.
dev/tsunamireg.h:
    Added macros for DMA ports used by Tsunami-Tru64.
dev/uart8250.cc:
    Got rid of a magic number.
    Transmit (Tx) interrupts should clear upon a read of the Interrupt ID register.
dev/uart8250.hh:
    Added comments and macros dealing with the UART Interrupt ID register.
kern/linux/linux_system.cc:
    Replaced htoa() with htog().
python/m5/objects/Pci.py:
    PciFake is a python class for Pci Devices that do nothing.
python/m5/objects/Tsunami.py:
    TsunamiFake was renamed as IsaFake.
sim/system.cc:
    Replaced htoa()s with htog()s.
dev/isa_fake.cc:
    New BitKeeper file ``dev/isa_fake.cc''
    TsunamiFake was renamed as IsaFake.
dev/isa_fake.hh:
    New BitKeeper file ``dev/isa_fake.hh''
    TsunmaiFake was renamed as IsaFake.
dev/pitreg.h:
    New BitKeeper file ``dev/pitreg.h''
    Useful macros for working with PIT (Periodic Interval Timer) registers.

--HG--
extra : convert_revision : 33f3a8a1034af4f6c71b32dd743e371c8613e780
2005-08-15 16:59:58 -04:00
Nathan Binkert
8a0bc84022 Allow CPUs to specify their own CPU ids.
Make the AlphaConsole calculate the number of CPUs instead
of passing that in as a parameter.

cpu/base.cc:
    pass the desired cpu_id into registerExecContext, offsetting it
    by the thread number.  a cpu_id of -1 means that it should be
    generated for you.
cpu/base.hh:
    Take the cpu_id as a parameter
cpu/o3/alpha_cpu_builder.cc:
cpu/simple/cpu.cc:
    Accept the cpu_id as a parameter
    while we're here, let's remove the multiplier since it is
    not used.
dev/alpha_console.cc:
    don't take the number of CPUs as a parameter.  Calculate it from
    the system based on the number of CPUs that have been registered.
    move init() code to startup() to ensure that all CPUs are registerd.
dev/alpha_console.hh:
python/m5/objects/AlphaConsole.py:
    don't take the number of CPUs as a parameter.
    move init() code to startup() to ensure that all CPUs are registerd.
python/m5/objects/BaseCPU.py:
    take the cpu_id as a parameter.  Default it to -1 which means
    that it will be generated.
sim/system.cc:
    allow the registerExecContext functioin to take a desired
    cpu_id as a parameter.  Check to ensure that the id isn't
    already used.  Accept -1 as a request to have an id assigned.
sim/system.hh:
    keep track of the number of registered exec contexts.
    provide a function for accessing the number of exec contexts
    that checks to ensure that they are all registered correctly.

--HG--
extra : convert_revision : 8e12f96ff8a49fa16cdbbdb4c05c651376c35788
2005-06-29 01:20:41 -04:00
Nathan Binkert
6ff9439afe Cleanup copyright stuff. Add our copyright files that
are ours

arch/alpha/alpha_linux_process.hh:
arch/alpha/alpha_tru64_process.hh:
base/loader/object_file.cc:
base/loader/object_file.hh:
sim/process.cc:
sim/process.hh:
    remove $Id$ string
cpu/ozone/cpu.cc:
cpu/ozone/cpu_impl.hh:
cpu/ozone/ea_list.cc:
cpu/ozone/ea_list.hh:
kern/linux/sched.hh:
kern/linux/thread_info.hh:
    Add M5 Copyright
cpu/trace/opt_cpu.cc:
dev/rtcreg.h:
    nit
kern/linux/aligned.hh:
kern/linux/hwrpb.hh:
util/oprofile-top.py:
util/stats/db.py:
util/stats/dbinit.py:
util/stats/display.py:
util/stats/info.py:
util/stats/print.py:
util/stats/stats.py:
    Cleanup copyright

--HG--
extra : convert_revision : 4274e9121ef7543e0b3999b31e935edb19c54d46
2005-06-05 11:02:38 -04:00
Steve Reinhardt
5f0f42f166 Fix minor doxygen issues.
Doxyfile:
    Turn on EXTRACT_ALL so we get full class hierarchy info.
base/range.hh:
cpu/o3/fetch.hh:
cpu/o3/rename_map.hh:
cpu/o3/rob.hh:
dev/ide_disk.cc:
dev/tsunami.cc:
dev/tsunami.hh:
dev/tsunami_cchip.hh:
    Fix doxygen issues.

--HG--
extra : convert_revision : 9e0e8d3510b35db201459b8a3211c5e6ad5f0bb4
2005-06-05 08:08:29 -04:00
Steve Reinhardt
ad8b9636f8 Many files:
Update copyright dates and author list

SConscript:
arch/alpha/alpha_linux_process.cc:
arch/alpha/alpha_linux_process.hh:
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
arch/alpha/alpha_tru64_process.cc:
arch/alpha/alpha_tru64_process.hh:
arch/alpha/aout_machdep.h:
arch/alpha/arguments.cc:
arch/alpha/arguments.hh:
arch/alpha/ev5.cc:
arch/alpha/ev5.hh:
arch/alpha/faults.cc:
arch/alpha/faults.hh:
arch/alpha/isa_desc:
arch/alpha/isa_traits.hh:
arch/alpha/osfpal.cc:
arch/alpha/osfpal.hh:
arch/alpha/pseudo_inst.cc:
arch/alpha/pseudo_inst.hh:
arch/alpha/vptr.hh:
arch/alpha/vtophys.cc:
arch/alpha/vtophys.hh:
base/bitfield.hh:
base/callback.hh:
base/circlebuf.cc:
base/circlebuf.hh:
base/cprintf.cc:
base/cprintf.hh:
base/cprintf_formats.hh:
base/crc.hh:
base/date.cc:
base/dbl_list.hh:
base/endian.hh:
base/fast_alloc.cc:
base/fast_alloc.hh:
base/fifo_buffer.cc:
base/fifo_buffer.hh:
base/hashmap.hh:
base/hostinfo.cc:
base/hostinfo.hh:
base/hybrid_pred.cc:
base/hybrid_pred.hh:
base/inet.cc:
base/inet.hh:
base/inifile.cc:
base/inifile.hh:
base/intmath.cc:
base/intmath.hh:
base/match.cc:
base/match.hh:
base/misc.cc:
base/misc.hh:
base/mod_num.hh:
base/mysql.cc:
base/mysql.hh:
base/output.cc:
base/output.hh:
base/pollevent.cc:
base/pollevent.hh:
base/predictor.hh:
base/random.cc:
base/random.hh:
base/range.cc:
base/range.hh:
base/refcnt.hh:
base/remote_gdb.cc:
base/remote_gdb.hh:
base/res_list.hh:
base/sat_counter.cc:
base/sat_counter.hh:
base/sched_list.hh:
base/socket.cc:
base/socket.hh:
base/statistics.cc:
base/statistics.hh:
base/compression/lzss_compression.cc:
base/compression/lzss_compression.hh:
base/compression/null_compression.hh:
base/loader/aout_object.cc:
base/loader/aout_object.hh:
base/loader/ecoff_object.cc:
base/loader/ecoff_object.hh:
base/loader/elf_object.cc:
base/loader/elf_object.hh:
base/loader/object_file.cc:
base/loader/object_file.hh:
base/loader/symtab.cc:
base/loader/symtab.hh:
base/stats/events.cc:
base/stats/events.hh:
base/stats/flags.hh:
base/stats/mysql.cc:
base/stats/mysql.hh:
base/stats/mysql_run.hh:
base/stats/output.hh:
base/stats/statdb.cc:
base/stats/statdb.hh:
base/stats/text.cc:
base/stats/text.hh:
base/stats/types.hh:
base/stats/visit.cc:
base/stats/visit.hh:
base/str.cc:
base/str.hh:
base/time.cc:
base/time.hh:
base/timebuf.hh:
base/trace.cc:
base/trace.hh:
base/userinfo.cc:
base/userinfo.hh:
build/SConstruct:
cpu/base.cc:
cpu/base.hh:
cpu/base_dyn_inst.cc:
cpu/base_dyn_inst.hh:
cpu/exec_context.cc:
cpu/exec_context.hh:
cpu/exetrace.cc:
cpu/exetrace.hh:
cpu/inst_seq.hh:
cpu/intr_control.cc:
cpu/intr_control.hh:
cpu/memtest/memtest.cc:
cpu/pc_event.cc:
cpu/pc_event.hh:
cpu/smt.hh:
cpu/static_inst.cc:
cpu/static_inst.hh:
cpu/memtest/memtest.hh:
cpu/o3/sat_counter.cc:
cpu/o3/sat_counter.hh:
cpu/ozone/cpu.hh:
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
cpu/trace/opt_cpu.cc:
cpu/trace/opt_cpu.hh:
cpu/trace/reader/ibm_reader.cc:
cpu/trace/reader/ibm_reader.hh:
cpu/trace/reader/itx_reader.cc:
cpu/trace/reader/itx_reader.hh:
cpu/trace/reader/m5_reader.cc:
cpu/trace/reader/m5_reader.hh:
cpu/trace/reader/mem_trace_reader.cc:
cpu/trace/reader/mem_trace_reader.hh:
cpu/trace/trace_cpu.cc:
cpu/trace/trace_cpu.hh:
dev/alpha_access.h:
dev/alpha_console.cc:
dev/alpha_console.hh:
dev/baddev.cc:
dev/baddev.hh:
dev/disk_image.cc:
dev/disk_image.hh:
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherdump.cc:
dev/etherdump.hh:
dev/etherint.cc:
dev/etherint.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/etherpkt.cc:
dev/etherpkt.hh:
dev/ethertap.cc:
dev/ethertap.hh:
dev/ide_ctrl.cc:
dev/ide_ctrl.hh:
dev/ide_disk.cc:
dev/ide_disk.hh:
dev/io_device.cc:
dev/io_device.hh:
dev/ns_gige.cc:
dev/ns_gige.hh:
dev/ns_gige_reg.h:
dev/pciconfigall.cc:
dev/pciconfigall.hh:
dev/pcidev.cc:
dev/pcidev.hh:
dev/pcireg.h:
dev/pktfifo.cc:
dev/pktfifo.hh:
dev/platform.cc:
dev/platform.hh:
dev/simconsole.cc:
dev/simconsole.hh:
dev/simple_disk.cc:
dev/simple_disk.hh:
dev/sinic.cc:
dev/sinic.hh:
dev/sinicreg.hh:
dev/tsunami.cc:
dev/tsunami.hh:
dev/tsunami_cchip.cc:
dev/tsunami_cchip.hh:
dev/tsunami_io.cc:
dev/tsunami_io.hh:
dev/tsunami_pchip.cc:
dev/tsunami_pchip.hh:
dev/tsunamireg.h:
dev/uart.cc:
dev/uart.hh:
dev/uart8250.cc:
dev/uart8250.hh:
docs/stl.hh:
encumbered/cpu/full/op_class.hh:
kern/kernel_stats.cc:
kern/kernel_stats.hh:
kern/linux/linux.hh:
kern/linux/linux_syscalls.cc:
kern/linux/linux_syscalls.hh:
kern/linux/linux_system.cc:
kern/linux/linux_system.hh:
kern/linux/linux_threadinfo.hh:
kern/linux/printk.cc:
kern/linux/printk.hh:
kern/system_events.cc:
kern/system_events.hh:
kern/tru64/dump_mbuf.cc:
kern/tru64/dump_mbuf.hh:
kern/tru64/mbuf.hh:
kern/tru64/printf.cc:
kern/tru64/printf.hh:
kern/tru64/tru64.hh:
kern/tru64/tru64_events.cc:
kern/tru64/tru64_events.hh:
kern/tru64/tru64_syscalls.cc:
kern/tru64/tru64_syscalls.hh:
kern/tru64/tru64_system.cc:
kern/tru64/tru64_system.hh:
python/SConscript:
python/m5/__init__.py:
python/m5/config.py:
python/m5/convert.py:
python/m5/multidict.py:
python/m5/smartdict.py:
sim/async.hh:
sim/builder.cc:
sim/builder.hh:
sim/debug.cc:
sim/debug.hh:
sim/eventq.cc:
sim/eventq.hh:
sim/host.hh:
sim/main.cc:
sim/param.cc:
sim/param.hh:
sim/process.cc:
sim/process.hh:
sim/root.cc:
sim/serialize.cc:
sim/serialize.hh:
sim/sim_events.cc:
sim/sim_events.hh:
sim/sim_exit.hh:
sim/sim_object.cc:
sim/sim_object.hh:
sim/startup.cc:
sim/startup.hh:
sim/stat_control.cc:
sim/stat_control.hh:
sim/stats.hh:
sim/syscall_emul.cc:
sim/syscall_emul.hh:
sim/system.cc:
sim/system.hh:
test/bitvectest.cc:
test/circletest.cc:
test/cprintftest.cc:
test/genini.py:
test/initest.cc:
test/lru_test.cc:
test/nmtest.cc:
test/offtest.cc:
test/paramtest.cc:
test/rangetest.cc:
test/sized_test.cc:
test/stattest.cc:
test/strnumtest.cc:
test/symtest.cc:
test/tokentest.cc:
test/tracetest.cc:
util/ccdrv/devtime.c:
util/m5/m5.c:
util/oprofile-top.py:
util/rundiff:
util/m5/m5op.h:
util/m5/m5op.s:
util/stats/db.py:
util/stats/dbinit.py:
util/stats/display.py:
util/stats/info.py:
util/stats/print.py:
util/stats/stats.py:
util/tap/tap.cc:
    Update copyright dates and author list

--HG--
extra : convert_revision : 0faba08fc0fc0146f1efb7f61e4b043c020ff9e4
2005-06-05 05:16:00 -04:00
Kevin Lim
77b9829f13 Update #defines for the O3CPU. Also include the copyright.
base/timebuf.hh:
    Updated copyright.
cpu/o3/2bit_local_pred.hh:
cpu/o3/alpha_cpu.hh:
cpu/o3/alpha_cpu_impl.hh:
cpu/o3/alpha_dyn_inst.hh:
cpu/o3/alpha_impl.hh:
cpu/o3/alpha_params.hh:
cpu/o3/btb.hh:
cpu/o3/comm.hh:
cpu/o3/commit.hh:
cpu/o3/cpu.cc:
cpu/o3/cpu.hh:
cpu/o3/cpu_policy.hh:
cpu/o3/decode.hh:
cpu/o3/fetch.hh:
cpu/o3/free_list.hh:
cpu/o3/iew.hh:
cpu/o3/inst_queue.hh:
cpu/o3/mem_dep_unit.hh:
cpu/o3/ras.hh:
cpu/o3/regfile.hh:
cpu/o3/rename.hh:
cpu/o3/rename_map.hh:
cpu/o3/rob.cc:
cpu/o3/rob.hh:
cpu/o3/rob_impl.hh:
cpu/o3/sat_counter.hh:
cpu/o3/store_set.hh:
cpu/o3/tournament_pred.hh:
    Updated #define to have correct path.
docs/footer.html:
    Remove e-mail addr.

--HG--
extra : convert_revision : 68d7af52674621dc3b6d6ac0d564790ffd595fe3
2005-06-05 03:25:26 -04:00
Nathan Binkert
11f0c01207 Merge zizzer.eecs.umich.edu:/bk/m5
into crampon.my.domain:/z/binkertn/research/m5/head

--HG--
extra : convert_revision : d46f23e63e4a8c6325bcdeaf6cdd76b9e6208707
2005-06-05 02:59:44 -04:00
Steve Reinhardt
550003e1b7 Change SamplingCPU to Sampler.
--HG--
extra : convert_revision : ddba327a572804954adcebfff1182b97d474c020
2005-06-05 02:59:43 -04:00
Nathan Binkert
e71ee12eac move eio stuff to encumbered
--HG--
extra : convert_revision : 9061382dba285c84931f8825e7159db0e9899944
2005-06-05 02:26:19 -04:00
Nathan Binkert
13c005a8af shuffle files around for new directory structure
--HG--
rename : cpu/base_cpu.cc => cpu/base.cc
rename : cpu/base_cpu.hh => cpu/base.hh
rename : cpu/beta_cpu/2bit_local_pred.cc => cpu/o3/2bit_local_pred.cc
rename : cpu/beta_cpu/2bit_local_pred.hh => cpu/o3/2bit_local_pred.hh
rename : cpu/beta_cpu/alpha_full_cpu.cc => cpu/o3/alpha_cpu.cc
rename : cpu/beta_cpu/alpha_full_cpu.hh => cpu/o3/alpha_cpu.hh
rename : cpu/beta_cpu/alpha_full_cpu_builder.cc => cpu/o3/alpha_cpu_builder.cc
rename : cpu/beta_cpu/alpha_full_cpu_impl.hh => cpu/o3/alpha_cpu_impl.hh
rename : cpu/beta_cpu/alpha_dyn_inst.cc => cpu/o3/alpha_dyn_inst.cc
rename : cpu/beta_cpu/alpha_dyn_inst.hh => cpu/o3/alpha_dyn_inst.hh
rename : cpu/beta_cpu/alpha_dyn_inst_impl.hh => cpu/o3/alpha_dyn_inst_impl.hh
rename : cpu/beta_cpu/alpha_impl.hh => cpu/o3/alpha_impl.hh
rename : cpu/beta_cpu/alpha_params.hh => cpu/o3/alpha_params.hh
rename : cpu/beta_cpu/bpred_unit.cc => cpu/o3/bpred_unit.cc
rename : cpu/beta_cpu/bpred_unit.hh => cpu/o3/bpred_unit.hh
rename : cpu/beta_cpu/bpred_unit_impl.hh => cpu/o3/bpred_unit_impl.hh
rename : cpu/beta_cpu/btb.cc => cpu/o3/btb.cc
rename : cpu/beta_cpu/btb.hh => cpu/o3/btb.hh
rename : cpu/beta_cpu/comm.hh => cpu/o3/comm.hh
rename : cpu/beta_cpu/commit.cc => cpu/o3/commit.cc
rename : cpu/beta_cpu/commit.hh => cpu/o3/commit.hh
rename : cpu/beta_cpu/commit_impl.hh => cpu/o3/commit_impl.hh
rename : cpu/beta_cpu/full_cpu.cc => cpu/o3/cpu.cc
rename : cpu/beta_cpu/full_cpu.hh => cpu/o3/cpu.hh
rename : cpu/beta_cpu/cpu_policy.hh => cpu/o3/cpu_policy.hh
rename : cpu/beta_cpu/decode.cc => cpu/o3/decode.cc
rename : cpu/beta_cpu/decode.hh => cpu/o3/decode.hh
rename : cpu/beta_cpu/decode_impl.hh => cpu/o3/decode_impl.hh
rename : cpu/beta_cpu/fetch.cc => cpu/o3/fetch.cc
rename : cpu/beta_cpu/fetch.hh => cpu/o3/fetch.hh
rename : cpu/beta_cpu/fetch_impl.hh => cpu/o3/fetch_impl.hh
rename : cpu/beta_cpu/free_list.cc => cpu/o3/free_list.cc
rename : cpu/beta_cpu/free_list.hh => cpu/o3/free_list.hh
rename : cpu/beta_cpu/iew.cc => cpu/o3/iew.cc
rename : cpu/beta_cpu/iew.hh => cpu/o3/iew.hh
rename : cpu/beta_cpu/iew_impl.hh => cpu/o3/iew_impl.hh
rename : cpu/beta_cpu/inst_queue.cc => cpu/o3/inst_queue.cc
rename : cpu/beta_cpu/inst_queue.hh => cpu/o3/inst_queue.hh
rename : cpu/beta_cpu/inst_queue_impl.hh => cpu/o3/inst_queue_impl.hh
rename : cpu/beta_cpu/mem_dep_unit.cc => cpu/o3/mem_dep_unit.cc
rename : cpu/beta_cpu/mem_dep_unit.hh => cpu/o3/mem_dep_unit.hh
rename : cpu/beta_cpu/mem_dep_unit_impl.hh => cpu/o3/mem_dep_unit_impl.hh
rename : cpu/beta_cpu/ras.cc => cpu/o3/ras.cc
rename : cpu/beta_cpu/ras.hh => cpu/o3/ras.hh
rename : cpu/beta_cpu/regfile.hh => cpu/o3/regfile.hh
rename : cpu/beta_cpu/rename.cc => cpu/o3/rename.cc
rename : cpu/beta_cpu/rename.hh => cpu/o3/rename.hh
rename : cpu/beta_cpu/rename_impl.hh => cpu/o3/rename_impl.hh
rename : cpu/beta_cpu/rename_map.cc => cpu/o3/rename_map.cc
rename : cpu/beta_cpu/rename_map.hh => cpu/o3/rename_map.hh
rename : cpu/beta_cpu/rob.cc => cpu/o3/rob.cc
rename : cpu/beta_cpu/rob.hh => cpu/o3/rob.hh
rename : cpu/beta_cpu/rob_impl.hh => cpu/o3/rob_impl.hh
rename : cpu/beta_cpu/sat_counter.cc => cpu/o3/sat_counter.cc
rename : cpu/beta_cpu/sat_counter.hh => cpu/o3/sat_counter.hh
rename : cpu/beta_cpu/store_set.cc => cpu/o3/store_set.cc
rename : cpu/beta_cpu/store_set.hh => cpu/o3/store_set.hh
rename : cpu/beta_cpu/tournament_pred.cc => cpu/o3/tournament_pred.cc
rename : cpu/beta_cpu/tournament_pred.hh => cpu/o3/tournament_pred.hh
rename : cpu/ooo_cpu/ooo_cpu.cc => cpu/ozone/cpu.cc
rename : cpu/ooo_cpu/ooo_cpu.hh => cpu/ozone/cpu.hh
rename : cpu/ooo_cpu/ooo_impl.hh => cpu/ozone/cpu_impl.hh
rename : cpu/ooo_cpu/ea_list.cc => cpu/ozone/ea_list.cc
rename : cpu/ooo_cpu/ea_list.hh => cpu/ozone/ea_list.hh
rename : cpu/simple_cpu/simple_cpu.cc => cpu/simple/cpu.cc
rename : cpu/simple_cpu/simple_cpu.hh => cpu/simple/cpu.hh
rename : cpu/full_cpu/smt.hh => cpu/smt.hh
rename : cpu/full_cpu/op_class.hh => encumbered/cpu/full/op_class.hh
extra : convert_revision : c4a891d8d6d3e0e9e5ea56be47d851da44d8c032
2005-06-04 20:50:10 -04:00
Nathan Binkert
6b6445eeb9 more portable
arch/alpha/alpha_tru64_process.cc:
    Sort #includes
    Make code more portable. g++ doesn't seem to always like
    struct ::stat (and others). So, we typedef stat outside of
    the namespace as something else and use the typedef
base/hostinfo.cc:
    use snprintf to quell warning
base/inifile.cc:
    use strncpy to quell warning
base/stats/events.cc:
    don't use strcpy
cpu/beta_cpu/btb.cc:
    use FloorLog2 instead of log2
cpu/beta_cpu/comm.hh:
cpu/beta_cpu/inst_queue.hh:
cpu/beta_cpu/sat_counter.hh:
    use sim/host.hh instead of stdint.h

--HG--
extra : convert_revision : 59bd9235dda74e72a8b6a70b3f3a981840384f3f
2005-06-04 14:16:04 -04:00
Steve Reinhardt
62fa781fee Rename sim/universe.{cc,hh} to root.{cc,hh} (since the
object defined there was renamed Root long ago).

SConscript:
arch/alpha/alpha_linux_process.cc:
arch/alpha/alpha_tru64_process.cc:
base/misc.cc:
base/pollevent.cc:
base/pollevent.hh:
base/stats/events.cc:
base/trace.hh:
cpu/beta_cpu/fetch_impl.hh:
cpu/beta_cpu/full_cpu.cc:
cpu/beta_cpu/inst_queue_impl.hh:
cpu/pc_event.cc:
cpu/static_inst.cc:
dev/etherbus.cc:
dev/etherdump.cc:
dev/etherlink.cc:
dev/ide_disk.cc:
dev/pcidev.cc:
sim/builder.cc:
sim/eventq.cc:
sim/main.cc:
sim/root.cc:
sim/stat_control.cc:
    Rename sim/universe.{cc,hh} to root.{cc,hh}.

--HG--
rename : sim/universe.cc => sim/root.cc
extra : convert_revision : b8699e81e285253d66da75412e7bb2c251c0389a
2005-06-01 21:59:27 -04:00
Steve Reinhardt
8031cd93b5 Standardize clock parameter names to 'clock'.
Fix description for Bus clock_ratio (no longer a ratio).
Add Clock param type (generic Frequency or Latency).

cpu/base_cpu.cc:
cpu/base_cpu.hh:
cpu/beta_cpu/alpha_full_cpu_builder.cc:
cpu/simple_cpu/simple_cpu.cc:
dev/ide_ctrl.cc:
dev/ns_gige.cc:
dev/ns_gige.hh:
dev/pciconfigall.cc:
dev/sinic.cc:
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
dev/uart.cc:
python/m5/objects/BaseCPU.py:
python/m5/objects/BaseCache.py:
python/m5/objects/BaseSystem.py:
python/m5/objects/Bus.py:
python/m5/objects/Ethernet.py:
python/m5/objects/Root.py:
sim/universe.cc:
    Standardize clock parameter names to 'clock'.
    Fix description for Bus clock_ratio (no longer a ratio).
python/m5/config.py:
    Minor tweaks on Frequency/Latency:
    - added new Clock param type to avoid ambiguities
    - factored out init code into getLatency()
    - made RootFrequency *not* a subclass of Frequency so it
    can't be directly assigned to a Frequency paremeter

--HG--
extra : convert_revision : fc4bb8562df171b454bbf696314cda57e1ec8506
2005-06-01 21:44:00 -04:00
Kevin Lim
2a85931c5e Added copyright.
--HG--
extra : convert_revision : f6d53ac5130ea9f77f39f7c1aa35eeb1d5107599
2005-05-26 23:30:12 -04:00
Steve Reinhardt
432e779fb0 Little debugging things.
cpu/base_cpu.cc:
    Get rid of leftover debugging code.

--HG--
extra : convert_revision : b33b2279499456b12a6242a9472ea5be724b37be
2005-05-24 16:37:30 -04:00
Steve Reinhardt
9725c13a0b Minor changes to get new cpu to compile with FULL_SYSTEM.
cpu/beta_cpu/full_cpu.hh:
    Make cpu_id protected rather than private so derived
    classes can access it.
cpu/beta_cpu/regfile.hh:
    Get rid of troublesome debugging statement.

--HG--
extra : convert_revision : ae1f841697ea8d736579b8278eaf8fc6bdf3b6c5
2005-05-20 17:13:37 -04:00
Kevin Lim
c2fcac7c0d Fix up code for initial release. The main bug that remains is properly forwarding data from stores to loads, specifically when they are of differing sizes.
cpu/base_dyn_inst.cc:
    Remove unused commented out code.
cpu/base_dyn_inst.hh:
    Fix up comments.
cpu/beta_cpu/2bit_local_pred.cc:
    Reorder code to match header file.
cpu/beta_cpu/2bit_local_pred.hh:
    Update comments.
cpu/beta_cpu/alpha_dyn_inst.hh:
    Remove useless comments.
cpu/beta_cpu/alpha_dyn_inst_impl.hh:
cpu/beta_cpu/alpha_full_cpu_impl.hh:
cpu/beta_cpu/comm.hh:
cpu/beta_cpu/iew_impl.hh:
    Remove unused commented code.
cpu/beta_cpu/alpha_full_cpu.hh:
    Remove obsolete comment.
cpu/beta_cpu/alpha_impl.hh:
cpu/beta_cpu/full_cpu.hh:
    Alphabetize includes.
cpu/beta_cpu/bpred_unit.hh:
    Remove unused global history code.
cpu/beta_cpu/btb.hh:
cpu/beta_cpu/free_list.hh:
    Use full path in #defines.
cpu/beta_cpu/commit.hh:
cpu/beta_cpu/decode.hh:
    Reorder functions.
cpu/beta_cpu/commit_impl.hh:
    Remove obsolete commented code.
cpu/beta_cpu/fetch.hh:
    Remove obsolete comments.
cpu/beta_cpu/fetch_impl.hh:
cpu/beta_cpu/rename_impl.hh:
    Remove commented code.
cpu/beta_cpu/full_cpu.cc:
    Remove useless defines.
cpu/beta_cpu/inst_queue.hh:
    Use full path for #defines.
cpu/beta_cpu/inst_queue_impl.hh:
    Reorder functions to match header file.
cpu/beta_cpu/mem_dep_unit.hh:
    Use full path name for #defines.
cpu/beta_cpu/ras.hh:
    Use full path names for #defines.  Remove mod operation.
cpu/beta_cpu/regfile.hh:
    Remove unused commented code, fix up current comments.
cpu/beta_cpu/tournament_pred.cc:
cpu/beta_cpu/tournament_pred.hh:
    Update programming style.

--HG--
extra : convert_revision : fb9d18a853f58a1108ff827e3c123d5b52a0608a
2005-05-19 01:28:25 -04:00
Kevin Lim
61d95de4c8 Large update of several parts of my code. The most notable change is the inclusion of a full-fledged load/store queue. At the moment it still has some issues running, but most of the code is hopefully close to the final version.
SConscript:
arch/isa_parser.py:
cpu/base_dyn_inst.cc:
    Remove OOO CPU stuff.
arch/alpha/faults.hh:
    Add fake memory fault.  This will be removed eventually.
arch/alpha/isa_desc:
    Change EA comp and Mem accessor to be const StaticInstPtrs.
cpu/base_dyn_inst.hh:
    Update read/write calls to use load queue and store queue indices.
cpu/beta_cpu/alpha_dyn_inst.hh:
    Change to const StaticInst in the register accessors.
cpu/beta_cpu/alpha_dyn_inst_impl.hh:
    Update syscall code with thread numbers.
cpu/beta_cpu/alpha_full_cpu.hh:
    Alter some of the full system code so it will compile without errors.
cpu/beta_cpu/alpha_full_cpu_builder.cc:
    Created a DerivAlphaFullCPU class so I can instantiate different CPUs that have different template parameters.
cpu/beta_cpu/alpha_full_cpu_impl.hh:
    Update some of the full system code so it compiles.
cpu/beta_cpu/alpha_params.hh:
cpu/beta_cpu/fetch_impl.hh:
    Remove asid.
cpu/beta_cpu/comm.hh:
    Remove global history field.
cpu/beta_cpu/commit.hh:
    Comment out rename map.
cpu/beta_cpu/commit_impl.hh:
    Update some of the full system code so it compiles.  Also change it so that it handles memory instructions properly.
cpu/beta_cpu/cpu_policy.hh:
    Removed IQ from the IEW template parameter to make it more uniform.
cpu/beta_cpu/decode.hh:
    Add debug function.
cpu/beta_cpu/decode_impl.hh:
    Slight updates for decode in the case where it causes a squash.
cpu/beta_cpu/fetch.hh:
cpu/beta_cpu/rob.hh:
    Comment out unneccessary code.
cpu/beta_cpu/full_cpu.cc:
    Changed some of the full system code so it compiles.  Updated exec contexts and so forth to hopefully make multithreading easier.
cpu/beta_cpu/full_cpu.hh:
    Updated some of the full system code to make it compile.
cpu/beta_cpu/iew.cc:
    Removed IQ from template parameter to IEW.
cpu/beta_cpu/iew.hh:
    Removed IQ from template parameter to IEW. Updated IEW to recognize the Load/Store queue.
cpu/beta_cpu/iew_impl.hh:
    New handling of memory instructions through the Load/Store queue.
cpu/beta_cpu/inst_queue.hh:
    Updated comment.
cpu/beta_cpu/inst_queue_impl.hh:
    Slightly different handling of memory instructions due to Load/Store queue.
cpu/beta_cpu/regfile.hh:
    Updated full system code so it compiles.
cpu/beta_cpu/rob_impl.hh:
    Moved some code around; no major functional changes.
cpu/ooo_cpu/ooo_cpu.hh:
    Slight updates to OOO CPU; still does not work.
cpu/static_inst.hh:
    Remove OOO CPU stuff.  Change ea comp and mem acc to return const StaticInst.
kern/kernel_stats.hh:
    Extra forward declares added due to compile error.

--HG--
extra : convert_revision : 594a7cdbe57f6c2bda7d08856fcd864604a6238e
2005-05-03 10:56:47 -04:00
Kevin Lim
6191d3e444 Merge ktlim@zizzer.eecs.umich.edu:/bk/m5
into zamp.eecs.umich.edu:/z/ktlim2/m5

--HG--
extra : convert_revision : ac0788599c365b2d7fe0870f0fea4b62c3b3ef22
2005-05-02 14:16:33 -04:00
Ron Dreslinski
e07fee31cb Clean up output for pc break events, and remove a unneeded break event.
cpu/pc_event.cc:
    Add a newline to the printout to clean up output
kern/linux/linux_system.cc:
    Remove the die_if_kernel pc break event, it is being called when not the kernel and leads to unneeded printouts

--HG--
extra : convert_revision : c359532db31c961074894cc6c44c8452592caca8
2005-04-28 17:24:04 -04:00
Kevin Lim
26d6d97f5d Merge ktlim@zizzer.eecs.umich.edu:/bk/m5
into zamp.eecs.umich.edu:/z/ktlim2/m5

--HG--
extra : convert_revision : 0baadd8d68bfa6f8e96307eb2d4426b0d9e0b8b4
2005-04-14 16:06:34 -04:00
Nathan Binkert
5eab6c4b41 Make the notion of a global event tick independent of the actual
CPU cycle ticks.  This allows the user to have CPUs of different
frequencies, and also allows frequencies and latencies that are
not evenly divisible by the CPU frequency.  For now, the CPU
frequency is still set to the global frequency, but soon, we'll
hopefully make the global frequency fixed at something like 1THz
and set all other frequencies independently.

arch/alpha/ev5.cc:
    The cycles counter is based on the current cpu cycle.
cpu/base_cpu.cc:
    frequency isn't the cpu parameter anymore, cycleTime is.
cpu/base_cpu.hh:
    frequency isn't the cpu parameter anymore, cycleTime is.
    create several public functions for getting the cpu frequency
    and the numbers of ticks for a given number of cycles, etc.
cpu/memtest/memtest.cc:
cpu/simple_cpu/simple_cpu.cc:
cpu/simple_cpu/simple_cpu.hh:
cpu/trace/trace_cpu.cc:
    Now that ticks aren't cpu cycles, fixup code to advance
    by the proper number of ticks.
cpu/memtest/memtest.hh:
cpu/trace/trace_cpu.hh:
    Provide a function to get the number of ticks for a given
    number of cycles.
dev/alpha_console.cc:
    Update for changes in the way that frequencies and latencies are
    accessed.  Move some stuff to init()
dev/alpha_console.hh:
    Need a pointer to the system and the cpu to get the frequency
    so we can pass the info to the console code.
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/ethertap.cc:
dev/ide_disk.hh:
dev/ns_gige.cc:
dev/ns_gige.hh:
    update for changes in the way bandwidths are passed from
    python to C++ to accomidate the new way that ticks works.
dev/ide_disk.cc:
    update for changes in the way bandwidths are passed from
    python to C++ to accomidate the new way that ticks works.
    Add some extra debugging printfs
dev/platform.cc:
dev/sinic.cc:
dev/sinic.hh:
    outline the constructor and destructor
dev/platform.hh:
    outline the constructor and destructor.
    don't keep track of the interrupt frequency.  Only provide the
    accessor function.
dev/tsunami.cc:
dev/tsunami.hh:
    outline the constructor and destructor
    Don't set the interrupt frequency here.  Get it from the actual device
    that does the interrupting.
dev/tsunami_io.cc:
dev/tsunami_io.hh:
    Make the interrupt interval a configuration parameter.  (And convert
    the interval to the new latency/frequency stuff in the python)
kern/linux/linux_system.cc:
    update for changes in the way bandwidths are passed from
    python to C++ to accomidate the new way that ticks works.
    For now, we must get the boot cpu's frequency as a parameter
    since allowing the system to have a pointer to the boot cpu would
    cause a cycle.
kern/tru64/tru64_system.cc:
    For now, we must get the boot cpu's frequency as a parameter
    since allowing the system to have a pointer to the boot cpu would
    cause a cycle.
python/m5/config.py:
    Fix support for cycle_time relative latencies and frequencies.
    Add support for getting a NetworkBandwidth or a MemoryBandwidth.
python/m5/objects/BaseCPU.mpy:
    All CPUs now have a cycle_time.  The default is the global frequency,
    but it is now possible to set the global frequency to some large value
    (like 1THz) and set each CPU frequency independently.
python/m5/objects/BaseCache.mpy:
python/m5/objects/Ide.mpy:
    Make this a Latency parameter
python/m5/objects/BaseSystem.mpy:
    We need to pass the boot CPU's frequency to the system
python/m5/objects/Ethernet.mpy:
    Update parameter types to use latency and bandwidth types
python/m5/objects/Platform.mpy:
    this frequency isn't needed.  We get it from the clock interrupt.
python/m5/objects/Tsunami.mpy:
    The clock generator should hold the frequency
sim/eventq.hh:
    Need to remove this assertion because the writeback event
    queue is different from the CPU's event queue which can cause
    this assertion to fail.
sim/process.cc:
    Fix comment.
sim/system.hh:
    Struct member to hold the boot CPU's frequency.
sim/universe.cc:
    remove unneeded variable.

--HG--
extra : convert_revision : 51efe4041095234bf458d9b3b0d417f4cae16fdc
2005-04-11 15:32:06 -04:00
Kevin Lim
cfa4221e19 Merge ktlim@zizzer.eecs.umich.edu:/bk/m5
into zamp.eecs.umich.edu:/z/ktlim2/m5

--HG--
extra : convert_revision : cbf8da2fe5c4155d9ed8318597d543ff105449d3
2005-03-18 15:32:53 -05:00
Ali Saidi
caf16a99cc during a cache miss in the simple cpu we were finalizing the trace
data too early (before the cache miss completed) and therefore
writing freeded memory after the cache miss completed.

Also removed some spurious setAddr() and setData() calls.

--HG--
extra : convert_revision : 3da82540c69c4c417aba3ed155e167d09431a1b2
2005-03-15 17:31:18 -05:00
Kevin Lim
3833533a64 Merge ktlim@zizzer.eecs.umich.edu:/bk/m5
into zamp.eecs.umich.edu:/z/ktlim2/m5

--HG--
extra : convert_revision : 1391d03656a1d75809217c5b2e2aecca6f8a04ba
2005-03-15 15:13:24 -05:00
Nathan Binkert
0acb2d0108 small cleanup to sampling cpu code.
cpu/base_cpu.cc:
    By default we should panic if the system doesn't explicitly support
    switchover.

--HG--
extra : convert_revision : 4da2ec316d609cfb351fc5ceaa6d8fe36be14d4e
2005-03-15 12:17:22 -05:00
Kevin Lim
c12a665c31 Merge ktlim@zizzer.eecs.umich.edu:/bk/m5
into zamp.eecs.umich.edu:/z/ktlim2/m5

--HG--
extra : convert_revision : a58535776cf5a3d17f8d9f65144cdf8db54289aa
2005-03-10 15:53:27 -05:00
Ron Dreslinski
e51850f1d2 Merge zizzer:/z/m5/Bitkeeper/m5
into zizzer.eecs.umich.edu:/.automount/zazzer/z/rdreslin/m5bk/timing_L1

--HG--
extra : convert_revision : a5ee8e5187503203058da35ca44918f1ff7ae1eb
2005-03-10 11:56:07 -05:00
Ali Saidi
232134a816 Changed all syscalls to use syscall return object.
arch/alpha/alpha_linux_process.cc:
arch/alpha/alpha_tru64_process.cc:
cpu/exec_context.hh:
sim/process.hh:
sim/syscall_emul.cc:
sim/syscall_emul.hh:
    Changed all syscalls to use syscall return object
arch/alpha/isa_traits.hh:
    Added syscall return object that packages return value and return
    status into an object.
sim/process.cc:
    renamed variable name to nm so base class function name() can be called

--HG--
extra : convert_revision : 6609c5ffecc9e3519d7a0cd160879fd21d54abfc
2005-03-09 15:52:10 -05:00
Kevin Lim
2162b433ad Hand-merge static_inst.hh. These execute functions are within an external file in the new CPU case.
cpu/static_inst.hh:
    Hand-merge.  These execute functions are within an external file in the new CPU case.

--HG--
extra : convert_revision : a34112f471fa31bdd5bb53552ddd704b9571c110
2005-03-08 21:03:20 -05:00
Ron Dreslinski
b290ecf1bb Merge zizzer:/z/m5/Bitkeeper/m5
into zizzer.eecs.umich.edu:/.automount/zazzer/z/rdreslin/m5bk/timing_L1

--HG--
extra : convert_revision : 2b73bffea88cb0e3bb5dff232a15afea8498f4e3
2005-03-07 10:58:15 -05:00
Steve Reinhardt
58c29640b7 Add a new operation class for IPR accesses, and have IPR-accessing
instructions use it (instead of IntALU, as before).  Default config
has a single non-pipelined 3-cycle unit.  A bit conservative for the
ev6 (some are 1, some are 3).

arch/alpha/isa_desc:
    Make hw_mfpr and hw_mtpr use IprAccessOp op class.
cpu/full_cpu/op_class.hh:
    Add IprAccess.

--HG--
extra : convert_revision : d4103da3343a586936839e29981fd15d6930d442
2005-03-01 00:39:57 -05:00
Steve Reinhardt
89dc94f3bc Make all StaticInst methods const. StaticInst objects represent a
particular binary machine instruction and should be immutable after
they are constructed.

cpu/simple_cpu/simple_cpu.hh:
    Make StaticInst parameters const.

--HG--
extra : convert_revision : e535fa10c842ce173336323f39d9108c1847f8ba
2005-02-25 21:44:33 -05:00
Kevin Lim
bb41c21d6a Merge ktlim@zizzer.eecs.umich.edu:/bk/m5
into zamp.eecs.umich.edu:/z/ktlim2/m5

--HG--
extra : convert_revision : ba556bbc93275fcd920a0529383fd480bb7218de
2005-02-25 18:01:19 -05:00
Kevin Lim
5c4714c1a9 Initial light-weight OoO CPU checkin, along with gcc-3.4 fixes.
SConscript:
    Include new files.
arch/alpha/isa_desc:
    Make the eaCompPtr and memAccPtr non-const so that execute() can be called on them.
arch/alpha/isa_traits.hh:
    Add enum for total number of data registers.
arch/isa_parser.py:
base/traceflags.py:
    Include new light-weight OoO CPU model.
cpu/base_dyn_inst.cc:
cpu/base_dyn_inst.hh:
    Changes to abstract more away from the base dyn inst class.
cpu/beta_cpu/2bit_local_pred.cc:
cpu/beta_cpu/2bit_local_pred.hh:
cpu/beta_cpu/tournament_pred.cc:
cpu/beta_cpu/tournament_pred.hh:
    Remove redundant SatCounter class.
cpu/beta_cpu/alpha_dyn_inst.cc:
cpu/beta_cpu/alpha_full_cpu.cc:
cpu/beta_cpu/alpha_full_cpu.hh:
cpu/beta_cpu/bpred_unit.cc:
cpu/beta_cpu/inst_queue.cc:
cpu/beta_cpu/mem_dep_unit.cc:
cpu/beta_cpu/ras.cc:
cpu/beta_cpu/rename_map.cc:
cpu/beta_cpu/rename_map.hh:
cpu/beta_cpu/rob.cc:
    Fix for gcc-3.4
cpu/beta_cpu/alpha_dyn_inst.hh:
cpu/beta_cpu/alpha_dyn_inst_impl.hh:
    Fixes for gcc-3.4.
    Include more variables and functions that are specific to AlphaDynInst which were once in BaseDynInst.
cpu/beta_cpu/alpha_full_cpu_builder.cc:
    Make params match the current params inherited from BaseCPU.
cpu/beta_cpu/alpha_full_cpu_impl.hh:
    Fixes for gcc-3.4
cpu/beta_cpu/full_cpu.cc:
    Use new params pointer in BaseCPU.
    Fix for gcc-3.4.
cpu/beta_cpu/full_cpu.hh:
    Use new params class from BaseCPU.
cpu/beta_cpu/iew_impl.hh:
    Remove unused function.
cpu/simple_cpu/simple_cpu.cc:
    Remove unused global variable.
cpu/static_inst.hh:
    Include OoODynInst for new lightweight OoO CPU

--HG--
extra : convert_revision : 34d9f2e64ca0313377391e0d059bf09c040286fa
2005-02-25 18:00:49 -05:00
Ron Dreslinski
45eb26e67c Merge zizzer:/z/m5/Bitkeeper/m5
into zizzer.eecs.umich.edu:/.automount/zazzer/z/rdreslin/m5bk/timing_L1

--HG--
extra : convert_revision : e7d839327b07393bfcda0b77758b0832eaf1c1c0
2005-02-25 15:12:05 -05:00
Steve Reinhardt
368882a847 Fix timing modeling of faults: functionally the very next instruction after
a faulting instruction is the fault handler, which appears as an independent
instruction to the timing model.  New code will stall fetch and not fetch the
fault handler as long as there's a faulting instruction in the pipeline (i.e.,
the faulting inst has to commit first).

Also fix Ali's bad-address assertion that doesn't apply to full system.

Added some more debugging support in the process.  Hopefully we'll move to the new
cpu model soon and we won't need it anymore.

arch/alpha/alpha_memory.cc:
    Reorganize lookup() so we can trace the result of the lookup as well.
arch/alpha/isa_traits.hh:
    Add NoopMachInst (so we can insert them in the pipeline on ifetch faults).
base/traceflags.py:
    Replace "Dispatch" flag with "Pipeline" (since I added similar
    DPRINTFs in other pipe stages).
cpu/exetrace.cc:
    Change default for printing mis-speculated instructions to true (since
    that's often what we want, and right now you can't change it from the
    command line...).

--HG--
extra : convert_revision : a29a98a373076d62bbbb1d6f40ba51ecae436dbc
2005-02-25 12:41:08 -05:00
Kevin Lim
e8a564b0fd Merge ktlim@zizzer.eecs.umich.edu:/bk/m5
into zamp.eecs.umich.edu:/z/ktlim2/m5

--HG--
extra : convert_revision : 8a558785c64b7c33e64523d3d887ea6e760c3d2b
2005-02-22 16:03:30 -05:00
Ron Dreslinski
9dd1ab1dba Merge zizzer:/z/m5/Bitkeeper/m5
into zizzer.eecs.umich.edu:/.automount/zazzer/z/rdreslin/m5bk/timing_L1

--HG--
extra : convert_revision : db688679bfd9c670ef44611de71640c3bf564fc0
2005-02-21 16:50:38 -05:00
Nathan Binkert
9b1e2db811 Clean up CPU stuff and make it use params structs
cpu/base_cpu.cc:
cpu/base_cpu.hh:
    Convert the CPU stuff to use a params struct
cpu/memtest/memtest.cc:
    The memory tester is really not a cpu, so don't derive from
    BaseCPU since it just makes things a pain in the butt.  Keep
    track of max loads in the memtest class now that the base class
    doesn't do it for us.
    Don't have any default parameters.
cpu/memtest/memtest.hh:
    The memory tester is really not a cpu, so don't derive from
    BaseCPU since it just makes things a pain in the butt.  Keep
    track of max loads in the memtest class now that the base class
    doesn't do it for us.
cpu/simple_cpu/simple_cpu.cc:
    Convert to use a params struct.
    remove default parameters
cpu/simple_cpu/simple_cpu.hh:
    convert to use a params struct
cpu/trace/opt_cpu.cc:
cpu/trace/opt_cpu.hh:
cpu/trace/trace_cpu.cc:
cpu/trace/trace_cpu.hh:
    this isn't really a cpu.  don't derive from BaseCPU
objects/MemTest.mpy:
    we only need one max_loads parameter
sim/main.cc:
    Don't check for the number of CPUs since we may be doing something
    else going on.  If we don't have anything to simulate, the
    simulator will exit anyway.

--HG--
extra : convert_revision : 2195a34a9ec90b5414324054ceb3bab643540dd5
2005-02-19 11:46:41 -05:00
Ron Dreslinski
f825d103da Merge zizzer:/z/m5/Bitkeeper/m5
into zizzer.eecs.umich.edu:/.automount/zazzer/z/rdreslin/m5bk/timing_L1

--HG--
extra : convert_revision : 8fb4bbf165b8c65a54db5fea18ec5aa95172a173
2005-02-18 13:10:37 -05:00
Nathan Binkert
dd4220ec10 rename the simple cpu's multiplier parameter. call it width.
it makes more sense and is less confusing.

cpu/simple_cpu/simple_cpu.cc:
cpu/simple_cpu/simple_cpu.hh:
    width is a better name than multiplier

--HG--
extra : convert_revision : ea2fa4faa160f5657aece41df469bbc9f7244b21
2005-02-17 14:02:03 -05:00
Ron Dreslinski
45ef238e3f Merge zizzer:/z/m5/Bitkeeper/m5
into zizzer.eecs.umich.edu:/.automount/zazzer/z/rdreslin/m5bk/timing_L1

--HG--
extra : convert_revision : 88afcacc41f5b0fae0ed1ac1821b7ca88c407e85
2005-02-17 12:14:04 -05:00
Kevin Lim
79e83cea97 Merge ktlim@zizzer.eecs.umich.edu:/bk/m5
into zamp.eecs.umich.edu:/z/ktlim2/m5

--HG--
extra : convert_revision : 11832134b169aa827a1d03c96ef89edddf4b3dab
2005-02-11 17:54:42 -05:00
Kevin Lim
c4d0ebd25c Fix up #defines to use full path; fix up code for g++ 3.4
SConscript:
    Remove efence option from automatically being used.

--HG--
extra : convert_revision : 466bb8077aa341db0b409720e2a73535b1fa6b69
2005-02-11 17:54:33 -05:00
Nathan Binkert
06a4686af9 Rework the command line paramters for python output and how
output files and the output directory are are handled.  Make
the output directory configuration via a command line parameter,
or an environment variable.

SConscript:
    Add new output file stuff
base/misc.cc:
dev/simconsole.cc:
    use new output file code
cpu/base_cpu.cc:
    use new output file code to generate output streams
dev/etherdump.cc:
    use the output file code to find the output directory
    use a real stream instead of a pointer
dev/etherdump.hh:
    use a real stream instead of a pointer
objects/Root.mpy:
    output_dir and config_output_file are not longer configured here.
sim/main.cc:
    - Completely rework the command line argument passing to deal with
    changes in python and output files.
    - Update help output to reflect changes.
    - Remove all direct support for .ini files.  They are strictly
    for intermediate representation.
    - Remove the --foo:bar=blah syntax for .ini files and add --foo.bar=blah
    syntax for python.  This will generate: foo.bar = 'blah' in the python
    script.
    - Add '-d' to set the output directory.
    - Use new output file code to access the output stream.
sim/serialize.cc:
    use the new code to find the output directory
sim/universe.cc:
    Get rid of makeOutputStream.  Use the new output file code.
    Remove output_dir and config_output_file as parameters.

--HG--
extra : convert_revision : df2f0e13d401c3a60cae1239aa1ec3511721544d
2005-02-11 09:47:41 -05:00
Ron Dreslinski
230a5a608d Merger
cpu/simple_cpu/simple_cpu.hh:
    Merge

--HG--
extra : convert_revision : 1b6003ac731051fefacb7d7a30c317553b4bf1bc
2005-02-09 12:56:24 -05:00
Ron Dreslinski
d9317dd348 Some more useful debugging info for kernel panic and die events
Increase the default number of CSHR's, we should really fix this or make it a parameter

Use a setBlocked call to tell the bus it should block

New technique for sampling and switchover:
1) Sampler switchover event happens
2) All cpus in the current phase of sampling associated with this sampler are signaled to switchover
3) Each cpu drains it's pipe of things being executed (stops fetching and waits for empty pipe)
4) Once the pipe is empty the cpu calls back to the sampler to signal it has finished, and moves into the switchedout state (continues not to fetch)
5) The sampler collects all the signals, once all cpus are drained it calls the new cpu's in the next phase to takeover from the correct cpu
6) The statistics are reset and the next switchover time is calculated from this point

cpu/base_cpu.cc:
cpu/base_cpu.hh:
cpu/simple_cpu/simple_cpu.cc:
cpu/simple_cpu/simple_cpu.hh:
    Reconfigure the way the sampling switchover works
cpu/pc_event.cc:
    More debugging information on kernel panic's
kern/linux/linux_system.cc:
    More debug info for Kernel Die events
kern/linux/linux_system.hh:
    More debug info for kernel die events

--HG--
extra : convert_revision : 61cc42e43ba738705aa1f1d167b65d4d6dee51ae
2005-02-09 10:27:00 -05:00
Kevin Lim
1e7a744c09 Hand merge
--HG--
extra : convert_revision : 86c7399b79c17558041a73056745227f70fe8b3b
2005-02-04 18:25:49 -05:00
Steve Reinhardt
0aaf8ec6b8 Add support for CPU models to execute the effective
address calculation and memory access portions separately.
Not currently used by any CPU models, but Kevin says he needs this.

Also clean up handling of execution tracing for memory accesses
(move it all into isa_desc and out of CPU models).

Got rid of some ancient unused code too.

arch/alpha/isa_desc:
    Add execute() methods to EAComp and MemAcc portions of memory
    access instructions, to allow CPU models to execute the effective
    address calculation and memory access portions separately.

    Requires the execution context to remember the effective address
    across the two invocations.  Added setEA() and getEA() methods to
    execution context to support this.  A model that does not use the
    split execution model can panic if these methods are called.

    Also added hook to call traceData->setAddr() after EA computation
    on any load or store operation.
arch/isa_parser.py:
    Call traceData->setData() on memory writes (stores).
cpu/simple_cpu/simple_cpu.cc:
    Get rid of unused code.
cpu/simple_cpu/simple_cpu.hh:
    Add (non-functional) setEA() and getEA() methods for new
    split memory access execution support.

--HG--
extra : convert_revision : bc2d2c758c4ca753812b9fa81f21038e55929ff0
2005-02-03 20:47:11 -05:00
Kevin Lim
f31a27a030 Move trace data function to .cc file.
--HG--
extra : convert_revision : 8180068747489978a2bbaa096dc73b0cfd14b052
2005-01-18 11:43:45 -05:00
Kevin Lim
f58d85128d Fixes so m5 compiles on gcc 3.4, which has much stricter syntax. Most changes come from templated code,
which is evaluated slightly differently than in previous versions of gcc.

arch/alpha/alpha_linux_process.cc:
    Alphabetize includes.
arch/alpha/vptr.hh:
    Change the constants that are being used for alpha pagebytes to come from the ISA.
base/random.hh:
cpu/static_inst.cc:
sim/param.cc:
    Fix up template syntax.
base/range.hh:
    Include iostream for << operator.
base/res_list.hh:
base/statistics.hh:
cpu/simple_cpu/simple_cpu.hh:
cpu/static_inst.hh:
sim/eventq.hh:
sim/param.hh:
    Fixup for templated code to resolve different scope lookup in gcc 3.4.  This defers the lookup of the
    function/variable until actual instantiation time by making it dependent on the templated class/function.
base/trace.cc:
    Fix call to new.
base/trace.hh:
    Fix up #define to have full path.
cpu/base_cpu.cc:
    Fix up call to new.
dev/etherlink.hh:
dev/ns_gige.hh:
dev/sinic.hh:
    Fixup for friend class/function declaration.  g++ 3.4 no longer allows typedefs to be declared as
    a friend class.
dev/pcidev.hh:
    Fix up re-definition of access level to params.
kern/linux/linux_syscalls.hh:
kern/tru64/tru64_syscalls.hh:
    Fix up header.  Fix up template syntax.
sim/serialize.cc:
    Include errno.h.
sim/startup.cc:
    Change startupq.  queue was getting destructed before all things had called ~StartupCallback(), which lead
    to a segfault.  This puts startupq in global space, and we allocate it ourselves.  Other code may be similar
    to this and may need changing in the future.
sim/syscall_emul.hh:
    Include cpu/exec_context.hh and sim/process.hh, as forward declarations are no longer sufficient.
sim/universe.cc:
    Include errno.h

--HG--
extra : convert_revision : e49d08ee89eb06a28351f02bafc028ca6652d5af
2005-01-14 18:34:56 -05:00
Kevin Lim
42f3b4ffb3 Merge changes.
base/traceflags.py:
    Merge extra new CPU flags
cpu/static_inst.hh:
    Include all the execute functions in static_inst_impl.hh

--HG--
extra : convert_revision : 78eb753bf709d37400e7c2418bb35d842d7c3f63
2005-01-11 19:00:16 -05:00
Kevin Lim
90d4436351 Slight fixes, add in commit trace flag.
base/traceflags.py:
    Add new commit rate trace flag.
build/SConstruct:
    Add extra option for efence.
cpu/beta_cpu/alpha_full_cpu_impl.hh:
    Use function calls instead of direct indexing (avoids confusion).
cpu/beta_cpu/commit_impl.hh:
    Add commit rate trace output (might not be worthwhile in the future).
cpu/beta_cpu/decode_impl.hh:
    Remove some older hacks.  Fix it so that the isntruction properly sets its next
    PC to the one calculated by the branch.
cpu/beta_cpu/fetch_impl.hh:
    Remove old commented code.
cpu/beta_cpu/iew_impl.hh:
    Add extra check to ensure that the instruction is valid.
cpu/beta_cpu/regfile.hh:
    Include trace file.

--HG--
extra : convert_revision : 4ee1dc88f8a5ed9b65486c6c111a3718a8040e42
2005-01-11 18:52:29 -05:00
Ron Dreslinski
d3d750151d Modified to work with do_events
No multiple requests to the same block outstanding from the same tester
Using false sharing, each tester only access a single byte within the block based on which tester it is
Allow more cycles before signalling deadlock, with do_events it may take some time with NACK/retry and many proccessors

--HG--
extra : convert_revision : 4c8eab99082c53840a5ad2a926457dfc27f23b77
2004-12-14 13:15:54 -05:00
Ron Dreslinski
bddb7ad7b5 Put back in SimpleCPU changes and Coherence Timing Bus changes
Small fixes to read() in simpleCPU and small fixes to cache_impl.hh
and to simple_mem_bank to deal with writeInv from DMA

--HG--
extra : convert_revision : db24028c34b7a535aa0db55b43bad1d3d75cd258
2004-11-18 06:11:01 -05:00
Nathan Binkert
25890b9404 back out ron's memory system changes because they break dma
--HG--
extra : convert_revision : 3e0af11cd9dc97743f288cee5248fa44013baddd
2004-11-18 02:34:53 -05:00
Nathan Binkert
44ef49bd2b undo simple CPU changes
--HG--
extra : convert_revision : dce0d9f7d34243899f699488c6534fb1ccea4849
2004-11-18 00:24:36 -05:00
Ron Dreslinski
60e88ba7ad Changes to use siinic:
Changed SimpleCPU to not due functional access until the cache returns
Updated config file to use a simple cpu for second cpu in dual mode.

cpu/simple_cpu/simple_cpu.cc:
cpu/simple_cpu/simple_cpu.hh:
    Update cache completion event to perform the functional read upon completion

--HG--
extra : convert_revision : 7a5b318d2040580fae92c165611425f513b14be9
2004-11-17 23:26:43 -05:00
Ron Dreslinski
f9ff53241f Merge zizzer:/z/m5/Bitkeeper/m5
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/clean

--HG--
extra : convert_revision : a64b84993c8852b19b1572c6913bf3dc6f6fc249
2004-11-17 09:54:38 -05:00
Steve Reinhardt
c9b0204e28 Add simple function-tracing support. Prints a message
every time the committed PC changes from one symbol scope
to another.
Set function_trace=y on target CPU to enable.
To defer start, use function_trace_start=<tick>
(in addition to setting function_trace=y).

cpu/base_cpu.cc:
cpu/base_cpu.hh:
    Add simple function-tracing support.
cpu/simple_cpu/simple_cpu.cc:
    Add function_trace, function_trace_start params
    Call traceFunctions() on instruction completion
cpu/simple_cpu/simple_cpu.hh:
    Add function_trace, function_trace_start params

--HG--
extra : convert_revision : 8a7f84028ccbaee585253629007f32fc8eae35e1
2004-11-16 17:20:38 -05:00
Steve Reinhardt
b1816cb837 Minor cleanup of symtab code/includes.
base/loader/symtab.cc:
base/loader/symtab.hh:
    Get rid of old unused calls.
cpu/simple_cpu/simple_cpu.hh:
    No need to include base/loader/symtab.hh
kern/linux/linux_system.cc:
kern/tru64/tru64_system.cc:
    Include base/loader/symtab.hh (since it's no longer included in system.hh)
sim/system.hh:
    Replace include of base/loader/symtab.hh with forward class decl.

--HG--
extra : convert_revision : 3a778c2f409ec94e3b00eaa9b3859943cb39918c
2004-11-15 20:30:51 -05:00
Steve Reinhardt
26c666b4f3 Minor fixes for pc sampling profile.
cpu/exetrace.cc:
    Fix dumb mistake.

--HG--
extra : convert_revision : 9d5d0d09775133d1a60cf459f1bd47afa8480663
2004-11-15 19:57:11 -05:00
Steve Reinhardt
fed64a3b36 Add support for sampled PC profiling to FullCPU.
Simple text list of symbol (or address) and count
will be dumped to m5prof.<cpu-name> if the cpu's
pc_sample_interval param is set.

SConscript:
    Add cpu/full_cpu/pc_sample_profile.cc
base/callback.hh:
    Add a comment about MakeCallback.
    Fix type in another comment.
base/loader/symtab.cc:
    Revamp findNearestSymbol() to provide addresses of both
    nearest symbols (preceding and following) as well as
    string for former.

    Move global definition of debugSymbolTable here too.
base/loader/symtab.hh:
    Revamp findNearestSymbol() to provide addresses of both
    nearest symbols (preceding and following) as well as
    string for former.

    Move global declaration of debugSymbolTable here too.
cpu/exetrace.cc:
    Use new findNearestSymbol() interface for trace symbols.
kern/linux/linux_system.cc:
sim/system.cc:
    Remove extern of debugSymbolTable (now in symtab.hh)
sim/process.cc:
    Initialize debugSymbolTable if binary has a symbol table.

--HG--
extra : convert_revision : 0b5393dc39c40ac88c953684708f1125da550671
2004-11-15 01:56:40 -05:00
Ron Dreslinski
f7d1166e04 Merge zizzer:/z/m5/Bitkeeper/m5
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/clean

--HG--
extra : convert_revision : 170f5fd8891b02ad3cc04112c6f304ede3254dae
2004-11-14 16:19:11 -05:00
Nathan Binkert
425dda00df Macros are nasty, so let's get rid of them. Convert all
all macros in ev5.hh to inline functions or constant typed
variables and make them follow our style while we're at it.

All of the stuff in this file actually belongs in the ISA
traits code, but this is a first step at getting things done
in the right manner.

arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
arch/alpha/ev5.cc:
arch/alpha/isa_desc:
dev/ns_gige.cc:
kern/tru64/tru64_events.cc:
    deal with changes in ev5.hh
arch/alpha/ev5.hh:
    Macros are nasty, so let's get rid of them.  Convert all
    all macros to inline functions or constant typed variables.
    Make them follow our style while we're at it.

    All of the stuff in this file actually belongs in the ISA
    traits code, but this is a first step at getting things done
    in the right manner.
arch/alpha/isa_traits.hh:
    move some of the ev5 specific code into the isa
arch/alpha/vtophys.cc:
base/remote_gdb.cc:
    deal with isa addition
cpu/exec_context.hh:
    be less isa specific and use the isa traits to figure out
    what we can.
dev/alpha_console.cc:
dev/pciconfigall.cc:
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
dev/uart.cc:
    deal with changes in ev5.hh
    I don't believe this masking is actually necessary.  We should
    look at removing it later.
dev/ide_ctrl.cc:
    sort #includes
    deal with changes in ev5.hh

--HG--
extra : convert_revision : c8a3adf0a4b1d198aefe38fc38b295abf289b08a
2004-11-13 14:01:38 -05:00
Ron Dreslinski
ad3e3217e3 Merge
--HG--
extra : convert_revision : d7a5cccd3472bc59b840a0e5285cd65dcc2484fe
2004-11-12 14:50:28 -05:00
Ron Dreslinski
501db90f2c Make changes so that coherence works on a timing bus for the top-level of caches.
This added a snoopResponse callback to the caches, and a NACK to requests.

cpu/memtest/memtest.cc:
    Modified to work with do_events:
    No multiple requests to the same block outstanding at the same time from the same tester
    Using false sharing, each tester does only 1 byte access using it's id as the blk offset
    Allow for cycles before signaling deadlock, with do events it can take time to complete (NACK/blocked bus)
cpu/memtest/memtest.hh:
    Updated to keep an id with each tester (used for address generation)
    Updated to keep a list of outstanding address to prevent multiple outstanding per tester
    //Should really look into doing store forwarding within the tester, then we can test more functionality

--HG--
extra : convert_revision : 05fbcf547e4ffab9d220aeb73126ed787ca82239
2004-11-12 14:40:07 -05:00
Nathan Binkert
4328480b56 Don't use the global check_interrupts variable. Add a per-cpu
checkInterrupts variable and use that to determine whether an interrupt
can occur on a given cycle.

arch/alpha/ev5.cc:
    XC -> CPU (and xc -> CPU) since we're really talking about a CPU here
    Don't use the global check_interrupts variable.  Add a per-cpu
    checkInterrupts variable and use that to determine whether an interrupt
    can occur on a given cycle.

--HG--
extra : convert_revision : be4c0247e5834005c60a45796a222cffd327b64e
2004-11-10 18:37:19 -05:00
Nathan Binkert
e2de2ea192 Fix to deal with the new base class parameter for registration
deferral

--HG--
extra : convert_revision : f968e3ba44604522cb10db8a60d7e18f1733e06a
2004-11-03 23:21:10 -05:00
Nathan Binkert
8056b9a48a Forgot about the tracing cpus for the changes to the base class
cpu/trace/opt_cpu.cc:
cpu/trace/trace_cpu.cc:
    we don't want to register this cpu since it's not a real cpu

--HG--
extra : convert_revision : 3b87b6ac3dd061018909bf4fdb4e2d611128d07b
2004-11-03 22:30:13 -05:00
Nathan Binkert
d82e0d11d1 make activation of exec contexts happen in startup
the registration stuff all moves into BaseCPU

cpu/base_cpu.cc:
    Move the registration stuff into the BaseCPU since all
    other CPUs use it.
cpu/base_cpu.hh:
    Move the defer registration stuff into the BaseCPU since all
    other CPUs use it.
cpu/simple_cpu/simple_cpu.cc:
cpu/simple_cpu/simple_cpu.hh:
    registration stuff moved to base class
sim/system.cc:
    the activation of exec contexts should happen at startup, not
    when they are registered.
sim/system.hh:
    the system now has a startup function

--HG--
extra : convert_revision : bb6a7c2da5a1ecf5fe7ede1078200bfe5245f8ef
2004-11-03 20:46:33 -05:00
Taeho Kgil
129b885abd Add Inorder CPU model
SConscript:
arch/isa_parser.py:
cpu/static_inst.hh:
    Add inorderCPU

--HG--
extra : convert_revision : 141372808fac5f6d125f9051ee0be982d21683aa
2004-11-03 17:56:26 -05:00
Nathan Binkert
d55eb90fc7 Don't use magic numbers.
arch/alpha/isa_traits.hh:
    Move defines to non full system code section so they can
    be used elsewhere
cpu/simple_cpu/simple_cpu.cc:
    Don't use magic numbers
cpu/simple_cpu/simple_cpu.hh:
    simple format nit

--HG--
extra : convert_revision : b8d492218340d41ab9420c6ad1e81a197db1c132
2004-10-25 16:23:22 -04:00
Kevin Lim
2fb632dbda Check in of various updates to the CPU. Mainly adds in stats, improves
branch prediction, and makes memory dependence work properly.

SConscript:
    Added return address stack, tournament predictor.
cpu/base_cpu.cc:
    Added debug break and print statements.
cpu/base_dyn_inst.cc:
cpu/base_dyn_inst.hh:
    Comment out possibly unneeded variables.
cpu/beta_cpu/2bit_local_pred.cc:
    2bit predictor no longer speculatively updates itself.
cpu/beta_cpu/alpha_dyn_inst.hh:
    Comment formatting.
cpu/beta_cpu/alpha_full_cpu.hh:
    Formatting
cpu/beta_cpu/alpha_full_cpu_builder.cc:
    Added new parameters for branch predictors, and IQ parameters.
cpu/beta_cpu/alpha_full_cpu_impl.hh:
    Register stats.
cpu/beta_cpu/alpha_params.hh:
    Added parameters for IQ, branch predictors, and store sets.
cpu/beta_cpu/bpred_unit.cc:
    Removed one class.
cpu/beta_cpu/bpred_unit.hh:
    Add in RAS, stats.  Changed branch predictor unit functionality
    so that it holds a history of past branches so it can update, and also
    hold a proper history of the RAS so it can be restored on branch
    mispredicts.
cpu/beta_cpu/bpred_unit_impl.hh:
    Added in stats, history of branches, RAS.  Now bpred unit actually
    modifies the instruction's predicted next PC.
cpu/beta_cpu/btb.cc:
    Add in sanity checks.
cpu/beta_cpu/comm.hh:
    Add in communication where needed, remove it where it's not.
cpu/beta_cpu/commit.hh:
cpu/beta_cpu/rename.hh:
cpu/beta_cpu/rename_impl.hh:
    Add in stats.
cpu/beta_cpu/commit_impl.hh:
    Stats, update what is sent back on branch mispredict.
cpu/beta_cpu/cpu_policy.hh:
    Change the bpred unit being used.
cpu/beta_cpu/decode.hh:
cpu/beta_cpu/decode_impl.hh:
    Stats.
cpu/beta_cpu/fetch.hh:
    Stats, change squash so it can handle squashes from decode differently
    than squashes from commit.
cpu/beta_cpu/fetch_impl.hh:
    Add in stats.  Change how a cache line is fetched.  Update to work with
    caches.  Also have separate functions for different behavior if squash
    is coming from decode vs commit.
cpu/beta_cpu/free_list.hh:
    Remove some old comments.
cpu/beta_cpu/full_cpu.cc:
cpu/beta_cpu/full_cpu.hh:
    Added function to remove instructions from back of instruction list
    until a certain sequence number.
cpu/beta_cpu/iew.hh:
    Stats, separate squashing behavior due to branches vs memory.
cpu/beta_cpu/iew_impl.hh:
    Stats, separate squashing behavior for branches vs memory.
cpu/beta_cpu/inst_queue.cc:
    Debug stuff
cpu/beta_cpu/inst_queue.hh:
    Stats, change how mem dep unit works, debug stuff
cpu/beta_cpu/inst_queue_impl.hh:
    Stats, change how mem dep unit works, debug stuff.  Also add in
    parameters that used to be hardcoded.
cpu/beta_cpu/mem_dep_unit.hh:
cpu/beta_cpu/mem_dep_unit_impl.hh:
    Add in stats, change how memory dependence unit works.  It now holds
    the memory instructions that are waiting for their memory dependences
    to resolve.  It provides which instructions are ready directly to the
    IQ.
cpu/beta_cpu/regfile.hh:
    Fix up sanity checks.
cpu/beta_cpu/rename_map.cc:
    Fix loop variable type.
cpu/beta_cpu/rob_impl.hh:
    Remove intermediate DynInstPtr
cpu/beta_cpu/store_set.cc:
    Add in debugging statements.
cpu/beta_cpu/store_set.hh:
    Reorder function arguments to match the rest of the calls.

--HG--
extra : convert_revision : aabf9b1fecd1d743265dfc3b174d6159937c6f44
2004-10-21 18:02:36 -04:00
Erik Hallnor
867a9b84d9 Bunch of little changes for tracking copies and getting OPT right.
cpu/simple_cpu/simple_cpu.cc:
    Send Copy
cpu/trace/opt_cpu.cc:
    Calculate the block size correctly. Set lookupTable value directly, since the old way only worked for FA caches.
cpu/trace/trace_cpu.cc:
    Don't start events if the hierarchy is in non-event mode.

--HG--
extra : convert_revision : daf2db5ed7428c2fb08652cf76f6fe99d8357db5
2004-10-17 00:07:21 -04:00
Erik Hallnor
72276af49f Make printouts look more like stats.
cpu/trace/opt_cpu.cc:
    Change printout to look more like real stats, should really just make these stats someday.

--HG--
extra : convert_revision : cd5db4657a53abeda0417ca6ba4407d366408358
2004-10-01 16:31:13 -04:00
Erik Hallnor
f2ac7b645f Updates to make traces work correctly in all circumstances. Add opt set associative simulation.
cpu/trace/opt_cpu.cc:
cpu/trace/opt_cpu.hh:
    Add the ability to simulate less than fully-associative opt caches.
cpu/trace/reader/itx_reader.cc:
    Add writeback to the command list.

--HG--
extra : convert_revision : a9c9c4be3358f4083d7e85772620441a3ad809db
2004-09-30 01:46:48 -04:00
Erik Hallnor
34742515f5 Add opt cpu and fix page copy warnings
SConscript:
    Add opt_cpu
cpu/simple_cpu/simple_cpu.cc:
    Fix page spanning copy warning.
cpu/trace/reader/itx_reader.cc:
    Fix reader to return correct address.

--HG--
extra : convert_revision : f03e244971af4197743c7c717d64f21db0ae42d3
2004-09-28 16:55:55 -04:00
Kevin Lim
e3fb9afa79 Update to make multiple instruction issue and different latencies work.
Also change to ref counted DynInst.

SConscript:
    Add branch predictor, BTB, load store queue, and storesets.
arch/isa_parser.py:
    Specify the template parameter for AlphaDynInst
base/traceflags.py:
    Add load store queue, store set, and mem dependence unit to the
    list of trace flags.
cpu/base_dyn_inst.cc:
    Change formating, add in debug statement.
cpu/base_dyn_inst.hh:
    Change DynInst to be RefCounted, add flag to clear whether or not this
    instruction can commit.  This is likely to be removed in the future.
cpu/beta_cpu/alpha_dyn_inst.cc:
    AlphaDynInst has been changed to be templated, so now this CC file
    is just used to force instantiations of AlphaDynInst.
cpu/beta_cpu/alpha_dyn_inst.hh:
    Changed AlphaDynInst to be templated on Impl.  Removed some unnecessary
    functions.
cpu/beta_cpu/alpha_full_cpu.cc:
    AlphaFullCPU has been changed to be templated, so this CC file is now
    just used to force instantation of AlphaFullCPU.
cpu/beta_cpu/alpha_full_cpu.hh:
    Change AlphaFullCPU to be templated on Impl.
cpu/beta_cpu/alpha_impl.hh:
    Update it to reflect AlphaDynInst and AlphaFullCPU being templated
    on Impl.  Also removed time buffers from here, as they are really
    a part of the CPU and are thus in the CPU policy now.
cpu/beta_cpu/alpha_params.hh:
    Make AlphaSimpleParams inherit from the BaseFullCPU so that it doesn't
    need to specifically declare any parameters that are already in the
    BaseFullCPU.
cpu/beta_cpu/comm.hh:
    Changed the structure of the time buffer communication structs.  Now
    they include the size of the packet of instructions it is sending.
    Added some parameters to the backwards communication struct, mainly
    for squashing.
cpu/beta_cpu/commit.hh:
    Update typenames to reflect change in location of time buffer structs.
    Update DynInst to DynInstPtr (it is refcounted now).
cpu/beta_cpu/commit_impl.hh:
    Formatting changes mainly.  Also sends back proper information
    on branch mispredicts so that the bpred unit can update itself.
    Updated behavior for non-speculative instructions (stores, any
    other non-spec instructions): once they reach the head of the ROB,
    the ROB signals back to the IQ that it can go ahead and issue the
    non-speculative instruction.  The instruction itself is updated so that
    commit won't try to commit it again until it is done executing.
cpu/beta_cpu/cpu_policy.hh:
    Added branch prediction unit, mem dependence prediction unit, load
    store queue.  Moved time buffer structs from AlphaSimpleImpl to here.
cpu/beta_cpu/decode.hh:
    Changed typedefs to reflect change in location of time buffer structs
    and also the change from DynInst to ref counted DynInstPtr.
cpu/beta_cpu/decode_impl.hh:
    Continues to buffer instructions even while unblocking now.  Changed
    how it loops through groups of instructions so it can properly block
    during the middle of a group of instructions.
cpu/beta_cpu/fetch.hh:
    Changed typedefs to reflect change in location of time buffer structs
    and the change to ref counted DynInsts.  Also added in branch
    brediction unit.
cpu/beta_cpu/fetch_impl.hh:
    Add in branch prediction.  Changed how fetch checks inputs and its
    current state to make for easier logic.
cpu/beta_cpu/free_list.cc:
    Changed int regs and float regs to logically use one flat namespace.
    Future change will be moving them to a single scoreboard to conserve
    space.
cpu/beta_cpu/free_list.hh:
    Mostly debugging statements.  Might be removed for performance in future.
cpu/beta_cpu/full_cpu.cc:
    Added in some debugging statements.  Updated BaseFullCPU to take
    a params object.
cpu/beta_cpu/full_cpu.hh:
    Added params class within BaseCPU that other param classes will be
    able to inherit from.  Updated typedefs to reflect change in location
    of time buffer structs and ref counted DynInst.
cpu/beta_cpu/iew.hh:
    Updated typedefs to reflect change in location of time buffer structs
    and use of ref counted DynInsts.
cpu/beta_cpu/iew_impl.hh:
    Added in load store queue, updated iew to be able to execute non-
    speculative instructions, instead of having them execute in commit.
cpu/beta_cpu/inst_queue.hh:
    Updated change to ref counted DynInsts.  Changed inst queue to hold
    non-speculative instructions as well, which are issued only when
    commit signals backwards that a nonspeculative instruction is at
    the head of the ROB.
cpu/beta_cpu/inst_queue_impl.hh:
    Updated to allow for non-speculative instructions to be in the inst
    queue.  Also added some debug functions.
cpu/beta_cpu/regfile.hh:
    Added debugging statements, changed formatting.
cpu/beta_cpu/rename.hh:
    Updated typedefs, added some functions to clean up code.
cpu/beta_cpu/rename_impl.hh:
    Moved some code into functions to make it easier to read.
cpu/beta_cpu/rename_map.cc:
    Changed int and float reg behavior to use a single flat namespace.  In
    the future, the rename maps can be combined to a single rename map to
    save space.
cpu/beta_cpu/rename_map.hh:
    Added destructor.
cpu/beta_cpu/rob.hh:
    Updated it with change from DynInst to ref counted DynInst.
cpu/beta_cpu/rob_impl.hh:
    Formatting, updated to use ref counted DynInst.
cpu/static_inst.hh:
    Updated forward declaration for AlphaDynInst now that it is templated.

--HG--
extra : convert_revision : 1045f240ee9b6a4bd368e1806aca029ebbdc6dd3
2004-09-23 14:06:03 -04:00
Ali Saidi
ac422ac949 Merge zizzer:/bk/m5 into zeep.eecs.umich.edu:/z/saidi/work/m5-smp
--HG--
extra : convert_revision : 19dc01e1c0d2c0ba6b4d804b902429fb0a6a5552
2004-09-22 18:39:37 -04:00
Erik Hallnor
15d08a3422 Update copies to work around alignment faults.
arch/alpha/isa_desc:
    whitespace fix.
cpu/simple_cpu/simple_cpu.cc:
    Add support to make sure we don't get alignment faults in copies. Warn if we go over an 8k page boundary.

--HG--
extra : convert_revision : 98b38da86a66215d80ea9eb6e6f1f68ee573cb57
2004-09-20 22:00:35 -04:00
Ali Saidi
9adb64ec70 pc event now clears lower 2 bits
always build with dynamic libraries for mysqlclient

SConscript:
    always use dynamic library now
cpu/pc_event.hh:
    cleared lower 2 bits, since everything must be 4byte aligned

--HG--
extra : convert_revision : 332ecd25a598e6a46a79bd653449aa7eb22a580a
2004-09-16 15:11:38 -04:00
Ali Saidi
a71541a3e8 switch contexts on palcode rather than kernel code
cpu/pc_event.cc:
    mask off lower three bits so we can have an event in palcode

--HG--
extra : convert_revision : 49fcdc5c359ca2bd9149f092f80f77abcd7b20ee
2004-09-16 00:37:21 -04:00
Ali Saidi
af620e1187 added system option to bin interrupt code seperately.
arch/alpha/ev5.cc:
    set the mode explictly rather than having a bool user/notuser
cpu/simple_cpu/simple_cpu.hh:
    there is no class Kernel
kern/kernel_stats.cc:
    use cpu_mode_num
kern/kernel_stats.hh:
    add interrupt mode and use cpu_mode_num rather than constant
kern/linux/linux_system.cc:
kern/linux/linux_system.hh:
kern/system_events.cc:
kern/system_events.hh:
    add events to change the mode to/from interrupt
sim/system.cc:
sim/system.hh:
    add a pal symbol table

--HG--
extra : convert_revision : 9d30e826b72122062a5ea12d094f94760e75c66a
2004-09-03 14:12:59 -04:00
Erik Hallnor
1401a06691 Update tracing functionality and add an ITX trace writer.
SConscript:
    Add build support for ITX trace writer
cpu/trace/reader/itx_reader.cc:
    Handle full 36 bit physical addressses.
cpu/trace/reader/itx_reader.hh:
    Need a string header file here
cpu/trace/trace_cpu.cc:
cpu/trace/trace_cpu.hh:
    Modify trace CPU to take a single trace and drive an instruction and data interfaces.

--HG--
extra : convert_revision : 4c81f2f9d9341df41f0ae45e4bda49800a43977c
2004-09-02 11:27:38 -04:00
Kevin Lim
04745696b6 Check in of new CPU. This checkin works under non-Fullsystem mode, with no caches.
SConscript:
    Added new CPU files to build.
arch/alpha/isa_desc:
    Changed rduniq and wruniq to be nonspeculative because the uniq register is not renamed.
arch/isa_parser.py:
    Added new CPU exec method.
base/statistics.hh:
    Minor change for namespace conflict.  Probably can change back one the new CPU files are cleaned up.
base/traceflags.py:
    Added new CPU trace flags.
cpu/static_inst.hh:
    Changed static inst to use a file that defines the execute functions.

--HG--
extra : convert_revision : bd4ce34361308280168324817fc1258dd253e519
2004-08-20 14:54:07 -04:00
Nathan Binkert
9023f5c96d - Clean up and factor out all of the binning code into a
single place so it's easier to work with.
-  Add support for binning kernel/user/idle time separately from
lisa's binning stuff, but make the two compatible.
-  KernelStats used to directly implement the pImpl idiom, but
it makes more sense to just remove the level of indirection and
make the exec context have a pointer to the stats.
-  Factor common code out of LinuxSystem and Tru64System and put
it into the System base class.  While doing that, make all
constructors take a pointer to a parameter struct instead of
naming the parameters individually to make it much easier to add
parameters to these classes.

SConscript:
    Move the function tracking and binning stuff around.
arch/alpha/ev5.cc:
    kernelStats is now a pointer
arch/alpha/pseudo_inst.cc:
    kernelStats is now a pointer
    the parameters to the system have been moved into their own
    struct
base/trace.hh:
    provide a little functor class for wrapping a string that
    can allow you to define name() in any scope very simply
    for use with DPRINTF
cpu/base_cpu.cc:
    New order of arguments for consistency.
cpu/exec_context.cc:
    kernelStats no longer has the level of indirection in it,
    execContext has the indirection now.  so, kernelStats is a pointer.
    We also need a pointer to the kernelBinning stuff from the system
    and we need to figure out if we want to do binning or not.
    Move a whole bunch of code into kern_binning.cc so it's all
    in the same place.
cpu/exec_context.hh:
    We want pointers to the kernel binning/stats stuff and we'll
    have the exec_context and system have the level of indirection
    instead of having the extra layer in the kernel stats class.
cpu/simple_cpu/simple_cpu.cc:
    call through the exec context to do the special binning
    stuff.
kern/kernel_stats.cc:
kern/kernel_stats.hh:
    Re-organize the stats stuff and remove the level of indirection
    (that was there to simplify building) and move the binning stuff
    into its own class/file.
kern/linux/linux_system.cc:
kern/linux/linux_system.hh:
kern/tru64/tru64_system.cc:
kern/tru64/tru64_system.hh:
sim/system.cc:
sim/system.hh:
    move lots of common system code into the base system class so
    that it can be shared between linux, tru64, and whatever else
    we decide to support in the future.

    Make the constructor take a pointer to a parameter struct so that
    it is easier to pass parameters to the parent.
kern/system_events.cc:
    move the majority of the binning code into the Kernel::Binning class
    in the kern_binning file
kern/system_events.hh:
    FnEvents only need to know the bin
    create the Idle start event to find the PCBB of the idle
    process when it starts.
kern/tru64/tru64_events.cc:
    memCtrl -> memctrl
sim/process.cc:
sim/process.hh:
    re-order args for consistency

--HG--
extra : convert_revision : 86cb39738c41fcd680f2aad125c9dde000227b2b
2004-08-20 11:35:31 -04:00
Ali Saidi
df61a1d3ef updated readme to reflect linux/scons changes
Put correct date in copyright headers based on bk changesets

LICENSE:
    Updated copyright on license file
README:
    Updaded readme to reflect shift to scons and linux support
cpu/trace/reader/ibm_reader.cc:
cpu/trace/reader/ibm_reader.hh:
cpu/trace/reader/itx_reader.cc:
cpu/trace/reader/itx_reader.hh:
cpu/trace/reader/m5_reader.cc:
cpu/trace/reader/m5_reader.hh:
cpu/trace/reader/mem_trace_reader.cc:
cpu/trace/reader/mem_trace_reader.hh:
cpu/trace/trace_cpu.cc:
cpu/trace/trace_cpu.hh:
    updated copyright (only changeset in 2004)
kern/kernel_stats.cc:
kern/kernel_stats.hh:
    updated copyright

--HG--
extra : convert_revision : 726aed4b38ff4d230c63a570df83c63075b3c76f
2004-07-28 17:56:36 -04:00
Nathan Binkert
bc5c52335c Add a clock multiplier for simple CPU so that it is possible
to do multiple instructions per cycle.

--HG--
extra : convert_revision : 5588ae38071f170792aad93899fef6842b7d818d
2004-07-14 23:01:54 -04:00
Erik Hallnor
4869ba881e Remove duplicate stat
cpu/trace/reader/m5_reader.cc:
    Wrap assert variable in NDEBUG

--HG--
extra : convert_revision : 8c79dc30eff2f2fa0110a04c30df17ec4417c28c
2004-07-06 11:29:23 -04:00
Andrew Schultz
bdc7803694 Merge zizzer:/bk/m5 into zizzer.eecs.umich.edu:/z/alschult/m5
--HG--
extra : convert_revision : 0bd6506e79600775dd0f72996120321f249b3411
2004-06-30 09:47:32 -04:00
Andrew Schultz
bdf9044d9d Change assert to check on virtual addresses because the physical
address can be zero for a copy

--HG--
extra : convert_revision : c6089969396aee2d67fa695a31cb7c5aea794338
2004-06-30 09:47:23 -04:00
Nathan Binkert
838273a196 fix up the recordEvent stuff to support ignoring events
arch/alpha/ev5.cc:
cpu/simple_cpu/simple_cpu.cc:
    update for new event interface
base/stats/events.cc:
    implement the ignore event function which matches sim objects from which
    to ignore events.

    Make insert event like insert data and make it able to insert many
    events in a single transaction with the database.
base/stats/events.hh:
    Make it possible to ignore events
sim/sim_object.cc:
    make recordEvent a member function of SimObject to implement
    the ignore function easily
sim/sim_object.hh:
    implement the ignore event stuff in the sim object.  This is a
    bit of a hack, but an easy place to put it.

--HG--
extra : convert_revision : ba3f25a14ad03662c53fb35514860d69be8cd4f0
2004-06-28 16:49:35 -04:00
Ali Saidi
17bfb1540e Merge zizzer:/bk/linux into zeep.eecs.umich.edu:/z/saidi/work/m5-endian
--HG--
extra : convert_revision : d4938c6011173d3017f47fd592c4b5e4c8d543a3
2004-06-23 17:55:54 -04:00
Ali Saidi
4deb819894 pull from head before pushing linux tree
--HG--
extra : convert_revision : 345f91c5c16c69db22035dc716e82fd77041380f
2004-06-22 13:48:49 -04:00
Ali Saidi
3f7b780af5 Merge saidi@zizzer.eecs.umich.edu:/bk/linux
into ali-saidis-computer.local:/research/linux

--HG--
extra : convert_revision : 446dc5fad11a6b29954dc5b1e974430853aa2969
2004-06-21 01:04:48 -04:00
Ali Saidi
c27139c701 start towards getting m5 endian compliant
base/inifile.cc:
    Added mac os support and fixed a bug, on error we need to exit the
    child process not return
base/intmath.hh:
    gcc on macos wanted a seperate function for the size_t type
base/loader/elf_object.cc:
    I'm not sure why this works under linux because it seems to return
    the wrong value.
base/stats/text.cc:
    added define/include for mac os x
cpu/exec_context.hh:
cpu/simple_cpu/simple_cpu.cc:
    added endian conversion code
dev/alpha_console.cc:
    rather than accessing a charecter array of varying size depending on
    the access, lets actually do this properly.
dev/alpha_console.hh:
    get rid of now nolonger used consoleData
dev/disk_image.cc:
    We have to byte swap the data is some cases, added function to do that
dev/ethertap.cc:
    added preproc directive for mac os

--HG--
extra : convert_revision : 2b5685765cfa2844926d7397f363d2788e3d640a
2004-06-21 00:58:30 -04:00
Ali Saidi
074969f8f1 Serialized cpu interrupts
cpu/simple_cpu/simple_cpu.cc:
    called basecpu serialization

--HG--
extra : convert_revision : 1a639b5e3c08e47a5d581c18b2b53fe87bd05b73
2004-06-17 15:36:59 -04:00
Steve Reinhardt
ed534a6c0b Merge isabel.reinhardt.house:/z/stever/bk/m5-head
into isabel.reinhardt.house:/z/stever/bk/m5

--HG--
extra : convert_revision : 1af377ff2dbe27f357410ab91a50b06c61f12e83
2004-06-15 10:48:31 -07:00
Steve Reinhardt
d53c6c168a Get software prefetching to work in full-system mode.
Mostly a matter of keeping prefetches to invalid addrs
from messing up VM IPRs.  Also discovered that wh64s were
not being treated as prefetches, when they really should be
(for the most part, anyway).

arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
    - Get rid of intrlock flag for locking VM fault regs (a la EV5);
    instead, just don't update regs on VPTE loads (a la EV6).
    - Add NO_FAULT MemReq flag to indicate references that should not
    cause page faults (i.e., prefetches).
arch/alpha/ev5.cc:
    - Get rid of intrlock flag for locking VM fault regs (a la EV5);
    instead, just don't update regs on VPTE loads (a la EV6).
    - Add Fault trace flag.
arch/alpha/isa_desc:
    - Add NO_FAULT MemReq flag to indicate references that should not
    cause page faults (i.e., prefetches).
    - Mark wh64 as a "data prefetch" instruction so it gets controlled
    properly by the FullCPU data prefetch control switch.
    - Align wh64 EA in decoder so issue stage doesn't need to worry about it.
arch/alpha/isa_traits.hh:
    - Get rid of intrlock flag for locking VM fault regs (a la EV5);
    instead, just don't update regs on VPTE loads (a la EV6).
base/traceflags.py:
    - Add Fault trace flag.
cpu/simple_cpu/simple_cpu.hh:
    - Pass MemReq flags to writeHint() operation.
cpu/static_inst.hh:
    Update comment re: prefetches.

--HG--
extra : convert_revision : 62e466b0f4c0ff9961796270fa2e371ec24bcbb6
2004-06-15 10:48:08 -07:00
Erik Hallnor
9a2202629e Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
into zizzer.eecs.umich.edu:/z/ehallnor/work/m5

--HG--
extra : convert_revision : 88c83150b7fd9260e0441334f2503b1e029d8c09
2004-06-13 05:52:59 -04:00
Erik Hallnor
018e92e45e Add some rewritten trace readers.
--HG--
extra : convert_revision : 4a085c5d8526d1bf3f7155cda40002281c0c3d1b
2004-06-13 05:52:28 -04:00
Lisa Hsu
a20f44979a lift common code *kernel_stats.* into the kern directory.
cpu/exec_context.hh:
    lift kernel_stats out in the linux tree.

--HG--
extra : convert_revision : 866c7f82d8b995b4dce295de1ab0980527d13f01
2004-06-10 01:14:35 -04:00
Lisa Hsu
22fe77f228 lif kernelt stats out of tru64 directory
cpu/exec_context.hh:
    change this to reflect the lifted kernel stats file.

--HG--
extra : convert_revision : 0dda3babdf51ee7a57430af69c7e20322b4eb622
2004-06-10 01:02:33 -04:00
Erik Hallnor
e7c7c92184 Tracing now works for upto 4 threads. Easy change to get it to work for more, but I don't have any test handy to test it.
cpu/trace/reader/m5_reader.cc:
    Add thread num.
cpu/trace/trace_cpu.cc:
    Increase thread count to 4, might want to make this a parameter (but it only really costs us storage).

--HG--
extra : convert_revision : 97cd7843668a3ef85aad06e3180dc04d2ca30ac1
2004-06-08 19:52:49 -04:00
Erik Hallnor
5f4297e865 Add the capability to read and write memory trace files. Currently is cycle accurate for a single thread FullCPU.
--HG--
extra : convert_revision : f8fe545313eb307cc6f5ff2c23894cc9870b1d5b
2004-06-08 17:31:04 -04:00
Ali Saidi
2f316082e4 Updated Copyright with information in bitkeeper changelogs
arch/alpha/alpha_linux_process.cc:
arch/alpha/alpha_linux_process.hh:
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
arch/alpha/alpha_tru64_process.cc:
arch/alpha/alpha_tru64_process.hh:
arch/alpha/aout_machdep.h:
arch/alpha/arguments.cc:
arch/alpha/arguments.hh:
arch/alpha/faults.cc:
arch/alpha/faults.hh:
arch/alpha/isa_traits.hh:
arch/alpha/osfpal.cc:
arch/alpha/osfpal.hh:
arch/alpha/pseudo_inst.cc:
arch/alpha/pseudo_inst.hh:
arch/alpha/vptr.hh:
arch/alpha/vtophys.cc:
arch/alpha/vtophys.hh:
base/bitfield.hh:
base/callback.hh:
base/circlebuf.cc:
base/circlebuf.hh:
base/compression/lzss_compression.cc:
base/compression/lzss_compression.hh:
base/compression/null_compression.hh:
base/cprintf.cc:
base/cprintf.hh:
base/cprintf_formats.hh:
base/date.cc:
base/dbl_list.hh:
base/endian.hh:
base/fast_alloc.cc:
base/fast_alloc.hh:
base/fifo_buffer.cc:
base/fifo_buffer.hh:
base/hashmap.hh:
base/hostinfo.cc:
base/hostinfo.hh:
base/hybrid_pred.cc:
base/hybrid_pred.hh:
base/inet.cc:
base/inet.hh:
base/inifile.cc:
base/inifile.hh:
base/intmath.cc:
base/intmath.hh:
base/loader/aout_object.cc:
base/loader/aout_object.hh:
base/loader/ecoff_object.cc:
base/loader/ecoff_object.hh:
base/loader/elf_object.cc:
base/loader/elf_object.hh:
base/loader/object_file.cc:
base/loader/object_file.hh:
base/loader/symtab.cc:
base/loader/symtab.hh:
base/misc.cc:
base/misc.hh:
base/mod_num.hh:
base/mysql.cc:
base/mysql.hh:
base/pollevent.cc:
base/pollevent.hh:
base/predictor.hh:
base/random.cc:
base/random.hh:
base/range.cc:
base/range.hh:
base/refcnt.hh:
base/remote_gdb.cc:
base/remote_gdb.hh:
base/res_list.hh:
base/sat_counter.cc:
base/sat_counter.hh:
base/sched_list.hh:
base/socket.cc:
base/socket.hh:
base/statistics.cc:
base/statistics.hh:
base/stats/events.cc:
base/stats/events.hh:
base/stats/flags.hh:
base/stats/mysql.cc:
base/stats/mysql.hh:
base/stats/mysql_run.hh:
base/stats/output.hh:
base/stats/statdb.cc:
base/stats/statdb.hh:
base/stats/text.cc:
base/stats/text.hh:
base/stats/types.hh:
base/stats/visit.cc:
base/stats/visit.hh:
base/str.cc:
base/str.hh:
base/time.cc:
base/time.hh:
base/trace.cc:
base/trace.hh:
base/userinfo.cc:
base/userinfo.hh:
cpu/base_cpu.cc:
cpu/base_cpu.hh:
cpu/exec_context.cc:
cpu/exec_context.hh:
cpu/exetrace.cc:
cpu/exetrace.hh:
cpu/full_cpu/op_class.hh:
cpu/full_cpu/smt.hh:
cpu/inst_seq.hh:
cpu/intr_control.cc:
cpu/intr_control.hh:
cpu/memtest/memtest.cc:
cpu/memtest/memtest.hh:
cpu/pc_event.cc:
cpu/pc_event.hh:
cpu/simple_cpu/simple_cpu.cc:
cpu/simple_cpu/simple_cpu.hh:
cpu/static_inst.cc:
cpu/static_inst.hh:
dev/alpha_console.cc:
dev/alpha_console.hh:
dev/baddev.cc:
dev/baddev.hh:
dev/disk_image.cc:
dev/disk_image.hh:
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherdump.cc:
dev/etherdump.hh:
dev/etherint.cc:
dev/etherint.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/etherpkt.cc:
dev/etherpkt.hh:
dev/ethertap.cc:
dev/ethertap.hh:
dev/ide_ctrl.cc:
dev/ide_ctrl.hh:
dev/ide_disk.cc:
dev/ide_disk.hh:
dev/io_device.cc:
dev/io_device.hh:
dev/ns_gige.cc:
dev/ns_gige.hh:
dev/ns_gige_reg.h:
dev/pciconfigall.cc:
dev/pciconfigall.hh:
dev/pcidev.cc:
dev/pcidev.hh:
dev/pcireg.h:
dev/platform.cc:
dev/platform.hh:
dev/simple_disk.cc:
dev/simple_disk.hh:
dev/tsunami.cc:
dev/tsunami.hh:
dev/tsunami_cchip.cc:
dev/tsunami_cchip.hh:
dev/tsunami_io.cc:
dev/tsunami_io.hh:
dev/tsunami_pchip.cc:
dev/tsunami_pchip.hh:
dev/tsunami_uart.hh:
dev/tsunamireg.h:
docs/stl.hh:
kern/linux/linux.hh:
kern/linux/linux_syscalls.cc:
kern/linux/linux_syscalls.hh:
kern/linux/linux_system.cc:
kern/linux/linux_system.hh:
kern/system_events.cc:
kern/system_events.hh:
kern/tru64/dump_mbuf.cc:
kern/tru64/dump_mbuf.hh:
kern/tru64/mbuf.hh:
kern/tru64/printf.cc:
kern/tru64/printf.hh:
kern/tru64/tru64.hh:
kern/tru64/tru64_events.cc:
kern/tru64/tru64_events.hh:
kern/tru64/tru64_syscalls.cc:
kern/tru64/tru64_syscalls.hh:
kern/tru64/tru64_system.cc:
kern/tru64/tru64_system.hh:
sim/async.hh:
sim/builder.cc:
sim/builder.hh:
sim/debug.cc:
sim/debug.hh:
sim/eventq.cc:
sim/eventq.hh:
sim/host.hh:
sim/main.cc:
sim/param.cc:
sim/param.hh:
sim/process.cc:
sim/process.hh:
sim/serialize.cc:
sim/serialize.hh:
sim/sim_events.cc:
sim/sim_events.hh:
sim/sim_exit.hh:
sim/sim_object.cc:
sim/sim_object.hh:
sim/stat_control.cc:
sim/stat_control.hh:
sim/stats.hh:
sim/syscall_emul.cc:
sim/syscall_emul.hh:
sim/system.cc:
sim/system.hh:
sim/universe.cc:
test/bitvectest.cc:
test/circletest.cc:
test/cprintftest.cc:
test/initest.cc:
test/lru_test.cc:
test/nmtest.cc:
test/offtest.cc:
test/paramtest.cc:
test/rangetest.cc:
test/sized_test.cc:
test/stattest.cc:
test/strnumtest.cc:
test/symtest.cc:
test/tokentest.cc:
test/tracetest.cc:
util/m5/m5.c:
util/m5/m5op.h:
util/tap/tap.cc:
    Updated Copyright
dev/console.cc:
dev/console.hh:
    This code isn't ours, and shouldn't have our copyright

--HG--
extra : convert_revision : 598f2e5eab5d5d3de2c1e862b389086e3212f7c4
2004-06-08 13:37:27 -04:00
Ali Saidi
caf5cad959 Merge saidi@zizzer:/z/m5/Bitkeeper/m5/
into zeep.eecs.umich.edu:/z/saidi/work/m5

--HG--
extra : convert_revision : 89e0bdd427b23a8f52b8ba53b18451df7be22f14
2004-06-01 16:03:16 -04:00
Ali Saidi
59cb44385a Added ability to specify system type/revision in config file. This
way a Tru64 system can be either Tlaser (by default) or Tsunami.

Added debugSymbolTable to Tru64 for symbol printing in InstExec Trace

cpu/exetrace.cc:
    Fixed bug if debugSymbolTable doesn't exist, we shouldn't try to
    look something up in it.
kern/tru64/tru64_system.hh:
    Added ability to specify system type/revision in config file. This
    way a Tru64 system can be either Tlaser (by default) or Tsunami.

--HG--
extra : convert_revision : c69a7411f0aa118ca5a766e43b7ceb7a5bb04cdf
2004-06-01 15:43:27 -04:00
Steve Reinhardt
53dde8579b Renamed OpClass enum members: they all end in 'Op' now.
Got rid of two inconsistent sets of strings that corresponded
to this enum, and replaced with a single set that clearly
matches the enum names.

arch/alpha/isa_desc:
arch/isa_parser.py:
cpu/full_cpu/op_class.hh:
    Renamed OpClass enum members.

--HG--
extra : convert_revision : bf596f7568a20b2e77c07ac349f253135141aef4
2004-05-31 16:19:31 -07:00
Ali Saidi
93983de0cf Merged head into linux tree
base/stats/mysql.hh:
    Rename of Statsistics namespace to stats... merge from head

--HG--
extra : convert_revision : a5a7f6268b35e75fba1b1800a74fcd6dbd09d974
2004-05-31 18:58:54 -04:00
Kevin Lim
67b5f6afc1 Merged in new FastCPU stuff with existing code.
arch/alpha/ev5.cc:
    Added templatized processInterrupts() function that can be used by all of the CPU models.
arch/alpha/isa_desc:
    Merged in changes to remove CPU dependence.
arch/isa_parser.py:
    Merged in changes.
cpu/static_inst.hh:
    Includes FastCPU execute methods.

--HG--
extra : convert_revision : fcaa1dca35a9b316c73982bec8680df564f50bd8
2004-05-28 11:41:52 -04:00
Kevin Lim
a896960cbf FastCPU model added. It's very similar to the SimpleCPU, just without a lot of the stats tracking.
Also various changes to make the CPU model less ISA dependent, which includes moving the code that checks for interrupts up to the ISA level, moving code that zeroes the zero registers up to the ISA level, and removing opcode and ra from the regfile.

arch/alpha/alpha_memory.cc:
    The regfile has been changed so it no longer has the opcode and ra.  Instead the xc holds the actual instruction, and from there the opcode and ra can be obtained with OPCODE() and RA().
arch/alpha/ev5.cc:
    Moved code that once existed within simpleCPU to ev5, and templatized it.
    This way the CPU models can call processInterrupts and the ISA specific interrupt handling is left to the ISA's code.
    Also moved ISA specific zero registers from simpleCPU to here.
arch/alpha/ev5.hh:
    Added macros for obtaining the opcode and ra from the instruction itself, as there is no longer opcode or ra in the regfile.
arch/alpha/isa_desc:
    Added in declarations for the FastCPU model.
arch/alpha/isa_traits.hh:
    Removed opcode and ra from the regfile.  The xc now holds the actual instruction, and the opcode and ra can be obtained through it.
    Also added the declaration for the templated zeroRegisters() function, which will set the zero registers to 0.
arch/isa_parser.py:
    Added in FastCPUExecContext so it will generate code for the FastCPU model as well.
cpu/exec_context.cc:
    Added in a more generic trap function so "ev5_trap" doesn't need to be called.  It currently still calls the old method, with plans for making this ISA dependent in the future.
cpu/exec_context.hh:
    Exec context now has the instruction within it.  Also added methods for exec context to read an instruction from memory, return the current instruction, and set the instruction if needed.
    Also has declaration for more generic trap() function.
cpu/simple_cpu/simple_cpu.cc:
    Removed references to opcode and ra, and instead sets the xc's instruction with the fetched instruction.
cpu/static_inst.hh:
    Added declaration for execute() using FastCPUExecContext.

--HG--
extra : convert_revision : 0441ea3700ac50b733e485395d4dd4ac83666f92
2004-05-27 17:46:16 -04:00
Nathan Binkert
f622d74f81 add a few statistics events
arch/alpha/ev5.cc:
    Add an event for faults
cpu/simple_cpu/simple_cpu.cc:
    add events for uncached reads/writes

--HG--
extra : convert_revision : 747bdf12761e2de6ebbf54fecc9e0b71915b3a02
2004-05-21 13:58:39 -04:00