Add a new operation class for IPR accesses, and have IPR-accessing
instructions use it (instead of IntALU, as before). Default config has a single non-pipelined 3-cycle unit. A bit conservative for the ev6 (some are 1, some are 3). arch/alpha/isa_desc: Make hw_mfpr and hw_mtpr use IprAccessOp op class. cpu/full_cpu/op_class.hh: Add IprAccess. --HG-- extra : convert_revision : d4103da3343a586936839e29981fd15d6930d442
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@ -1610,7 +1610,8 @@ output decoder {{
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}};
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def format HwMoveIPR(code) {{
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iop = InstObjParams(name, Name, 'HwMoveIPR', CodeBlock(code))
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iop = InstObjParams(name, Name, 'HwMoveIPR', CodeBlock(code),
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['IprAccessOp'])
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header_output = BasicDeclare.subst(iop)
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decoder_output = BasicConstructor.subst(iop)
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decode_block = BasicDecode.subst(iop)
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@ -51,6 +51,7 @@ enum OpClass {
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FloatSqrtOp, /* floating point square root */
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MemReadOp, /* memory read port */
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MemWriteOp, /* memory write port */
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IprAccessOp, /* Internal Processor Register read/write port */
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InstPrefetchOp, /* instruction prefetch port (on I-cache) */
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Num_OpClasses /* total functional unit classes */
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};
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