gem5/cpu
Kevin Lim 61d95de4c8 Large update of several parts of my code. The most notable change is the inclusion of a full-fledged load/store queue. At the moment it still has some issues running, but most of the code is hopefully close to the final version.
SConscript:
arch/isa_parser.py:
cpu/base_dyn_inst.cc:
    Remove OOO CPU stuff.
arch/alpha/faults.hh:
    Add fake memory fault.  This will be removed eventually.
arch/alpha/isa_desc:
    Change EA comp and Mem accessor to be const StaticInstPtrs.
cpu/base_dyn_inst.hh:
    Update read/write calls to use load queue and store queue indices.
cpu/beta_cpu/alpha_dyn_inst.hh:
    Change to const StaticInst in the register accessors.
cpu/beta_cpu/alpha_dyn_inst_impl.hh:
    Update syscall code with thread numbers.
cpu/beta_cpu/alpha_full_cpu.hh:
    Alter some of the full system code so it will compile without errors.
cpu/beta_cpu/alpha_full_cpu_builder.cc:
    Created a DerivAlphaFullCPU class so I can instantiate different CPUs that have different template parameters.
cpu/beta_cpu/alpha_full_cpu_impl.hh:
    Update some of the full system code so it compiles.
cpu/beta_cpu/alpha_params.hh:
cpu/beta_cpu/fetch_impl.hh:
    Remove asid.
cpu/beta_cpu/comm.hh:
    Remove global history field.
cpu/beta_cpu/commit.hh:
    Comment out rename map.
cpu/beta_cpu/commit_impl.hh:
    Update some of the full system code so it compiles.  Also change it so that it handles memory instructions properly.
cpu/beta_cpu/cpu_policy.hh:
    Removed IQ from the IEW template parameter to make it more uniform.
cpu/beta_cpu/decode.hh:
    Add debug function.
cpu/beta_cpu/decode_impl.hh:
    Slight updates for decode in the case where it causes a squash.
cpu/beta_cpu/fetch.hh:
cpu/beta_cpu/rob.hh:
    Comment out unneccessary code.
cpu/beta_cpu/full_cpu.cc:
    Changed some of the full system code so it compiles.  Updated exec contexts and so forth to hopefully make multithreading easier.
cpu/beta_cpu/full_cpu.hh:
    Updated some of the full system code to make it compile.
cpu/beta_cpu/iew.cc:
    Removed IQ from template parameter to IEW.
cpu/beta_cpu/iew.hh:
    Removed IQ from template parameter to IEW. Updated IEW to recognize the Load/Store queue.
cpu/beta_cpu/iew_impl.hh:
    New handling of memory instructions through the Load/Store queue.
cpu/beta_cpu/inst_queue.hh:
    Updated comment.
cpu/beta_cpu/inst_queue_impl.hh:
    Slightly different handling of memory instructions due to Load/Store queue.
cpu/beta_cpu/regfile.hh:
    Updated full system code so it compiles.
cpu/beta_cpu/rob_impl.hh:
    Moved some code around; no major functional changes.
cpu/ooo_cpu/ooo_cpu.hh:
    Slight updates to OOO CPU; still does not work.
cpu/static_inst.hh:
    Remove OOO CPU stuff.  Change ea comp and mem acc to return const StaticInst.
kern/kernel_stats.hh:
    Extra forward declares added due to compile error.

--HG--
extra : convert_revision : 594a7cdbe57f6c2bda7d08856fcd864604a6238e
2005-05-03 10:56:47 -04:00
..
beta_cpu Large update of several parts of my code. The most notable change is the inclusion of a full-fledged load/store queue. At the moment it still has some issues running, but most of the code is hopefully close to the final version. 2005-05-03 10:56:47 -04:00
full_cpu Add a new operation class for IPR accesses, and have IPR-accessing 2005-03-01 00:39:57 -05:00
memtest Make the notion of a global event tick independent of the actual 2005-04-11 15:32:06 -04:00
ooo_cpu Large update of several parts of my code. The most notable change is the inclusion of a full-fledged load/store queue. At the moment it still has some issues running, but most of the code is hopefully close to the final version. 2005-05-03 10:56:47 -04:00
simple_cpu Merge ktlim@zizzer.eecs.umich.edu:/bk/m5 2005-04-14 16:06:34 -04:00
trace Make the notion of a global event tick independent of the actual 2005-04-11 15:32:06 -04:00
base_cpu.cc Merge ktlim@zizzer.eecs.umich.edu:/bk/m5 2005-04-14 16:06:34 -04:00
base_cpu.hh Make the notion of a global event tick independent of the actual 2005-04-11 15:32:06 -04:00
base_dyn_inst.cc Large update of several parts of my code. The most notable change is the inclusion of a full-fledged load/store queue. At the moment it still has some issues running, but most of the code is hopefully close to the final version. 2005-05-03 10:56:47 -04:00
base_dyn_inst.hh Large update of several parts of my code. The most notable change is the inclusion of a full-fledged load/store queue. At the moment it still has some issues running, but most of the code is hopefully close to the final version. 2005-05-03 10:56:47 -04:00
exec_context.cc - Clean up and factor out all of the binning code into a 2004-08-20 11:35:31 -04:00
exec_context.hh Changed all syscalls to use syscall return object. 2005-03-09 15:52:10 -05:00
exetrace.cc Fix timing modeling of faults: functionally the very next instruction after 2005-02-25 12:41:08 -05:00
exetrace.hh Updated Copyright with information in bitkeeper changelogs 2004-06-08 13:37:27 -04:00
inst_seq.hh Updated Copyright with information in bitkeeper changelogs 2004-06-08 13:37:27 -04:00
intr_control.cc Updated Copyright with information in bitkeeper changelogs 2004-06-08 13:37:27 -04:00
intr_control.hh Updated Copyright with information in bitkeeper changelogs 2004-06-08 13:37:27 -04:00
pc_event.cc Clean up output for pc break events, and remove a unneeded break event. 2005-04-28 17:24:04 -04:00
pc_event.hh pc event now clears lower 2 bits 2004-09-16 15:11:38 -04:00
static_inst.cc Make all StaticInst methods const. StaticInst objects represent a 2005-02-25 21:44:33 -05:00
static_inst.hh Large update of several parts of my code. The most notable change is the inclusion of a full-fledged load/store queue. At the moment it still has some issues running, but most of the code is hopefully close to the final version. 2005-05-03 10:56:47 -04:00