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Slight fixes, add in commit trace flag.

Browse source 
base/traceflags.py:
    Add new commit rate trace flag.
build/SConstruct:
    Add extra option for efence.
cpu/beta_cpu/alpha_full_cpu_impl.hh:
    Use function calls instead of direct indexing (avoids confusion).
cpu/beta_cpu/commit_impl.hh:
    Add commit rate trace output (might not be worthwhile in the future).
cpu/beta_cpu/decode_impl.hh:
    Remove some older hacks.  Fix it so that the isntruction properly sets its next
    PC to the one calculated by the branch.
cpu/beta_cpu/fetch_impl.hh:
    Remove old commented code.
cpu/beta_cpu/iew_impl.hh:
    Add extra check to ensure that the instruction is valid.
cpu/beta_cpu/regfile.hh:
    Include trace file.

--HG--
extra : convert_revision : 4ee1dc88f8a5ed9b65486c6c111a3718a8040e42
This commit is contained in:
Kevin Lim 2005-01-11 18:52:29 -05:00
parent 2fb632dbda
commit 90d4436351
8 changed files with 23 additions and 31 deletions
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3
base/traceflags.py
View file

@ -136,7 +136,8 @@ baseFlags = [
'StoreSet',
'MemDepUnit',
'DynInst',
'FullCPU'
'FullCPU',
'CommitRate'
]
#

7
build/SConstruct
View file

@ -114,11 +114,16 @@ def MySqlOpt(env):
def NoFastAllocOpt(env):
env.Append(CPPDEFINES = 'NO_FAST_ALLOC')
# Enable efence
def EfenceOpt(env):
env.Append(LIBS=['efence'])
# Configuration options map.
options_map = {
'MEASURE' : MeasureOpt,
'MYSQL' : MySqlOpt,
'NO_FAST_ALLOC' : NoFastAllocOpt
'NO_FAST_ALLOC' : NoFastAllocOpt,
'EFENCE' : EfenceOpt
}
# The 'local_configs' file can be used to define additional base

12
cpu/beta_cpu/alpha_full_cpu_impl.hh
View file

@ -127,7 +127,7 @@ AlphaFullCPU<Impl>::copyToXC()
for (int i = 0; i < AlphaISA::NumIntRegs; ++i)
{
renamed_reg = renameMap.lookup(i);
xc->regs.intRegFile[i] = regFile.intRegFile[renamed_reg];
xc->regs.intRegFile[i] = regFile.readIntReg(renamed_reg);
DPRINTF(FullCPU, "FullCPU: Copying register %i, has data %lli.\n",
renamed_reg, regFile.intRegFile[renamed_reg]);
}
@ -136,8 +136,8 @@ AlphaFullCPU<Impl>::copyToXC()
for (int i = 0; i < AlphaISA::NumFloatRegs; ++i)
{
renamed_reg = renameMap.lookup(i + AlphaISA::FP_Base_DepTag);
xc->regs.floatRegFile.d[i] = regFile.floatRegFile[renamed_reg].d;
xc->regs.floatRegFile.q[i] = regFile.floatRegFile[renamed_reg].q;
xc->regs.floatRegFile.d[i] = regFile.readFloatRegDouble(renamed_reg);
xc->regs.floatRegFile.q[i] = regFile.readFloatRegInt(renamed_reg);
}
xc->regs.miscRegs.fpcr = regFile.miscRegs.fpcr;
@ -169,15 +169,15 @@ AlphaFullCPU<Impl>::copyFromXC()
renamed_reg, regFile.intRegFile[renamed_reg],
xc->regs.intRegFile[i]);
regFile.intRegFile[renamed_reg] = xc->regs.intRegFile[i];
regFile.setIntReg(renamed_reg, xc->regs.intRegFile[i]);
}
// Then loop through the floating point registers.
for (int i = 0; i < AlphaISA::NumFloatRegs; ++i)
{
renamed_reg = renameMap.lookup(i + AlphaISA::FP_Base_DepTag);
regFile.floatRegFile[renamed_reg].d = xc->regs.floatRegFile.d[i];
regFile.floatRegFile[renamed_reg].q = xc->regs.floatRegFile.q[i] ;
regFile.setFloatRegDouble(renamed_reg, xc->regs.floatRegFile.d[i]);
regFile.setFloatRegInt(renamed_reg, xc->regs.floatRegFile.q[i]);
}
// Then loop through the misc registers.

1
cpu/beta_cpu/commit_impl.hh
View file

@ -323,6 +323,7 @@ SimpleCommit<Impl>::commitInsts()
head_inst = rob->readHeadInst();
}
DPRINTF(CommitRate, "%i\n", num_committed);
n_committed_dist.sample(num_committed);
}

9
cpu/beta_cpu/decode_impl.hh
View file

@ -147,7 +147,7 @@ SimpleDecode<Impl>::squash(DynInstPtr &inst)
{
DPRINTF(Decode, "Decode: Squashing due to incorrect branch prediction "
"detected at decode.\n");
Addr new_PC = inst->nextPC;
Addr new_PC = inst->readNextPC();
toFetch->decodeInfo.branchMispredict = true;
toFetch->decodeInfo.doneSeqNum = inst->seqNum;
@ -355,10 +355,9 @@ SimpleDecode<Impl>::decode()
// Go ahead and compute any PC-relative branches.
if (inst->isDirectCtrl() && inst->isUncondCtrl() &&
inst->numDestRegs() == 0 && inst->numSrcRegs() == 0) {
inst->execute();
inst->setExecuted();
if (inst->isDirectCtrl() && inst->isUncondCtrl()) {
inst->setNextPC(inst->branchTarget());
if (inst->mispredicted()) {
++decodeBranchMispred;

16
cpu/beta_cpu/fetch_impl.hh
View file

@ -195,22 +195,6 @@ SimpleFetch<Impl>::lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC)
predict_taken = branchPred.predict(inst, next_PC);
#if 0
predict_taken = branchPred.BPLookup(next_PC)
DPRINTF(Fetch, "Fetch: Branch predictor predicts taken? %i\n",
predict_taken);
// Only check the BTB if the BP has predicted taken.
if (predict_taken && branchPred.BTBValid(next_PC)) {
predict_target = branchPred.BTBLookup(next_PC);
DPRINTF(Fetch, "Fetch: BTB target is %#x.\n", predict_target);
} else {
predict_taken = false;
DPRINTF(Fetch, "Fetch: BTB does not have a valid entry.\n");
}
#endif
if (predict_taken) {
++predictedBranches;
}

4
cpu/beta_cpu/iew_impl.hh
View file

@ -249,7 +249,6 @@ SimpleIEW<Impl, IQ>::squashDueToBranch(DynInstPtr &inst)
// Prediction was incorrect, so send back inverse.
toCommit->branchTaken = inst->readCalcTarg() !=
(inst->readPC() + sizeof(MachInst));
// toCommit->globalHist = inst->readGlobalHist();
}
template<class Impl, class IQ>
@ -363,10 +362,11 @@ SimpleIEW<Impl, IQ>::dispatchInsts()
continue;
} else if (inst->isExecuted()) {
assert(0 && "Instruction shouldn't be executed.\n");
DPRINTF(IEW, "IEW: Issue: Executed branch encountered, "
"skipping.\n");
assert(inst->isDirectCtrl());
// assert(inst->isDirectCtrl());
inst->setIssued();
inst->setCanCommit();

2
cpu/beta_cpu/regfile.hh
View file

@ -8,6 +8,8 @@ using namespace std;
#include "arch/alpha/isa_traits.hh"
#include "cpu/beta_cpu/comm.hh"
#include "base/trace.hh"
// This really only depends on the ISA, and not the Impl. It might be nicer
// to see if I can make it depend on nothing...
// Things that are in the ifdef FULL_SYSTEM are pretty dependent on the ISA,