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cpu/simple_cpu/simple_cpu.hh:
    Merge

--HG--
extra : convert_revision : 1b6003ac731051fefacb7d7a30c317553b4bf1bc
This commit is contained in:
Ron Dreslinski 2005-02-09 12:56:24 -05:00
parent d9317dd348 c4089562d5
commit 230a5a608d
74 changed files with 1152 additions and 372 deletions
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20
arch/alpha/alpha_linux_process.cc
View file

@ -26,24 +26,24 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <errno.h>
#include <unistd.h>
#include <fcntl.h> // for host open() flags
#include <sys/types.h>
#include <sys/stat.h>
#include <string.h> // for memset()
#include <dirent.h>
#include <errno.h>
#include <fcntl.h> // for host open() flags
#include <string.h> // for memset()
#include <sys/stat.h>
#include <sys/types.h>
#include <unistd.h>
#include "sim/host.hh"
#include "cpu/base_cpu.hh"
#include "mem/functional_mem/functional_memory.hh"
#include "sim/process.hh"
#include "cpu/exec_context.hh"
#include "mem/functional_mem/functional_memory.hh"
#include "sim/fake_syscall.hh"
#include "sim/host.hh"
#include "sim/process.hh"
#include "sim/sim_events.hh"
#include "sim/syscall_emul.hh"
#include "arch/alpha/alpha_common_syscall_emul.hh"
#include "sim/syscall_emul.hh"
#include "sim/universe.hh" // for curTick & ticksPerSecond
#include "arch/alpha/alpha_linux_process.hh"

171
arch/alpha/isa_desc
View file

@ -790,48 +790,14 @@ output header {{
protected:
/// Constructor
MemoryNoDisp(const char *mnem, MachInst _machInst, OpClass __opClass,
StaticInstPtr<AlphaISA> _eaCompPtr,
StaticInstPtr<AlphaISA> _memAccPtr)
StaticInstPtr<AlphaISA> _eaCompPtr = nullStaticInstPtr,
StaticInstPtr<AlphaISA> _memAccPtr = nullStaticInstPtr)
: Memory(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr)
{
}
std::string generateDisassembly(Addr pc, const SymbolTable *symtab);
};
/**
* Base class for "fake" effective-address computation
* instructions returnded by eaCompInst().
*/
class EACompBase : public AlphaStaticInst
{
public:
/// Constructor
EACompBase(MachInst machInst)
: AlphaStaticInst("(eacomp)", machInst, IntAluOp)
{
}
%(BasicExecDeclare)s
};
/**
* Base class for "fake" memory-access instructions returnded by
* memAccInst().
*/
class MemAccBase : public AlphaStaticInst
{
public:
/// Constructor
MemAccBase(MachInst machInst, OpClass __opClass)
: AlphaStaticInst("(memacc)", machInst, __opClass)
{
}
%(BasicExecDeclare)s
};
}};
@ -850,21 +816,6 @@ output decoder {{
}
}};
output exec {{
Fault
EACompBase::execute(%(CPU_exec_context)s *, Trace::InstRecord *)
{
panic("attempt to execute eacomp");
}
Fault
MemAccBase::execute(%(CPU_exec_context)s *, Trace::InstRecord *)
{
panic("attempt to execute memacc");
}
}};
def format LoadAddress(code) {{
iop = InstObjParams(name, Name, 'MemoryDisp32', CodeBlock(code))
header_output = BasicDeclare.subst(iop)
@ -885,21 +836,25 @@ def template LoadStoreDeclare {{
/**
* "Fake" effective address computation class for "%(mnemonic)s".
*/
class EAComp : public EACompBase
class EAComp : public %(base_class)s
{
public:
/// Constructor
EAComp(MachInst machInst);
%(BasicExecDeclare)s
};
/**
* "Fake" memory access instruction class for "%(mnemonic)s".
*/
class MemAcc : public MemAccBase
class MemAcc : public %(base_class)s
{
public:
/// Constructor
MemAcc(MachInst machInst);
%(BasicExecDeclare)s
};
public:
@ -912,14 +867,17 @@ def template LoadStoreDeclare {{
}};
def template LoadStoreConstructor {{
/** TODO: change op_class to AddrGenOp or something (requires
* creating new member of OpClass enum in op_class.hh, updating
* config files, etc.). */
inline %(class_name)s::EAComp::EAComp(MachInst machInst)
: EACompBase(machInst)
: %(base_class)s("%(mnemonic)s (EAComp)", machInst, IntAluOp)
{
%(ea_constructor)s;
}
inline %(class_name)s::MemAcc::MemAcc(MachInst machInst)
: MemAccBase(machInst, %(op_class)s)
: %(base_class)s("%(mnemonic)s (MemAcc)", machInst, %(op_class)s)
{
%(memacc_constructor)s;
}
@ -932,6 +890,64 @@ def template LoadStoreConstructor {{
}
}};
def template EACompExecute {{
Fault
%(class_name)s::EAComp::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData)
{
Addr EA;
Fault fault = No_Fault;
%(fp_enable_check)s;
%(op_decl)s;
%(op_rd)s;
%(code)s;
if (fault == No_Fault) {
%(op_wb)s;
xc->setEA(EA);
}
return fault;
}
}};
def template MemAccExecute {{
Fault
%(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData)
{
Addr EA;
Fault fault = No_Fault;
%(fp_enable_check)s;
%(op_decl)s;
%(op_nonmem_rd)s;
EA = xc->getEA();
if (fault == No_Fault) {
%(op_mem_rd)s;
%(code)s;
}
if (fault == No_Fault) {
%(op_mem_wb)s;
}
if (fault == No_Fault) {
%(postacc_code)s;
}
if (fault == No_Fault) {
%(op_nonmem_wb)s;
}
return fault;
}
}};
def template LoadStoreExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData)
@ -1022,18 +1038,33 @@ def LoadStoreBase(name, Name, ea_code, memacc_code, postacc_code = '',
# Would be nice to autogenerate this list, but oh well.
valid_mem_flags = ['LOCKED', 'NO_FAULT', 'EVICT_NEXT', 'PF_EXCLUSIVE']
inst_flags = []
mem_flags = []
for f in flags:
if f in valid_mem_flags:
mem_flags.append(f)
else:
inst_flags.append(f)
mem_flags = [f for f in flags if f in valid_mem_flags]
inst_flags = [f for f in flags if f not in valid_mem_flags]
# add hook to get effective addresses into execution trace output.
ea_code += '\nif (traceData) { traceData->setAddr(EA); }\n'
# generate code block objects
ea_cblk = CodeBlock(ea_code)
memacc_cblk = CodeBlock(memacc_code)
postacc_cblk = CodeBlock(postacc_code)
# Some CPU models execute the memory operation as an atomic unit,
# while others want to separate them into an effective address
# computation and a memory access operation. As a result, we need
# to generate three StaticInst objects. Note that the latter two
# are nested inside the larger "atomic" one.
# generate InstObjParams for EAComp object
ea_iop = InstObjParams(name, Name, base_class, ea_cblk, inst_flags)
# generate InstObjParams for MemAcc object
memacc_iop = InstObjParams(name, Name, base_class, memacc_cblk, inst_flags)
# in the split execution model, the MemAcc portion is responsible
# for the post-access code.
memacc_iop.postacc_code = postacc_cblk.code
# generate InstObjParams for unified execution
cblk = CodeBlock(ea_code + memacc_code + postacc_code)
iop = InstObjParams(name, Name, base_class, cblk, inst_flags)
@ -1043,13 +1074,17 @@ def LoadStoreBase(name, Name, ea_code, memacc_code, postacc_code = '',
iop.memacc_code = memacc_cblk.code
iop.postacc_code = postacc_cblk.code
mem_flags = string.join(mem_flags, '|')
if mem_flags != '':
iop.constructor += '\n\tmemAccessFlags = ' + mem_flags + ';'
if mem_flags:
s = '\n\tmemAccessFlags = ' + string.join(mem_flags, '|') + ';'
iop.constructor += s
memacc_iop.constructor += s
# (header_output, decoder_output, decode_block, exec_output)
return (LoadStoreDeclare.subst(iop), LoadStoreConstructor.subst(iop),
decode_template.subst(iop), exec_template.subst(iop))
decode_template.subst(iop),
EACompExecute.subst(ea_iop)
+ MemAccExecute.subst(memacc_iop)
+ exec_template.subst(iop))
}};
@ -1460,8 +1495,8 @@ output header {{
/// Constructor
HwLoadStore(const char *mnem, MachInst _machInst, OpClass __opClass,
StaticInstPtr<AlphaISA> _eaCompPtr,
StaticInstPtr<AlphaISA> _memAccPtr);
StaticInstPtr<AlphaISA> _eaCompPtr = nullStaticInstPtr,
StaticInstPtr<AlphaISA> _memAccPtr = nullStaticInstPtr);
std::string generateDisassembly(Addr pc, const SymbolTable *symtab);
};

11
arch/alpha/vptr.hh
View file

@ -26,8 +26,8 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __VPTR_HH__
#define __VPTR_HH__
#ifndef __ARCH_ALPHA_VPTR_HH__
#define __ARCH_ALPHA_VPTR_HH__
#include "arch/alpha/vtophys.hh"
@ -69,14 +69,15 @@ class VPtr
const VPtr<T> &operator+=(int offset)
{
ptr += offset;
assert((ptr & (ALPHA_PGBYTES - 1)) + sizeof(T) < ALPHA_PGBYTES);
assert((ptr & (AlphaISA::PageBytes - 1)) + sizeof(T)
< AlphaISA::PageBytes);
return *this;
}
const VPtr<T> &operator=(Addr p)
{
assert((p & (ALPHA_PGBYTES - 1)) + sizeof(T) < ALPHA_PGBYTES);
assert((p & (AlphaISA::PageBytes)) + sizeof(T) < AlphaISA::PageBytes);
ptr = p;
return *this;
@ -110,4 +111,4 @@ class VPtr
}
};
#endif // __VPTR_HH__
#endif // __ARCH_ALPHA_VPTR_HH__

6
arch/isa_parser.py
View file

@ -1210,10 +1210,12 @@ class MemOperandTraits(OperandTraits):
def makeWrite(self, op_desc):
(size, type, is_signed) = operandSizeMap[op_desc.eff_ext]
eff_type = 'uint%d_t' % size
return 'fault = xc->write((%s&)%s, EA, %s_flags,' \
' &%s_write_result);\n' \
wb = 'fault = xc->write((%s&)%s, EA, %s_flags, &%s_write_result);\n' \
% (eff_type, op_desc.munged_name, op_desc.base_name,
op_desc.base_name)
wb += 'if (traceData) { traceData->setData(%s); }' % \
op_desc.munged_name
return wb
class NPCOperandTraits(OperandTraits):
def makeConstructor(self, op_desc):

20
base/random.hh
View file

@ -37,61 +37,61 @@ double getDouble();
template <typename T>
struct Random;
struct Random<int8_t>
template<> struct Random<int8_t>
{
static int8_t get()
{ return getLong() & (int8_t)-1; }
};
struct Random<uint8_t>
template<> struct Random<uint8_t>
{
static uint8_t get()
{ return getLong() & (uint8_t)-1; }
};
struct Random<int16_t>
template<> struct Random<int16_t>
{
static int16_t get()
{ return getLong() & (int16_t)-1; }
};
struct Random<uint16_t>
template<> struct Random<uint16_t>
{
static uint16_t get()
{ return getLong() & (uint16_t)-1; }
};
struct Random<int32_t>
template<> struct Random<int32_t>
{
static int32_t get()
{ return (int32_t)getLong(); }
};
struct Random<uint32_t>
template<> struct Random<uint32_t>
{
static uint32_t get()
{ return (uint32_t)getLong(); }
};
struct Random<int64_t>
template<> struct Random<int64_t>
{
static int64_t get()
{ return (int64_t)getLong() << 32 || (uint64_t)getLong(); }
};
struct Random<uint64_t>
template<> struct Random<uint64_t>
{
static uint64_t get()
{ return (uint64_t)getLong() << 32 || (uint64_t)getLong(); }
};
struct Random<float>
template<> struct Random<float>
{
static float get()
{ return getDouble(); }
};
struct Random<double>
template<> struct Random<double>
{
static double get()
{ return getDouble(); }

1
base/range.hh
View file

@ -30,6 +30,7 @@
#define __BASE_RANGE_HH__
#include <cassert>
#include <iostream>
#include <string>
/**

2
base/res_list.hh
View file

@ -352,7 +352,7 @@ res_list<T>::insert_after(iterator prev, T *d)
iterator p;
if (!allocate_storage)
panic("Can't copy data... not allocating storage");
this->panic("Can't copy data... not allocating storage");
p = insert_after(prev);
if (p.notnull())

128
base/statistics.hh
View file

@ -407,7 +407,7 @@ class Wrap : public Child
public:
Wrap()
{
map(new Data<Child>(*this));
map(new Data<Child>(*this));
}
/**
@ -417,10 +417,10 @@ class Wrap : public Child
*/
Parent &name(const std::string &_name)
{
Data<Child> *data = statData();
Data<Child> *data = this->statData();
data->name = _name;
setPrint();
return self();
this->setPrint();
return this->self();
}
/**
@ -431,8 +431,8 @@ class Wrap : public Child
*/
Parent &desc(const std::string &_desc)
{
statData()->desc = _desc;
return self();
this->statData()->desc = _desc;
return this->self();
}
/**
@ -442,8 +442,8 @@ class Wrap : public Child
*/
Parent &precision(int _precision)
{
statData()->precision = _precision;
return self();
this->statData()->precision = _precision;
return this->self();
}
/**
@ -453,8 +453,8 @@ class Wrap : public Child
*/
Parent &flags(StatFlags _flags)
{
statData()->flags |= _flags;
return self();
this->statData()->flags |= _flags;
return this->self();
}
/**
@ -466,8 +466,8 @@ class Wrap : public Child
template <class Stat>
Parent &prereq(const Stat &prereq)
{
statData()->prereq = prereq.statData();
return self();
this->statData()->prereq = prereq.statData();
return this->self();
}
};
@ -487,11 +487,11 @@ class WrapVec : public Wrap<Parent, Child, Data>
*/
Parent &subname(int index, const std::string &name)
{
std::vector<std::string> &subn = statData()->subnames;
std::vector<std::string> &subn = this->statData()->subnames;
if (subn.size() <= index)
subn.resize(index + 1);
subn[index] = name;
return self();
return this->self();
}
/**
@ -503,12 +503,12 @@ class WrapVec : public Wrap<Parent, Child, Data>
*/
Parent &subdesc(int index, const std::string &desc)
{
std::vector<std::string> &subd = statData()->subdescs;
std::vector<std::string> &subd = this->statData()->subdescs;
if (subd.size() <= index)
subd.resize(index + 1);
subd[index] = desc;
return self();
return this->self();
}
};
@ -523,19 +523,19 @@ class WrapVec2d : public WrapVec<Parent, Child, Data>
*/
Parent &ysubnames(const char **names)
{
Data<Child> *data = statData();
data->y_subnames.resize(y);
for (int i = 0; i < y; ++i)
Data<Child> *data = this->statData();
data->y_subnames.resize(this->y);
for (int i = 0; i < this->y; ++i)
data->y_subnames[i] = names[i];
return self();
return this->self();
}
Parent &ysubname(int index, const std::string subname)
{
Data<Child> *data = statData();
assert(index < y);
data->y_subnames.resize(y);
Data<Child> *data = this->statData();
assert(index < this->y);
data->y_subnames.resize(this->y);
data->y_subnames[index] = subname.c_str();
return self();
return this->self();
}
};
@ -711,7 +711,7 @@ class ScalarBase : public DataAccess
/** Define the params of the storage class. */
typedef typename Storage::Params params_t;
/** Define the bin type. */
typedef typename Bin::Bin<Storage> bin_t;
typedef typename Bin::template Bin<Storage> bin_t;
protected:
/** The bin of this stat. */
@ -914,7 +914,7 @@ class VectorBase : public DataAccess
/** Define the params of the storage class. */
typedef typename Storage::Params params_t;
/** Define the bin type. */
typedef typename Bin::VectorBin<Storage> bin_t;
typedef typename Bin::template VectorBin<Storage> bin_t;
protected:
/** The bin of this stat. */
@ -1022,7 +1022,7 @@ class ScalarProxy
/** Define the params of the storage class. */
typedef typename Storage::Params params_t;
/** Define the bin type. */
typedef typename Bin::VectorBin<Storage> bin_t;
typedef typename Bin::template VectorBin<Storage> bin_t;
private:
/** Pointer to the bin in the parent VectorBase. */
@ -1155,7 +1155,7 @@ class ScalarProxy
const StatData *statData() const { return getStatData(stat); }
std::string str() const
{
return csprintf("%s[%d]", statData()->name, index);
return csprintf("%s[%d]", this->statData()->name, index);
}
};
@ -1176,7 +1176,7 @@ class Vector2dBase : public DataAccess
{
public:
typedef typename Storage::Params params_t;
typedef typename Bin::VectorBin<Storage> bin_t;
typedef typename Bin::template VectorBin<Storage> bin_t;
protected:
size_t x;
@ -1204,7 +1204,7 @@ class Vector2dBase : public DataAccess
data->cvec[i] = this->data(i)->value(params);
}
std::string ysubname(int i) const { return (*y_subnames)[i]; }
std::string ysubname(int i) const { return (*this->y_subnames)[i]; }
friend class VectorProxy<Storage, Bin>;
VectorProxy<Storage, Bin> operator[](int index);
@ -1225,7 +1225,7 @@ class VectorProxy
{
public:
typedef typename Storage::Params params_t;
typedef typename Bin::VectorBin<Storage> bin_t;
typedef typename Bin::template VectorBin<Storage> bin_t;
private:
bin_t *bin;
@ -1622,7 +1622,7 @@ class DistBase : public DataAccess
/** Define the params of the storage class. */
typedef typename Storage::Params params_t;
/** Define the bin type. */
typedef typename Bin::Bin<Storage> bin_t;
typedef typename Bin::template Bin<Storage> bin_t;
protected:
/** The bin of this stat. */
@ -1698,7 +1698,7 @@ class VectorDistBase : public DataAccess
{
public:
typedef typename Storage::Params params_t;
typedef typename Bin::VectorBin<Storage> bin_t;
typedef typename Bin::template VectorBin<Storage> bin_t;
protected:
bin_t bin;
@ -1749,7 +1749,7 @@ class DistProxy
{
public:
typedef typename Storage::Params params_t;
typedef typename Bin::Bin<Storage> bin_t;
typedef typename Bin::template Bin<Storage> bin_t;
typedef VectorDistBase<Storage, Bin> base_t;
private:
@ -2206,7 +2206,7 @@ class Scalar
Scalar()
{
setInit();
this->setInit();
}
/**
@ -2258,7 +2258,7 @@ class Average
Average()
{
setInit();
this->setInit();
}
/**
@ -2290,8 +2290,8 @@ class Vector
* @return A reference to this stat.
*/
Vector &init(size_t size) {
bin.init(size, params);
setInit();
this->bin.init(size, this->params);
this->setInit();
return *this;
}
@ -2314,8 +2314,8 @@ class AverageVector
* @return A reference to this stat.
*/
AverageVector &init(size_t size) {
bin.init(size, params);
setInit();
this->bin.init(size, this->params);
this->setInit();
return *this;
}
@ -2333,10 +2333,10 @@ class Vector2d
{
public:
Vector2d &init(size_t _x, size_t _y) {
statData()->x = x = _x;
statData()->y = y = _y;
bin.init(x * y, params);
setInit();
this->statData()->x = this->x = _x;
this->statData()->y = this->y = _y;
this->bin.init(this->x * this->y, this->params);
this->setInit();
return *this;
}
@ -2367,12 +2367,12 @@ class Distribution
* @return A reference to this distribution.
*/
Distribution &init(Counter min, Counter max, Counter bkt) {
params.min = min;
params.max = max;
params.bucket_size = bkt;
params.size = (int)rint((max - min) / bkt + 1.0);
bin.init(params);
setInit();
this->params.min = min;
this->params.max = max;
this->params.bucket_size = bkt;
this->params.size = (int)rint((max - min) / bkt + 1.0);
this->bin.init(this->params);
this->setInit();
return *this;
}
@ -2399,8 +2399,8 @@ class StandardDeviation
* Construct and initialize this distribution.
*/
StandardDeviation() {
bin.init(params);
setInit();
this->bin.init(this->params);
this->setInit();
}
};
@ -2426,8 +2426,8 @@ class AverageDeviation
*/
AverageDeviation()
{
bin.init(params);
setInit();
this->bin.init(this->params);
this->setInit();
}
};
@ -2457,12 +2457,12 @@ class VectorDistribution
* @return A reference to this distribution.
*/
VectorDistribution &init(int size, Counter min, Counter max, Counter bkt) {
params.min = min;
params.max = max;
params.bucket_size = bkt;
params.size = (int)rint((max - min) / bkt + 1.0);
bin.init(size, params);
setInit();
this->params.min = min;
this->params.max = max;
this->params.bucket_size = bkt;
this->params.size = (int)rint((max - min) / bkt + 1.0);
this->bin.init(size, this->params);
this->setInit();
return *this;
}
@ -2491,8 +2491,8 @@ class VectorStandardDeviation
* @return A reference to this distribution.
*/
VectorStandardDeviation &init(int size) {
bin.init(size, params);
setInit();
this->bin.init(size, this->params);
this->setInit();
return *this;
}
@ -2521,8 +2521,8 @@ class VectorAverageDeviation
* @return A reference to this distribution.
*/
VectorAverageDeviation &init(int size) {
bin.init(size, params);
setInit();
this->bin.init(size, this->params);
this->setInit();
return *this;
}

2
base/trace.cc
View file

@ -71,7 +71,7 @@ Log::init(int _size)
size = _size;
buffer = new (Record *)[size];
buffer = new Record *[size];
for (int i = 0; i < size; ++i) {
buffer[i] = NULL;

6
base/trace.hh
View file

@ -26,8 +26,8 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __TRACE_HH__
#define __TRACE_HH__
#ifndef __BASE_TRACE_HH__
#define __BASE_TRACE_HH__
#include <vector>
@ -228,4 +228,4 @@ do { \
#endif // TRACING_ON
#endif // __TRACE_HH__
#endif // __BASE_TRACE_HH__

8
configs/boot/devtime.rcS Normal file
View file

@ -0,0 +1,8 @@
insmod /modules/devtime.ko dataAddr=0x9000004 count=100
rmmod devtime
insmod /modules/devtime.ko dataAddr=0x1a0000300 count=100
rmmod devtime
insmod /modules/devtime.ko memTest=1 count=100
rmmod devtime
m5 exit

1
configs/boot/nat-netperf-maerts-client.rcS
View file

@ -11,6 +11,7 @@ route add default gw 10.0.0.1
echo "0" > /proc/sys/net/ipv4/tcp_timestamps
echo "0" > /proc/sys/net/ipv4/tcp_sack
echo "1" > /proc/sys/net/ipv4/tcp_vegas_cong_avoid
echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_rmem
echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_wmem
echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_mem

1
configs/boot/nat-netperf-server.rcS
View file

@ -9,6 +9,7 @@ ifconfig eth0 $SERVER txqueuelen 1000
echo "0" > /proc/sys/net/ipv4/tcp_timestamps
echo "0" > /proc/sys/net/ipv4/tcp_sack
echo "1" > /proc/sys/net/ipv4/tcp_vegas_cong_avoid
echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_rmem
echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_wmem
echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_mem

1
configs/boot/nat-netperf-stream-client.rcS
View file

@ -8,6 +8,7 @@ ifconfig eth0 $CLIENT txqueuelen 1000
echo "0" > /proc/sys/net/ipv4/tcp_timestamps
echo "0" > /proc/sys/net/ipv4/tcp_sack
echo "1" > /proc/sys/net/ipv4/tcp_vegas_cong_avoid
echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_rmem
echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_wmem
echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_mem

1
configs/boot/nat-spec-surge-client.rcS
View file

@ -20,6 +20,7 @@ echo "0" > /proc/sys/net/ipv4/tcp_timestamps
echo "0" > /proc/sys/net/ipv4/tcp_sack
echo "15" > /proc/sys/net/ipv4/tcp_fin_timeout
echo "16384" > /proc/sys/net/ipv4/tcp_max_syn_backlog
echo "1" > /proc/sys/net/ipv4/tcp_vegas_cong_avoid
echo "1024 65535" > /proc/sys/net/ipv4/ip_local_port_range
echo "10000000 10000000 10000000" > /proc/sys/net/ipv4/tcp_rmem

1
configs/boot/nat-spec-surge-server.rcS
View file

@ -23,6 +23,7 @@ echo "0" > /proc/sys/net/ipv4/tcp_timestamps
echo "0" > /proc/sys/net/ipv4/tcp_sack
echo "15" > /proc/sys/net/ipv4/tcp_fin_timeout
echo "16384" > /proc/sys/net/ipv4/tcp_max_syn_backlog
echo "1" > /proc/sys/net/ipv4/tcp_vegas_cong_avoid
echo "1024 65535" > /proc/sys/net/ipv4/ip_local_port_range
echo "10000000 10000000 10000000" > /proc/sys/net/ipv4/tcp_rmem

2
configs/boot/natbox-netperf.rcS
View file

@ -10,6 +10,8 @@ ifconfig eth1 $INTIF txqueuelen 1000
echo "0" > /proc/sys/net/ipv4/tcp_timestamps
echo "0" > /proc/sys/net/ipv4/tcp_sack
echo "1" > /proc/sys/net/ipv4/tcp_vegas_cong_avoid
echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_rmem
echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_wmem
echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_mem

1
configs/boot/natbox-spec-surge.rcS
View file

@ -10,6 +10,7 @@ ifconfig eth1 $INTIF txqueuelen 1000
echo "0" > /proc/sys/net/ipv4/tcp_timestamps
echo "0" > /proc/sys/net/ipv4/tcp_sack
echo "1" > /proc/sys/net/ipv4/tcp_vegas_cong_avoid
echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_rmem
echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_wmem
echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_mem

4
cpu/base_cpu.cc
View file

@ -77,7 +77,7 @@ BaseCPU::BaseCPU(const string &_name, int _number_of_threads, bool _def_reg,
maxThreadsPerCPU = number_of_threads;
// allocate per-thread instruction-based event queues
comInstEventQueue = new (EventQueue *)[number_of_threads];
comInstEventQueue = new EventQueue *[number_of_threads];
for (int i = 0; i < number_of_threads; ++i)
comInstEventQueue[i] = new EventQueue("instruction-based event queue");
@ -102,7 +102,7 @@ BaseCPU::BaseCPU(const string &_name, int _number_of_threads, bool _def_reg,
}
// allocate per-thread load-based event queues
comLoadEventQueue = new (EventQueue *)[number_of_threads];
comLoadEventQueue = new EventQueue *[number_of_threads];
for (int i = 0; i < number_of_threads; ++i)
comLoadEventQueue[i] = new EventQueue("load-based event queue");

1
cpu/simple_cpu/simple_cpu.cc
View file

@ -75,6 +75,7 @@
using namespace std;
SimpleCPU::TickEvent::TickEvent(SimpleCPU *c)
: Event(&mainEventQueue, CPU_Tick_Pri), cpu(c), multiplier(1)
{

17
cpu/simple_cpu/simple_cpu.hh
View file

@ -26,8 +26,8 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __SIMPLE_CPU_HH__
#define __SIMPLE_CPU_HH__
#ifndef __CPU_SIMPLE_CPU_SIMPLE_CPU_HH__
#define __CPU_SIMPLE_CPU_SIMPLE_CPU_HH__
#include "base/statistics.hh"
#include "cpu/base_cpu.hh"
@ -103,12 +103,6 @@ class SimpleCPU : public BaseCPU
private:
Trace::InstRecord *traceData;
template<typename T>
void trace_data(T data) {
if (traceData) {
traceData->setData(data);
}
};
public:
//
@ -258,6 +252,11 @@ class SimpleCPU : public BaseCPU
template <class T>
Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
// These functions are only used in CPU models that split
// effective address computation from the actual memory access.
void setEA(Addr EA) { panic("SimpleCPU::setEA() not implemented\n"); }
Addr getEA() { panic("SimpleCPU::getEA() not implemented\n"); }
void prefetch(Addr addr, unsigned flags)
{
// need to do this...
@ -355,4 +354,4 @@ class SimpleCPU : public BaseCPU
ExecContext *xcBase() { return xc; }
};
#endif // __SIMPLE_CPU_HH__
#endif // __CPU_SIMPLE_CPU_SIMPLE_CPU_HH__

2
cpu/static_inst.cc
View file

@ -85,4 +85,4 @@ StaticInst<ISA>::hasBranchTarget(Addr pc, ExecContext *xc, Addr &tgt)
// force instantiation of template function(s) above
template StaticInst<AlphaISA>;
template class StaticInst<AlphaISA>;

2
cpu/static_inst.hh
View file

@ -456,7 +456,7 @@ class StaticInstPtr : public RefCountingPtr<StaticInst<ISA> >
/// Convert to pointer to StaticInstBase class.
operator const StaticInstBasePtr()
{
return get();
return this->get();
}
};

10
dev/etherlink.hh
View file

@ -30,13 +30,13 @@
* Device module for modelling a fixed bandwidth full duplex ethernet link
*/
#ifndef __ETHERLINK_HH__
#define __ETHERLINK_HH__
#ifndef __DEV_ETHERLINK_HH__
#define __DEV_ETHERLINK_HH__
#include "sim/host.hh"
#include "sim/eventq.hh"
#include "dev/etherint.hh"
#include "dev/etherpkt.hh"
#include "sim/eventq.hh"
#include "sim/host.hh"
#include "sim/sim_object.hh"
class EtherDump;
@ -71,7 +71,7 @@ class EtherLink : public SimObject
PacketPtr packet;
void txDone();
typedef EventWrapper<Link, &Link::txDone> DoneEvent;
friend class DoneEvent;
friend void DoneEvent::process();
DoneEvent doneEvent;
friend class LinkDelayEvent;

8
dev/ns_gige.hh
View file

@ -261,12 +261,12 @@ class NSGigE : public PciDev
void rxKick();
Tick rxKickTick;
typedef EventWrapper<NSGigE, &NSGigE::rxKick> RxKickEvent;
friend class RxKickEvent;
friend void RxKickEvent::process();
void txKick();
Tick txKickTick;
typedef EventWrapper<NSGigE, &NSGigE::txKick> TxKickEvent;
friend class TxKickEvent;
friend void TxKickEvent::process();
/**
* Retransmit event
@ -279,7 +279,7 @@ class NSGigE : public PciDev
txKick();
}
typedef EventWrapper<NSGigE, &NSGigE::txEventTransmit> TxEvent;
friend class TxEvent;
friend void TxEvent::process();
TxEvent txEvent;
void txDump() const;
@ -313,7 +313,7 @@ class NSGigE : public PciDev
void cpuIntrClear();
typedef EventWrapper<NSGigE, &NSGigE::cpuInterrupt> IntrEvent;
friend class IntrEvent;
friend void IntrEvent::process();
IntrEvent *intrEvent;
NSGigEInt *interface;

9
dev/pcidev.hh
View file

@ -78,10 +78,6 @@ class PciConfigData : public SimObject
*/
class PciDev : public DmaDevice
{
protected:
struct Params;
Params *_params;
public:
struct Params
{
@ -110,6 +106,11 @@ class PciDev : public DmaDevice
/** The function number */
uint32_t functionNum;
};
protected:
Params *_params;
public:
const Params *params() const { return _params; }
protected:

44
dev/rtcreg.h Normal file
View file

@ -0,0 +1,44 @@
/*
* Copyright (c) 2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#define RTC_SEC 0x00
#define RTC_SEC_ALRM 0x01
#define RTC_MIN 0x02
#define RTC_MIN_ALRM 0x03
#define RTC_HR 0x04
#define RTC_HR_ALRM 0x05
#define RTC_DOW 0x06
#define RTC_DOM 0x07
#define RTC_MON 0x08
#define RTC_YEAR 0x09
#define RTC_CNTRL_REGA 0x0A
#define RTC_CNTRL_REGB 0x0B
#define RTC_CNTRL_REGC 0x0C
#define RTC_CNTRL_REGD 0x0D

2
dev/simconsole.cc
View file

@ -315,7 +315,7 @@ CREATE_SIM_OBJECT(SimConsole)
{
string filename;
if (!output.isValid()) {
if (filename.empty()) {
filename = getInstanceName();
} else if (append_name) {
filename = (string)output + "." + getInstanceName();

8
dev/sinic.hh
View file

@ -59,7 +59,7 @@ class Base : public PciDev
void cpuIntrClear();
typedef EventWrapper<Base, &Base::cpuInterrupt> IntrEvent;
friend class IntrEvent;
friend void IntrEvent::process();
IntrEvent *intrEvent;
Interface *interface;
@ -155,12 +155,12 @@ class Device : public Base
void rxKick();
Tick rxKickTick;
typedef EventWrapper<Device, &Device::rxKick> RxKickEvent;
friend class RxKickEvent;
friend void RxKickEvent::process();
void txKick();
Tick txKickTick;
typedef EventWrapper<Device, &Device::txKick> TxKickEvent;
friend class TxKickEvent;
friend void TxKickEvent::process();
/**
* Retransmit event
@ -173,7 +173,7 @@ class Device : public Base
txKick();
}
typedef EventWrapper<Device, &Device::txEventTransmit> TxEvent;
friend class TxEvent;
friend void TxEvent::process();
TxEvent txEvent;
void txDump() const;

7
dev/tsunami_cchip.cc
View file

@ -173,6 +173,13 @@ TsunamiCChip::read(MemReqPtr &req, uint8_t *data)
break;
case sizeof(uint32_t):
if (regnum == TSDEV_CC_DRIR) {
warn("accessing DRIR with 32 bit read, "
"hopefully your just reading this for timing");
*(uint64_t*)data = drir;
} else
panic("invalid access size(?) for tsunami register!\n");
return No_Fault;
case sizeof(uint16_t):
case sizeof(uint8_t):
default:

23
dev/tsunami_io.cc
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2004 The Regents of The University of Michigan
* Copyright (c) 2004-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -45,6 +45,7 @@
#include "sim/builder.hh"
#include "dev/tsunami_cchip.hh"
#include "dev/tsunamireg.h"
#include "dev/rtcreg.h"
#include "mem/functional_mem/memory_control.hh"
using namespace std;
@ -217,36 +218,36 @@ TsunamiIO::read(MemReqPtr &req, uint8_t *data)
return No_Fault;
case TSDEV_RTC_DATA:
switch(RTCAddress) {
case RTC_CONTROL_REGISTERA:
case RTC_CNTRL_REGA:
*(uint8_t*)data = uip << 7 | 0x26;
uip = !uip;
return No_Fault;
case RTC_CONTROL_REGISTERB:
case RTC_CNTRL_REGB:
// DM and 24/12 and UIE
*(uint8_t*)data = 0x46;
return No_Fault;
case RTC_CONTROL_REGISTERC:
case RTC_CNTRL_REGC:
// If we want to support RTC user access in linux
// This won't work, but for now it's fine
*(uint8_t*)data = 0x00;
return No_Fault;
case RTC_CONTROL_REGISTERD:
case RTC_CNTRL_REGD:
panic("RTC Control Register D not implemented");
case RTC_SECOND:
case RTC_SEC:
*(uint8_t *)data = tm.tm_sec;
return No_Fault;
case RTC_MINUTE:
case RTC_MIN:
*(uint8_t *)data = tm.tm_min;
return No_Fault;
case RTC_HOUR:
case RTC_HR:
*(uint8_t *)data = tm.tm_hour;
return No_Fault;
case RTC_DAY_OF_WEEK:
case RTC_DOW:
*(uint8_t *)data = tm.tm_wday;
return No_Fault;
case RTC_DAY_OF_MONTH:
case RTC_DOM:
*(uint8_t *)data = tm.tm_mday;
case RTC_MONTH:
case RTC_MON:
*(uint8_t *)data = tm.tm_mon + 1;
return No_Fault;
case RTC_YEAR:

17
dev/tsunamireg.h
View file

@ -122,23 +122,6 @@
#define TSDEV_RTC_ADDR 0x70
#define TSDEV_RTC_DATA 0x71
// RTC defines
#define RTC_SECOND 0 // second of minute [0..59]
#define RTC_SECOND_ALARM 1 // seconds to alarm
#define RTC_MINUTE 2 // minute of hour [0..59]
#define RTC_MINUTE_ALARM 3 // minutes to alarm
#define RTC_HOUR 4 // hour of day [0..23]
#define RTC_HOUR_ALARM 5 // hours to alarm
#define RTC_DAY_OF_WEEK 6 // day of week [1..7]
#define RTC_DAY_OF_MONTH 7 // day of month [1..31]
#define RTC_MONTH 8 // month of year [1..12]
#define RTC_YEAR 9 // year [00..99]
#define RTC_CONTROL_REGISTERA 10 // control register A
#define RTC_CONTROL_REGISTERB 11 // control register B
#define RTC_CONTROL_REGISTERC 12 // control register C
#define RTC_CONTROL_REGISTERD 13 // control register D
#define RTC_REGNUMBER_RTC_CR1 0x6A // control register 1
#define PCHIP_PCI0_MEMORY ULL(0x00000000000)
#define PCHIP_PCI0_IO ULL(0x001FC000000)
#define TSUNAMI_UNCACHABLE_BIT ULL(0x80000000000)

7
kern/linux/linux_syscalls.hh
View file

@ -26,14 +26,15 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __LINUX_SYSCALLS_HH__
#define __LINUX_SYSCALLS_HH__
#ifndef __KERN_LINUX_LINUX_SYSCALLS_HH__
#define __KERN_LINUX_LINUX_SYSCALLS_HH__
#include "kern/linux/linux.hh"
template <class OS>
class SystemCalls;
template <>
class SystemCalls<Linux>
{
public:
@ -322,4 +323,4 @@ class SystemCalls<Linux>
};
#endif // __LINUX_SYSCALLS_HH__
#endif // __KERN_LINUX_LINUX_SYSCALLS_HH__

7
kern/tru64/tru64_syscalls.hh
View file

@ -26,14 +26,15 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __TRU64_SYSCALLS_HH__
#define __TRU64_SYSCALLS_HH__
#ifndef __KERN_TRU64_TRU64_SYSCALLS_HH__
#define __KERN_TRU64_TRU64_SYSCALLS_HH__
#include "kern/tru64/tru64.hh"
template <class OS>
class SystemCalls;
template <>
class SystemCalls<Tru64>
{
public:
@ -355,4 +356,4 @@ class SystemCalls<Tru64>
}
};
#endif // __TRU64_SYSCALLS_HH__
#endif // __KERN_TRU64_TRU64_SYSCALLS_HH__

3
objects/AlphaConsole.mpy
View file

@ -1,8 +1,9 @@
from Device import PioDevice
simobj AlphaConsole(PioDevice):
type = 'AlphaConsole'
cpu = Param.BaseCPU(Super, "Processor")
disk = Param.SimpleDisk("Simple Disk")
num_cpus = Param.Int(1, "Number of CPU's")
num_cpus = Param.Int(1, "Number of CPUs")
sim_console = Param.SimConsole(Super, "The Simulator Console")
system = Param.BaseSystem(Super, "system object")

3
objects/AlphaTLB.mpy
View file

@ -1,9 +1,12 @@
simobj AlphaTLB(SimObject):
type = 'AlphaTLB'
abstract = True
size = Param.Int("TLB size")
simobj AlphaDTB(AlphaTLB):
type = 'AlphaDTB'
size = 64
simobj AlphaITB(AlphaTLB):
type = 'AlphaITB'
size = 48

1
objects/BadDevice.mpy
View file

@ -1,4 +1,5 @@
from Device import PioDevice
simobj BadDevice(PioDevice):
type = 'BadDevice'
devicename = Param.String("Name of device to error on")

3
objects/BaseCPU.mpy
View file

@ -1,4 +1,5 @@
simobj BaseCPU(SimObject):
type = 'BaseCPU'
abstract = True
icache = Param.BaseMem(NULL, "L1 instruction cache object")
dcache = Param.BaseMem(NULL, "L1 data cache object")
@ -18,7 +19,7 @@ simobj BaseCPU(SimObject):
max_loads_any_thread = Param.Counter(0,
"terminate when any thread reaches this load count")
defer_registration = Param.Bool(false,
defer_registration = Param.Bool(False,
"defer registration with system (for sampling)")
def check(self):

18
objects/BaseCache.mpy
View file

@ -1,30 +1,38 @@
from BaseMem import BaseMem
simobj BaseCache(BaseMem):
adaptive_compression = Param.Bool(false,
type = 'BaseCache'
adaptive_compression = Param.Bool(False,
"Use an adaptive compression scheme")
assoc = Param.Int("associativity")
block_size = Param.Int("block size in bytes")
compressed_bus = Param.Bool(false,
compressed_bus = Param.Bool(False,
"This cache connects to a compressed memory")
compression_latency = Param.Int(0,
"Latency in cycles of compression algorithm")
do_copy = Param.Bool(false, "perform fast copies in the cache")
do_copy = Param.Bool(False, "perform fast copies in the cache")
hash_delay = Param.Int(1, "time in cycles of hash access")
in_bus = Param.Bus(NULL, "incoming bus object")
lifo = Param.Bool(False,
"whether this NIC partition should use LIFO repl. policy")
max_miss_count = Param.Counter(0,
"number of misses to handle before calling exit")
mshrs = Param.Int("number of MSHRs (max outstanding requests)")
out_bus = Param.Bus("outgoing bus object")
prioritizeRequests = Param.Bool(false,
prioritizeRequests = Param.Bool(False,
"always service demand misses first")
protocol = Param.CoherenceProtocol(NULL, "coherence protocol to use")
repl = Param.Repl(NULL, "replacement policy")
size = Param.Int("capacity in bytes")
store_compressed = Param.Bool(false,
split = Param.Bool(False, "whether or not this cache is split")
split_size = Param.Int(0,
"How many ways of the cache belong to CPU/LRU partition")
store_compressed = Param.Bool(False,
"Store compressed data in the cache")
subblock_size = Param.Int(0,
"Size of subblock in IIC used for compression")
tgts_per_mshr = Param.Int("max number of accesses per MSHR")
trace_addr = Param.Addr(0, "address to trace")
two_queue = Param.Bool(False,
"whether the lifo should have two queue replacement")
write_buffers = Param.Int(8, "number of write buffers")

3
objects/BaseSystem.mpy
View file

@ -1,4 +1,5 @@
simobj BaseSystem(SimObject):
type = 'BaseSystem'
abstract = True
memctrl = Param.MemoryController(Super, "memory controller")
physmem = Param.PhysicalMemory(Super, "phsyical memory")
@ -10,5 +11,5 @@ simobj BaseSystem(SimObject):
boot_osflags = Param.String("a", "boot flags to pass to the kernel")
system_type = Param.UInt64("Type of system we are emulating")
system_rev = Param.UInt64("Revision of system we are emulating")
bin = Param.Bool(false, "is this system binned")
bin = Param.Bool(False, "is this system binned")
binned_fns = VectorParam.String([], "functions broken down and binned")

1
objects/Bus.mpy
View file

@ -1,5 +1,6 @@
from BaseHier import BaseHier
simobj Bus(BaseHier):
type = 'Bus'
clock_ratio = Param.Int("ratio of CPU to bus frequency")
width = Param.Int("bus width in bytes")

3
objects/CoherenceProtocol.mpy
View file

@ -1,5 +1,6 @@
Coherence = Enum('uni', 'msi', 'mesi', 'mosi', 'moesi')
simobj CoherenceProtocol(SimObject):
do_upgrades = Param.Bool(true, "use upgrade transactions?")
type = 'CoherenceProtocol'
do_upgrades = Param.Bool(True, "use upgrade transactions?")
protocol = Param.Coherence("name of coherence protocol")

6
objects/Device.mpy
View file

@ -11,21 +11,23 @@ from FunctionalMemory import FunctionalMemory
# initialization phase at which point all SimObject pointers will be
# valid.
simobj FooPioDevice(FunctionalMemory):
abstract = True
type = 'PioDevice'
abstract = True
addr = Param.Addr("Device Address")
mmu = Param.MemoryController(Super, "Memory Controller")
io_bus = Param.Bus(NULL, "The IO Bus to attach to")
pio_latency = Param.Tick(1, "Programmed IO latency in bus cycles")
simobj FooDmaDevice(FooPioDevice):
abstract = True
type = 'DmaDevice'
abstract = True
simobj PioDevice(FooPioDevice):
type = 'PioDevice'
abstract = True
platform = Param.Platform(Super, "Platform")
simobj DmaDevice(PioDevice):
type = 'DmaDevice'
abstract = True

6
objects/DiskImage.mpy
View file

@ -1,12 +1,14 @@
simobj DiskImage(SimObject):
type = 'DiskImage'
abstract = True
image_file = Param.String("disk image file")
read_only = Param.Bool(false, "read only image")
read_only = Param.Bool(False, "read only image")
simobj RawDiskImage(DiskImage):
pass
type = 'RawDiskImage'
simobj CowDiskImage(DiskImage):
type = 'CowDiskImage'
child = Param.DiskImage("child image")
table_size = Param.Int(65536, "initial table size")
image_file = ''

23
objects/Ethernet.mpy
View file

@ -2,10 +2,12 @@ from Device import DmaDevice
from Pci import PciDevice
simobj EtherInt(SimObject):
type = 'EtherInt'
abstract = True
peer = Param.EtherInt(NULL, "peer interface")
simobj EtherLink(SimObject):
type = 'EtherLink'
int1 = Param.EtherInt("interface 1")
int2 = Param.EtherInt("interface 2")
delay = Param.Tick(0, "transmit delay of packets in us")
@ -13,31 +15,35 @@ simobj EtherLink(SimObject):
dump = Param.EtherDump(NULL, "dump object")
simobj EtherBus(SimObject):
loopback = Param.Bool(true,
type = 'EtherBus'
loopback = Param.Bool(True,
"send packet back to the interface from which it came")
dump = Param.EtherDump(NULL, "dump object")
speed = Param.UInt64(100000000, "bus speed in bits per second")
simobj EtherTap(EtherInt):
type = 'EtherTap'
bufsz = Param.Int(10000, "tap buffer size")
dump = Param.EtherDump(NULL, "dump object")
port = Param.UInt16(3500, "tap port")
simobj EtherDump(SimObject):
type = 'EtherDump'
file = Param.String("dump file")
simobj EtherDev(DmaDevice):
type = 'EtherDev'
hardware_address = Param.EthernetAddr(NextEthernetAddr,
"Ethernet Hardware Address")
dma_data_free = Param.Bool(false, "DMA of Data is free")
dma_desc_free = Param.Bool(false, "DMA of Descriptors is free")
dma_data_free = Param.Bool(False, "DMA of Data is free")
dma_desc_free = Param.Bool(False, "DMA of Descriptors is free")
dma_read_delay = Param.Tick(0, "fixed delay for dma reads")
dma_read_factor = Param.Tick(0, "multiplier for dma reads")
dma_write_delay = Param.Tick(0, "fixed delay for dma writes")
dma_write_factor = Param.Tick(0, "multiplier for dma writes")
rx_filter = Param.Bool(true, "Enable Receive Filter")
rx_filter = Param.Bool(True, "Enable Receive Filter")
rx_delay = Param.Tick(1000, "Receive Delay")
tx_delay = Param.Tick(1000, "Transmit Delay")
@ -47,17 +53,18 @@ simobj EtherDev(DmaDevice):
tlaser = Param.Turbolaser(Super, "Turbolaser")
simobj NSGigE(PciDevice):
type = 'NSGigE'
hardware_address = Param.EthernetAddr(NextEthernetAddr,
"Ethernet Hardware Address")
dma_data_free = Param.Bool(false, "DMA of Data is free")
dma_desc_free = Param.Bool(false, "DMA of Descriptors is free")
dma_data_free = Param.Bool(False, "DMA of Data is free")
dma_desc_free = Param.Bool(False, "DMA of Descriptors is free")
dma_read_delay = Param.Tick(0, "fixed delay for dma reads")
dma_read_factor = Param.Tick(0, "multiplier for dma reads")
dma_write_delay = Param.Tick(0, "fixed delay for dma writes")
dma_write_factor = Param.Tick(0, "multiplier for dma writes")
rx_filter = Param.Bool(true, "Enable Receive Filter")
rx_filter = Param.Bool(True, "Enable Receive Filter")
rx_delay = Param.Tick(1000, "Receive Delay")
tx_delay = Param.Tick(1000, "Transmit Delay")
@ -69,9 +76,11 @@ simobj NSGigE(PciDevice):
physmem = Param.PhysicalMemory(Super, "Physical Memory")
simobj EtherDevInt(EtherInt):
type = 'EtherDevInt'
device = Param.EtherDev("Ethernet device of this interface")
simobj NSGigEInt(EtherInt):
type = 'NSGigEInt'
device = Param.NSGigE("Ethernet device of this interface")

2
objects/Ide.mpy
View file

@ -3,10 +3,12 @@ from Pci import PciDevice
IdeID = Enum('master', 'slave')
simobj IdeDisk(SimObject):
type = 'IdeDisk'
delay = Param.Tick(1, "Fixed disk delay in microseconds")
driveID = Param.IdeID('master', "Drive ID")
image = Param.DiskImage("Disk image")
physmem = Param.PhysicalMemory(Super, "Physical memory")
simobj IdeController(PciDevice):
type = 'IdeController'
disks = VectorParam.IdeDisk("IDE disks attached to this controller")

1
objects/IntrControl.mpy
View file

@ -1,2 +1,3 @@
simobj IntrControl(SimObject):
type = 'IntrControl'
cpu = Param.BaseCPU(Super, "the cpu")

1
objects/MemTest.mpy
View file

@ -1,4 +1,5 @@
simobj MemTest(SimObject):
type = 'MemTest'
cache = Param.BaseCache("L1 cache")
check_mem = Param.FunctionalMemory("check memory")
main_mem = Param.FunctionalMemory("hierarchical memory")

4
objects/Pci.mpy
View file

@ -1,6 +1,7 @@
from Device import FooPioDevice, DmaDevice
simobj PciConfigData(FooPioDevice):
type = 'PciConfigData'
addr = 0xffffffffffffffffL
VendorID = Param.UInt16("Vendor ID")
DeviceID = Param.UInt16("Device ID")
@ -38,9 +39,10 @@ simobj PciConfigData(FooPioDevice):
MinimumGrant = Param.UInt8(0x00, "Minimum Grant")
simobj PciConfigAll(FooPioDevice):
pass
type = 'PciConfigAll'
simobj PciDevice(DmaDevice):
type = 'PciDevice'
abstract = True
pci_bus = Param.Int("PCI bus")
pci_dev = Param.Int("PCI device number")

1
objects/PhysicalMemory.mpy
View file

@ -1,6 +1,7 @@
from FunctionalMemory import FunctionalMemory
simobj PhysicalMemory(FunctionalMemory):
type = 'PhysicalMemory'
range = Param.AddrRange("Device Address")
file = Param.String('', "memory mapped file")
mmu = Param.MemoryController(Super, "Memory Controller")

1
objects/Platform.mpy
View file

@ -1,4 +1,5 @@
simobj Platform(SimObject):
type = 'Platform'
abstract = True
interrupt_frequency = Param.Tick(1200, "frequency of interrupts")
intrctrl = Param.IntrControl(Super, "interrupt controller")

3
objects/Process.mpy
View file

@ -1,12 +1,15 @@
simobj Process(SimObject):
type = 'Process'
abstract = True
output = Param.String('cout', 'filename for stdout/stderr')
simobj LiveProcess(Process):
type = 'LiveProcess'
cmd = VectorParam.String("command line (executable plus arguments)")
env = VectorParam.String('', "environment settings")
input = Param.String('cin', "filename for stdin")
simobj EioProcess(Process):
type = 'EioProcess'
chkpt = Param.String('', "EIO checkpoint file name (optional)")
file = Param.String("EIO trace file name")

2
objects/Repl.mpy
View file

@ -1,7 +1,9 @@
simobj Repl(SimObject):
type = 'Repl'
abstract = True
simobj GenRepl(Repl):
type = 'GenRepl'
fresh_res = Param.Int("associativity")
num_pools = Param.Int("capacity in bytes")
pool_res = Param.Int("block size in bytes")

3
objects/Root.mpy
View file

@ -1,10 +1,11 @@
from HierParams import HierParams
simobj Root(SimObject):
type = 'Root'
frequency = Param.Tick(200000000, "tick frequency")
output_dir = Param.String('.', "directory to output data to")
output_file = Param.String('cout', "file to dump simulator output to")
config_output_file = Param.String('m5config.out',
"file to dump simulator config to")
full_system = Param.Bool("Full system simulation?")
hier = HierParams(do_data = false, do_events = true)
hier = HierParams(do_data = False, do_events = True)
checkpoint = Param.String('', "Checkpoint file")

6
objects/SimConsole.mpy
View file

@ -1,9 +1,11 @@
simobj ConsoleListener(SimObject):
type = 'ConsoleListener'
port = Param.UInt16(3456, "listen port")
simobj SimConsole(SimObject):
append_name = Param.Bool(true, "append name() to filename")
type = 'SimConsole'
append_name = Param.Bool(True, "append name() to filename")
intr_control = Param.IntrControl(Super, "interrupt controller")
listener = Param.ConsoleListener("console listener")
number = Param.Int(0, "console number")
output = Param.String("", "file to dump output to")
output = Param.String('', "file to dump output to")

1
objects/SimpleDisk.mpy
View file

@ -1,3 +1,4 @@
simobj SimpleDisk(SimObject):
type = 'SimpleDisk'
disk = Param.DiskImage("Disk Image")
physmem = Param.PhysicalMemory(Super, "Physical Memory")

6
objects/Tsunami.mpy
View file

@ -2,20 +2,24 @@ from Device import FooPioDevice
from Platform import Platform
simobj Tsunami(Platform):
type = 'Tsunami'
pciconfig = Param.PciConfigAll("PCI configuration")
system = Param.BaseSystem(Super, "system")
interrupt_frequency = Param.Int(1024, "frequency of interrupts")
simobj TsunamiCChip(FooPioDevice):
type = 'TsunamiCChip'
tsunami = Param.Tsunami(Super, "Tsunami")
simobj TsunamiFake(FooPioDevice):
pass
type = 'TsunamiFake'
simobj TsunamiIO(FooPioDevice):
type = 'TsunamiIO'
time = Param.UInt64(1136073600,
"System time to use (0 for actual time, default is 1/1/06)")
tsunami = Param.Tsunami(Super, "Tsunami")
simobj TsunamiPChip(FooPioDevice):
type = 'TsunamiPChip'
tsunami = Param.Tsunami(Super, "Tsunami")

1
objects/Uart.mpy
View file

@ -1,5 +1,6 @@
from Device import PioDevice
simobj Uart(PioDevice):
type = 'Uart'
console = Param.SimConsole(Super, "The console")
size = Param.Addr(0x8, "Device size")

34
sim/eventq.hh
View file

@ -30,8 +30,8 @@
* EventQueue interfaces
*/
#ifndef __EVENTQ_HH__
#define __EVENTQ_HH__
#ifndef __SIM_EVENTQ_HH__
#define __SIM_EVENTQ_HH__
#include <assert.h>
@ -43,11 +43,24 @@
#include "sim/host.hh" // for Tick
#include "base/fast_alloc.hh"
#include "sim/serialize.hh"
#include "base/trace.hh"
#include "sim/serialize.hh"
class EventQueue; // forward declaration
//////////////////////
//
// Main Event Queue
//
// Events on this queue are processed at the *beginning* of each
// cycle, before the pipeline simulation is performed.
//
// defined in eventq.cc
//
//////////////////////
extern EventQueue mainEventQueue;
/*
* An item on an event queue. The action caused by a given
* event is specified by deriving a subclass and overriding the
@ -228,7 +241,7 @@ DelayFunction(Tick when, T *object)
public:
DelayEvent(Tick when, T *o)
: Event(&mainEventQueue), object(o)
{ setFlags(AutoDestroy); schedule(when); }
{ setFlags(this->AutoDestroy); schedule(when); }
void process() { (object->*F)(); }
const char *description() { return "delay"; }
};
@ -386,16 +399,5 @@ EventQueue::reschedule(Event *event)
}
//////////////////////
//
// Main Event Queue
//
// Events on this queue are processed at the *beginning* of each
// cycle, before the pipeline simulation is performed.
//
// defined in eventq.cc
//
//////////////////////
extern EventQueue mainEventQueue;
#endif // __EVENTQ_HH__
#endif // __SIM_EVENTQ_HH__

8
sim/param.cc
View file

@ -493,11 +493,11 @@ EnumVectorParam<Map>::showType(ostream &os) const
showEnumType(os, map, num_values);
}
template EnumParam<const char *>;
template EnumVectorParam<const char *>;
template class EnumParam<const char *>;
template class EnumVectorParam<const char *>;
template EnumParam<EnumParamMap>;
template EnumVectorParam<EnumParamMap>;
template class EnumParam<EnumParamMap>;
template class EnumVectorParam<EnumParamMap>;
////////////////////////////////////////////////////////////////////////
//

9
sim/param.hh
View file

@ -26,9 +26,10 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __PARAM_HH__
#define __PARAM_HH__
#ifndef __SIM_PARAM_HH__
#define __SIM_PARAM_HH__
#include <iostream>
#include <list>
#include <string>
#include <vector>
@ -524,7 +525,7 @@ class MappedEnumParam : public EnumParam<EnumParamMap>
{
if (!isValid())
die("not found");
return (ENUM)value[n];
return (ENUM)value[this->n];
}
};
@ -782,4 +783,4 @@ SimObjectVectorParam<OBJ_CLASS *>::showType(std::ostream &os) const \
template <class T> bool parseParam(const std::string &str, T &data);
template <class T> void showParam(std::ostream &os, const T &data);
#endif // _PARAM_HH
#endif // _SIM_PARAM_HH_

15
sim/pyconfig/SConscript
View file

@ -28,14 +28,15 @@
import os, os.path, re
def WriteEmbeddedPyFile(target, source, path, name, ext):
def WriteEmbeddedPyFile(target, source, path, name, ext, filename):
if isinstance(source, str):
source = file(source, 'r')
if isinstance(target, str):
target = file(target, 'w')
print >>target, "AddModule(%s, %s, %s, '''\\" % (`path`, `name`, `ext`)
print >>target, "AddModule(%s, %s, %s, %s, '''\\" % \
(`path`, `name`, `ext`, `filename`)
for line in source:
line = line
@ -105,7 +106,7 @@ def MakeEmbeddedPyFile(target, source, env):
name,ext = pyfile.split('.')
if name == '__init__':
node['.hasinit'] = True
node[pyfile] = (src,name,ext)
node[pyfile] = (src,name,ext,src)
done = False
while not done:
@ -136,12 +137,12 @@ def MakeEmbeddedPyFile(target, source, env):
raise NameError, 'package directory missing __init__.py'
populate(entry, path + [ name ])
else:
pyfile,name,ext = entry
files.append((pyfile, path, name, ext))
pyfile,name,ext,filename = entry
files.append((pyfile, path, name, ext, filename))
populate(tree)
for pyfile, path, name, ext in files:
WriteEmbeddedPyFile(target, pyfile, path, name, ext)
for pyfile, path, name, ext, filename in files:
WriteEmbeddedPyFile(target, pyfile, path, name, ext, filename)
CFileCounter = 0
def MakePythonCFile(target, source, env):

106
sim/pyconfig/m5config.py
View file

@ -26,14 +26,14 @@
from __future__ import generators
import os, re, sys, types
noDot = False
try:
import pydot
except:
noDot = True
env = {}
env.update(os.environ)
def defined(key):
return env.has_key(key)
def define(key, value = True):
env[key] = value
def panic(*args, **kwargs):
sys.exit(*args, **kwargs)
@ -59,9 +59,6 @@ class Singleton(type):
cls._instance = super(Singleton, cls).__call__(*args, **kwargs)
return cls._instance
if os.environ.has_key('FULL_SYSTEM'):
FULL_SYSTEM = True
#####################################################################
#
# M5 Python Configuration Utility
@ -216,6 +213,10 @@ def isParamContext(value):
return False
class_decorator = '_M5M5_SIMOBJECT_'
expr_decorator = '_M5M5_EXPRESSION_'
dot_decorator = '_M5M5_DOT_'
# The metaclass for ConfigNode (and thus for everything that derives
# from ConfigNode, including SimObject). This class controls how new
# classes that derive from ConfigNode are instantiated, and provides
@ -225,7 +226,6 @@ def isParamContext(value):
class MetaConfigNode(type):
keywords = { 'abstract' : types.BooleanType,
'check' : types.FunctionType,
'_init' : types.FunctionType,
'type' : (types.NoneType, types.StringType) }
# __new__ is called before __init__, and is where the statements
@ -241,6 +241,11 @@ class MetaConfigNode(type):
'_disable' : {} }
for key,val in dict.items():
del dict[key]
if key.startswith(expr_decorator):
key = key[len(expr_decorator):]
if mcls.keywords.has_key(key):
if not isinstance(val, mcls.keywords[key]):
raise TypeError, \
@ -250,11 +255,9 @@ class MetaConfigNode(type):
if isinstance(val, types.FunctionType):
val = classmethod(val)
priv[key] = val
del dict[key]
elif key.startswith('_'):
priv[key] = val
del dict[key]
elif not isNullPointer(val) and isConfigNode(val):
dict[key] = val()
@ -262,19 +265,22 @@ class MetaConfigNode(type):
elif isSimObjSequence(val):
dict[key] = [ v() for v in val ]
else:
dict[key] = val
# If your parent has a value in it that's a config node, clone it.
for base in bases:
if not isConfigNode(base):
continue
for name,value in base._values.iteritems():
if dict.has_key(name):
for key,value in base._values.iteritems():
if dict.has_key(key):
continue
if isConfigNode(value):
priv['_values'][name] = value()
priv['_values'][key] = value()
elif isSimObjSequence(value):
priv['_values'][name] = [ val() for val in value ]
priv['_values'][key] = [ val() for val in value ]
# entries left in dict will get passed to __init__, where we'll
# deal with them as params.
@ -288,12 +294,12 @@ class MetaConfigNode(type):
cls._bases = [c for c in cls.__mro__ if isConfigNode(c)]
# initialize attributes with values from class definition
for pname,value in dict.iteritems():
setattr(cls, pname, value)
if hasattr(cls, '_init'):
cls._init()
del cls._init
for key,value in dict.iteritems():
key = key.split(dot_decorator)
c = cls
for item in key[:-1]:
c = getattr(c, item)
setattr(c, key[-1], value)
def _isvalue(cls, name):
for c in cls._bases:
@ -385,7 +391,6 @@ class MetaConfigNode(type):
raise AttributeError, \
"object '%s' has no attribute '%s'" % (cls.__name__, cls)
# Set attribute (called on foo.attr = value when foo is an
# instance of class cls).
def __setattr__(cls, attr, value):
@ -657,7 +662,7 @@ class Node(object):
% (self.name, ptype, value._path)
found, done = obj.find(ptype, value._path)
if isinstance(found, Proxy):
done = false
done = False
obj = obj.parent
return found
@ -715,6 +720,48 @@ class Node(object):
for c in self.children:
c.display()
# print type and parameter values to .ini file
def outputDot(self, dot):
label = "{%s|" % self.path
if isSimObject(self.realtype):
label += '%s|' % self.type
if self.children:
# instantiate children in same order they were added for
# backward compatibility (else we can end up with cpu1
# before cpu0).
for c in self.children:
dot.add_edge(pydot.Edge(self.path,c.path, style="bold"))
simobjs = []
for param in self.params:
try:
if param.value is None:
raise AttributeError, 'Parameter with no value'
value = param.convert(param.value)
string = param.string(value)
except:
print 'exception in %s:%s' % (self.name, param.name)
raise
ptype = eval(param.ptype)
if isConfigNode(ptype) and string != "Null":
simobjs.append(string)
else:
label += '%s = %s\\n' % (param.name, string)
for so in simobjs:
label += "|<%s> %s" % (so, so)
dot.add_edge(pydot.Edge("%s:%s" % (self.path, so), so, tailport="w"))
label += '}'
dot.add_node(pydot.Node(self.path,shape="Mrecord",label=label))
# recursively dump out children
for c in self.children:
c.outputDot(dot)
def _string(cls, value):
if not isinstance(value, Node):
raise AttributeError, 'expecting %s got %s' % (Node, value)
@ -1212,10 +1259,6 @@ class Enum(type):
# "Constants"... handy aliases for various values.
#
# For compatibility with C++ bool constants.
false = False
true = True
# Some memory range specifications use this as a default upper bound.
MAX_ADDR = Addr._max
MaxTick = Tick._max
@ -1251,6 +1294,15 @@ def instantiate(root):
instance = root.instantiate('root')
instance.fixup()
instance.display()
if not noDot:
dot = pydot.Dot()
instance.outputDot(dot)
dot.orientation = "portrait"
dot.size = "8.5,11"
dot.ranksep="equally"
dot.rank="samerank"
dot.write("config.dot")
dot.write_ps("config.ps")
from objects import *

1
sim/serialize.cc
View file

@ -29,6 +29,7 @@
#include <sys/time.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <errno.h>
#include <fstream>
#include <list>

24
sim/startup.cc
View file

@ -29,20 +29,32 @@
#include <list>
#include "base/misc.hh"
#include "sim/startup.hh"
#include "sim/debug.hh"
#include "sim/startup.hh"
typedef std::list<StartupCallback *> startupq_t;
startupq_t &startupq() { static startupq_t queue; return queue; }
StartupCallback::StartupCallback() { startupq().push_back(this); }
StartupCallback::~StartupCallback() { startupq().remove(this); }
startupq_t *startupq = NULL;
StartupCallback::StartupCallback()
{
if (startupq == NULL)
startupq = new startupq_t;
startupq->push_back(this);
}
StartupCallback::~StartupCallback()
{
startupq->remove(this);
}
void StartupCallback::startup() { }
void
SimStartup()
{
startupq_t::iterator i = startupq().begin();
startupq_t::iterator end = startupq().end();
startupq_t::iterator i = startupq->begin();
startupq_t::iterator end = startupq->end();
while (i != end) {
(*i)->startup();

84
sim/syscall_emul.hh
View file

@ -26,8 +26,8 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __SYSCALL_EMUL_HH__
#define __SYSCALL_EMUL_HH__
#ifndef __SIM_SYSCALL_EMUL_HH__
#define __SIM_SYSCALL_EMUL_HH__
///
/// @file syscall_emul.hh
@ -35,14 +35,16 @@
/// This file defines objects used to emulate syscalls from the target
/// application on the host machine.
#include <errno.h>
#include <string>
#include "base/intmath.hh" // for RoundUp
#include "targetarch/isa_traits.hh" // for Addr
#include "mem/functional_mem/functional_memory.hh"
#include "targetarch/isa_traits.hh" // for Addr
class Process;
class ExecContext;
#include "base/trace.hh"
#include "cpu/exec_context.hh"
#include "sim/process.hh"
///
/// System call descriptor.
@ -197,6 +199,36 @@ int unlinkFunc(SyscallDesc *desc, int num, Process *p, ExecContext *xc);
/// Target rename() handler.
int renameFunc(SyscallDesc *desc, int num, Process *p, ExecContext *xc);
/// This struct is used to build an target-OS-dependent table that
/// maps the target's open() flags to the host open() flags.
struct OpenFlagTransTable {
int tgtFlag; //!< Target system flag value.
int hostFlag; //!< Corresponding host system flag value.
};
/// A readable name for 1,000,000, for converting microseconds to seconds.
const int one_million = 1000000;
/// Approximate seconds since the epoch (1/1/1970). About a billion,
/// by my reckoning. We want to keep this a constant (not use the
/// real-world time) to keep simulations repeatable.
const unsigned seconds_since_epoch = 1000000000;
/// Helper function to convert current elapsed time to seconds and
/// microseconds.
template <class T1, class T2>
void
getElapsedTime(T1 &sec, T2 &usec)
{
int cycles_per_usec = ticksPerSecond / one_million;
int elapsed_usecs = curTick / cycles_per_usec;
sec = elapsed_usecs / one_million;
usec = elapsed_usecs % one_million;
}
//////////////////////////////////////////////////////////////////////
//
// The following emulation functions are generic, but need to be
@ -238,14 +270,6 @@ ioctlFunc(SyscallDesc *desc, int callnum, Process *process,
}
}
/// This struct is used to build an target-OS-dependent table that
/// maps the target's open() flags to the host open() flags.
struct OpenFlagTransTable {
int tgtFlag; //!< Target system flag value.
int hostFlag; //!< Corresponding host system flag value.
};
/// Target open() handler.
template <class OS>
int
@ -260,7 +284,7 @@ openFunc(SyscallDesc *desc, int callnum, Process *process,
if (path == "/dev/sysdev0") {
// This is a memory-mapped high-resolution timer device on Alpha.
// We don't support it, so just punt.
DCOUT(SyscallWarnings) << "Ignoring open(" << path << ", ...)" << endl;
DCOUT(SyscallWarnings) << "Ignoring open(" << path << ", ...)" << std::endl;
return -ENOENT;
}
@ -278,7 +302,7 @@ openFunc(SyscallDesc *desc, int callnum, Process *process,
// any target flags left?
if (tgtFlags != 0)
cerr << "Syscall: open: cannot decode flags: " << tgtFlags << endl;
std::cerr << "Syscall: open: cannot decode flags: " << tgtFlags << std::endl;
#ifdef __CYGWIN32__
hostFlags |= O_BINARY;
@ -414,7 +438,7 @@ getrlimitFunc(SyscallDesc *desc, int callnum, Process *process,
break;
default:
cerr << "getrlimitFunc: unimplemented resource " << resource << endl;
std::cerr << "getrlimitFunc: unimplemented resource " << resource << std::endl;
abort();
break;
}
@ -423,28 +447,6 @@ getrlimitFunc(SyscallDesc *desc, int callnum, Process *process,
return 0;
}
/// A readable name for 1,000,000, for converting microseconds to seconds.
const int one_million = 1000000;
/// Approximate seconds since the epoch (1/1/1970). About a billion,
/// by my reckoning. We want to keep this a constant (not use the
/// real-world time) to keep simulations repeatable.
const unsigned seconds_since_epoch = 1000000000;
/// Helper function to convert current elapsed time to seconds and
/// microseconds.
template <class T1, class T2>
void
getElapsedTime(T1 &sec, T2 &usec)
{
int cycles_per_usec = ticksPerSecond / one_million;
int elapsed_usecs = curTick / cycles_per_usec;
sec = elapsed_usecs / one_million;
usec = elapsed_usecs % one_million;
}
/// Target gettimeofday() handler.
template <class OS>
int
@ -476,7 +478,7 @@ getrusageFunc(SyscallDesc *desc, int callnum, Process *process,
// plow ahead
DCOUT(SyscallWarnings)
<< "Warning: getrusage() only supports RUSAGE_SELF."
<< " Parameter " << who << " ignored." << endl;
<< " Parameter " << who << " ignored." << std::endl;
}
getElapsedTime(rup->ru_utime.tv_sec, rup->ru_utime.tv_usec);
@ -502,6 +504,4 @@ getrusageFunc(SyscallDesc *desc, int callnum, Process *process,
return 0;
}
#endif // __SYSCALL_EMUL_HH__
#endif // __SIM_SYSCALL_EMUL_HH__

11
sim/universe.cc
View file

@ -28,6 +28,7 @@
#include <sys/types.h>
#include <sys/stat.h>
#include <errno.h>
#include <cstring>
#include <fstream>
@ -142,7 +143,8 @@ CREATE_SIM_OBJECT(Root)
__ticksPerNS = freq / 1.0e9;
__ticksPerPS = freq / 1.0e12;
if (output_dir.isValid()) {
outputDirectory = output_dir;
if (!outputDirectory.empty()) {
outputDirectory = output_dir;
// guarantee that directory ends with a '/'
@ -158,9 +160,10 @@ CREATE_SIM_OBJECT(Root)
}
outputStream = makeOutputStream(output_file);
configStream = config_output_file.isValid()
? makeOutputStream(config_output_file)
: outputStream;
configStream = outputStream;
string cof = config_output_file;
if (!cof.empty())
configStream = makeOutputStream(cof);
return root;
}

12
test/genini.py
View file

@ -26,12 +26,14 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import getopt, os, os.path, sys
from os.path import join as joinpath, realpath
sys.path.append('..')
sys.path.append('../configs/kernel')
sys.path.append('../sim/pyconfig')
mypath = sys.path[0]
sys.path.append(joinpath(mypath, '..'))
sys.path.append(joinpath(mypath, '../configs/kernel'))
sys.path.append(joinpath(mypath, '../sim/pyconfig'))
from importer import mpy_exec, AddToPath
from importer import mpy_exec, mpy_execfile, AddToPath
from m5config import *
try:
@ -51,7 +53,7 @@ except getopt.GetoptError:
for arg in args:
AddToPath(os.path.dirname(arg))
mpy_exec(file(arg, 'r'), globals())
mpy_execfile(arg)
if globals().has_key('root') and isinstance(root, type) \
and issubclass(root, Root):

183
util/pbs/job.py Executable file
View file

@ -0,0 +1,183 @@
#!/usr/bin/env python
# Copyright (c) 2005 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Nathan Binkert
# Steve Reinhardt
# Ali Saidi
import os, os.path, shutil, signal, socket, sys, time
from os import environ as env
from os.path import join as joinpath, expanduser
class rsync:
def __init__(self):
self.sudo = False
self.rsync = 'rsync'
self.compress = False
self.archive = True
self.delete = False
self.options = ''
def do(self, src, dst):
args = []
if self.sudo:
args.append('sudo')
args.append(self.rsync)
if (self.archive):
args.append('-a')
if (self.compress):
args.append('-z')
if (self.delete):
args.append('--delete')
if len(self.options):
args.append(self.options)
args.append(src)
args.append(dst)
return os.spawnvp(os.P_WAIT, args[0], args)
def cleandir(dir):
for root, dirs, files in os.walk(dir, False):
for name in files:
os.remove(joinpath(root, name))
for name in dirs:
os.rmdir(joinpath(root, name))
def date():
return time.strftime('%a %b %e %H:%M:%S %Z %Y', time.localtime())
def remfile(file):
if os.path.isfile(file):
os.unlink(file)
def readval(filename):
file = open(filename, 'r')
value = file.readline().strip()
file.close()
return value
if __name__ == '__main__':
rootdir = env.setdefault('ROOTDIR', os.getcwd())
jobid = env['PBS_JOBID']
jobname = env['PBS_JOBNAME']
jobdir = joinpath(rootdir, jobname)
basedir = joinpath(rootdir, 'Base')
user = env['USER']
env['POOLJOB'] = 'True'
env['OUTPUT_DIR'] = jobdir
env['JOBFILE'] = joinpath(basedir, 'test.py')
env['JOBNAME'] = jobname
def echofile(filename, string):
try:
f = file(joinpath(jobdir, filename), 'w')
print >>f, string
f.flush()
f.close()
except IOError,e:
sys.exit(e)
if os.path.isdir("/work"):
workbase = "/work"
else:
workbase = "/tmp/"
workdir = joinpath(workbase, '%s.%s' % (user, jobid))
os.umask(0022)
echofile('.start', date())
echofile('.jobid', jobid)
echofile('.host', socket.gethostname())
if os.path.isdir(workdir):
cleandir(workdir)
else:
os.mkdir(workdir)
if os.path.isdir('/z/dist'):
sync = rsync()
sync.delete = True
sync.sudo = True
sync.do('poolfs::dist/m5/', '/z/dist/m5/')
try:
os.chdir(workdir)
except OSError,e:
sys.exit(e)
os.symlink(joinpath(jobdir, 'output'), 'status.out')
args = [ joinpath(basedir, 'm5'), joinpath(basedir, 'run.mpy') ]
if not len(args):
sys.exit("no arguments")
print 'starting job... %s' % date()
print ' '.join(args)
print
sys.stdout.flush()
childpid = os.fork()
if not childpid:
# Execute command
sys.stdin.close()
fd = os.open(joinpath(jobdir, "output"),
os.O_WRONLY | os.O_CREAT | os.O_TRUNC)
os.dup2(fd, sys.stdout.fileno())
os.dup2(fd, sys.stderr.fileno())
os.execvp(args[0], args)
def handler(signum, frame):
if childpid != 0:
os.kill(childpid, signum)
signal.signal(signal.SIGHUP, handler)
signal.signal(signal.SIGINT, handler)
signal.signal(signal.SIGQUIT, handler)
signal.signal(signal.SIGTERM, handler)
signal.signal(signal.SIGSTOP, handler)
signal.signal(signal.SIGCONT, handler)
signal.signal(signal.SIGUSR1, handler)
signal.signal(signal.SIGUSR2, handler)
done = 0
while not done:
try:
thepid,ec = os.waitpid(childpid, 0)
if ec:
print 'Exit code ', ec
echofile('.failure', date())
else:
echofile('.success', date())
done = 1
except OSError:
pass
print '\njob complete... %s' % date()
echofile('.stop', date())

83
util/pbs/jobfile.py Normal file
View file

@ -0,0 +1,83 @@
# Copyright (c) 2005 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Nathan Binkert
from os.path import expanduser
def crossproduct(options):
number = len(options)
indexes = [ 0 ] * number
maxes = [ len(opt) for opt in options ]
def next():
for i in xrange(number - 1, -1, -1):
indexes[i] += 1
if indexes[i] < maxes[i]:
return False
indexes[i] = 0
return True
done = False
while not done:
result = []
for i in xrange(number):
result.append(options[i][indexes[i]])
yield result
done = next()
class JobFile(object):
def __init__(self, file):
self.data = {}
execfile(expanduser(file), self.data)
self.options = self.data['options']
self.environment = self.data['environment']
self.jobinfo = {}
self.jobs = []
for job in crossproduct(self.options):
jobname = '.'.join([ id[0] for id in job ])
self.jobs.append(jobname)
list = []
for info in job:
for item in info[1:]:
list.append(item)
self.jobinfo[jobname] = list
def env(self, jobname):
env = {}
for key,val in self.jobinfo[jobname]:
env[key] = val
for key,val in self.environment:
env[key] = val
return env
def printinfo(self, jobname):
print '%s:' % jobname
for key,val in self.jobinfo[jobname]:
print ' %s = %s' % (key, val)
for key,val in self.environment:
print ' %s = %s' % (key, val)

126
util/pbs/pbs.py Executable file
View file

@ -0,0 +1,126 @@
# Copyright (c) 2005 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Nathan Binkert
import os, re, sys
def ssh(host, script, tty = False, user = ''):
args = [ 'ssh', '-x' ]
if user:
args.append('-l' + user)
if tty:
args.append('-t')
args.append(host)
args.append(script)
return os.spawnvp(os.P_WAIT, args[0], args)
class qsub:
def __init__(self):
self.hold = False
self.join = False
self.keep_stdout = False
self.keep_stderr = False
self.node_type = ''
self.mail_abort = False
self.mail_begin = False
self.mail_end = False
self.name = ''
self.stdout = ''
self.priority = 0
self.queue = ''
self.pbshost = ''
self.qsub = 'qsub'
self.env = {}
self.onlyecho = False
self.verbose = False
def do(self, script, ):
args = [self.qsub]
if self.env:
arg = '-v'
arg += ','.join([ '%s=%s' % i for i in self.env.iteritems() ])
args.append(arg)
if self.hold:
args.append('-h')
if len(self.stdout):
args.append('-olocalhost:' + self.stdout)
if self.keep_stdout and self.keep_stderr:
args.append('-koe')
elif self.keep_stdout:
args.append('-ko')
elif self.keep_stderr:
args.append('-ke')
else:
args.append('-kn')
if self.join:
args.append('-joe')
if len(self.node_type):
args.append('-lnodes=' + self.node_type)
if self.mail_abort or self.mail_begin or self.mail_end:
flags = ''
if self.mail_abort:
flags.append('a')
if self.mail_begin:
flags.append('b')
if self.mail_end:
flags.append('e')
if len(flags):
args.append('-m ' + flags)
if len(self.name):
args.append("-N%s" % self.name)
if self.priority != 0:
args.append('-p' + self.priority)
if len(self.queue):
args.append('-q' + self.queue)
args.append(script)
if self.verbose or self.onlyecho:
print >>sys.stderr, 'PBS Command: ', ' '.join(args)
if self.onlyecho:
return 0
print >>sys.stderr, 'PBS Jobid: ',
ec = os.spawnvp(os.P_WAIT, args[0], args)
if ec != 0 and len(self.pbshost):
ec = ssh(self.pbshost, ' '.join(args))
return ec

169
util/pbs/send.py Executable file
View file

@ -0,0 +1,169 @@
#!/usr/bin/env python
# Copyright (c) 2005 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Ali Saidi
# Nathan Binkert
import os, os.path, re, sys
from os import environ as env, listdir
from os.path import basename, isdir, isfile, islink, join as joinpath
from filecmp import cmp as filecmp
from shutil import copyfile
progname = basename(sys.argv[0])
usage = """\
Usage:
%(progname)s [-c] [-e] [-f] [-q queue] [-v] <regexp>
-c clean directory if job can be run
-e only echo pbs command info, don't actually send the job
-f force the job to run regardless of state
-q <queue> submit job to the named queue
-v be verbose
%(progname)s -l [-v] <regexp>
-l list job names, don't submit
-v be verbose (list job parameters)
%(progname)s -h
-h display this help
""" % locals()
try:
import getopt
opts, args = getopt.getopt(sys.argv[1:], '-cefhlq:v')
except getopt.GetoptError:
sys.exit(usage)
clean = False
onlyecho = False
exprs = []
force = False
listonly = False
queue = ''
verbose = False
for o,a in opts:
if o == '-c':
clean = True
if o == '-e':
onlyecho = True
if o == '-f':
force = True
if o == '-h':
print usage
sys.exit(0)
if o == '-l':
listonly = True
if o == '-q':
queue = a
if o == '-v':
verbose = True
for arg in args:
exprs.append(re.compile(arg))
if not listonly and not onlyecho and isdir('Link'):
print 'Checking for outdated files in Link directory'
entries = listdir('Link')
for entry in entries:
link = joinpath('Link', entry)
if not islink(link):
continue
base = joinpath('Base', entry)
if not isfile(base) or not filecmp(link, base):
print '%s is different than source %s...copying' % (base, link)
copyfile(link, base)
import job, jobfile, pbs
test = jobfile.JobFile(joinpath('Base', 'test.py'))
joblist = []
for jobname in test.jobs:
if not exprs:
joblist.append(jobname)
continue
for expr in exprs:
if expr.match(jobname):
joblist.append(jobname)
break
if listonly:
if verbose:
for jobname in joblist:
test.printinfo(jobname)
else:
for jobname in joblist:
print jobname
sys.exit(0)
if not onlyecho:
jl = []
for jobname in joblist:
if os.path.exists(jobname):
if not force:
if os.path.isfile(joinpath(jobname, '.success')):
continue
if os.path.isfile(joinpath(jobname, '.start')) and \
not os.path.isfile(joinpath(jobname, '.stop')):
continue
if not clean:
sys.exit('job directory not clean!')
job.cleandir(jobname)
else:
os.mkdir(jobname)
jl.append(jobname)
joblist = jl
rootdir = re.sub(r'^/\.automount/', r'/n/', os.getcwd())
for jobname in joblist:
jobdir = joinpath(rootdir, jobname)
if not onlyecho and not os.path.isdir(jobdir):
sys.exit('%s is not a directory. Cannot build job' % jobdir)
print >>sys.stderr, 'Job name: %s' % jobname
print >>sys.stderr, 'Job directory: %s' % jobdir
qsub = pbs.qsub()
qsub.pbshost = 'simpool.eecs.umich.edu'
qsub.stdout = joinpath(jobdir, 'jobout')
qsub.name = jobname
qsub.join = True
qsub.node_type = 'FAST'
qsub.onlyecho = onlyecho
qsub.env['ROOTDIR'] = rootdir
qsub.verbose = verbose
if len(queue):
qsub.queue = queue
qsub.do(joinpath('Base', 'job.py'))
print >>sys.stderr, ''

2
util/stats/info.py
View file

@ -324,7 +324,7 @@ class Vector(Statistic,FormulaStat):
def __eq__(self, other):
if issequence(self.value) != issequence(other.value):
return false
return False
if issequence(self.value):
if len(self.value) != len(other.value):

4
util/tracediff
View file

@ -1,5 +1,5 @@
#! /usr/bin/env perl
# Copyright (c) 2003-2004 The Regents of The University of Michigan
# Copyright (c) 2003-2005 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
@ -53,7 +53,7 @@ $simargs = '"' . join('" "', @ARGV) . '"';
# Redirect config output to cout so that gets diffed too (in case
# that's the source of the problem).
$simargs += " --Universe:config_output_file=cout";
$simargs .= " --root:config_output_file=cout";
$cmd1 = "$sim1 $simargs --stats:text_file=tracediff-$$-1.stats 2>&1 |";
$cmd2 = "$sim2 $simargs --stats:text_file=tracediff-$$-2.stats 2>&1 |";