Renamed OpClass enum members: they all end in 'Op' now.
Got rid of two inconsistent sets of strings that corresponded to this enum, and replaced with a single set that clearly matches the enum names. arch/alpha/isa_desc: arch/isa_parser.py: cpu/full_cpu/op_class.hh: Renamed OpClass enum members. --HG-- extra : convert_revision : bf596f7568a20b2e77c07ac349f253135141aef4
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@ -811,7 +811,7 @@ output header {{
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public:
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/// Constructor
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EACompBase(MachInst machInst)
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: AlphaStaticInst("(eacomp)", machInst, IntALU)
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: AlphaStaticInst("(eacomp)", machInst, IntAluOp)
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{
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}
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@ -1072,7 +1072,7 @@ def format LoadOrPrefetch(ea_code, memacc_code, *pf_flags) {{
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# Declare the prefetch instruction object.
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# convert flags from tuple to list to make them mutable
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pf_flags = list(pf_flags) + ['IsMemRef', 'IsLoad', 'IsDataPrefetch', 'RdPort']
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pf_flags = list(pf_flags) + ['IsMemRef', 'IsLoad', 'IsDataPrefetch', 'MemReadOp']
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(pf_header_output, pf_decoder_output, _, pf_exec_output) = \
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LoadStoreBase(name, Name + 'Prefetch', ea_code, '',
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@ -2083,13 +2083,13 @@ decode OPCODE default Unknown::unknown() {
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}
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0x13: decode INTFUNC { // integer multiplies
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0x00: mull({{ Rc.sl = Ra.sl * Rb_or_imm.sl; }}, IntMULT);
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0x20: mulq({{ Rc = Ra * Rb_or_imm; }}, IntMULT);
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0x00: mull({{ Rc.sl = Ra.sl * Rb_or_imm.sl; }}, IntMultOp);
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0x20: mulq({{ Rc = Ra * Rb_or_imm; }}, IntMultOp);
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0x30: umulh({{
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uint64_t hi, lo;
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mul128(Ra, Rb_or_imm, hi, lo);
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Rc = hi;
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}}, IntMULT);
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}}, IntMultOp);
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0x40: mullv({{
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// 32-bit multiply with trap on overflow
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int64_t Rax = Ra.sl; // sign extended version of Ra.sl
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@ -2102,7 +2102,7 @@ decode OPCODE default Unknown::unknown() {
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if (sign_bits != 0 && sign_bits != mask(33))
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fault = Integer_Overflow_Fault;
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Rc.sl = tmp<31:0>;
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}}, IntMULT);
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}}, IntMultOp);
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0x60: mulqv({{
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// 64-bit multiply with trap on overflow
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uint64_t hi, lo;
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@ -2113,7 +2113,7 @@ decode OPCODE default Unknown::unknown() {
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(hi == mask(64) && lo<63:> == 1)))
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fault = Integer_Overflow_Fault;
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Rc = lo;
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}}, IntMULT);
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}}, IntMultOp);
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}
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0x1c: decode INTFUNC {
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@ -2141,11 +2141,11 @@ decode OPCODE default Unknown::unknown() {
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format BasicOperateWithNopCheck {
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0x70: decode RB {
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31: ftoit({{ Rc = Fa.uq; }}, FloatCVT);
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31: ftoit({{ Rc = Fa.uq; }}, FloatCvtOp);
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}
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0x78: decode RB {
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31: ftois({{ Rc.sl = t_to_s(Fa.uq); }},
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FloatCVT);
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FloatCvtOp);
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}
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}
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}
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@ -2192,8 +2192,8 @@ decode OPCODE default Unknown::unknown() {
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0x4: decode RB {
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31: decode FP_FULLFUNC {
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format BasicOperateWithNopCheck {
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0x004: itofs({{ Fc.uq = s_to_t(Ra.ul); }}, FloatCVT);
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0x024: itoft({{ Fc.uq = Ra.uq; }}, FloatCVT);
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0x004: itofs({{ Fc.uq = s_to_t(Ra.ul); }}, FloatCvtOp);
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0x024: itoft({{ Fc.uq = Ra.uq; }}, FloatCvtOp);
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0x014: FailUnimpl::itoff(); // VAX-format conversion
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}
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}
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@ -2208,19 +2208,19 @@ decode OPCODE default Unknown::unknown() {
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if (Fb < 0.0)
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fault = Arithmetic_Fault;
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Fc = sqrt(Fb);
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}}, FloatSQRT);
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}}, FloatSqrtOp);
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#else
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0x0b: sqrts({{
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if (Fb.sf < 0.0)
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fault = Arithmetic_Fault;
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Fc.sf = sqrt(Fb.sf);
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}}, FloatSQRT);
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}}, FloatSqrtOp);
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#endif
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0x2b: sqrtt({{
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if (Fb < 0.0)
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fault = Arithmetic_Fault;
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Fc = sqrt(Fb);
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}}, FloatSQRT);
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}}, FloatSqrtOp);
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}
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}
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}
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@ -2246,19 +2246,19 @@ decode OPCODE default Unknown::unknown() {
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#ifdef SS_COMPATIBLE_FP
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0x00: adds({{ Fc = Fa + Fb; }});
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0x01: subs({{ Fc = Fa - Fb; }});
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0x02: muls({{ Fc = Fa * Fb; }}, FloatMULT);
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0x03: divs({{ Fc = Fa / Fb; }}, FloatDIV);
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0x02: muls({{ Fc = Fa * Fb; }}, FloatMultOp);
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0x03: divs({{ Fc = Fa / Fb; }}, FloatDivOp);
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#else
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0x00: adds({{ Fc.sf = Fa.sf + Fb.sf; }});
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0x01: subs({{ Fc.sf = Fa.sf - Fb.sf; }});
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0x02: muls({{ Fc.sf = Fa.sf * Fb.sf; }}, FloatMULT);
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0x03: divs({{ Fc.sf = Fa.sf / Fb.sf; }}, FloatDIV);
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0x02: muls({{ Fc.sf = Fa.sf * Fb.sf; }}, FloatMultOp);
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0x03: divs({{ Fc.sf = Fa.sf / Fb.sf; }}, FloatDivOp);
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#endif
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0x20: addt({{ Fc = Fa + Fb; }});
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0x21: subt({{ Fc = Fa - Fb; }});
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0x22: mult({{ Fc = Fa * Fb; }}, FloatMULT);
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0x23: divt({{ Fc = Fa / Fb; }}, FloatDIV);
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0x22: mult({{ Fc = Fa * Fb; }}, FloatMultOp);
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0x23: divt({{ Fc = Fa / Fb; }}, FloatDivOp);
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}
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}
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@ -2272,14 +2272,14 @@ decode OPCODE default Unknown::unknown() {
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1: decode FP_FULLFUNC {
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format BasicOperateWithNopCheck {
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0x0a5, 0x5a5: cmpteq({{ Fc = (Fa == Fb) ? 2.0 : 0.0; }},
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FloatCMP);
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FloatCmpOp);
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0x0a7, 0x5a7: cmptle({{ Fc = (Fa <= Fb) ? 2.0 : 0.0; }},
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FloatCMP);
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FloatCmpOp);
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0x0a6, 0x5a6: cmptlt({{ Fc = (Fa < Fb) ? 2.0 : 0.0; }},
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FloatCMP);
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FloatCmpOp);
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0x0a4, 0x5a4: cmptun({{ // unordered
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Fc = (!(Fa < Fb) && !(Fa == Fb) && !(Fa > Fb)) ? 2.0 : 0.0;
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}}, FloatCMP);
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}}, FloatCmpOp);
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}
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}
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@ -2371,7 +2371,7 @@ decode OPCODE default Unknown::unknown() {
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format MiscPrefetch {
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0xf800: wh64({{ EA = Rb; }},
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{{ xc->writeHint(EA, 64); }},
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IsMemRef, IsStore, WrPort);
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IsMemRef, IsStore, MemWriteOp);
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}
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format BasicOperate {
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@ -2401,8 +2401,8 @@ decode OPCODE default Unknown::unknown() {
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// them the same though.
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0x0000: trapb({{ }}, IsSerializing, No_OpClass);
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0x0400: excb({{ }}, IsSerializing, No_OpClass);
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0x4000: mb({{ }}, IsMemBarrier, RdPort);
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0x4400: wmb({{ }}, IsWriteBarrier, WrPort);
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0x4000: mb({{ }}, IsMemBarrier, MemReadOp);
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0x4400: wmb({{ }}, IsWriteBarrier, MemWriteOp);
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}
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#ifdef FULL_SYSTEM
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@ -1493,19 +1493,19 @@ class CodeBlock:
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# These are good enough for most cases, and will be overridden
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# later otherwise.
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if 'IsStore' in self.flags:
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self.op_class = 'WrPort'
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self.op_class = 'MemWriteOp'
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elif 'IsLoad' in self.flags or 'IsPrefetch' in self.flags:
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self.op_class = 'RdPort'
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self.op_class = 'MemReadOp'
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elif 'IsFloating' in self.flags:
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self.op_class = 'FloatADD'
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self.op_class = 'FloatAddOp'
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else:
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self.op_class = 'IntALU'
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self.op_class = 'IntAluOp'
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# Assume all instruction flags are of the form 'IsFoo'
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instFlagRE = re.compile(r'Is.*')
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# OpClass constants are just a little more complicated
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opClassRE = re.compile(r'Int.*|Float.*|.*Port|No_OpClass')
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# OpClass constants end in 'Op' except No_OpClass
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opClassRE = re.compile(r'.*Op|No_OpClass')
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class InstObjParams:
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def __init__(self, mnem, class_name, base_class = '',
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@ -40,23 +40,23 @@
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*/
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enum OpClass {
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No_OpClass = 0, /* inst does not use a functional unit */
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IntALU, /* integer ALU */
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IntMULT, /* integer multiplier */
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IntDIV, /* integer divider */
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FloatADD, /* floating point adder/subtractor */
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FloatCMP, /* floating point comparator */
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FloatCVT, /* floating point<->integer converter */
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FloatMULT, /* floating point multiplier */
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FloatDIV, /* floating point divider */
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FloatSQRT, /* floating point square root */
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RdPort, /* memory read port */
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WrPort, /* memory write port */
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IPrefPort,
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IntAluOp, /* integer ALU */
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IntMultOp, /* integer multiplier */
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IntDivOp, /* integer divider */
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FloatAddOp, /* floating point adder/subtractor */
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FloatCmpOp, /* floating point comparator */
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FloatCvtOp, /* floating point<->integer converter */
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FloatMultOp, /* floating point multiplier */
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FloatDivOp, /* floating point divider */
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FloatSqrtOp, /* floating point square root */
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MemReadOp, /* memory read port */
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MemWriteOp, /* memory write port */
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InstPrefetchOp, /* instruction prefetch port (on I-cache) */
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Num_OpClasses /* total functional unit classes */
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};
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/**
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* Array mapping OpClass enum values to strings.
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* Array mapping OpClass enum values to strings. Defined in fu_pool.cc.
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*/
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extern const char *opClassStrings[];
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