Merge zizzer:/z/m5/Bitkeeper/m5
into zizzer.eecs.umich.edu:/.automount/zazzer/z/rdreslin/m5bk/timing_L1 --HG-- extra : convert_revision : db688679bfd9c670ef44611de71640c3bf564fc0
This commit is contained in:
commit
9dd1ab1dba
|
@ -50,25 +50,12 @@ vector<BaseCPU *> BaseCPU::cpuList;
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int maxThreadsPerCPU = 1;
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#ifdef FULL_SYSTEM
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BaseCPU::BaseCPU(const string &_name, int _number_of_threads, bool _def_reg,
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Counter max_insts_any_thread,
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Counter max_insts_all_threads,
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Counter max_loads_any_thread,
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Counter max_loads_all_threads,
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System *_system, Tick freq,
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bool _function_trace, Tick _function_trace_start)
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: SimObject(_name), frequency(freq), checkInterrupts(true),
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deferRegistration(_def_reg), number_of_threads(_number_of_threads),
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system(_system)
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BaseCPU::BaseCPU(Params *p)
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: SimObject(p->name), frequency(p->freq), checkInterrupts(true),
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params(p), number_of_threads(p->numberOfThreads), system(p->system)
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#else
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BaseCPU::BaseCPU(const string &_name, int _number_of_threads, bool _def_reg,
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Counter max_insts_any_thread,
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Counter max_insts_all_threads,
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Counter max_loads_any_thread,
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Counter max_loads_all_threads,
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bool _function_trace, Tick _function_trace_start)
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: SimObject(_name), deferRegistration(_def_reg),
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number_of_threads(_number_of_threads)
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BaseCPU::BaseCPU(Params *p)
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: SimObject(p->name), params(p), number_of_threads(p->numberOfThreads)
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#endif
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{
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// add self to global list of CPUs
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@ -85,12 +72,12 @@ BaseCPU::BaseCPU(const string &_name, int _number_of_threads, bool _def_reg,
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//
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// set up instruction-count-based termination events, if any
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//
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if (max_insts_any_thread != 0)
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if (p->max_insts_any_thread != 0)
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for (int i = 0; i < number_of_threads; ++i)
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new SimExitEvent(comInstEventQueue[i], max_insts_any_thread,
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new SimExitEvent(comInstEventQueue[i], p->max_insts_any_thread,
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"a thread reached the max instruction count");
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if (max_insts_all_threads != 0) {
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if (p->max_insts_all_threads != 0) {
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// allocate & initialize shared downcounter: each event will
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// decrement this when triggered; simulation will terminate
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// when counter reaches 0
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@ -99,7 +86,7 @@ BaseCPU::BaseCPU(const string &_name, int _number_of_threads, bool _def_reg,
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for (int i = 0; i < number_of_threads; ++i)
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new CountedExitEvent(comInstEventQueue[i],
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"all threads reached the max instruction count",
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max_insts_all_threads, *counter);
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p->max_insts_all_threads, *counter);
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}
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// allocate per-thread load-based event queues
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@ -110,12 +97,12 @@ BaseCPU::BaseCPU(const string &_name, int _number_of_threads, bool _def_reg,
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//
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// set up instruction-count-based termination events, if any
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//
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if (max_loads_any_thread != 0)
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if (p->max_loads_any_thread != 0)
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for (int i = 0; i < number_of_threads; ++i)
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new SimExitEvent(comLoadEventQueue[i], max_loads_any_thread,
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new SimExitEvent(comLoadEventQueue[i], p->max_loads_any_thread,
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"a thread reached the max load count");
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if (max_loads_all_threads != 0) {
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if (p->max_loads_all_threads != 0) {
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// allocate & initialize shared downcounter: each event will
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// decrement this when triggered; simulation will terminate
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// when counter reaches 0
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@ -124,7 +111,7 @@ BaseCPU::BaseCPU(const string &_name, int _number_of_threads, bool _def_reg,
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for (int i = 0; i < number_of_threads; ++i)
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new CountedExitEvent(comLoadEventQueue[i],
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"all threads reached the max load count",
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max_loads_all_threads, *counter);
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p->max_loads_all_threads, *counter);
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}
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#ifdef FULL_SYSTEM
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@ -133,18 +120,18 @@ BaseCPU::BaseCPU(const string &_name, int _number_of_threads, bool _def_reg,
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#endif
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functionTracingEnabled = false;
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if (_function_trace) {
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if (p->functionTrace) {
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functionTraceStream = simout.find(csprintf("ftrace.%s", name()));
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currentFunctionStart = currentFunctionEnd = 0;
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functionEntryTick = _function_trace_start;
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functionEntryTick = p->functionTraceStart;
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if (_function_trace_start == 0) {
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if (p->functionTraceStart == 0) {
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functionTracingEnabled = true;
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} else {
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Event *e =
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new EventWrapper<BaseCPU, &BaseCPU::enableFunctionTrace>(this,
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true);
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e->schedule(_function_trace_start);
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e->schedule(p->functionTraceStart);
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}
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}
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}
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@ -163,7 +150,7 @@ BaseCPU::~BaseCPU()
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void
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BaseCPU::init()
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{
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if (!deferRegistration)
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if (!params->deferRegistration)
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registerExecContexts();
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}
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@ -91,28 +91,31 @@ class BaseCPU : public SimObject
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virtual void haltContext(int thread_num) {}
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public:
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struct Params
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{
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std::string name;
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int numberOfThreads;
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bool deferRegistration;
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Counter max_insts_any_thread;
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Counter max_insts_all_threads;
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Counter max_loads_any_thread;
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Counter max_loads_all_threads;
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Tick freq;
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bool functionTrace;
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Tick functionTraceStart;
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#ifdef FULL_SYSTEM
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BaseCPU(const std::string &_name, int _number_of_threads, bool _def_reg,
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Counter max_insts_any_thread, Counter max_insts_all_threads,
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Counter max_loads_any_thread, Counter max_loads_all_threads,
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System *_system, Tick freq,
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bool _function_trace = false, Tick _function_trace_start = 0);
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#else
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BaseCPU(const std::string &_name, int _number_of_threads, bool _def_reg,
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Counter max_insts_any_thread = 0,
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Counter max_insts_all_threads = 0,
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Counter max_loads_any_thread = 0,
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Counter max_loads_all_threads = 0,
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bool _function_trace = false, Tick _function_trace_start = 0);
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System *system;
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#endif
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};
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const Params *params;
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BaseCPU(Params *params);
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virtual ~BaseCPU();
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virtual void init();
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virtual void regStats();
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bool deferRegistration;
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void registerExecContexts();
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/// Prepare for another CPU to take over execution. When it is
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@ -36,6 +36,7 @@
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#include "base/misc.hh"
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#include "base/statistics.hh"
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#include "cpu/exec_context.hh"
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#include "cpu/memtest/memtest.hh"
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#include "mem/cache/base_cache.hh"
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#include "mem/functional_mem/main_memory.hh"
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@ -59,10 +60,8 @@ MemTest::MemTest(const string &name,
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unsigned _percentSourceUnaligned,
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unsigned _percentDestUnaligned,
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Addr _traceAddr,
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Counter max_loads_any_thread,
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Counter max_loads_all_threads)
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: BaseCPU(name, 1, true, 0, 0, max_loads_any_thread,
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max_loads_all_threads),
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Counter _max_loads)
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: SimObject(name),
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tickEvent(this),
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cacheInterface(_cache_interface),
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mainMem(main_mem),
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@ -74,12 +73,13 @@ MemTest::MemTest(const string &name,
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progressInterval(_progressInterval),
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nextProgressMessage(_progressInterval),
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percentSourceUnaligned(_percentSourceUnaligned),
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percentDestUnaligned(percentDestUnaligned)
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percentDestUnaligned(percentDestUnaligned),
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maxLoads(_max_loads)
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{
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vector<string> cmd;
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cmd.push_back("/bin/ls");
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vector<string> null_vec;
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xc = new ExecContext(this ,0,mainMem,0);
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xc = new ExecContext(NULL, 0, mainMem, 0);
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blockSize = cacheInterface->getBlockSize();
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blockAddrMask = blockSize - 1;
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@ -160,7 +160,8 @@ MemTest::completeRequest(MemReqPtr &req, uint8_t *data)
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nextProgressMessage += progressInterval;
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}
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comLoadEventQueue[0]->serviceEvents(numReads);
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if (numReads >= maxLoads)
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SimExit(curTick, "Maximum number of loads reached!");
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break;
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case Write:
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@ -402,8 +403,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(MemTest)
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Param<unsigned> percent_source_unaligned;
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Param<unsigned> percent_dest_unaligned;
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Param<Addr> trace_addr;
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Param<Counter> max_loads_any_thread;
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Param<Counter> max_loads_all_threads;
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Param<Counter> max_loads;
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END_DECLARE_SIM_OBJECT_PARAMS(MemTest)
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@ -413,23 +413,17 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(MemTest)
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INIT_PARAM(cache, "L1 cache"),
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INIT_PARAM(main_mem, "hierarchical memory"),
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INIT_PARAM(check_mem, "check memory"),
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INIT_PARAM_DFLT(memory_size, "memory size", 65536),
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INIT_PARAM_DFLT(percent_reads, "target read percentage", 65),
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INIT_PARAM_DFLT(percent_copies, "target copy percentage", 0),
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INIT_PARAM_DFLT(percent_uncacheable, "target uncacheable percentage", 10),
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INIT_PARAM_DFLT(progress_interval,
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"progress report interval (in accesses)", 1000000),
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INIT_PARAM_DFLT(percent_source_unaligned, "percent of copy source address "
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"that are unaligned", 50),
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INIT_PARAM_DFLT(percent_dest_unaligned, "percent of copy dest address "
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"that are unaligned", 50),
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INIT_PARAM_DFLT(trace_addr, "address to trace", 0),
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INIT_PARAM_DFLT(max_loads_any_thread,
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"terminate when any thread reaches this load count",
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0),
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INIT_PARAM_DFLT(max_loads_all_threads,
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"terminate when all threads have reached this load count",
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0)
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INIT_PARAM(memory_size, "memory size"),
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INIT_PARAM(percent_reads, "target read percentage"),
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INIT_PARAM(percent_copies, "target copy percentage"),
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INIT_PARAM(percent_uncacheable, "target uncacheable percentage"),
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INIT_PARAM(progress_interval, "progress report interval (in accesses)"),
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INIT_PARAM(percent_source_unaligned,
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"percent of copy source address that are unaligned"),
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INIT_PARAM(percent_dest_unaligned,
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"percent of copy dest address that are unaligned"),
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INIT_PARAM(trace_addr, "address to trace"),
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INIT_PARAM(max_loads, "terminate when we have reached this load count")
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END_INIT_SIM_OBJECT_PARAMS(MemTest)
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@ -440,8 +434,7 @@ CREATE_SIM_OBJECT(MemTest)
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check_mem, memory_size, percent_reads, percent_copies,
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percent_uncacheable, progress_interval,
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percent_source_unaligned, percent_dest_unaligned,
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trace_addr, max_loads_any_thread,
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max_loads_all_threads);
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trace_addr, max_loads);
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}
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REGISTER_SIM_OBJECT("MemTest", MemTest)
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@ -26,20 +26,21 @@
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __MEMTEST_HH__
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#define __MEMTEST_HH__
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#ifndef __CPU_MEMTEST_MEMTEST_HH__
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#define __CPU_MEMTEST_MEMTEST_HH__
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#include <set>
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#include "base/statistics.hh"
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#include "cpu/base_cpu.hh"
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#include "cpu/exec_context.hh"
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#include "mem/functional_mem/functional_memory.hh"
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#include "mem/mem_interface.hh"
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#include "sim/eventq.hh"
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#include "sim/sim_exit.hh"
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#include "sim/sim_object.hh"
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#include "sim/stats.hh"
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class MemTest : public BaseCPU
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class ExecContext;
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class MemTest : public SimObject
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{
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public:
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@ -55,8 +56,7 @@ class MemTest : public BaseCPU
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unsigned _percentSourceUnaligned,
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unsigned _percentDestUnaligned,
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Addr _traceAddr,
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Counter max_loads_any_thread,
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Counter max_loads_all_threads);
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Counter _max_loads);
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// register statistics
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virtual void regStats();
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@ -116,6 +116,7 @@ class MemTest : public BaseCPU
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Tick noResponseCycles;
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uint64_t numReads;
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uint64_t maxLoads;
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Stats::Scalar<> numReadsStat;
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Stats::Scalar<> numWritesStat;
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Stats::Scalar<> numCopiesStat;
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|
@ -146,7 +147,7 @@ class MemCompleteEvent : public Event
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virtual const char *description();
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};
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#endif // __MEMTEST_HH__
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#endif // __CPU_MEMTEST_MEMTEST_HH__
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|
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|
|
|
@ -113,54 +113,22 @@ SimpleCPU::CacheCompletionEvent::description()
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return "SimpleCPU cache completion event";
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}
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#ifdef FULL_SYSTEM
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SimpleCPU::SimpleCPU(const string &_name,
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System *_system,
|
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Counter max_insts_any_thread,
|
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Counter max_insts_all_threads,
|
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Counter max_loads_any_thread,
|
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Counter max_loads_all_threads,
|
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AlphaITB *itb, AlphaDTB *dtb,
|
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FunctionalMemory *mem,
|
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MemInterface *icache_interface,
|
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MemInterface *dcache_interface,
|
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bool _def_reg, Tick freq,
|
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bool _function_trace, Tick _function_trace_start,
|
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int width)
|
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: BaseCPU(_name, /* number_of_threads */ 1, _def_reg,
|
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max_insts_any_thread, max_insts_all_threads,
|
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max_loads_any_thread, max_loads_all_threads,
|
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_system, freq, _function_trace, _function_trace_start),
|
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#else
|
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SimpleCPU::SimpleCPU(const string &_name, Process *_process,
|
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Counter max_insts_any_thread,
|
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Counter max_insts_all_threads,
|
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Counter max_loads_any_thread,
|
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Counter max_loads_all_threads,
|
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MemInterface *icache_interface,
|
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MemInterface *dcache_interface,
|
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bool _def_reg,
|
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bool _function_trace, Tick _function_trace_start,
|
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int width)
|
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: BaseCPU(_name, /* number_of_threads */ 1, _def_reg,
|
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max_insts_any_thread, max_insts_all_threads,
|
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max_loads_any_thread, max_loads_all_threads,
|
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_function_trace, _function_trace_start),
|
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#endif
|
||||
tickEvent(this, width), xc(NULL), cacheCompletionEvent(this)
|
||||
SimpleCPU::SimpleCPU(Params *p)
|
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: BaseCPU(p), tickEvent(this, p->width), xc(NULL),
|
||||
cacheCompletionEvent(this)
|
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{
|
||||
_status = Idle;
|
||||
#ifdef FULL_SYSTEM
|
||||
xc = new ExecContext(this, 0, system, itb, dtb, mem);
|
||||
xc = new ExecContext(this, 0, p->system, p->itb, p->dtb, p->mem);
|
||||
|
||||
// initialize CPU, including PC
|
||||
TheISA::initCPU(&xc->regs);
|
||||
#else
|
||||
xc = new ExecContext(this, /* thread_num */ 0, _process, /* asid */ 0);
|
||||
xc = new ExecContext(this, /* thread_num */ 0, p->process, /* asid */ 0);
|
||||
#endif // !FULL_SYSTEM
|
||||
|
||||
icacheInterface = icache_interface;
|
||||
dcacheInterface = dcache_interface;
|
||||
icacheInterface = p->icache_interface;
|
||||
dcacheInterface = p->dcache_interface;
|
||||
|
||||
memReq = new MemReq();
|
||||
memReq->xc = xc;
|
||||
|
@ -887,71 +855,67 @@ END_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU)
|
|||
|
||||
BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleCPU)
|
||||
|
||||
INIT_PARAM_DFLT(max_insts_any_thread,
|
||||
"terminate when any thread reaches this inst count",
|
||||
0),
|
||||
INIT_PARAM_DFLT(max_insts_all_threads,
|
||||
"terminate when all threads have reached this inst count",
|
||||
0),
|
||||
INIT_PARAM_DFLT(max_loads_any_thread,
|
||||
"terminate when any thread reaches this load count",
|
||||
0),
|
||||
INIT_PARAM_DFLT(max_loads_all_threads,
|
||||
"terminate when all threads have reached this load count",
|
||||
0),
|
||||
INIT_PARAM(max_insts_any_thread,
|
||||
"terminate when any thread reaches this inst count"),
|
||||
INIT_PARAM(max_insts_all_threads,
|
||||
"terminate when all threads have reached this inst count"),
|
||||
INIT_PARAM(max_loads_any_thread,
|
||||
"terminate when any thread reaches this load count"),
|
||||
INIT_PARAM(max_loads_all_threads,
|
||||
"terminate when all threads have reached this load count"),
|
||||
|
||||
#ifdef FULL_SYSTEM
|
||||
INIT_PARAM(itb, "Instruction TLB"),
|
||||
INIT_PARAM(dtb, "Data TLB"),
|
||||
INIT_PARAM(mem, "memory"),
|
||||
INIT_PARAM(system, "system object"),
|
||||
INIT_PARAM_DFLT(mult, "system clock multiplier", 1),
|
||||
INIT_PARAM(mult, "system clock multiplier"),
|
||||
#else
|
||||
INIT_PARAM(workload, "processes to run"),
|
||||
#endif // FULL_SYSTEM
|
||||
|
||||
INIT_PARAM_DFLT(icache, "L1 instruction cache object", NULL),
|
||||
INIT_PARAM_DFLT(dcache, "L1 data cache object", NULL),
|
||||
INIT_PARAM_DFLT(defer_registration, "defer registration with system "
|
||||
"(for sampling)", false),
|
||||
|
||||
INIT_PARAM_DFLT(width, "cpu width", 1),
|
||||
INIT_PARAM_DFLT(function_trace, "Enable function trace", false),
|
||||
INIT_PARAM_DFLT(function_trace_start, "Cycle to start function trace", 0)
|
||||
INIT_PARAM(icache, "L1 instruction cache object"),
|
||||
INIT_PARAM(dcache, "L1 data cache object"),
|
||||
INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
|
||||
INIT_PARAM(width, "cpu width"),
|
||||
INIT_PARAM(function_trace, "Enable function trace"),
|
||||
INIT_PARAM(function_trace_start, "Cycle to start function trace")
|
||||
|
||||
END_INIT_SIM_OBJECT_PARAMS(SimpleCPU)
|
||||
|
||||
|
||||
CREATE_SIM_OBJECT(SimpleCPU)
|
||||
{
|
||||
SimpleCPU *cpu;
|
||||
#ifdef FULL_SYSTEM
|
||||
if (mult != 1)
|
||||
panic("processor clock multiplier must be 1\n");
|
||||
#endif
|
||||
|
||||
cpu = new SimpleCPU(getInstanceName(), system,
|
||||
max_insts_any_thread, max_insts_all_threads,
|
||||
max_loads_any_thread, max_loads_all_threads,
|
||||
itb, dtb, mem,
|
||||
(icache) ? icache->getInterface() : NULL,
|
||||
(dcache) ? dcache->getInterface() : NULL,
|
||||
defer_registration,
|
||||
ticksPerSecond * mult,
|
||||
function_trace, function_trace_start,
|
||||
width);
|
||||
SimpleCPU::Params *params = new SimpleCPU::Params();
|
||||
params->name = getInstanceName();
|
||||
params->numberOfThreads = 1;
|
||||
params->max_insts_any_thread = max_insts_any_thread;
|
||||
params->max_insts_all_threads = max_insts_all_threads;
|
||||
params->max_loads_any_thread = max_loads_any_thread;
|
||||
params->max_loads_all_threads = max_loads_all_threads;
|
||||
params->deferRegistration = defer_registration;
|
||||
params->freq = ticksPerSecond;
|
||||
params->functionTrace = function_trace;
|
||||
params->functionTraceStart = function_trace_start;
|
||||
params->icache_interface = (icache) ? icache->getInterface() : NULL;
|
||||
params->dcache_interface = (dcache) ? dcache->getInterface() : NULL;
|
||||
params->width = width;
|
||||
|
||||
#ifdef FULL_SYSTEM
|
||||
params->itb = itb;
|
||||
params->dtb = dtb;
|
||||
params->mem = mem;
|
||||
params->system = system;
|
||||
#else
|
||||
params->process = workload;
|
||||
#endif
|
||||
|
||||
cpu = new SimpleCPU(getInstanceName(), workload,
|
||||
max_insts_any_thread, max_insts_all_threads,
|
||||
max_loads_any_thread, max_loads_all_threads,
|
||||
(icache) ? icache->getInterface() : NULL,
|
||||
(dcache) ? dcache->getInterface() : NULL,
|
||||
defer_registration,
|
||||
function_trace, function_trace_start,
|
||||
width);
|
||||
|
||||
#endif // FULL_SYSTEM
|
||||
|
||||
SimpleCPU *cpu = new SimpleCPU(params);
|
||||
return cpu;
|
||||
}
|
||||
|
||||
|
|
|
@ -124,32 +124,24 @@ class SimpleCPU : public BaseCPU
|
|||
}
|
||||
};
|
||||
|
||||
public:
|
||||
struct Params : public BaseCPU::Params
|
||||
{
|
||||
MemInterface *icache_interface;
|
||||
MemInterface *dcache_interface;
|
||||
int width;
|
||||
#ifdef FULL_SYSTEM
|
||||
|
||||
SimpleCPU(const std::string &_name,
|
||||
System *_system,
|
||||
Counter max_insts_any_thread, Counter max_insts_all_threads,
|
||||
Counter max_loads_any_thread, Counter max_loads_all_threads,
|
||||
AlphaITB *itb, AlphaDTB *dtb, FunctionalMemory *mem,
|
||||
MemInterface *icache_interface, MemInterface *dcache_interface,
|
||||
bool _def_reg, Tick freq,
|
||||
bool _function_trace, Tick _function_trace_start, int width);
|
||||
|
||||
AlphaITB *itb;
|
||||
AlphaDTB *dtb;
|
||||
FunctionalMemory *mem;
|
||||
#else
|
||||
|
||||
SimpleCPU(const std::string &_name, Process *_process,
|
||||
Counter max_insts_any_thread,
|
||||
Counter max_insts_all_threads,
|
||||
Counter max_loads_any_thread,
|
||||
Counter max_loads_all_threads,
|
||||
MemInterface *icache_interface, MemInterface *dcache_interface,
|
||||
bool _def_reg,
|
||||
bool _function_trace, Tick _function_trace_start, int width);
|
||||
|
||||
Process *process;
|
||||
#endif
|
||||
|
||||
};
|
||||
SimpleCPU(Params *params);
|
||||
virtual ~SimpleCPU();
|
||||
|
||||
public:
|
||||
// execution context
|
||||
ExecContext *xc;
|
||||
|
||||
|
|
|
@ -48,7 +48,7 @@ OptCPU::OptCPU(const string &name,
|
|||
int block_size,
|
||||
int cache_size,
|
||||
int _assoc)
|
||||
: BaseCPU(name, 1, true), tickEvent(this), trace(_trace),
|
||||
: SimObject(name), tickEvent(this), trace(_trace),
|
||||
numBlks(cache_size/block_size), assoc(_assoc), numSets(numBlks/assoc),
|
||||
setMask(numSets - 1)
|
||||
{
|
||||
|
|
|
@ -32,14 +32,14 @@
|
|||
* trace to access a fully associative cache with optimal replacement.
|
||||
*/
|
||||
|
||||
#ifndef __OPT_CPU_HH__
|
||||
#define __OPT_CPU_HH__
|
||||
#ifndef __CPU_TRACE_OPT_CPU_HH__
|
||||
#define __CPU_TRACE_OPT_CPU_HH__
|
||||
|
||||
#include <vector>
|
||||
|
||||
#include "cpu/base_cpu.hh"
|
||||
#include "mem/mem_req.hh" // for MemReqPtr
|
||||
#include "sim/eventq.hh" // for Event
|
||||
#include "sim/sim_object.hh"
|
||||
|
||||
// Forward Declaration
|
||||
class MemTraceReader;
|
||||
|
@ -47,8 +47,9 @@ class MemTraceReader;
|
|||
/**
|
||||
* A CPU object to simulate a fully-associative cache with optimal replacement.
|
||||
*/
|
||||
class OptCPU : public BaseCPU
|
||||
class OptCPU : public SimObject
|
||||
{
|
||||
private:
|
||||
typedef int RefIndex;
|
||||
|
||||
typedef std::vector<RefIndex> L3Table;
|
||||
|
@ -219,4 +220,4 @@ class OptCPU : public BaseCPU
|
|||
void tick();
|
||||
};
|
||||
|
||||
#endif
|
||||
#endif // __CPU_TRACE_OPT_CPU_HH__
|
||||
|
|
|
@ -47,7 +47,7 @@ TraceCPU::TraceCPU(const string &name,
|
|||
MemInterface *icache_interface,
|
||||
MemInterface *dcache_interface,
|
||||
MemTraceReader *data_trace)
|
||||
: BaseCPU(name, 4, true), icacheInterface(icache_interface),
|
||||
: SimObject(name), icacheInterface(icache_interface),
|
||||
dcacheInterface(dcache_interface),
|
||||
dataTrace(data_trace), outstandingRequests(0), tickEvent(this)
|
||||
{
|
||||
|
|
|
@ -32,14 +32,14 @@
|
|||
* provided memory hierarchy.
|
||||
*/
|
||||
|
||||
#ifndef __TRACE_CPU_HH__
|
||||
#define __TRACE_CPU_HH__
|
||||
#ifndef __CPU_TRACE_TRACE_CPU_HH__
|
||||
#define __CPU_TRACE_TRACE_CPU_HH__
|
||||
|
||||
#include <string>
|
||||
|
||||
#include "cpu/base_cpu.hh"
|
||||
#include "mem/mem_req.hh" // for MemReqPtr
|
||||
#include "sim/eventq.hh" // for Event
|
||||
#include "sim/sim_object.hh"
|
||||
|
||||
// Forward declaration.
|
||||
class MemInterface;
|
||||
|
@ -48,8 +48,9 @@ class MemTraceReader;
|
|||
/**
|
||||
* A cpu object for running memory traces through a memory hierarchy.
|
||||
*/
|
||||
class TraceCPU : public BaseCPU
|
||||
class TraceCPU : public SimObject
|
||||
{
|
||||
private:
|
||||
/** Interface for instruction trace requests, if any. */
|
||||
MemInterface *icacheInterface;
|
||||
/** Interface for data trace requests, if any. */
|
||||
|
@ -133,5 +134,5 @@ class TraceCompleteEvent : public Event
|
|||
virtual const char *description();
|
||||
};
|
||||
|
||||
#endif //__TRACE_CPU_HH__
|
||||
#endif // __CPU_TRACE_TRACE_CPU_HH__
|
||||
|
||||
|
|
|
@ -3,10 +3,7 @@ simobj MemTest(SimObject):
|
|||
cache = Param.BaseCache("L1 cache")
|
||||
check_mem = Param.FunctionalMemory("check memory")
|
||||
main_mem = Param.FunctionalMemory("hierarchical memory")
|
||||
max_loads_all_threads = Param.Counter(0,
|
||||
"terminate when all threads have reached this load count")
|
||||
max_loads_any_thread = Param.Counter(0,
|
||||
"terminate when any thread reaches this load count")
|
||||
max_loads = Param.Counter("number of loads to execute")
|
||||
memory_size = Param.Int(65536, "memory size")
|
||||
percent_copies = Param.Percent(0, "target copy percentage")
|
||||
percent_dest_unaligned = Param.Percent(50,
|
||||
|
|
|
@ -402,12 +402,6 @@ main(int argc, char **argv)
|
|||
// Reset to put the stats in a consistent state.
|
||||
Stats::reset();
|
||||
|
||||
// Nothing to simulate if we don't have at least one CPU somewhere.
|
||||
if (BaseCPU::numSimulatedCPUs() == 0) {
|
||||
cerr << "Fatal: no CPUs to simulate." << endl;
|
||||
exit(1);
|
||||
}
|
||||
|
||||
warn("Entering event queue. Starting simulation...\n");
|
||||
SimStartup();
|
||||
while (!mainEventQueue.empty()) {
|
||||
|
|
Loading…
Reference in a new issue