gem5/cpu
Steve Reinhardt 53dde8579b Renamed OpClass enum members: they all end in 'Op' now.
Got rid of two inconsistent sets of strings that corresponded
to this enum, and replaced with a single set that clearly
matches the enum names.

arch/alpha/isa_desc:
arch/isa_parser.py:
cpu/full_cpu/op_class.hh:
    Renamed OpClass enum members.

--HG--
extra : convert_revision : bf596f7568a20b2e77c07ac349f253135141aef4
2004-05-31 16:19:31 -07:00
..
full_cpu Renamed OpClass enum members: they all end in 'Op' now. 2004-05-31 16:19:31 -07:00
memtest Change the namespace Statistics to Stats 2004-05-21 13:03:17 -04:00
simple_cpu Merged in new FastCPU stuff with existing code. 2004-05-28 11:41:52 -04:00
base_cpu.cc Change the namespace Statistics to Stats 2004-05-21 13:03:17 -04:00
base_cpu.hh Change the namespace Statistics to Stats 2004-05-21 13:03:17 -04:00
exec_context.cc Merged in new FastCPU stuff with existing code. 2004-05-28 11:41:52 -04:00
exec_context.hh FastCPU model added. It's very similar to the SimpleCPU, just without a lot of the stats tracking. 2004-05-27 17:46:16 -04:00
exetrace.cc Minor cleanup of trace/output stuff (leftover from EINTR bug fix). 2003-12-19 08:04:40 -08:00
exetrace.hh More conversions of ref-counted parameters to references: 2004-02-02 15:45:22 -08:00
inst_seq.hh File moves for the reorg. Tree is in broken state until I commit the makefile and 2003-10-10 09:57:26 -07:00
intr_control.cc General fixes for Sampling CPU in full system mode, and serialization of sampling CPU 2003-11-02 19:38:22 -05:00
intr_control.hh General fixes for Sampling CPU in full system mode, and serialization of sampling CPU 2003-11-02 19:38:22 -05:00
pc_event.cc Remove all of the Tru64 specific stuff from the base System object 2003-10-14 12:19:59 -04:00
pc_event.hh Move to non-architecture specific MemReq 2003-10-23 16:40:08 -04:00
static_inst.cc Make include paths explicit and update makefile accordingly. 2003-10-10 11:09:00 -07:00
static_inst.hh Merged in new FastCPU stuff with existing code. 2004-05-28 11:41:52 -04:00