More progress toward compiling... partly by
fixing things, partly by ignoring CPU models that don't currently compile. SConscript: Split sources for fast, simple, and o3 CPU models into separate source lists. For now none of these are included in the base source list, so you won't get any CPU models at all... but we still can't compile the other stuff so it's not an issue. Also get rid of obsolete encumbered/mem file. base/loader/aout_object.cc: base/loader/aout_object.hh: base/loader/ecoff_object.cc: base/loader/ecoff_object.hh: base/loader/elf_object.cc: base/loader/elf_object.hh: base/loader/object_file.hh: cpu/exec_context.cc: sim/process.cc: sim/system.cc: sim/system.hh: FunctionalMemory -> Memory cpu/pc_event.hh: Get rid of unused badpc. cpu/simple/cpu.cc: cpu/simple/cpu.hh: Move Port functions into .cc file. mem/port.hh: Make recvAddressRangesQuery panic by default instead of being abstract... do CPUs need to implement this? mem/request.hh: Add prefetch flags. sim/syscall_emul.hh: Start to fix... --HG-- extra : convert_revision : ece53b3855f20916caaa381598ac37e8c7adfba7
This commit is contained in:
parent
091e6b72cf
commit
b8a2d1e5c7
18 changed files with 123 additions and 97 deletions
82
SConscript
82
SConscript
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@ -45,9 +45,6 @@ Import('env')
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# Base sources used by all configurations.
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base_sources = Split('''
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arch/alpha/decoder.cc
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arch/alpha/alpha_o3_exec.cc
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arch/alpha/fast_cpu_exec.cc
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arch/alpha/simple_cpu_exec.cc
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arch/alpha/faults.cc
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arch/alpha/isa_traits.cc
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@ -87,44 +84,11 @@ base_sources = Split('''
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base/stats/text.cc
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cpu/base.cc
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cpu/base_dyn_inst.cc
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cpu/exec_context.cc
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cpu/exetrace.cc
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cpu/pc_event.cc
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cpu/static_inst.cc
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cpu/o3/2bit_local_pred.cc
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cpu/o3/alpha_dyn_inst.cc
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cpu/o3/alpha_cpu.cc
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cpu/o3/alpha_cpu_builder.cc
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cpu/o3/bpred_unit.cc
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cpu/o3/btb.cc
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cpu/o3/commit.cc
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cpu/o3/decode.cc
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cpu/o3/fetch.cc
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cpu/o3/free_list.cc
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cpu/o3/cpu.cc
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cpu/o3/iew.cc
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cpu/o3/inst_queue.cc
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cpu/o3/ldstq.cc
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cpu/o3/mem_dep_unit.cc
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cpu/o3/ras.cc
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cpu/o3/rename.cc
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cpu/o3/rename_map.cc
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cpu/o3/rob.cc
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cpu/o3/sat_counter.cc
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cpu/o3/store_set.cc
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cpu/o3/tournament_pred.cc
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cpu/fast/cpu.cc
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cpu/sampler/sampler.cc
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cpu/simple/cpu.cc
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cpu/trace/reader/mem_trace_reader.cc
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cpu/trace/reader/ibm_reader.cc
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cpu/trace/reader/itx_reader.cc
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cpu/trace/reader/m5_reader.cc
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cpu/trace/opt_cpu.cc
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cpu/trace/trace_cpu.cc
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encumbered/mem/functional/main.cc
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mem/memory.cc
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mem/page_table.cc
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@ -153,8 +117,28 @@ base_sources = Split('''
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sim/trace_context.cc
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''')
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fast_cpu_sources = Split('''
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arch/alpha/fast_cpu_exec.cc
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cpu/fast/cpu.cc
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''')
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simple_cpu_sources = Split('''
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arch/alpha/simple_cpu_exec.cc
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cpu/simple/cpu.cc
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''')
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trace_reader_sources = Split('''
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cpu/trace/reader/mem_trace_reader.cc
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cpu/trace/reader/ibm_reader.cc
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cpu/trace/reader/itx_reader.cc
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cpu/trace/reader/m5_reader.cc
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cpu/trace/opt_cpu.cc
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cpu/trace/trace_cpu.cc
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''')
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full_cpu_sources = Split('''
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arch/alpha/full_cpu_exec.cc
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cpu/base_dyn_inst.cc
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encumbered/cpu/full/bpred.cc
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encumbered/cpu/full/commit.cc
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encumbered/cpu/full/cpu.cc
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@ -191,6 +175,32 @@ full_cpu_sources = Split('''
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encumbered/cpu/full/iq/standard/iq_standard.cc
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''')
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o3_cpu_sources = Split('''
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arch/alpha/alpha_o3_exec.cc
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cpu/o3/2bit_local_pred.cc
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cpu/o3/alpha_dyn_inst.cc
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cpu/o3/alpha_cpu.cc
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cpu/o3/alpha_cpu_builder.cc
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cpu/o3/bpred_unit.cc
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cpu/o3/btb.cc
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cpu/o3/commit.cc
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cpu/o3/decode.cc
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cpu/o3/fetch.cc
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cpu/o3/free_list.cc
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cpu/o3/cpu.cc
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cpu/o3/iew.cc
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cpu/o3/inst_queue.cc
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cpu/o3/ldstq.cc
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cpu/o3/mem_dep_unit.cc
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cpu/o3/ras.cc
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cpu/o3/rename.cc
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cpu/o3/rename_map.cc
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cpu/o3/rob.cc
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cpu/o3/sat_counter.cc
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cpu/o3/store_set.cc
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cpu/o3/tournament_pred.cc
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''')
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# MySql sources
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mysql_sources = Split('''
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base/mysql.cc
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@ -30,7 +30,7 @@
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#include "base/loader/aout_object.hh"
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#include "mem/functional/functional.hh"
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#include "mem/memory.hh"
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#include "base/loader/symtab.hh"
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#include "base/trace.hh" // for DPRINTF
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@ -78,7 +78,7 @@ AoutObject::AoutObject(const string &_filename, int _fd,
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bool
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AoutObject::loadSections(FunctionalMemory *mem, bool loadPhys)
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AoutObject::loadSections(Memory *mem, bool loadPhys)
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{
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Addr textAddr = text.baseAddr;
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Addr dataAddr = data.baseAddr;
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@ -46,8 +46,7 @@ class AoutObject : public ObjectFile
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public:
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virtual ~AoutObject() {}
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virtual bool loadSections(FunctionalMemory *mem,
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bool loadPhys = false);
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virtual bool loadSections(Memory *mem, bool loadPhys = false);
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virtual bool loadGlobalSymbols(SymbolTable *symtab);
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virtual bool loadLocalSymbols(SymbolTable *symtab);
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@ -30,7 +30,7 @@
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#include "base/loader/ecoff_object.hh"
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#include "mem/functional/functional.hh"
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#include "mem/memory.hh"
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#include "base/loader/symtab.hh"
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#include "base/trace.hh" // for DPRINTF
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@ -82,7 +82,7 @@ EcoffObject::EcoffObject(const string &_filename, int _fd,
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bool
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EcoffObject::loadSections(FunctionalMemory *mem, bool loadPhys)
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EcoffObject::loadSections(Memory *mem, bool loadPhys)
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{
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Addr textAddr = text.baseAddr;
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Addr dataAddr = data.baseAddr;
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@ -50,8 +50,7 @@ class EcoffObject : public ObjectFile
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public:
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virtual ~EcoffObject() {}
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virtual bool loadSections(FunctionalMemory *mem,
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bool loadPhys = false);
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virtual bool loadSections(Memory *mem, bool loadPhys = false);
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virtual bool loadGlobalSymbols(SymbolTable *symtab);
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virtual bool loadLocalSymbols(SymbolTable *symtab);
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@ -43,7 +43,7 @@
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#include "base/loader/elf_object.hh"
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#include "mem/functional/functional.hh"
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#include "mem/memory.hh"
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#include "base/loader/symtab.hh"
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#include "base/trace.hh" // for DPRINTF
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@ -170,7 +170,7 @@ ElfObject::ElfObject(const string &_filename, int _fd,
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bool
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ElfObject::loadSections(FunctionalMemory *mem, bool loadPhys)
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ElfObject::loadSections(Memory *mem, bool loadPhys)
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{
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Addr textAddr = text.baseAddr;
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Addr dataAddr = data.baseAddr;
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@ -48,8 +48,7 @@ class ElfObject : public ObjectFile
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public:
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virtual ~ElfObject() {}
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virtual bool loadSections(FunctionalMemory *mem,
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bool loadPhys = false);
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virtual bool loadSections(Memory *mem, bool loadPhys = false);
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virtual bool loadGlobalSymbols(SymbolTable *symtab);
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virtual bool loadLocalSymbols(SymbolTable *symtab);
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@ -31,7 +31,7 @@
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#include "targetarch/isa_traits.hh" // for Addr
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class FunctionalMemory;
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class Memory;
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class SymbolTable;
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class ObjectFile
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@ -67,8 +67,7 @@ class ObjectFile
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void close();
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virtual bool loadSections(FunctionalMemory *mem,
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bool loadPhys = false) = 0;
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virtual bool loadSections(Memory *mem, bool loadPhys = false) = 0;
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virtual bool loadGlobalSymbols(SymbolTable *symtab) = 0;
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virtual bool loadLocalSymbols(SymbolTable *symtab) = 0;
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@ -51,7 +51,7 @@ using namespace std;
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#if FULL_SYSTEM
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ExecContext::ExecContext(BaseCPU *_cpu, int _thread_num, System *_sys,
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AlphaITB *_itb, AlphaDTB *_dtb,
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FunctionalMemory *_mem)
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Memory *_mem)
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: _status(ExecContext::Unallocated), cpu(_cpu), thread_num(_thread_num),
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cpu_id(-1), mem(_mem), itb(_itb), dtb(_dtb), system(_sys),
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memctrl(_sys->memctrl), physmem(_sys->physmem),
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}
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#else
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ExecContext::ExecContext(BaseCPU *_cpu, int _thread_num, System *_system,
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FunctionalMemory *_mem, Process *_process, int _asid)
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Memory *_mem, Process *_process, int _asid)
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: _status(ExecContext::Unallocated),
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cpu(_cpu), thread_num(_thread_num), cpu_id(-1),
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system(_system), mem(_mem),
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@ -31,16 +31,11 @@
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#include <vector>
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#include "mem/mem_req.hh"
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class ExecContext;
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class PCEventQueue;
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class PCEvent
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{
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protected:
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static const Addr badpc = MemReq::inval_addr;
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protected:
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std::string description;
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PCEventQueue *queue;
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@ -102,17 +102,42 @@ SimpleCPU::CacheCompletionEvent::CacheCompletionEvent(SimpleCPU *_cpu)
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{
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}
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void SimpleCPU::CacheCompletionEvent::process()
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bool
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SimpleCPU::CpuPort::recvTiming(Packet &pkt)
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{
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cpu->processCacheCompletion();
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cpu->processResponse(pkt);
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return true;
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}
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const char *
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SimpleCPU::CacheCompletionEvent::description()
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Tick
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SimpleCPU::CpuPort::recvAtomic(Packet &pkt)
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{
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return "SimpleCPU cache completion event";
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panic("CPU doesn't expect callback!");
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return curTick;
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}
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void
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SimpleCPU::CpuPort::recvFunctional(Packet &pkt)
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{
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panic("CPU doesn't expect callback!");
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}
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void
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SimpleCPU::CpuPort::recvStatusChange(Status status)
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{
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cpu->recvStatusChange(status);
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}
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Packet *
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SimpleCPU::CpuPort::recvRetry()
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{
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return cpu->processRetry();
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}
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SimpleCPU::SimpleCPU(Params *p)
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: BaseCPU(p), tickEvent(this, p->width), xc(NULL),
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cacheCompletionEvent(this), dcachePort(this), icachePort(this)
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@ -697,9 +722,9 @@ SimpleCPU::sendDcacheRequest()
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void
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SimpleCPU::processResponse(Packet *response)
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{
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// For what things is the CPU the consumer of the packet it sent out?
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// This may create a memory leak if that's the case and it's expected of the
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// SimpleCPU to delete its own packet.
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// For what things is the CPU the consumer of the packet it sent
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// out? This may create a memory leak if that's the case and it's
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// expected of the SimpleCPU to delete its own packet.
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pkt = response;
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switch (status()) {
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@ -79,19 +79,15 @@ class SimpleCPU : public BaseCPU
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protected:
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virtual bool recvTiming(Packet &pkt)
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{ cpu->processCacheCompletion(pkt); return true; }
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virtual bool recvTiming(Packet &pkt);
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virtual Tick recvAtomic(Packet &pkt)
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{ panic("CPU doesn't expect callback!"); return curTick; }
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virtual Tick recvAtomic(Packet &pkt);
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virtual void recvFunctional(Packet &pkt)
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{ panic("CPU doesn't expect callback!"); }
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virtual void recvFunctional(Packet &pkt);
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virtual void recvStatusChange(Status status)
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{ cpu->recvStatusChange(status); }
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virtual void recvStatusChange(Status status);
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virtual Packet *recvRetry() { return cpu->processRetry(); }
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virtual Packet *recvRetry();
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};
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CpuPort icachePort;
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@ -121,7 +121,7 @@ class Port
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need to use two different ports.
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*/
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virtual void recvAddressRangesQuery(std::list<Range<Addr> > &range_list,
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bool &owner) = 0;
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bool &owner) { panic("??"); }
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public:
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|
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@ -54,6 +54,10 @@ const unsigned ALTMODE = 0x008;
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const unsigned UNCACHEABLE = 0x010;
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/** The request should not cause a page fault. */
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const unsigned NO_FAULT = 0x020;
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/** The request should be prefetched into the exclusive state. */
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const unsigned PF_EXCLUSIVE = 0x100;
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/** The request should be marked as LRU. */
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const unsigned EVICT_NEXT = 0x200;
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class Request
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{
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@ -42,8 +42,8 @@
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#include "encumbered/cpu/full/thread.hh"
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#include "encumbered/eio/eio.hh"
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#include "mem/page_table.hh"
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#include "mem/functional/physical.hh"
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#include "mem/functional/proxy.hh"
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#include "mem/memory.hh"
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#include "mem/proxy.hh"
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#include "sim/builder.hh"
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#include "sim/fake_syscall.hh"
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#include "sim/process.hh"
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|
@ -154,7 +154,7 @@ Process::startup()
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if (execContexts.empty())
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fatal("Process %s is not associated with any CPUs!\n", name());
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initVirtMem = new ProxyMemory<FunctionalMemory>(system->physmem, pTable);
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initVirtMem = new ProxyMemory<Memory>(system->physmem, pTable);
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// first exec context for this process... initialize & enable
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ExecContext *xc = execContexts[0];
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|
@ -245,7 +245,7 @@ DEFINE_SIM_OBJECT_CLASS_NAME("Process", Process)
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static void
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copyStringArray(vector<string> &strings, Addr array_ptr, Addr data_ptr,
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FunctionalMemory *func)
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Memory *func)
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{
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for (int i = 0; i < strings.size(); ++i) {
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func->prot_write(array_ptr, (uint8_t*)&data_ptr, sizeof(Addr));
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|
|
|
@ -43,7 +43,7 @@
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#include <sys/uio.h>
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#include "base/intmath.hh" // for RoundUp
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#include "mem/functional/functional.hh"
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#include "mem/port.hh"
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#include "targetarch/isa_traits.hh" // for Addr
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#include "base/trace.hh"
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|
@ -103,18 +103,18 @@ class BaseBufferArg {
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//
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// copy data into simulator space (read from target memory)
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//
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virtual bool copyIn(FunctionalMemory *mem)
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virtual bool copyIn(Port *memport)
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{
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mem->access(Read, addr, bufPtr, size);
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memport->readBlobFunctional(addr, bufPtr, size);
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return true; // no EFAULT detection for now
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}
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//
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// copy data out of simulator space (write to target memory)
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//
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virtual bool copyOut(FunctionalMemory *mem)
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virtual bool copyOut(Port *memport)
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{
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mem->access(Write, addr, bufPtr, size);
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memport->writeBlobFunctional(addr, bufPtr, size);
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return true; // no EFAULT detection for now
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}
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|
@ -314,7 +314,7 @@ openFunc(SyscallDesc *desc, int callnum, Process *process,
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{
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std::string path;
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|
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if (xc->mem->readString(path, xc->getSyscallArg(0)) != No_Fault)
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if (xc->mem->readStringFunctional(path, xc->getSyscallArg(0)) != No_Fault)
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return -EFAULT;
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|
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if (path == "/dev/sysdev0") {
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|
@ -361,7 +361,7 @@ chmodFunc(SyscallDesc *desc, int callnum, Process *process,
|
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{
|
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std::string path;
|
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|
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if (xc->mem->readString(path, xc->getSyscallArg(0)) != No_Fault)
|
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if (xc->mem->readStringFunctional(path, xc->getSyscallArg(0)) != No_Fault)
|
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return -EFAULT;
|
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|
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uint32_t mode = xc->getSyscallArg(1);
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|
@ -414,7 +414,7 @@ statFunc(SyscallDesc *desc, int callnum, Process *process,
|
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{
|
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std::string path;
|
||||
|
||||
if (xc->mem->readString(path, xc->getSyscallArg(0)) != No_Fault)
|
||||
if (xc->mem->readStringFunctional(path, xc->getSyscallArg(0)) != No_Fault)
|
||||
return -EFAULT;
|
||||
|
||||
struct stat hostBuf;
|
||||
|
@ -461,7 +461,7 @@ lstatFunc(SyscallDesc *desc, int callnum, Process *process,
|
|||
{
|
||||
std::string path;
|
||||
|
||||
if (xc->mem->readString(path, xc->getSyscallArg(0)) != No_Fault)
|
||||
if (xc->mem->readStringFunctional(path, xc->getSyscallArg(0)) != No_Fault)
|
||||
return -EFAULT;
|
||||
|
||||
struct stat hostBuf;
|
||||
|
@ -483,7 +483,7 @@ lstat64Func(SyscallDesc *desc, int callnum, Process *process,
|
|||
{
|
||||
std::string path;
|
||||
|
||||
if (xc->mem->readString(path, xc->getSyscallArg(0)) != No_Fault)
|
||||
if (xc->mem->readStringFunctional(path, xc->getSyscallArg(0)) != No_Fault)
|
||||
return -EFAULT;
|
||||
|
||||
struct stat64 hostBuf;
|
||||
|
@ -530,7 +530,7 @@ statfsFunc(SyscallDesc *desc, int callnum, Process *process,
|
|||
{
|
||||
std::string path;
|
||||
|
||||
if (xc->mem->readString(path, xc->getSyscallArg(0)) != No_Fault)
|
||||
if (xc->mem->readStringFunctional(path, xc->getSyscallArg(0)) != No_Fault)
|
||||
return -EFAULT;
|
||||
|
||||
struct statfs hostBuf;
|
||||
|
@ -700,7 +700,7 @@ utimesFunc(SyscallDesc *desc, int callnum, Process *process,
|
|||
{
|
||||
std::string path;
|
||||
|
||||
if (xc->mem->readString(path, xc->getSyscallArg(0)) != No_Fault)
|
||||
if (xc->mem->readStringFunctional(path, xc->getSyscallArg(0)) != No_Fault)
|
||||
return -EFAULT;
|
||||
|
||||
TypedBufferArg<typename OS::timeval [2]> tp(xc->getSyscallArg(1));
|
||||
|
|
|
@ -29,7 +29,7 @@
|
|||
#include "base/loader/object_file.hh"
|
||||
#include "base/loader/symtab.hh"
|
||||
#include "cpu/exec_context.hh"
|
||||
#include "mem/functional/physical.hh"
|
||||
#include "mem/memory.hh"
|
||||
#include "sim/builder.hh"
|
||||
#include "sim/system.hh"
|
||||
#include "base/trace.hh"
|
||||
|
@ -410,7 +410,7 @@ printSystems()
|
|||
|
||||
BEGIN_DECLARE_SIM_OBJECT_PARAMS(System)
|
||||
|
||||
SimObjectParam<PhysicalMemory *> physmem;
|
||||
SimObjectParam<Memory *> physmem;
|
||||
|
||||
#if FULL_SYSTEM
|
||||
Param<Tick> boot_cpu_frequency;
|
||||
|
|
|
@ -44,7 +44,7 @@ class BaseCPU;
|
|||
class ExecContext;
|
||||
class MemoryController;
|
||||
class ObjectFile;
|
||||
class PhysicalMemory;
|
||||
class Memory;
|
||||
|
||||
#if FULL_SYSTEM
|
||||
class Platform;
|
||||
|
@ -56,7 +56,7 @@ namespace Kernel { class Binning; }
|
|||
class System : public SimObject
|
||||
{
|
||||
public:
|
||||
PhysicalMemory *physmem;
|
||||
Memory *physmem;
|
||||
PCEventQueue pcEventQueue;
|
||||
|
||||
std::vector<ExecContext *> execContexts;
|
||||
|
@ -176,7 +176,7 @@ class System : public SimObject
|
|||
struct Params
|
||||
{
|
||||
std::string name;
|
||||
PhysicalMemory *physmem;
|
||||
Memory *physmem;
|
||||
|
||||
#if FULL_SYSTEM
|
||||
Tick boot_cpu_frequency;
|
||||
|
|
Loading…
Reference in a new issue