b8a2d1e5c7
fixing things, partly by ignoring CPU models that don't currently compile. SConscript: Split sources for fast, simple, and o3 CPU models into separate source lists. For now none of these are included in the base source list, so you won't get any CPU models at all... but we still can't compile the other stuff so it's not an issue. Also get rid of obsolete encumbered/mem file. base/loader/aout_object.cc: base/loader/aout_object.hh: base/loader/ecoff_object.cc: base/loader/ecoff_object.hh: base/loader/elf_object.cc: base/loader/elf_object.hh: base/loader/object_file.hh: cpu/exec_context.cc: sim/process.cc: sim/system.cc: sim/system.hh: FunctionalMemory -> Memory cpu/pc_event.hh: Get rid of unused badpc. cpu/simple/cpu.cc: cpu/simple/cpu.hh: Move Port functions into .cc file. mem/port.hh: Make recvAddressRangesQuery panic by default instead of being abstract... do CPUs need to implement this? mem/request.hh: Add prefetch flags. sim/syscall_emul.hh: Start to fix... --HG-- extra : convert_revision : ece53b3855f20916caaa381598ac37e8c7adfba7
1118 lines
28 KiB
C++
1118 lines
28 KiB
C++
/*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <cmath>
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#include <cstdio>
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#include <cstdlib>
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#include <iostream>
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#include <iomanip>
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#include <list>
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#include <sstream>
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#include <string>
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#include "base/cprintf.hh"
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#include "base/inifile.hh"
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#include "base/loader/symtab.hh"
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#include "base/misc.hh"
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#include "base/pollevent.hh"
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#include "base/range.hh"
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#include "base/stats/events.hh"
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#include "base/trace.hh"
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#include "cpu/base.hh"
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#include "cpu/exec_context.hh"
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#include "cpu/exetrace.hh"
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#include "cpu/profile.hh"
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#include "cpu/sampler/sampler.hh"
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#include "cpu/simple/cpu.hh"
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#include "cpu/smt.hh"
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#include "cpu/static_inst.hh"
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#include "kern/kernel_stats.hh"
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#include "mem/base_mem.hh"
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#include "mem/mem_interface.hh"
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#include "sim/builder.hh"
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#include "sim/debug.hh"
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#include "sim/host.hh"
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#include "sim/sim_events.hh"
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#include "sim/sim_object.hh"
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#include "sim/stats.hh"
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#if FULL_SYSTEM
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#include "base/remote_gdb.hh"
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#include "mem/functional/memory_control.hh"
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#include "mem/functional/physical.hh"
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#include "sim/system.hh"
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#include "targetarch/alpha_memory.hh"
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#include "targetarch/stacktrace.hh"
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#include "targetarch/vtophys.hh"
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#else // !FULL_SYSTEM
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#include "mem/functional/functional.hh"
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#endif // FULL_SYSTEM
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using namespace std;
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SimpleCPU::TickEvent::TickEvent(SimpleCPU *c, int w)
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: Event(&mainEventQueue, CPU_Tick_Pri), cpu(c), width(w)
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{
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}
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void
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SimpleCPU::TickEvent::process()
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{
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int count = width;
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do {
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cpu->tick();
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} while (--count > 0 && cpu->status() == Running);
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}
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const char *
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SimpleCPU::TickEvent::description()
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{
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return "SimpleCPU tick event";
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}
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SimpleCPU::CacheCompletionEvent::CacheCompletionEvent(SimpleCPU *_cpu)
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: Event(&mainEventQueue), cpu(_cpu)
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{
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}
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bool
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SimpleCPU::CpuPort::recvTiming(Packet &pkt)
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{
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cpu->processResponse(pkt);
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return true;
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}
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Tick
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SimpleCPU::CpuPort::recvAtomic(Packet &pkt)
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{
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panic("CPU doesn't expect callback!");
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return curTick;
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}
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void
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SimpleCPU::CpuPort::recvFunctional(Packet &pkt)
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{
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panic("CPU doesn't expect callback!");
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}
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void
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SimpleCPU::CpuPort::recvStatusChange(Status status)
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{
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cpu->recvStatusChange(status);
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}
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Packet *
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SimpleCPU::CpuPort::recvRetry()
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{
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return cpu->processRetry();
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}
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SimpleCPU::SimpleCPU(Params *p)
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: BaseCPU(p), tickEvent(this, p->width), xc(NULL),
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cacheCompletionEvent(this), dcachePort(this), icachePort(this)
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{
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_status = Idle;
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#if FULL_SYSTEM
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xc = new ExecContext(this, 0, p->system, p->itb, p->dtb, p->mem);
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// initialize CPU, including PC
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TheISA::initCPU(&xc->regs);
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#else
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xc = new ExecContext(this, /* thread_num */ 0, p->process, /* asid */ 0);
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#endif // !FULL_SYSTEM
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req = new CpuRequest;
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req->asid = 0;
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numInst = 0;
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startNumInst = 0;
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numLoad = 0;
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startNumLoad = 0;
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lastIcacheStall = 0;
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lastDcacheStall = 0;
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execContexts.push_back(xc);
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}
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SimpleCPU::~SimpleCPU()
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{
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}
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void
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SimpleCPU::switchOut(Sampler *s)
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{
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sampler = s;
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if (status() == DcacheWaitResponse) {
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DPRINTF(Sampler,"Outstanding dcache access, waiting for completion\n");
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_status = DcacheWaitSwitch;
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}
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else {
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_status = SwitchedOut;
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if (tickEvent.scheduled())
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tickEvent.squash();
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sampler->signalSwitched();
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}
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}
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void
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SimpleCPU::takeOverFrom(BaseCPU *oldCPU)
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{
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BaseCPU::takeOverFrom(oldCPU);
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assert(!tickEvent.scheduled());
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// if any of this CPU's ExecContexts are active, mark the CPU as
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// running and schedule its tick event.
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for (int i = 0; i < execContexts.size(); ++i) {
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ExecContext *xc = execContexts[i];
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if (xc->status() == ExecContext::Active && _status != Running) {
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_status = Running;
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tickEvent.schedule(curTick);
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}
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}
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}
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void
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SimpleCPU::activateContext(int thread_num, int delay)
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{
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assert(thread_num == 0);
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assert(xc);
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assert(_status == Idle);
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notIdleFraction++;
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scheduleTickEvent(delay);
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_status = Running;
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}
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void
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SimpleCPU::suspendContext(int thread_num)
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{
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assert(thread_num == 0);
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assert(xc);
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assert(_status == Running);
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notIdleFraction--;
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unscheduleTickEvent();
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_status = Idle;
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}
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void
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SimpleCPU::deallocateContext(int thread_num)
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{
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// for now, these are equivalent
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suspendContext(thread_num);
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}
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void
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SimpleCPU::haltContext(int thread_num)
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{
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// for now, these are equivalent
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suspendContext(thread_num);
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}
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void
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SimpleCPU::regStats()
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{
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using namespace Stats;
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BaseCPU::regStats();
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numInsts
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.name(name() + ".num_insts")
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.desc("Number of instructions executed")
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;
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numMemRefs
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.name(name() + ".num_refs")
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.desc("Number of memory references")
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;
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notIdleFraction
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.name(name() + ".not_idle_fraction")
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.desc("Percentage of non-idle cycles")
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;
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idleFraction
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.name(name() + ".idle_fraction")
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.desc("Percentage of idle cycles")
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;
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icacheStallCycles
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.name(name() + ".icache_stall_cycles")
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.desc("ICache total stall cycles")
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.prereq(icacheStallCycles)
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;
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dcacheStallCycles
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.name(name() + ".dcache_stall_cycles")
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.desc("DCache total stall cycles")
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.prereq(dcacheStallCycles)
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;
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icacheRetryCycles
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.name(name() + ".icache_retry_cycles")
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.desc("ICache total retry cycles")
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.prereq(icacheRetryCycles)
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;
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dcacheRetryCycles
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.name(name() + ".dcache_retry_cycles")
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.desc("DCache total retry cycles")
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.prereq(dcacheRetryCycles)
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;
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idleFraction = constant(1.0) - notIdleFraction;
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}
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void
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SimpleCPU::resetStats()
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{
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startNumInst = numInst;
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notIdleFraction = (_status != Idle);
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}
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void
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SimpleCPU::serialize(ostream &os)
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{
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BaseCPU::serialize(os);
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SERIALIZE_ENUM(_status);
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SERIALIZE_SCALAR(inst);
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nameOut(os, csprintf("%s.xc", name()));
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xc->serialize(os);
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nameOut(os, csprintf("%s.tickEvent", name()));
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tickEvent.serialize(os);
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nameOut(os, csprintf("%s.cacheCompletionEvent", name()));
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cacheCompletionEvent.serialize(os);
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}
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void
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SimpleCPU::unserialize(Checkpoint *cp, const string §ion)
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{
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BaseCPU::unserialize(cp, section);
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UNSERIALIZE_ENUM(_status);
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UNSERIALIZE_SCALAR(inst);
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xc->unserialize(cp, csprintf("%s.xc", section));
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tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
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cacheCompletionEvent
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.unserialize(cp, csprintf("%s.cacheCompletionEvent", section));
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}
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void
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change_thread_state(int thread_number, int activate, int priority)
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{
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}
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Fault
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SimpleCPU::copySrcTranslate(Addr src)
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{
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#if 0
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static bool no_warn = true;
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int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
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// Only support block sizes of 64 atm.
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assert(blk_size == 64);
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int offset = src & (blk_size - 1);
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// Make sure block doesn't span page
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if (no_warn &&
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(src & TheISA::PageMask) != ((src + blk_size) & TheISA::PageMask) &&
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(src >> 40) != 0xfffffc) {
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warn("Copied block source spans pages %x.", src);
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no_warn = false;
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}
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memReq->reset(src & ~(blk_size - 1), blk_size);
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// translate to physical address
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Fault fault = xc->translateDataReadReq(memReq);
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assert(fault != Alignment_Fault);
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if (fault == No_Fault) {
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xc->copySrcAddr = src;
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xc->copySrcPhysAddr = memReq->paddr + offset;
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} else {
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xc->copySrcAddr = 0;
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xc->copySrcPhysAddr = 0;
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}
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return fault;
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#else
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return No_Fault
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#endif
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}
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Fault
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SimpleCPU::copy(Addr dest)
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{
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#if 0
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static bool no_warn = true;
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int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
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// Only support block sizes of 64 atm.
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assert(blk_size == 64);
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uint8_t data[blk_size];
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//assert(xc->copySrcAddr);
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int offset = dest & (blk_size - 1);
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// Make sure block doesn't span page
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if (no_warn &&
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(dest & TheISA::PageMask) != ((dest + blk_size) & TheISA::PageMask) &&
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(dest >> 40) != 0xfffffc) {
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no_warn = false;
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warn("Copied block destination spans pages %x. ", dest);
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}
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memReq->reset(dest & ~(blk_size -1), blk_size);
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// translate to physical address
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Fault fault = xc->translateDataWriteReq(memReq);
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assert(fault != Alignment_Fault);
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if (fault == No_Fault) {
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Addr dest_addr = memReq->paddr + offset;
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// Need to read straight from memory since we have more than 8 bytes.
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memReq->paddr = xc->copySrcPhysAddr;
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xc->mem->read(memReq, data);
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memReq->paddr = dest_addr;
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xc->mem->write(memReq, data);
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if (dcacheInterface) {
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memReq->cmd = Copy;
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memReq->completionEvent = NULL;
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memReq->paddr = xc->copySrcPhysAddr;
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memReq->dest = dest_addr;
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memReq->size = 64;
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memReq->time = curTick;
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memReq->flags &= ~INST_READ;
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dcacheInterface->access(memReq);
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}
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}
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return fault;
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#else
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return No_Fault;
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#endif
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}
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// precise architected memory state accessor macros
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template <class T>
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Fault
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SimpleCPU::read(Addr addr, T &data, unsigned flags)
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{
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if (status() == DcacheWaitResponse || status() == DcacheWaitSwitch) {
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// Fault fault = xc->read(memReq,data);
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// Not sure what to check for no fault...
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if (pkt->result == Success) {
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memcpy(&data, pkt->data, sizeof(T));
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}
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if (traceData) {
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traceData->setAddr(addr);
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}
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// @todo: Figure out a way to create a Fault from the packet result.
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return No_Fault;
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}
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// memReq->reset(addr, sizeof(T), flags);
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// translate to physical address
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// NEED NEW TRANSLATION HERE
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Fault fault = xc->translateDataReadReq(memReq);
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// Now do the access.
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if (fault == No_Fault) {
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pkt = new Packet;
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pkt->cmd = Read;
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req->paddr = addr;
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pkt->size = sizeof(T);
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pkt->req = req;
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sendDcacheRequest();
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}
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/*
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memReq->cmd = Read;
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memReq->completionEvent = NULL;
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memReq->time = curTick;
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memReq->flags &= ~INST_READ;
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MemAccessResult result = dcacheInterface->access(memReq);
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|
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// Ugly hack to get an event scheduled *only* if the access is
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// a miss. We really should add first-class support for this
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// at some point.
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if (result != MA_HIT && dcacheInterface->doEvents()) {
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memReq->completionEvent = &cacheCompletionEvent;
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lastDcacheStall = curTick;
|
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unscheduleTickEvent();
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_status = DcacheMissStall;
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} else {
|
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// do functional access
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fault = xc->read(memReq, data);
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}
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} else if(fault == No_Fault) {
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// do functional access
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fault = xc->read(memReq, data);
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}
|
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*/
|
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// This will need a new way to tell if it has a dcache attached.
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if (/*!dcacheInterface && */(memReq->flags & UNCACHEABLE))
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recordEvent("Uncached Read");
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return fault;
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}
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|
|
#ifndef DOXYGEN_SHOULD_SKIP_THIS
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|
|
|
template
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|
Fault
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SimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
|
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|
|
template
|
|
Fault
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SimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
|
|
|
|
template
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|
Fault
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SimpleCPU::read(Addr addr, uint16_t &data, unsigned flags);
|
|
|
|
template
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Fault
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SimpleCPU::read(Addr addr, uint8_t &data, unsigned flags);
|
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|
|
#endif //DOXYGEN_SHOULD_SKIP_THIS
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|
|
|
template<>
|
|
Fault
|
|
SimpleCPU::read(Addr addr, double &data, unsigned flags)
|
|
{
|
|
return read(addr, *(uint64_t*)&data, flags);
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|
}
|
|
|
|
template<>
|
|
Fault
|
|
SimpleCPU::read(Addr addr, float &data, unsigned flags)
|
|
{
|
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return read(addr, *(uint32_t*)&data, flags);
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}
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|
|
|
|
template<>
|
|
Fault
|
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SimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
|
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{
|
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return read(addr, (uint32_t&)data, flags);
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}
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|
|
|
|
template <class T>
|
|
Fault
|
|
SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
|
|
{
|
|
// memReq->reset(addr, sizeof(T), flags);
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|
req->vaddr = addr;
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|
req->time = curTick;
|
|
req->size = sizeof(T);
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|
|
// translate to physical address
|
|
// NEED NEW TRANSLATION HERE
|
|
Fault fault = xc->translateDataWriteReq(memReq);
|
|
|
|
// Now do the access.
|
|
if (fault == No_Fault) {
|
|
pkt = new Packet;
|
|
pkt->cmd = Write;
|
|
pkt->size = sizeof(T);
|
|
pkt->req = req;
|
|
|
|
// Copy data into the packet.
|
|
pkt->data = new uint8_t[64];
|
|
memcpy(pkt->data, &data, sizeof(T));
|
|
|
|
sendDcacheRequest();
|
|
}
|
|
|
|
/*
|
|
// do functional access
|
|
if (fault == No_Fault)
|
|
fault = xc->write(memReq, data);
|
|
|
|
if (fault == No_Fault && dcacheInterface) {
|
|
memReq->cmd = Write;
|
|
memcpy(memReq->data,(uint8_t *)&data,memReq->size);
|
|
memReq->completionEvent = NULL;
|
|
memReq->time = curTick;
|
|
memReq->flags &= ~INST_READ;
|
|
MemAccessResult result = dcacheInterface->access(memReq);
|
|
|
|
// Ugly hack to get an event scheduled *only* if the access is
|
|
// a miss. We really should add first-class support for this
|
|
// at some point.
|
|
if (result != MA_HIT && dcacheInterface->doEvents()) {
|
|
memReq->completionEvent = &cacheCompletionEvent;
|
|
lastDcacheStall = curTick;
|
|
unscheduleTickEvent();
|
|
_status = DcacheMissStall;
|
|
}
|
|
}
|
|
*/
|
|
if (res && (fault == No_Fault))
|
|
*res = memReq->result;
|
|
|
|
// This will need a new way to tell if it's hooked up to a cache or not.
|
|
if (/*!dcacheInterface && */(memReq->flags & UNCACHEABLE))
|
|
recordEvent("Uncached Write");
|
|
|
|
// If the write needs to have a fault on the access, consider calling
|
|
// changeStatus() and changing it to "bad addr write" or something.
|
|
return fault;
|
|
}
|
|
|
|
|
|
#ifndef DOXYGEN_SHOULD_SKIP_THIS
|
|
template
|
|
Fault
|
|
SimpleCPU::write(uint64_t data, Addr addr, unsigned flags, uint64_t *res);
|
|
|
|
template
|
|
Fault
|
|
SimpleCPU::write(uint32_t data, Addr addr, unsigned flags, uint64_t *res);
|
|
|
|
template
|
|
Fault
|
|
SimpleCPU::write(uint16_t data, Addr addr, unsigned flags, uint64_t *res);
|
|
|
|
template
|
|
Fault
|
|
SimpleCPU::write(uint8_t data, Addr addr, unsigned flags, uint64_t *res);
|
|
|
|
#endif //DOXYGEN_SHOULD_SKIP_THIS
|
|
|
|
template<>
|
|
Fault
|
|
SimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
|
|
{
|
|
return write(*(uint64_t*)&data, addr, flags, res);
|
|
}
|
|
|
|
template<>
|
|
Fault
|
|
SimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
|
|
{
|
|
return write(*(uint32_t*)&data, addr, flags, res);
|
|
}
|
|
|
|
|
|
template<>
|
|
Fault
|
|
SimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
|
|
{
|
|
return write((uint32_t)data, addr, flags, res);
|
|
}
|
|
|
|
|
|
#if FULL_SYSTEM
|
|
Addr
|
|
SimpleCPU::dbg_vtophys(Addr addr)
|
|
{
|
|
return vtophys(xc, addr);
|
|
}
|
|
#endif // FULL_SYSTEM
|
|
|
|
void
|
|
SimpleCPU::sendIcacheRequest()
|
|
{
|
|
#if 1
|
|
bool success = icachePort.sendTiming(pkt);
|
|
|
|
unscheduleTickEvent();
|
|
|
|
lastIcacheStall = curTick;
|
|
|
|
if (!success) {
|
|
// Need to wait for retry
|
|
_status = IcacheRetry;
|
|
} else {
|
|
// Need to wait for cache to respond
|
|
_status = IcacheWaitResponse;
|
|
}
|
|
#else
|
|
Tick latency = icachePort.sendAtomic(pkt);
|
|
|
|
unscheduleTickEvent();
|
|
scheduleTickEvent(latency);
|
|
|
|
// Note that Icache miss cycles will be incorrect. Unless
|
|
// we check the status of the packet sent (is this valid?),
|
|
// we won't know if the latency is a hit or a miss.
|
|
icacheStallCycles += latency;
|
|
|
|
_status = IcacheAccessComplete;
|
|
#endif
|
|
}
|
|
|
|
void
|
|
SimpleCPU::sendDcacheRequest()
|
|
{
|
|
unscheduleTickEvent();
|
|
|
|
#if 1
|
|
bool success = dcachePort.sendTiming(pkt);
|
|
|
|
lastDcacheStall = curTick;
|
|
|
|
if (!success) {
|
|
_status = DcacheRetry;
|
|
} else {
|
|
_status = DcacheWaitResponse;
|
|
}
|
|
#else
|
|
Tick latency = dcachePort.sendAtomic(pkt);
|
|
|
|
scheduleTickEvent(latency);
|
|
|
|
// Note that Dcache miss cycles will be incorrect. Unless
|
|
// we check the status of the packet sent (is this valid?),
|
|
// we won't know if the latency is a hit or a miss.
|
|
dcacheStallCycles += latency;
|
|
|
|
// Delete the packet right here?
|
|
delete pkt;
|
|
#endif
|
|
}
|
|
|
|
void
|
|
SimpleCPU::processResponse(Packet *response)
|
|
{
|
|
// For what things is the CPU the consumer of the packet it sent
|
|
// out? This may create a memory leak if that's the case and it's
|
|
// expected of the SimpleCPU to delete its own packet.
|
|
pkt = response;
|
|
|
|
switch (status()) {
|
|
case IcacheWaitResponse:
|
|
icacheStallCycles += curTick - lastIcacheStall;
|
|
|
|
_status = IcacheAccessComplete;
|
|
scheduleTickEvent(1);
|
|
|
|
// Copy the icache data into the instruction itself.
|
|
memcpy(&inst, pkt->data, sizeof(inst));
|
|
|
|
delete pkt;
|
|
break;
|
|
case DcacheWaitResponse:
|
|
if (req->cmd.isRead()) {
|
|
curStaticInst->execute(this,traceData);
|
|
if (traceData)
|
|
traceData->finalize();
|
|
}
|
|
|
|
delete pkt;
|
|
|
|
dcacheStallCycles += curTick - lastDcacheStall;
|
|
_status = Running;
|
|
scheduleTickEvent(1);
|
|
break;
|
|
case DcacheWaitSwitch:
|
|
if (memReq->cmd.isRead()) {
|
|
curStaticInst->execute(this,traceData);
|
|
if (traceData)
|
|
traceData->finalize();
|
|
}
|
|
|
|
delete pkt;
|
|
|
|
_status = SwitchedOut;
|
|
sampler->signalSwitched();
|
|
case SwitchedOut:
|
|
// If this CPU has been switched out due to sampling/warm-up,
|
|
// ignore any further status changes (e.g., due to cache
|
|
// misses outstanding at the time of the switch).
|
|
delete pkt;
|
|
|
|
return;
|
|
default:
|
|
panic("SimpleCPU::processCacheCompletion: bad state");
|
|
break;
|
|
}
|
|
}
|
|
|
|
Packet *
|
|
SimpleCPU::processRetry()
|
|
{
|
|
switch(status()) {
|
|
case IcacheRetry:
|
|
icacheRetryCycles += curTick - lastIcacheStall;
|
|
return pkt;
|
|
break;
|
|
case DcacheRetry:
|
|
dcacheRetryCycles += curTick - lastDcacheStall;
|
|
return pkt;
|
|
break;
|
|
default:
|
|
panic("SimpleCPU::processRetry: bad state");
|
|
break;
|
|
}
|
|
}
|
|
|
|
#if FULL_SYSTEM
|
|
void
|
|
SimpleCPU::post_interrupt(int int_num, int index)
|
|
{
|
|
BaseCPU::post_interrupt(int_num, index);
|
|
|
|
if (xc->status() == ExecContext::Suspended) {
|
|
DPRINTF(IPI,"Suspended Processor awoke\n");
|
|
xc->activate();
|
|
}
|
|
}
|
|
#endif // FULL_SYSTEM
|
|
|
|
/* start simulation, program loaded, processor precise state initialized */
|
|
void
|
|
SimpleCPU::tick()
|
|
{
|
|
numCycles++;
|
|
|
|
traceData = NULL;
|
|
|
|
Fault fault = No_Fault;
|
|
|
|
#if FULL_SYSTEM
|
|
if (checkInterrupts && check_interrupts() && !xc->inPalMode() &&
|
|
status() != IcacheMissComplete) {
|
|
int ipl = 0;
|
|
int summary = 0;
|
|
checkInterrupts = false;
|
|
IntReg *ipr = xc->regs.ipr;
|
|
|
|
if (xc->regs.ipr[TheISA::IPR_SIRR]) {
|
|
for (int i = TheISA::INTLEVEL_SOFTWARE_MIN;
|
|
i < TheISA::INTLEVEL_SOFTWARE_MAX; i++) {
|
|
if (ipr[TheISA::IPR_SIRR] & (ULL(1) << i)) {
|
|
// See table 4-19 of 21164 hardware reference
|
|
ipl = (i - TheISA::INTLEVEL_SOFTWARE_MIN) + 1;
|
|
summary |= (ULL(1) << i);
|
|
}
|
|
}
|
|
}
|
|
|
|
uint64_t interrupts = xc->cpu->intr_status();
|
|
for (int i = TheISA::INTLEVEL_EXTERNAL_MIN;
|
|
i < TheISA::INTLEVEL_EXTERNAL_MAX; i++) {
|
|
if (interrupts & (ULL(1) << i)) {
|
|
// See table 4-19 of 21164 hardware reference
|
|
ipl = i;
|
|
summary |= (ULL(1) << i);
|
|
}
|
|
}
|
|
|
|
if (ipr[TheISA::IPR_ASTRR])
|
|
panic("asynchronous traps not implemented\n");
|
|
|
|
if (ipl && ipl > xc->regs.ipr[TheISA::IPR_IPLR]) {
|
|
ipr[TheISA::IPR_ISR] = summary;
|
|
ipr[TheISA::IPR_INTID] = ipl;
|
|
xc->ev5_trap(Interrupt_Fault);
|
|
|
|
DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
|
|
ipr[TheISA::IPR_IPLR], ipl, summary);
|
|
}
|
|
}
|
|
#endif
|
|
|
|
// maintain $r0 semantics
|
|
xc->regs.intRegFile[ZeroReg] = 0;
|
|
#ifdef TARGET_ALPHA
|
|
xc->regs.floatRegFile.d[ZeroReg] = 0.0;
|
|
#endif // TARGET_ALPHA
|
|
|
|
if (status() == IcacheAccessComplete) {
|
|
// We've already fetched an instruction and were stalled on an
|
|
// I-cache miss. No need to fetch it again.
|
|
|
|
// Set status to running; tick event will get rescheduled if
|
|
// necessary at end of tick() function.
|
|
_status = Running;
|
|
} else {
|
|
// Try to fetch an instruction
|
|
|
|
// set up memory request for instruction fetch
|
|
#if FULL_SYSTEM
|
|
#define IFETCH_FLAGS(pc) ((pc) & 1) ? PHYSICAL : 0
|
|
#else
|
|
#define IFETCH_FLAGS(pc) 0
|
|
#endif
|
|
|
|
req->vaddr = xc->regs.pc & ~3;
|
|
req->time = curTick;
|
|
req->size = sizeof(MachInst);
|
|
|
|
/* memReq->reset(xc->regs.pc & ~3, sizeof(uint32_t),
|
|
IFETCH_FLAGS(xc->regs.pc));
|
|
*/
|
|
//NEED NEW TRANSLATION HERE
|
|
fault = xc->translateInstReq(memReq);
|
|
|
|
if (fault == No_Fault) {
|
|
pkt = new Packet;
|
|
pkt->cmd = Read;
|
|
pkt->addr = req->paddr;
|
|
pkt->size = sizeof(MachInst);
|
|
pkt->req = req;
|
|
|
|
sendIcacheRequest();
|
|
/* fault = xc->mem->read(memReq, inst);
|
|
|
|
if (icacheInterface && fault == No_Fault) {
|
|
memReq->completionEvent = NULL;
|
|
|
|
memReq->time = curTick;
|
|
memReq->flags |= INST_READ;
|
|
MemAccessResult result = icacheInterface->access(memReq);
|
|
|
|
// Ugly hack to get an event scheduled *only* if the access is
|
|
// a miss. We really should add first-class support for this
|
|
// at some point.
|
|
if (result != MA_HIT && icacheInterface->doEvents()) {
|
|
memReq->completionEvent = &cacheCompletionEvent;
|
|
lastIcacheStall = curTick;
|
|
unscheduleTickEvent();
|
|
_status = IcacheMissStall;
|
|
return;
|
|
}
|
|
}
|
|
*/
|
|
}
|
|
}
|
|
|
|
// If we've got a valid instruction (i.e., no fault on instruction
|
|
// fetch), then execute it.
|
|
if (fault == No_Fault) {
|
|
|
|
// keep an instruction count
|
|
numInst++;
|
|
numInsts++;
|
|
|
|
// check for instruction-count-based events
|
|
comInstEventQueue[0]->serviceEvents(numInst);
|
|
|
|
// decode the instruction
|
|
inst = gtoh(inst);
|
|
curStaticInst = StaticInst<TheISA>::decode(inst);
|
|
|
|
traceData = Trace::getInstRecord(curTick, xc, this, curStaticInst,
|
|
xc->regs.pc);
|
|
|
|
#if FULL_SYSTEM
|
|
xc->setInst(inst);
|
|
#endif // FULL_SYSTEM
|
|
|
|
xc->func_exe_inst++;
|
|
|
|
fault = curStaticInst->execute(this, traceData);
|
|
|
|
#if FULL_SYSTEM
|
|
if (xc->fnbin) {
|
|
assert(xc->kernelStats);
|
|
system->kernelBinning->execute(xc, inst);
|
|
}
|
|
|
|
if (xc->profile) {
|
|
bool usermode = (xc->regs.ipr[AlphaISA::IPR_DTB_CM] & 0x18) != 0;
|
|
xc->profilePC = usermode ? 1 : xc->regs.pc;
|
|
ProfileNode *node = xc->profile->consume(xc, inst);
|
|
if (node)
|
|
xc->profileNode = node;
|
|
}
|
|
#endif
|
|
|
|
if (curStaticInst->isMemRef()) {
|
|
numMemRefs++;
|
|
}
|
|
|
|
if (curStaticInst->isLoad()) {
|
|
++numLoad;
|
|
comLoadEventQueue[0]->serviceEvents(numLoad);
|
|
}
|
|
|
|
// If we have a dcache miss, then we can't finialize the instruction
|
|
// trace yet because we want to populate it with the data later
|
|
if (traceData &&
|
|
!(status() == DcacheWaitResponse && memReq->cmd.isRead())) {
|
|
traceData->finalize();
|
|
}
|
|
|
|
traceFunctions(xc->regs.pc);
|
|
|
|
} // if (fault == No_Fault)
|
|
|
|
if (fault != No_Fault) {
|
|
#if FULL_SYSTEM
|
|
xc->ev5_trap(fault);
|
|
#else // !FULL_SYSTEM
|
|
fatal("fault (%d) detected @ PC 0x%08p", fault, xc->regs.pc);
|
|
#endif // FULL_SYSTEM
|
|
}
|
|
else {
|
|
// go to the next instruction
|
|
xc->regs.pc = xc->regs.npc;
|
|
xc->regs.npc += sizeof(MachInst);
|
|
}
|
|
|
|
#if FULL_SYSTEM
|
|
Addr oldpc;
|
|
do {
|
|
oldpc = xc->regs.pc;
|
|
system->pcEventQueue.service(xc);
|
|
} while (oldpc != xc->regs.pc);
|
|
#endif
|
|
|
|
assert(status() == Running ||
|
|
status() == Idle ||
|
|
status() == DcacheWaitResponse);
|
|
|
|
if (status() == Running && !tickEvent.scheduled())
|
|
tickEvent.schedule(curTick + cycles(1));
|
|
}
|
|
|
|
////////////////////////////////////////////////////////////////////////
|
|
//
|
|
// SimpleCPU Simulation Object
|
|
//
|
|
BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU)
|
|
|
|
Param<Counter> max_insts_any_thread;
|
|
Param<Counter> max_insts_all_threads;
|
|
Param<Counter> max_loads_any_thread;
|
|
Param<Counter> max_loads_all_threads;
|
|
|
|
#if FULL_SYSTEM
|
|
SimObjectParam<AlphaITB *> itb;
|
|
SimObjectParam<AlphaDTB *> dtb;
|
|
SimObjectParam<FunctionalMemory *> mem;
|
|
SimObjectParam<System *> system;
|
|
Param<int> cpu_id;
|
|
Param<Tick> profile;
|
|
#else
|
|
SimObjectParam<Process *> workload;
|
|
#endif // FULL_SYSTEM
|
|
|
|
Param<int> clock;
|
|
SimObjectParam<BaseMem *> icache;
|
|
SimObjectParam<BaseMem *> dcache;
|
|
|
|
Param<bool> defer_registration;
|
|
Param<int> width;
|
|
Param<bool> function_trace;
|
|
Param<Tick> function_trace_start;
|
|
|
|
END_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU)
|
|
|
|
BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleCPU)
|
|
|
|
INIT_PARAM(max_insts_any_thread,
|
|
"terminate when any thread reaches this inst count"),
|
|
INIT_PARAM(max_insts_all_threads,
|
|
"terminate when all threads have reached this inst count"),
|
|
INIT_PARAM(max_loads_any_thread,
|
|
"terminate when any thread reaches this load count"),
|
|
INIT_PARAM(max_loads_all_threads,
|
|
"terminate when all threads have reached this load count"),
|
|
|
|
#if FULL_SYSTEM
|
|
INIT_PARAM(itb, "Instruction TLB"),
|
|
INIT_PARAM(dtb, "Data TLB"),
|
|
INIT_PARAM(mem, "memory"),
|
|
INIT_PARAM(system, "system object"),
|
|
INIT_PARAM(cpu_id, "processor ID"),
|
|
INIT_PARAM(profile, ""),
|
|
#else
|
|
INIT_PARAM(workload, "processes to run"),
|
|
#endif // FULL_SYSTEM
|
|
|
|
INIT_PARAM(clock, "clock speed"),
|
|
INIT_PARAM(icache, "L1 instruction cache object"),
|
|
INIT_PARAM(dcache, "L1 data cache object"),
|
|
INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
|
|
INIT_PARAM(width, "cpu width"),
|
|
INIT_PARAM(function_trace, "Enable function trace"),
|
|
INIT_PARAM(function_trace_start, "Cycle to start function trace")
|
|
|
|
END_INIT_SIM_OBJECT_PARAMS(SimpleCPU)
|
|
|
|
|
|
CREATE_SIM_OBJECT(SimpleCPU)
|
|
{
|
|
SimpleCPU::Params *params = new SimpleCPU::Params();
|
|
params->name = getInstanceName();
|
|
params->numberOfThreads = 1;
|
|
params->max_insts_any_thread = max_insts_any_thread;
|
|
params->max_insts_all_threads = max_insts_all_threads;
|
|
params->max_loads_any_thread = max_loads_any_thread;
|
|
params->max_loads_all_threads = max_loads_all_threads;
|
|
params->deferRegistration = defer_registration;
|
|
params->clock = clock;
|
|
params->functionTrace = function_trace;
|
|
params->functionTraceStart = function_trace_start;
|
|
params->icache_interface = (icache) ? icache->getInterface() : NULL;
|
|
params->dcache_interface = (dcache) ? dcache->getInterface() : NULL;
|
|
params->width = width;
|
|
|
|
#if FULL_SYSTEM
|
|
params->itb = itb;
|
|
params->dtb = dtb;
|
|
params->mem = mem;
|
|
params->system = system;
|
|
params->cpu_id = cpu_id;
|
|
params->profile = profile;
|
|
#else
|
|
params->process = workload;
|
|
#endif
|
|
|
|
SimpleCPU *cpu = new SimpleCPU(params);
|
|
return cpu;
|
|
}
|
|
|
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REGISTER_SIM_OBJECT("SimpleCPU", SimpleCPU)
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