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Bunch of little changes for tracking copies and getting OPT right.

Browse source 
cpu/simple_cpu/simple_cpu.cc:
    Send Copy
cpu/trace/opt_cpu.cc:
    Calculate the block size correctly. Set lookupTable value directly, since the old way only worked for FA caches.
cpu/trace/trace_cpu.cc:
    Don't start events if the hierarchy is in non-event mode.

--HG--
extra : convert_revision : daf2db5ed7428c2fb08652cf76f6fe99d8357db5
This commit is contained in:
Erik Hallnor 2004-10-17 00:07:21 -04:00
parent 800d970c26
commit 867a9b84d9
3 changed files with 41 additions and 10 deletions
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9
cpu/simple_cpu/simple_cpu.cc
View file

@ -400,6 +400,15 @@ SimpleCPU::copy(Addr dest)
xc->mem->read(memReq, data);
memReq->paddr = dest_addr;
xc->mem->write(memReq, data);
if (dcacheInterface) {
memReq->cmd = Copy;
memReq->completionEvent = NULL;
memReq->paddr = xc->copySrcPhysAddr;
memReq->dest = dest_addr;
memReq->size = 64;
memReq->time = curTick;
dcacheInterface->access(memReq);
}
}
return fault;
}

19
cpu/trace/opt_cpu.cc
View file

@ -52,7 +52,13 @@ OptCPU::OptCPU(const string &name,
numBlks(cache_size/block_size), assoc(_assoc), numSets(numBlks/assoc),
setMask(numSets - 1)
{
int log_block_size = (int)(log((double) block_size)/log(2.0));
int log_block_size = 0;
int tmp_block_size = block_size;
while (tmp_block_size > 1) {
++log_block_size;
tmp_block_size = tmp_block_size >> 1;
}
assert(1<<log_block_size == block_size);
MemReqPtr req;
trace->getNextReq(req);
refInfo.resize(numSets);
@ -124,7 +130,7 @@ OptCPU::processSet(int set)
for (int start = assoc/2; start >= 0; --start) {
heapify(set,start);
}
verifyHeap(set,0);
//verifyHeap(set,0);
for (; i < refInfo[set].size(); ++i) {
RefIndex cache_index = lookupValue(refInfo[set][i].addr);
@ -134,8 +140,11 @@ OptCPU::processSet(int set)
// replace from cacheHeap[0]
// mark replaced block as absent
setValue(refInfo[set][cacheHeap[0]].addr, -1);
setValue(refInfo[set][i].addr, 0);
cacheHeap[0] = i;
heapify(set, 0);
// Make sure its in the cache
assert(lookupValue(refInfo[set][i].addr) != -1);
} else {
// hit
hits++;
@ -143,9 +152,11 @@ OptCPU::processSet(int set)
refInfo[set][i].addr);
assert(refInfo[set][cacheHeap[cache_index]].nextRefTime == i);
assert(heapLeft(cache_index) >= assoc);
cacheHeap[cache_index] = i;
processRankIncrease(set, cache_index);
assert(lookupValue(refInfo[set][i].addr) != -1);
}
cacheHeap[cache_index] = i;
processRankIncrease(set, cache_index);
}
}
void

23
cpu/trace/trace_cpu.cc
View file

@ -75,9 +75,14 @@ TraceCPU::tick()
icacheInterface->squash(nextReq->asid);
} else {
++instReqs;
nextReq->completionEvent =
new TraceCompleteEvent(nextReq, this);
icacheInterface->access(nextReq);
if (icacheInterface->doEvents()) {
nextReq->completionEvent =
new TraceCompleteEvent(nextReq, this);
icacheInterface->access(nextReq);
} else {
icacheInterface->access(nextReq);
completeRequest(nextReq);
}
}
} else {
if (dcacheInterface->isBlocked())
@ -85,9 +90,15 @@ TraceCPU::tick()
++dataReqs;
nextReq->time = curTick;
nextReq->completionEvent =
new TraceCompleteEvent(nextReq, this);
dcacheInterface->access(nextReq);
if (dcacheInterface->doEvents()) {
nextReq->completionEvent =
new TraceCompleteEvent(nextReq, this);
dcacheInterface->access(nextReq);
} else {
dcacheInterface->access(nextReq);
completeRequest(nextReq);
}
}
nextCycle = dataTrace->getNextReq(nextReq);
}