gem5/cpu
Kevin Lim a896960cbf FastCPU model added. It's very similar to the SimpleCPU, just without a lot of the stats tracking.
Also various changes to make the CPU model less ISA dependent, which includes moving the code that checks for interrupts up to the ISA level, moving code that zeroes the zero registers up to the ISA level, and removing opcode and ra from the regfile.

arch/alpha/alpha_memory.cc:
    The regfile has been changed so it no longer has the opcode and ra.  Instead the xc holds the actual instruction, and from there the opcode and ra can be obtained with OPCODE() and RA().
arch/alpha/ev5.cc:
    Moved code that once existed within simpleCPU to ev5, and templatized it.
    This way the CPU models can call processInterrupts and the ISA specific interrupt handling is left to the ISA's code.
    Also moved ISA specific zero registers from simpleCPU to here.
arch/alpha/ev5.hh:
    Added macros for obtaining the opcode and ra from the instruction itself, as there is no longer opcode or ra in the regfile.
arch/alpha/isa_desc:
    Added in declarations for the FastCPU model.
arch/alpha/isa_traits.hh:
    Removed opcode and ra from the regfile.  The xc now holds the actual instruction, and the opcode and ra can be obtained through it.
    Also added the declaration for the templated zeroRegisters() function, which will set the zero registers to 0.
arch/isa_parser.py:
    Added in FastCPUExecContext so it will generate code for the FastCPU model as well.
cpu/exec_context.cc:
    Added in a more generic trap function so "ev5_trap" doesn't need to be called.  It currently still calls the old method, with plans for making this ISA dependent in the future.
cpu/exec_context.hh:
    Exec context now has the instruction within it.  Also added methods for exec context to read an instruction from memory, return the current instruction, and set the instruction if needed.
    Also has declaration for more generic trap() function.
cpu/simple_cpu/simple_cpu.cc:
    Removed references to opcode and ra, and instead sets the xc's instruction with the fetched instruction.
cpu/static_inst.hh:
    Added declaration for execute() using FastCPUExecContext.

--HG--
extra : convert_revision : 0441ea3700ac50b733e485395d4dd4ac83666f92
2004-05-27 17:46:16 -04:00
..
full_cpu Get rid of LVQ-port function unit... only used for redundant 2004-02-02 18:58:23 -08:00
memtest Major stats package cleanup 2004-05-04 17:01:00 -04:00
simple_cpu FastCPU model added. It's very similar to the SimpleCPU, just without a lot of the stats tracking. 2004-05-27 17:46:16 -04:00
base_cpu.cc Basic cleanup pass to get rid of a few things that made the Python 2004-04-02 22:57:08 -08:00
base_cpu.hh insn->inst 2004-02-02 18:14:11 -08:00
exec_context.cc FastCPU model added. It's very similar to the SimpleCPU, just without a lot of the stats tracking. 2004-05-27 17:46:16 -04:00
exec_context.hh FastCPU model added. It's very similar to the SimpleCPU, just without a lot of the stats tracking. 2004-05-27 17:46:16 -04:00
exetrace.cc Minor cleanup of trace/output stuff (leftover from EINTR bug fix). 2003-12-19 08:04:40 -08:00
exetrace.hh More conversions of ref-counted parameters to references: 2004-02-02 15:45:22 -08:00
inst_seq.hh File moves for the reorg. Tree is in broken state until I commit the makefile and 2003-10-10 09:57:26 -07:00
intr_control.cc General fixes for Sampling CPU in full system mode, and serialization of sampling CPU 2003-11-02 19:38:22 -05:00
intr_control.hh General fixes for Sampling CPU in full system mode, and serialization of sampling CPU 2003-11-02 19:38:22 -05:00
pc_event.cc Remove all of the Tru64 specific stuff from the base System object 2003-10-14 12:19:59 -04:00
pc_event.hh Move to non-architecture specific MemReq 2003-10-23 16:40:08 -04:00
static_inst.cc Make include paths explicit and update makefile accordingly. 2003-10-10 11:09:00 -07:00
static_inst.hh FastCPU model added. It's very similar to the SimpleCPU, just without a lot of the stats tracking. 2004-05-27 17:46:16 -04:00