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Merge zizzer:/z/m5/Bitkeeper/m5

Browse source 
into zizzer.eecs.umich.edu:/.automount/zazzer/z/rdreslin/m5bk/timing_L1

--HG--
extra : convert_revision : 2b73bffea88cb0e3bb5dff232a15afea8498f4e3
This commit is contained in:
Ron Dreslinski 2005-03-07 10:58:15 -05:00
parent 45eb26e67c e5f945967b
commit b290ecf1bb
8 changed files with 108 additions and 76 deletions
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126
arch/alpha/isa_desc
View file

@ -187,15 +187,16 @@ output header {{
/// Print a register name for disassembly given the unique
/// dependence tag number (FP or int).
void printReg(std::ostream &os, int reg);
void printReg(std::ostream &os, int reg) const;
std::string generateDisassembly(Addr pc, const SymbolTable *symtab);
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
}};
output decoder {{
void
AlphaStaticInst::printReg(std::ostream &os, int reg)
AlphaStaticInst::printReg(std::ostream &os, int reg) const
{
if (reg < FP_Base_DepTag) {
ccprintf(os, "r%d", reg);
@ -206,7 +207,8 @@ output decoder {{
}
std::string
AlphaStaticInst::generateDisassembly(Addr pc, const SymbolTable *symtab)
AlphaStaticInst::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
std::stringstream ss;
@ -237,7 +239,7 @@ output decoder {{
// Declarations for execute() methods.
def template BasicExecDeclare {{
Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *);
Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const;
}};
// Basic instruction class declaration template.
@ -267,7 +269,7 @@ def template BasicConstructor {{
// Basic instruction class execute method template.
def template BasicExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData)
Trace::InstRecord *traceData) const
{
Fault fault = No_Fault;
@ -330,14 +332,16 @@ output header {{
~Nop() { }
std::string generateDisassembly(Addr pc, const SymbolTable *symtab);
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
%(BasicExecDeclare)s
};
}};
output decoder {{
std::string Nop::generateDisassembly(Addr pc, const SymbolTable *symtab)
std::string Nop::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
#ifdef SS_COMPATIBLE_DISASSEMBLY
return originalDisassembly;
@ -360,7 +364,7 @@ output decoder {{
output exec {{
Fault
Nop::execute(%(CPU_exec_context)s *, Trace::InstRecord *)
Nop::execute(%(CPU_exec_context)s *, Trace::InstRecord *) const
{
return No_Fault;
}
@ -410,13 +414,14 @@ output header {{
{
}
std::string generateDisassembly(Addr pc, const SymbolTable *symtab);
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
}};
output decoder {{
std::string
IntegerImm::generateDisassembly(Addr pc, const SymbolTable *symtab)
IntegerImm::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
@ -588,12 +593,13 @@ output header {{
}
#if defined(linux)
int getC99RoundingMode(uint64_t fpcr_val);
int getC99RoundingMode(uint64_t fpcr_val) const;
#endif
// This differs from the AlphaStaticInst version only in
// printing suffixes for non-default rounding & trapping modes.
std::string generateDisassembly(Addr pc, const SymbolTable *symtab);
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
}};
@ -618,7 +624,7 @@ def template FloatingPointDecode {{
output decoder {{
#if defined(linux)
int
AlphaFP::getC99RoundingMode(uint64_t fpcr_val)
AlphaFP::getC99RoundingMode(uint64_t fpcr_val) const
{
if (roundingMode == Dynamic) {
return alphaToC99RoundingMode[bits(fpcr_val, 59, 58)];
@ -630,7 +636,7 @@ output decoder {{
#endif
std::string
AlphaFP::generateDisassembly(Addr pc, const SymbolTable *symtab)
AlphaFP::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::string mnem_str(mnemonic);
@ -751,7 +757,8 @@ output header {{
{
}
std::string generateDisassembly(Addr pc, const SymbolTable *symtab);
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
public:
@ -796,21 +803,22 @@ output header {{
{
}
std::string generateDisassembly(Addr pc, const SymbolTable *symtab);
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
}};
output decoder {{
std::string
Memory::generateDisassembly(Addr pc, const SymbolTable *symtab)
Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
return csprintf("%-10s %c%d,%d(r%d)", mnemonic,
flags[IsFloating] ? 'f' : 'r', RA, MEMDISP, RB);
}
std::string
MemoryNoDisp::generateDisassembly(Addr pc, const SymbolTable *symtab)
MemoryNoDisp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
return csprintf("%-10s (r%d)", mnemonic, RB);
}
@ -894,7 +902,7 @@ def template LoadStoreConstructor {{
def template EACompExecute {{
Fault
%(class_name)s::EAComp::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData)
Trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = No_Fault;
@ -916,7 +924,7 @@ def template EACompExecute {{
def template MemAccExecute {{
Fault
%(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData)
Trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = No_Fault;
@ -950,7 +958,7 @@ def template MemAccExecute {{
def template LoadStoreExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData)
Trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = No_Fault;
@ -984,7 +992,7 @@ def template LoadStoreExecute {{
def template PrefetchExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData)
Trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = No_Fault;
@ -1158,9 +1166,9 @@ output header {{
{
protected:
/// Cached program counter from last disassembly
Addr cachedPC;
mutable Addr cachedPC;
/// Cached symbol table pointer from last disassembly
const SymbolTable *cachedSymtab;
mutable const SymbolTable *cachedSymtab;
/// Constructor
PCDependentDisassembly(const char *mnem, MachInst _machInst,
@ -1170,7 +1178,8 @@ output header {{
{
}
const std::string &disassemble(Addr pc, const SymbolTable *symtab);
const std::string &
disassemble(Addr pc, const SymbolTable *symtab) const;
};
/**
@ -1192,7 +1201,8 @@ output header {{
Addr branchTarget(Addr branchPC) const;
std::string generateDisassembly(Addr pc, const SymbolTable *symtab);
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
/**
@ -1216,7 +1226,8 @@ output header {{
Addr branchTarget(ExecContext *xc) const;
std::string generateDisassembly(Addr pc, const SymbolTable *symtab);
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
}};
@ -1236,7 +1247,8 @@ output decoder {{
}
const std::string &
PCDependentDisassembly::disassemble(Addr pc, const SymbolTable *symtab)
PCDependentDisassembly::disassemble(Addr pc,
const SymbolTable *symtab) const
{
if (!cachedDisassembly ||
pc != cachedPC || symtab != cachedSymtab)
@ -1254,7 +1266,7 @@ output decoder {{
}
std::string
Branch::generateDisassembly(Addr pc, const SymbolTable *symtab)
Branch::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
@ -1292,7 +1304,7 @@ output decoder {{
}
std::string
Jump::generateDisassembly(Addr pc, const SymbolTable *symtab)
Jump::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
@ -1391,13 +1403,15 @@ output header {{
{
}
std::string generateDisassembly(Addr pc, const SymbolTable *symtab);
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
}};
output decoder {{
std::string
EmulatedCallPal::generateDisassembly(Addr pc, const SymbolTable *symtab)
EmulatedCallPal::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
#ifdef SS_COMPATIBLE_DISASSEMBLY
return csprintf("%s %s", "call_pal", mnemonic);
@ -1433,7 +1447,8 @@ output header {{
CallPalBase(const char *mnem, MachInst _machInst,
OpClass __opClass);
std::string generateDisassembly(Addr pc, const SymbolTable *symtab);
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
}};
@ -1463,7 +1478,7 @@ output decoder {{
}
std::string
CallPalBase::generateDisassembly(Addr pc, const SymbolTable *symtab)
CallPalBase::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
return csprintf("%-10s %#x", "call_pal", palFunc);
}
@ -1498,7 +1513,8 @@ output header {{
StaticInstPtr<AlphaISA> _eaCompPtr = nullStaticInstPtr,
StaticInstPtr<AlphaISA> _memAccPtr = nullStaticInstPtr);
std::string generateDisassembly(Addr pc, const SymbolTable *symtab);
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
}};
@ -1520,7 +1536,7 @@ output decoder {{
}
std::string
HwLoadStore::generateDisassembly(Addr pc, const SymbolTable *symtab)
HwLoadStore::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
#ifdef SS_COMPATIBLE_DISASSEMBLY
return csprintf("%-10s r%d,%d(r%d)", mnemonic, RA, disp, RB);
@ -1571,13 +1587,14 @@ output header {{
{
}
std::string generateDisassembly(Addr pc, const SymbolTable *symtab);
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
}};
output decoder {{
std::string
HwMoveIPR::generateDisassembly(Addr pc, const SymbolTable *symtab)
HwMoveIPR::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
if (_numSrcRegs > 0) {
// must be mtpr
@ -1593,7 +1610,8 @@ output decoder {{
}};
def format HwMoveIPR(code) {{
iop = InstObjParams(name, Name, 'HwMoveIPR', CodeBlock(code))
iop = InstObjParams(name, Name, 'HwMoveIPR', CodeBlock(code),
['IprAccessOp'])
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
@ -1628,7 +1646,8 @@ output header {{
%(BasicExecDeclare)s
std::string generateDisassembly(Addr pc, const SymbolTable *symtab);
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
/**
@ -1644,7 +1663,7 @@ output header {{
{
private:
/// Have we warned on this instruction yet?
bool warned;
mutable bool warned;
public:
/// Constructor
@ -1658,19 +1677,22 @@ output header {{
%(BasicExecDeclare)s
std::string generateDisassembly(Addr pc, const SymbolTable *symtab);
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
}};
output decoder {{
std::string
FailUnimplemented::generateDisassembly(Addr pc, const SymbolTable *symtab)
FailUnimplemented::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
return csprintf("%-10s (unimplemented)", mnemonic);
}
std::string
WarnUnimplemented::generateDisassembly(Addr pc, const SymbolTable *symtab)
WarnUnimplemented::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
#ifdef SS_COMPATIBLE_DISASSEMBLY
return csprintf("%-10s", mnemonic);
@ -1683,7 +1705,7 @@ output decoder {{
output exec {{
Fault
FailUnimplemented::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData)
Trace::InstRecord *traceData) const
{
panic("attempt to execute unimplemented instruction '%s' "
"(inst 0x%08x, opcode 0x%x)", mnemonic, machInst, OPCODE);
@ -1692,7 +1714,7 @@ output exec {{
Fault
WarnUnimplemented::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData)
Trace::InstRecord *traceData) const
{
if (!warned) {
warn("instruction '%s' unimplemented\n", mnemonic);
@ -1734,7 +1756,8 @@ output header {{
%(BasicExecDeclare)s
std::string generateDisassembly(Addr pc, const SymbolTable *symtab);
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
}};
@ -1745,7 +1768,7 @@ output header {{
output decoder {{
std::string
Unknown::generateDisassembly(Addr pc, const SymbolTable *symtab)
Unknown::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
return csprintf("%-10s (inst 0x%x, opcode 0x%x)",
"unknown", machInst, OPCODE);
@ -1754,7 +1777,8 @@ output decoder {{
output exec {{
Fault
Unknown::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData)
Unknown::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
panic("attempt to execute unknown instruction "
"(inst 0x%08x, opcode 0x%x)", machInst, OPCODE);
@ -2542,7 +2566,7 @@ decode OPCODE default Unknown::unknown() {
}
format BasicOperate {
0x1e: hw_rei({{ xc->hwrei(); }});
0x1e: hw_rei({{ xc->hwrei(); }}, IsSerializing);
// M5 special opcodes use the reserved 0x01 opcode space
0x01: decode M5FUNC {

6
base/statistics.hh
View file

@ -2872,12 +2872,6 @@ operator/(Temp l, Temp r)
return NodePtr(new BinaryNode<std::divides<Result> >(l, r));
}
inline Temp
operator%(Temp l, Temp r)
{
return NodePtr(new BinaryNode<std::modulus<Result> >(l, r));
}
inline Temp
operator-(Temp l)
{

1
configs/boot/netperf-server.rcS
View file

@ -22,6 +22,7 @@ echo "running netserver..."
/benchmarks/netperf/netserver
echo -n "signal client to begin..."
sleep 1
echo "server ready" | /usr/bin/netcat -c $CLIENT 8000
echo "done."

1
cpu/full_cpu/op_class.hh
View file

@ -51,6 +51,7 @@ enum OpClass {
FloatSqrtOp, /* floating point square root */
MemReadOp, /* memory read port */
MemWriteOp, /* memory write port */
IprAccessOp, /* Internal Processor Register read/write port */
InstPrefetchOp, /* instruction prefetch port (on I-cache) */
Num_OpClasses /* total functional unit classes */
};

16
cpu/simple_cpu/simple_cpu.hh
View file

@ -268,47 +268,47 @@ class SimpleCPU : public BaseCPU
// storage (which is pretty hard to imagine they would have reason
// to do).
uint64_t readIntReg(StaticInst<TheISA> *si, int idx)
uint64_t readIntReg(const StaticInst<TheISA> *si, int idx)
{
return xc->readIntReg(si->srcRegIdx(idx));
}
float readFloatRegSingle(StaticInst<TheISA> *si, int idx)
float readFloatRegSingle(const StaticInst<TheISA> *si, int idx)
{
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
return xc->readFloatRegSingle(reg_idx);
}
double readFloatRegDouble(StaticInst<TheISA> *si, int idx)
double readFloatRegDouble(const StaticInst<TheISA> *si, int idx)
{
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
return xc->readFloatRegDouble(reg_idx);
}
uint64_t readFloatRegInt(StaticInst<TheISA> *si, int idx)
uint64_t readFloatRegInt(const StaticInst<TheISA> *si, int idx)
{
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
return xc->readFloatRegInt(reg_idx);
}
void setIntReg(StaticInst<TheISA> *si, int idx, uint64_t val)
void setIntReg(const StaticInst<TheISA> *si, int idx, uint64_t val)
{
xc->setIntReg(si->destRegIdx(idx), val);
}
void setFloatRegSingle(StaticInst<TheISA> *si, int idx, float val)
void setFloatRegSingle(const StaticInst<TheISA> *si, int idx, float val)
{
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
xc->setFloatRegSingle(reg_idx, val);
}
void setFloatRegDouble(StaticInst<TheISA> *si, int idx, double val)
void setFloatRegDouble(const StaticInst<TheISA> *si, int idx, double val)
{
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
xc->setFloatRegDouble(reg_idx, val);
}
void setFloatRegInt(StaticInst<TheISA> *si, int idx, uint64_t val)
void setFloatRegInt(const StaticInst<TheISA> *si, int idx, uint64_t val)
{
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
xc->setFloatRegInt(reg_idx, val);

2
cpu/static_inst.cc
View file

@ -68,7 +68,7 @@ StaticInst<AlphaISA>::nullStaticInstPtr;
template <class ISA>
bool
StaticInst<ISA>::hasBranchTarget(Addr pc, ExecContext *xc, Addr &tgt)
StaticInst<ISA>::hasBranchTarget(Addr pc, ExecContext *xc, Addr &tgt) const
{
if (isDirectCtrl()) {
tgt = branchTarget(pc);

24
cpu/static_inst.hh
View file

@ -285,13 +285,13 @@ class StaticInst : public StaticInstBase
* String representation of disassembly (lazily evaluated via
* disassemble()).
*/
std::string *cachedDisassembly;
mutable std::string *cachedDisassembly;
/**
* Internal function to generate disassembly string.
*/
virtual std::string generateDisassembly(Addr pc,
const SymbolTable *symtab) = 0;
virtual std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
/// Constructor.
StaticInst(const char *_mnemonic, MachInst _machInst, OpClass __opClass)
@ -311,23 +311,27 @@ class StaticInst : public StaticInstBase
/**
* Execute this instruction under SimpleCPU model.
*/
virtual Fault execute(SimpleCPU *xc, Trace::InstRecord *traceData) = 0;
virtual Fault execute(SimpleCPU *xc,
Trace::InstRecord *traceData) const = 0;
/**
/**
* Execute this instruction under InorderCPU model.
*/
virtual Fault execute(InorderCPU *xc, Trace::InstRecord *traceData) = 0;
virtual Fault execute(InorderCPU *xc,
Trace::InstRecord *traceData) const = 0;
/**
* Execute this instruction under FastCPU model.
*/
virtual Fault execute(FastCPU *xc, Trace::InstRecord *traceData) = 0;
virtual Fault execute(FastCPU *xc,
Trace::InstRecord *traceData) const = 0;
/**
* Execute this instruction under detailed FullCPU model.
*/
virtual Fault execute(DynInst *xc, Trace::InstRecord *traceData) = 0;
virtual Fault execute(DynInst *xc,
Trace::InstRecord *traceData) const = 0;
/**
* Return the target address for a PC-relative branch.
@ -357,7 +361,7 @@ class StaticInst : public StaticInstBase
* Return true if the instruction is a control transfer, and if so,
* return the target address as well.
*/
bool hasBranchTarget(Addr pc, ExecContext *xc, Addr &tgt);
bool hasBranchTarget(Addr pc, ExecContext *xc, Addr &tgt) const;
/**
* Return string representation of disassembled instruction.
@ -367,7 +371,7 @@ class StaticInst : public StaticInstBase
* should not be cached, this function should be overridden directly.
*/
virtual const std::string &disassemble(Addr pc,
const SymbolTable *symtab = 0)
const SymbolTable *symtab = 0) const
{
if (!cachedDisassembly)
cachedDisassembly =

8
sim/pyconfig/m5config.py
View file

@ -234,6 +234,9 @@ class MetaConfigNode(type):
for key,val in dict.items():
del dict[key]
# See description of decorators in the importer.py file
# We just strip off the expr_decorator now since we don't
# need from this point on.
if key.startswith(expr_decorator):
key = key[len(expr_decorator):]
@ -285,6 +288,9 @@ class MetaConfigNode(type):
# initialize attributes with values from class definition
for key,value in dict.iteritems():
# turn an expression that was munged in the importer
# because it had dots into a list so that we can find the
# proper variable to modify.
key = key.split(dot_decorator)
c = cls
for item in key[:-1]:
@ -692,9 +698,11 @@ class Node(object):
# instantiate children in same order they were added for
# backward compatibility (else we can end up with cpu1
# before cpu0).
self.children.sort(lambda x,y: cmp(x.name, y.name))
children = [ c.name for c in self.children if not c.paramcontext]
print 'children =', ' '.join(children)
self.params.sort(lambda x,y: cmp(x.name, y.name))
for param in self.params:
try:
if param.value is None: