Merge zizzer:/z/m5/Bitkeeper/m5
into zizzer.eecs.umich.edu:/.automount/zazzer/z/rdreslin/m5bk/timing_L1 --HG-- extra : convert_revision : 2b73bffea88cb0e3bb5dff232a15afea8498f4e3
This commit is contained in:
Ron Dreslinski
commit
b290ecf1bb
8 changed files with 108 additions and 76 deletions
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@ -187,15 +187,16 @@ output header {{
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/// Print a register name for disassembly given the unique
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/// dependence tag number (FP or int).
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void printReg(std::ostream &os, int reg);
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void printReg(std::ostream &os, int reg) const;
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab);
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std::string
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generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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}};
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output decoder {{
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void
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AlphaStaticInst::printReg(std::ostream &os, int reg)
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AlphaStaticInst::printReg(std::ostream &os, int reg) const
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{
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if (reg < FP_Base_DepTag) {
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ccprintf(os, "r%d", reg);
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@ -206,7 +207,8 @@ output decoder {{
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}
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std::string
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AlphaStaticInst::generateDisassembly(Addr pc, const SymbolTable *symtab)
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AlphaStaticInst::generateDisassembly(Addr pc,
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const SymbolTable *symtab) const
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{
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std::stringstream ss;
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@ -237,7 +239,7 @@ output decoder {{
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// Declarations for execute() methods.
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def template BasicExecDeclare {{
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Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *);
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Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const;
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}};
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// Basic instruction class declaration template.
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@ -267,7 +269,7 @@ def template BasicConstructor {{
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// Basic instruction class execute method template.
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def template BasicExecute {{
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Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData)
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Trace::InstRecord *traceData) const
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{
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Fault fault = No_Fault;
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@ -330,14 +332,16 @@ output header {{
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~Nop() { }
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab);
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std::string
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generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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%(BasicExecDeclare)s
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};
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}};
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output decoder {{
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std::string Nop::generateDisassembly(Addr pc, const SymbolTable *symtab)
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std::string Nop::generateDisassembly(Addr pc,
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const SymbolTable *symtab) const
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{
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#ifdef SS_COMPATIBLE_DISASSEMBLY
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return originalDisassembly;
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@ -360,7 +364,7 @@ output decoder {{
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output exec {{
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Fault
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Nop::execute(%(CPU_exec_context)s *, Trace::InstRecord *)
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Nop::execute(%(CPU_exec_context)s *, Trace::InstRecord *) const
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{
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return No_Fault;
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}
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@ -410,13 +414,14 @@ output header {{
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{
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}
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab);
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std::string
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generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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}};
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output decoder {{
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std::string
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IntegerImm::generateDisassembly(Addr pc, const SymbolTable *symtab)
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IntegerImm::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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std::stringstream ss;
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@ -588,12 +593,13 @@ output header {{
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}
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#if defined(linux)
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int getC99RoundingMode(uint64_t fpcr_val);
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int getC99RoundingMode(uint64_t fpcr_val) const;
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#endif
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// This differs from the AlphaStaticInst version only in
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// printing suffixes for non-default rounding & trapping modes.
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab);
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std::string
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generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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}};
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@ -618,7 +624,7 @@ def template FloatingPointDecode {{
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output decoder {{
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#if defined(linux)
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int
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AlphaFP::getC99RoundingMode(uint64_t fpcr_val)
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AlphaFP::getC99RoundingMode(uint64_t fpcr_val) const
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{
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if (roundingMode == Dynamic) {
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return alphaToC99RoundingMode[bits(fpcr_val, 59, 58)];
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@ -630,7 +636,7 @@ output decoder {{
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#endif
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std::string
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AlphaFP::generateDisassembly(Addr pc, const SymbolTable *symtab)
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AlphaFP::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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std::string mnem_str(mnemonic);
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@ -751,7 +757,8 @@ output header {{
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{
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}
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab);
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std::string
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generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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public:
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@ -796,21 +803,22 @@ output header {{
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{
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}
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab);
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std::string
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generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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}};
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output decoder {{
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std::string
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Memory::generateDisassembly(Addr pc, const SymbolTable *symtab)
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Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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return csprintf("%-10s %c%d,%d(r%d)", mnemonic,
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flags[IsFloating] ? 'f' : 'r', RA, MEMDISP, RB);
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}
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std::string
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MemoryNoDisp::generateDisassembly(Addr pc, const SymbolTable *symtab)
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MemoryNoDisp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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return csprintf("%-10s (r%d)", mnemonic, RB);
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}
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@ -894,7 +902,7 @@ def template LoadStoreConstructor {{
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def template EACompExecute {{
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Fault
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%(class_name)s::EAComp::execute(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData)
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Trace::InstRecord *traceData) const
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{
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Addr EA;
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Fault fault = No_Fault;
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@ -916,7 +924,7 @@ def template EACompExecute {{
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def template MemAccExecute {{
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Fault
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%(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData)
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Trace::InstRecord *traceData) const
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{
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Addr EA;
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Fault fault = No_Fault;
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@ -950,7 +958,7 @@ def template MemAccExecute {{
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def template LoadStoreExecute {{
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Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData)
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Trace::InstRecord *traceData) const
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{
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Addr EA;
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Fault fault = No_Fault;
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@ -984,7 +992,7 @@ def template LoadStoreExecute {{
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def template PrefetchExecute {{
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Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData)
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Trace::InstRecord *traceData) const
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{
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Addr EA;
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Fault fault = No_Fault;
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@ -1158,9 +1166,9 @@ output header {{
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{
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protected:
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/// Cached program counter from last disassembly
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Addr cachedPC;
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mutable Addr cachedPC;
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/// Cached symbol table pointer from last disassembly
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const SymbolTable *cachedSymtab;
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mutable const SymbolTable *cachedSymtab;
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/// Constructor
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PCDependentDisassembly(const char *mnem, MachInst _machInst,
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@ -1170,7 +1178,8 @@ output header {{
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{
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}
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const std::string &disassemble(Addr pc, const SymbolTable *symtab);
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const std::string &
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disassemble(Addr pc, const SymbolTable *symtab) const;
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};
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/**
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@ -1192,7 +1201,8 @@ output header {{
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Addr branchTarget(Addr branchPC) const;
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab);
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std::string
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generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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/**
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@ -1216,7 +1226,8 @@ output header {{
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Addr branchTarget(ExecContext *xc) const;
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab);
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std::string
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generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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}};
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@ -1236,7 +1247,8 @@ output decoder {{
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}
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const std::string &
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PCDependentDisassembly::disassemble(Addr pc, const SymbolTable *symtab)
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PCDependentDisassembly::disassemble(Addr pc,
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const SymbolTable *symtab) const
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{
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if (!cachedDisassembly ||
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pc != cachedPC || symtab != cachedSymtab)
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@ -1254,7 +1266,7 @@ output decoder {{
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}
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std::string
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Branch::generateDisassembly(Addr pc, const SymbolTable *symtab)
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Branch::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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std::stringstream ss;
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@ -1292,7 +1304,7 @@ output decoder {{
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}
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std::string
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Jump::generateDisassembly(Addr pc, const SymbolTable *symtab)
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Jump::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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std::stringstream ss;
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@ -1391,13 +1403,15 @@ output header {{
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{
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}
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab);
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std::string
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generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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}};
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output decoder {{
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std::string
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EmulatedCallPal::generateDisassembly(Addr pc, const SymbolTable *symtab)
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EmulatedCallPal::generateDisassembly(Addr pc,
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const SymbolTable *symtab) const
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{
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#ifdef SS_COMPATIBLE_DISASSEMBLY
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return csprintf("%s %s", "call_pal", mnemonic);
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@ -1433,7 +1447,8 @@ output header {{
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CallPalBase(const char *mnem, MachInst _machInst,
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OpClass __opClass);
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab);
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std::string
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generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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}};
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@ -1463,7 +1478,7 @@ output decoder {{
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}
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std::string
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CallPalBase::generateDisassembly(Addr pc, const SymbolTable *symtab)
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CallPalBase::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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return csprintf("%-10s %#x", "call_pal", palFunc);
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}
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@ -1498,7 +1513,8 @@ output header {{
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StaticInstPtr<AlphaISA> _eaCompPtr = nullStaticInstPtr,
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StaticInstPtr<AlphaISA> _memAccPtr = nullStaticInstPtr);
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab);
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std::string
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generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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}};
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@ -1520,7 +1536,7 @@ output decoder {{
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}
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std::string
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HwLoadStore::generateDisassembly(Addr pc, const SymbolTable *symtab)
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HwLoadStore::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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#ifdef SS_COMPATIBLE_DISASSEMBLY
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return csprintf("%-10s r%d,%d(r%d)", mnemonic, RA, disp, RB);
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@ -1571,13 +1587,14 @@ output header {{
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{
|
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}
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab);
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std::string
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generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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}};
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output decoder {{
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std::string
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HwMoveIPR::generateDisassembly(Addr pc, const SymbolTable *symtab)
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HwMoveIPR::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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if (_numSrcRegs > 0) {
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// must be mtpr
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@ -1593,7 +1610,8 @@ output decoder {{
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}};
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def format HwMoveIPR(code) {{
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iop = InstObjParams(name, Name, 'HwMoveIPR', CodeBlock(code))
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iop = InstObjParams(name, Name, 'HwMoveIPR', CodeBlock(code),
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['IprAccessOp'])
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header_output = BasicDeclare.subst(iop)
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decoder_output = BasicConstructor.subst(iop)
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decode_block = BasicDecode.subst(iop)
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@ -1628,7 +1646,8 @@ output header {{
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|
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%(BasicExecDeclare)s
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab);
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std::string
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generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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/**
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@ -1644,7 +1663,7 @@ output header {{
|
|||
{
|
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private:
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/// Have we warned on this instruction yet?
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bool warned;
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mutable bool warned;
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public:
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/// Constructor
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|
|
@ -1658,19 +1677,22 @@ output header {{
|
|||
|
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%(BasicExecDeclare)s
|
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|
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab);
|
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std::string
|
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generateDisassembly(Addr pc, const SymbolTable *symtab) const;
|
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};
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}};
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output decoder {{
|
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std::string
|
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FailUnimplemented::generateDisassembly(Addr pc, const SymbolTable *symtab)
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FailUnimplemented::generateDisassembly(Addr pc,
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const SymbolTable *symtab) const
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{
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return csprintf("%-10s (unimplemented)", mnemonic);
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}
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|
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std::string
|
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WarnUnimplemented::generateDisassembly(Addr pc, const SymbolTable *symtab)
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WarnUnimplemented::generateDisassembly(Addr pc,
|
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const SymbolTable *symtab) const
|
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{
|
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#ifdef SS_COMPATIBLE_DISASSEMBLY
|
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return csprintf("%-10s", mnemonic);
|
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|
|
@ -1683,7 +1705,7 @@ output decoder {{
|
|||
output exec {{
|
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Fault
|
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FailUnimplemented::execute(%(CPU_exec_context)s *xc,
|
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Trace::InstRecord *traceData)
|
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Trace::InstRecord *traceData) const
|
||||
{
|
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panic("attempt to execute unimplemented instruction '%s' "
|
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"(inst 0x%08x, opcode 0x%x)", mnemonic, machInst, OPCODE);
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|
|
@ -1692,7 +1714,7 @@ output exec {{
|
|||
|
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Fault
|
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WarnUnimplemented::execute(%(CPU_exec_context)s *xc,
|
||||
Trace::InstRecord *traceData)
|
||||
Trace::InstRecord *traceData) const
|
||||
{
|
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if (!warned) {
|
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warn("instruction '%s' unimplemented\n", mnemonic);
|
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|
|
@ -1734,7 +1756,8 @@ output header {{
|
|||
|
||||
%(BasicExecDeclare)s
|
||||
|
||||
std::string generateDisassembly(Addr pc, const SymbolTable *symtab);
|
||||
std::string
|
||||
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
|
||||
};
|
||||
}};
|
||||
|
||||
|
|
@ -1745,7 +1768,7 @@ output header {{
|
|||
|
||||
output decoder {{
|
||||
std::string
|
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Unknown::generateDisassembly(Addr pc, const SymbolTable *symtab)
|
||||
Unknown::generateDisassembly(Addr pc, const SymbolTable *symtab) const
|
||||
{
|
||||
return csprintf("%-10s (inst 0x%x, opcode 0x%x)",
|
||||
"unknown", machInst, OPCODE);
|
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|
|
@ -1754,7 +1777,8 @@ output decoder {{
|
|||
|
||||
output exec {{
|
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Fault
|
||||
Unknown::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData)
|
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Unknown::execute(%(CPU_exec_context)s *xc,
|
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Trace::InstRecord *traceData) const
|
||||
{
|
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panic("attempt to execute unknown instruction "
|
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"(inst 0x%08x, opcode 0x%x)", machInst, OPCODE);
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|
|
@ -2542,7 +2566,7 @@ decode OPCODE default Unknown::unknown() {
|
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}
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format BasicOperate {
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0x1e: hw_rei({{ xc->hwrei(); }});
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0x1e: hw_rei({{ xc->hwrei(); }}, IsSerializing);
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|
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// M5 special opcodes use the reserved 0x01 opcode space
|
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0x01: decode M5FUNC {
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|
|
|
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|
|
@ -2872,12 +2872,6 @@ operator/(Temp l, Temp r)
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return NodePtr(new BinaryNode<std::divides<Result> >(l, r));
|
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}
|
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|
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inline Temp
|
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operator%(Temp l, Temp r)
|
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{
|
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return NodePtr(new BinaryNode<std::modulus<Result> >(l, r));
|
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}
|
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|
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inline Temp
|
||||
operator-(Temp l)
|
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{
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|
|
|
|||
|
|
@ -22,6 +22,7 @@ echo "running netserver..."
|
|||
/benchmarks/netperf/netserver
|
||||
|
||||
echo -n "signal client to begin..."
|
||||
sleep 1
|
||||
echo "server ready" | /usr/bin/netcat -c $CLIENT 8000
|
||||
echo "done."
|
||||
|
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|
|
|
|||
|
|
@ -51,6 +51,7 @@ enum OpClass {
|
|||
FloatSqrtOp, /* floating point square root */
|
||||
MemReadOp, /* memory read port */
|
||||
MemWriteOp, /* memory write port */
|
||||
IprAccessOp, /* Internal Processor Register read/write port */
|
||||
InstPrefetchOp, /* instruction prefetch port (on I-cache) */
|
||||
Num_OpClasses /* total functional unit classes */
|
||||
};
|
||||
|
|
|
|||
|
|
@ -268,47 +268,47 @@ class SimpleCPU : public BaseCPU
|
|||
// storage (which is pretty hard to imagine they would have reason
|
||||
// to do).
|
||||
|
||||
uint64_t readIntReg(StaticInst<TheISA> *si, int idx)
|
||||
uint64_t readIntReg(const StaticInst<TheISA> *si, int idx)
|
||||
{
|
||||
return xc->readIntReg(si->srcRegIdx(idx));
|
||||
}
|
||||
|
||||
float readFloatRegSingle(StaticInst<TheISA> *si, int idx)
|
||||
float readFloatRegSingle(const StaticInst<TheISA> *si, int idx)
|
||||
{
|
||||
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
|
||||
return xc->readFloatRegSingle(reg_idx);
|
||||
}
|
||||
|
||||
double readFloatRegDouble(StaticInst<TheISA> *si, int idx)
|
||||
double readFloatRegDouble(const StaticInst<TheISA> *si, int idx)
|
||||
{
|
||||
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
|
||||
return xc->readFloatRegDouble(reg_idx);
|
||||
}
|
||||
|
||||
uint64_t readFloatRegInt(StaticInst<TheISA> *si, int idx)
|
||||
uint64_t readFloatRegInt(const StaticInst<TheISA> *si, int idx)
|
||||
{
|
||||
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
|
||||
return xc->readFloatRegInt(reg_idx);
|
||||
}
|
||||
|
||||
void setIntReg(StaticInst<TheISA> *si, int idx, uint64_t val)
|
||||
void setIntReg(const StaticInst<TheISA> *si, int idx, uint64_t val)
|
||||
{
|
||||
xc->setIntReg(si->destRegIdx(idx), val);
|
||||
}
|
||||
|
||||
void setFloatRegSingle(StaticInst<TheISA> *si, int idx, float val)
|
||||
void setFloatRegSingle(const StaticInst<TheISA> *si, int idx, float val)
|
||||
{
|
||||
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
|
||||
xc->setFloatRegSingle(reg_idx, val);
|
||||
}
|
||||
|
||||
void setFloatRegDouble(StaticInst<TheISA> *si, int idx, double val)
|
||||
void setFloatRegDouble(const StaticInst<TheISA> *si, int idx, double val)
|
||||
{
|
||||
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
|
||||
xc->setFloatRegDouble(reg_idx, val);
|
||||
}
|
||||
|
||||
void setFloatRegInt(StaticInst<TheISA> *si, int idx, uint64_t val)
|
||||
void setFloatRegInt(const StaticInst<TheISA> *si, int idx, uint64_t val)
|
||||
{
|
||||
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
|
||||
xc->setFloatRegInt(reg_idx, val);
|
||||
|
|
|
|||
|
|
@ -68,7 +68,7 @@ StaticInst<AlphaISA>::nullStaticInstPtr;
|
|||
|
||||
template <class ISA>
|
||||
bool
|
||||
StaticInst<ISA>::hasBranchTarget(Addr pc, ExecContext *xc, Addr &tgt)
|
||||
StaticInst<ISA>::hasBranchTarget(Addr pc, ExecContext *xc, Addr &tgt) const
|
||||
{
|
||||
if (isDirectCtrl()) {
|
||||
tgt = branchTarget(pc);
|
||||
|
|
|
|||
|
|
@ -285,13 +285,13 @@ class StaticInst : public StaticInstBase
|
|||
* String representation of disassembly (lazily evaluated via
|
||||
* disassemble()).
|
||||
*/
|
||||
std::string *cachedDisassembly;
|
||||
mutable std::string *cachedDisassembly;
|
||||
|
||||
/**
|
||||
* Internal function to generate disassembly string.
|
||||
*/
|
||||
virtual std::string generateDisassembly(Addr pc,
|
||||
const SymbolTable *symtab) = 0;
|
||||
virtual std::string
|
||||
generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
|
||||
|
||||
/// Constructor.
|
||||
StaticInst(const char *_mnemonic, MachInst _machInst, OpClass __opClass)
|
||||
|
|
@ -311,23 +311,27 @@ class StaticInst : public StaticInstBase
|
|||
/**
|
||||
* Execute this instruction under SimpleCPU model.
|
||||
*/
|
||||
virtual Fault execute(SimpleCPU *xc, Trace::InstRecord *traceData) = 0;
|
||||
virtual Fault execute(SimpleCPU *xc,
|
||||
Trace::InstRecord *traceData) const = 0;
|
||||
|
||||
/**
|
||||
/**
|
||||
* Execute this instruction under InorderCPU model.
|
||||
*/
|
||||
virtual Fault execute(InorderCPU *xc, Trace::InstRecord *traceData) = 0;
|
||||
virtual Fault execute(InorderCPU *xc,
|
||||
Trace::InstRecord *traceData) const = 0;
|
||||
|
||||
|
||||
/**
|
||||
* Execute this instruction under FastCPU model.
|
||||
*/
|
||||
virtual Fault execute(FastCPU *xc, Trace::InstRecord *traceData) = 0;
|
||||
virtual Fault execute(FastCPU *xc,
|
||||
Trace::InstRecord *traceData) const = 0;
|
||||
|
||||
/**
|
||||
* Execute this instruction under detailed FullCPU model.
|
||||
*/
|
||||
virtual Fault execute(DynInst *xc, Trace::InstRecord *traceData) = 0;
|
||||
virtual Fault execute(DynInst *xc,
|
||||
Trace::InstRecord *traceData) const = 0;
|
||||
|
||||
/**
|
||||
* Return the target address for a PC-relative branch.
|
||||
|
|
@ -357,7 +361,7 @@ class StaticInst : public StaticInstBase
|
|||
* Return true if the instruction is a control transfer, and if so,
|
||||
* return the target address as well.
|
||||
*/
|
||||
bool hasBranchTarget(Addr pc, ExecContext *xc, Addr &tgt);
|
||||
bool hasBranchTarget(Addr pc, ExecContext *xc, Addr &tgt) const;
|
||||
|
||||
/**
|
||||
* Return string representation of disassembled instruction.
|
||||
|
|
@ -367,7 +371,7 @@ class StaticInst : public StaticInstBase
|
|||
* should not be cached, this function should be overridden directly.
|
||||
*/
|
||||
virtual const std::string &disassemble(Addr pc,
|
||||
const SymbolTable *symtab = 0)
|
||||
const SymbolTable *symtab = 0) const
|
||||
{
|
||||
if (!cachedDisassembly)
|
||||
cachedDisassembly =
|
||||
|
|
|
|||
|
|
@ -234,6 +234,9 @@ class MetaConfigNode(type):
|
|||
for key,val in dict.items():
|
||||
del dict[key]
|
||||
|
||||
# See description of decorators in the importer.py file
|
||||
# We just strip off the expr_decorator now since we don't
|
||||
# need from this point on.
|
||||
if key.startswith(expr_decorator):
|
||||
key = key[len(expr_decorator):]
|
||||
|
||||
|
|
@ -285,6 +288,9 @@ class MetaConfigNode(type):
|
|||
|
||||
# initialize attributes with values from class definition
|
||||
for key,value in dict.iteritems():
|
||||
# turn an expression that was munged in the importer
|
||||
# because it had dots into a list so that we can find the
|
||||
# proper variable to modify.
|
||||
key = key.split(dot_decorator)
|
||||
c = cls
|
||||
for item in key[:-1]:
|
||||
|
|
@ -692,9 +698,11 @@ class Node(object):
|
|||
# instantiate children in same order they were added for
|
||||
# backward compatibility (else we can end up with cpu1
|
||||
# before cpu0).
|
||||
self.children.sort(lambda x,y: cmp(x.name, y.name))
|
||||
children = [ c.name for c in self.children if not c.paramcontext]
|
||||
print 'children =', ' '.join(children)
|
||||
|
||||
self.params.sort(lambda x,y: cmp(x.name, y.name))
|
||||
for param in self.params:
|
||||
try:
|
||||
if param.value is None:
|
||||
|
|
|
|||
Loading…
Reference in a new issue