gem5/cpu
Steve Reinhardt 8031cd93b5 Standardize clock parameter names to 'clock'.
Fix description for Bus clock_ratio (no longer a ratio).
Add Clock param type (generic Frequency or Latency).

cpu/base_cpu.cc:
cpu/base_cpu.hh:
cpu/beta_cpu/alpha_full_cpu_builder.cc:
cpu/simple_cpu/simple_cpu.cc:
dev/ide_ctrl.cc:
dev/ns_gige.cc:
dev/ns_gige.hh:
dev/pciconfigall.cc:
dev/sinic.cc:
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
dev/uart.cc:
python/m5/objects/BaseCPU.py:
python/m5/objects/BaseCache.py:
python/m5/objects/BaseSystem.py:
python/m5/objects/Bus.py:
python/m5/objects/Ethernet.py:
python/m5/objects/Root.py:
sim/universe.cc:
    Standardize clock parameter names to 'clock'.
    Fix description for Bus clock_ratio (no longer a ratio).
python/m5/config.py:
    Minor tweaks on Frequency/Latency:
    - added new Clock param type to avoid ambiguities
    - factored out init code into getLatency()
    - made RootFrequency *not* a subclass of Frequency so it
    can't be directly assigned to a Frequency paremeter

--HG--
extra : convert_revision : fc4bb8562df171b454bbf696314cda57e1ec8506
2005-06-01 21:44:00 -04:00
..
beta_cpu Standardize clock parameter names to 'clock'. 2005-06-01 21:44:00 -04:00
full_cpu Add a new operation class for IPR accesses, and have IPR-accessing 2005-03-01 00:39:57 -05:00
memtest Make the notion of a global event tick independent of the actual 2005-04-11 15:32:06 -04:00
ooo_cpu Large update of several parts of my code. The most notable change is the inclusion of a full-fledged load/store queue. At the moment it still has some issues running, but most of the code is hopefully close to the final version. 2005-05-03 10:56:47 -04:00
simple_cpu Standardize clock parameter names to 'clock'. 2005-06-01 21:44:00 -04:00
trace Make the notion of a global event tick independent of the actual 2005-04-11 15:32:06 -04:00
base_cpu.cc Standardize clock parameter names to 'clock'. 2005-06-01 21:44:00 -04:00
base_cpu.hh Standardize clock parameter names to 'clock'. 2005-06-01 21:44:00 -04:00
base_dyn_inst.cc Added copyright. 2005-05-26 23:30:12 -04:00
base_dyn_inst.hh Added copyright. 2005-05-26 23:30:12 -04:00
exec_context.cc - Clean up and factor out all of the binning code into a 2004-08-20 11:35:31 -04:00
exec_context.hh Changed all syscalls to use syscall return object. 2005-03-09 15:52:10 -05:00
exetrace.cc Fix timing modeling of faults: functionally the very next instruction after 2005-02-25 12:41:08 -05:00
exetrace.hh Updated Copyright with information in bitkeeper changelogs 2004-06-08 13:37:27 -04:00
inst_seq.hh Updated Copyright with information in bitkeeper changelogs 2004-06-08 13:37:27 -04:00
intr_control.cc Updated Copyright with information in bitkeeper changelogs 2004-06-08 13:37:27 -04:00
intr_control.hh Updated Copyright with information in bitkeeper changelogs 2004-06-08 13:37:27 -04:00
pc_event.cc Clean up output for pc break events, and remove a unneeded break event. 2005-04-28 17:24:04 -04:00
pc_event.hh pc event now clears lower 2 bits 2004-09-16 15:11:38 -04:00
static_inst.cc Make all StaticInst methods const. StaticInst objects represent a 2005-02-25 21:44:33 -05:00
static_inst.hh Large update of several parts of my code. The most notable change is the inclusion of a full-fledged load/store queue. At the moment it still has some issues running, but most of the code is hopefully close to the final version. 2005-05-03 10:56:47 -04:00