Add the capability to read and write memory trace files. Currently is cycle accurate for a single thread FullCPU.
--HG-- extra : convert_revision : f8fe545313eb307cc6f5ff2c23894cc9870b1d5b
This commit is contained in:
parent
73308846cc
commit
5f4297e865
93
cpu/trace/reader/m5_reader.cc
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93
cpu/trace/reader/m5_reader.cc
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@ -0,0 +1,93 @@
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/*
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* Copyright (c) 2003-2004 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met: redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer;
|
||||
* redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution;
|
||||
* neither the name of the copyright holders nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/**
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* @file
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* Declaration of a memory trace reader for a M5 memory trace.
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*/
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#include "cpu/trace/reader/m5_reader.hh"
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#include "mem/trace/m5_format.hh"
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#include "mem/mem_cmd.hh"
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#include "sim/builder.hh"
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using namespace std;
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M5Reader::M5Reader(const string &name, const string &filename)
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: MemTraceReader(name)
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{
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traceFile.open(filename.c_str(), ios::binary);
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}
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Tick
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M5Reader::getNextReq(MemReqPtr &req)
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{
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M5Format ref;
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MemReqPtr tmp_req;
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// Need to read EOF char before eof() will return true.
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traceFile.read((char*) &ref, sizeof(ref));
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if (!traceFile.eof()) {
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//traceFile.read((char*) &ref, sizeof(ref));
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int gcount = traceFile.gcount();
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assert(gcount != 0 || traceFile.eof());
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assert(gcount == sizeof(ref));
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assert(ref.cmd < 12);
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tmp_req = new MemReq();
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tmp_req->paddr = ref.paddr;
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tmp_req->asid = ref.asid;
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tmp_req->cmd = (MemCmdEnum)ref.cmd;
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tmp_req->size = ref.size;
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tmp_req->dest = ref.dest;
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} else {
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ref.cycle = 0;
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}
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req = tmp_req;
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return ref.cycle;
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}
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BEGIN_DECLARE_SIM_OBJECT_PARAMS(M5Reader)
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Param<string> filename;
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END_DECLARE_SIM_OBJECT_PARAMS(M5Reader)
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BEGIN_INIT_SIM_OBJECT_PARAMS(M5Reader)
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INIT_PARAM(filename, "trace file")
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END_INIT_SIM_OBJECT_PARAMS(M5Reader)
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CREATE_SIM_OBJECT(M5Reader)
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{
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return new M5Reader(getInstanceName(), filename);
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}
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REGISTER_SIM_OBJECT("M5Reader", M5Reader)
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67
cpu/trace/reader/m5_reader.hh
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67
cpu/trace/reader/m5_reader.hh
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@ -0,0 +1,67 @@
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/*
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* Copyright (c) 2003-2004 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
|
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* modification, are permitted provided that the following conditions are
|
||||
* met: redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer;
|
||||
* redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution;
|
||||
* neither the name of the copyright holders nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/**
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* @file
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* Definition of a memory trace reader for a M5 memory trace.
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*/
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#ifndef __M5_READER_HH__
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#define __M5_READER_HH__
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#include <fstream>
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#include "cpu/trace/reader/mem_trace_reader.hh"
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/**
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* A memory trace reader for an M5 memory trace. @sa M5Writer.
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*/
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class M5Reader : public MemTraceReader
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{
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/** The traceFile. */
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std::ifstream traceFile;
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std::string fn;
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public:
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/**
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* Construct an M5 memory trace reader.
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*/
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M5Reader(const std::string &name, const std::string &filename);
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/**
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* Read the next request from the trace. Returns the request in the
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* provided MemReqPtr and the cycle of the request in the return value.
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* @param req Return the next request from the trace.
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* @return The cycle the reference was started.
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*/
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virtual Tick getNextReq(MemReqPtr &req);
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};
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#endif // __M5_READER_HH__
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37
cpu/trace/reader/mem_trace_reader.cc
Normal file
37
cpu/trace/reader/mem_trace_reader.cc
Normal file
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@ -0,0 +1,37 @@
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/*
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* Copyright (c) 2003-2004 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
|
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* modification, are permitted provided that the following conditions are
|
||||
* met: redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer;
|
||||
* redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution;
|
||||
* neither the name of the copyright holders nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/**
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* @file
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* SimObject Declaration of pure virtual MemTraceReader class.
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*/
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#include "cpu/trace/reader/mem_trace_reader.hh"
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#include "sim/param.hh"
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DEFINE_SIM_OBJECT_CLASS_NAME("MemTraceReader", MemTraceReader);
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57
cpu/trace/reader/mem_trace_reader.hh
Normal file
57
cpu/trace/reader/mem_trace_reader.hh
Normal file
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@ -0,0 +1,57 @@
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/*
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* Copyright (c) 2003-2004 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met: redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer;
|
||||
* redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution;
|
||||
* neither the name of the copyright holders nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/**
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* Definitions for a pure virtual interface to a memory trace reader.
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*/
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#ifndef __MEM_TRACE_READER_HH__
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#define __MEM_TRACE_READER_HH__
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#include "sim/sim_object.hh"
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#include "mem/mem_req.hh" // For MemReqPtr
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/**
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* Pure virtual base class for memory trace readers.
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*/
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class MemTraceReader : public SimObject
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{
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public:
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/** Construct this MemoryTrace reader. */
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MemTraceReader(const std::string &name) : SimObject(name) {}
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/**
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* Read the next request from the trace. Returns the request in the
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* provided MemReqPtr and the cycle of the request in the return value.
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* @param req Return the next request from the trace.
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* @return The cycle of the request, 0 if none in trace.
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*/
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virtual Tick getNextReq(MemReqPtr &req) = 0;
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};
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#endif //__MEM_TRACE_READER_HH__
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192
cpu/trace/trace_cpu.cc
Normal file
192
cpu/trace/trace_cpu.cc
Normal file
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@ -0,0 +1,192 @@
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/*
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* Copyright (c) 2003 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met: redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer;
|
||||
* redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution;
|
||||
* neither the name of the copyright holders nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/**
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* @file
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* Declaration of a memory trace CPU object. Uses a memory trace to drive the
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* provided memory hierarchy.
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*/
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#include <algorithm> // For min
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#include "cpu/trace/trace_cpu.hh"
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#include "cpu/trace/reader/mem_trace_reader.hh"
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#include "mem/base_mem.hh" // For PARAM constructor
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#include "mem/mem_interface.hh"
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#include "sim/builder.hh"
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#include "sim/sim_events.hh"
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using namespace std;
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TraceCPU::TraceCPU(const string &name,
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MemInterface *icache_interface,
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MemInterface *dcache_interface,
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MemTraceReader *inst_trace,
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MemTraceReader *data_trace,
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int icache_ports,
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int dcache_ports)
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: BaseCPU(name, 1), icacheInterface(icache_interface),
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dcacheInterface(dcache_interface), instTrace(inst_trace),
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dataTrace(data_trace), icachePorts(icache_ports),
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dcachePorts(dcache_ports), outstandingRequests(0), tickEvent(this)
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{
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if (instTrace) {
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assert(icacheInterface);
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nextInstCycle = instTrace->getNextReq(nextInstReq);
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}
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if (dataTrace) {
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assert(dcacheInterface);
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nextDataCycle = dataTrace->getNextReq(nextDataReq);
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}
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tickEvent.schedule(0);
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}
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void
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TraceCPU::tick()
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{
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assert(outstandingRequests >= 0);
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assert(outstandingRequests < 1000);
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int instReqs = 0;
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int dataReqs = 0;
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// Do data first to match tracing with FullCPU dumps
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while (nextDataReq && (dataReqs < dcachePorts) &&
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curTick >= nextDataCycle) {
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if (dcacheInterface->isBlocked())
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break;
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++outstandingRequests;
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++dataReqs;
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nextDataReq->time = curTick;
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nextDataReq->completionEvent =
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new TraceCompleteEvent(nextDataReq, this);
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dcacheInterface->access(nextDataReq);
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nextDataCycle = dataTrace->getNextReq(nextDataReq);
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}
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while (nextInstReq && (instReqs < icachePorts) &&
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curTick >= nextInstCycle) {
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if (icacheInterface->isBlocked())
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break;
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nextInstReq->time = curTick;
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if (nextInstReq->cmd == Squash) {
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icacheInterface->squash(nextInstReq->asid);
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} else {
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++outstandingRequests;
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++instReqs;
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nextInstReq->completionEvent =
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new TraceCompleteEvent(nextInstReq, this);
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icacheInterface->access(nextInstReq);
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}
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nextInstCycle = instTrace->getNextReq(nextInstReq);
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}
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if (!nextInstReq && !nextDataReq) {
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// No more requests to send. Finish trailing events and exit.
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if (mainEventQueue.empty()) {
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new SimExitEvent("Finshed Memory Trace");
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} else {
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tickEvent.schedule(mainEventQueue.nextEventTime() + 1);
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}
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} else {
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tickEvent.schedule(max(curTick + 1,
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min(nextInstCycle, nextDataCycle)));
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}
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}
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void
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TraceCPU::completeRequest(MemReqPtr& req)
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{
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--outstandingRequests;
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}
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void
|
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TraceCompleteEvent::process()
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{
|
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tester->completeRequest(req);
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}
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const char *
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TraceCompleteEvent::description()
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{
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return "trace access complete";
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}
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TraceCPU::TickEvent::TickEvent(TraceCPU *c)
|
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: Event(&mainEventQueue, CPU_Tick_Pri), cpu(c)
|
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{
|
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}
|
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|
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void
|
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TraceCPU::TickEvent::process()
|
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{
|
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cpu->tick();
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}
|
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|
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const char *
|
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TraceCPU::TickEvent::description()
|
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{
|
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return "TraceCPU tick event";
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}
|
||||
|
||||
|
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BEGIN_DECLARE_SIM_OBJECT_PARAMS(TraceCPU)
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|
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SimObjectParam<BaseMem *> icache;
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SimObjectParam<BaseMem *> dcache;
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SimObjectParam<MemTraceReader *> inst_trace;
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SimObjectParam<MemTraceReader *> data_trace;
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Param<int> inst_ports;
|
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Param<int> data_ports;
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|
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END_DECLARE_SIM_OBJECT_PARAMS(TraceCPU)
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BEGIN_INIT_SIM_OBJECT_PARAMS(TraceCPU)
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INIT_PARAM_DFLT(icache, "instruction cache", NULL),
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INIT_PARAM_DFLT(dcache, "data cache", NULL),
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INIT_PARAM_DFLT(inst_trace, "instruction trace", NULL),
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INIT_PARAM_DFLT(data_trace, "data trace", NULL),
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INIT_PARAM_DFLT(inst_ports, "instruction cache read ports", 4),
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INIT_PARAM_DFLT(data_ports, "data cache read/write ports", 4)
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|
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END_INIT_SIM_OBJECT_PARAMS(TraceCPU)
|
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|
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CREATE_SIM_OBJECT(TraceCPU)
|
||||
{
|
||||
return new TraceCPU(getInstanceName(),
|
||||
(icache) ? icache->getInterface() : NULL,
|
||||
(dcache) ? dcache->getInterface() : NULL,
|
||||
inst_trace, data_trace, inst_ports, data_ports);
|
||||
}
|
||||
|
||||
REGISTER_SIM_OBJECT("TraceCPU", TraceCPU)
|
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|
151
cpu/trace/trace_cpu.hh
Normal file
151
cpu/trace/trace_cpu.hh
Normal file
|
@ -0,0 +1,151 @@
|
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/*
|
||||
* Copyright (c) 2003 The Regents of The University of Michigan
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met: redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer;
|
||||
* redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution;
|
||||
* neither the name of the copyright holders nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
* Declaration of a memory trace CPU object. Uses a memory trace to drive the
|
||||
* provided memory hierarchy.
|
||||
*/
|
||||
|
||||
#ifndef __TRACE_CPU_HH__
|
||||
#define __TRACE_CPU_HH__
|
||||
|
||||
#include <string>
|
||||
|
||||
#include "cpu/base_cpu.hh"
|
||||
#include "mem/mem_req.hh" // for MemReqPtr
|
||||
#include "sim/eventq.hh" // for Event
|
||||
|
||||
// Forward declaration.
|
||||
class MemInterface;
|
||||
class MemTraceReader;
|
||||
|
||||
/**
|
||||
* A cpu object for running memory traces through a memory hierarchy.
|
||||
*/
|
||||
class TraceCPU : public BaseCPU
|
||||
{
|
||||
/** Interface for instruction trace requests, if any. */
|
||||
MemInterface *icacheInterface;
|
||||
/** Interface for data trace requests, if any. */
|
||||
MemInterface *dcacheInterface;
|
||||
|
||||
/** Instruction reference trace. */
|
||||
MemTraceReader *instTrace;
|
||||
/** Data reference trace. */
|
||||
MemTraceReader *dataTrace;
|
||||
|
||||
/** Number of Icache read ports. */
|
||||
int icachePorts;
|
||||
/** Number of Dcache read/write ports. */
|
||||
int dcachePorts;
|
||||
|
||||
/** Number of outstanding requests. */
|
||||
int outstandingRequests;
|
||||
|
||||
/** Cycle of the next instruction request, 0 if not available. */
|
||||
Tick nextInstCycle;
|
||||
/** Cycle of the next data request, 0 if not available. */
|
||||
Tick nextDataCycle;
|
||||
|
||||
/** Next instruction request. */
|
||||
MemReqPtr nextInstReq;
|
||||
/** Next data request. */
|
||||
MemReqPtr nextDataReq;
|
||||
|
||||
/**
|
||||
* Event to call the TraceCPU::tick
|
||||
*/
|
||||
class TickEvent : public Event
|
||||
{
|
||||
private:
|
||||
/** The associated CPU */
|
||||
TraceCPU *cpu;
|
||||
|
||||
public:
|
||||
/**
|
||||
* Construct this event;
|
||||
*/
|
||||
TickEvent(TraceCPU *c);
|
||||
|
||||
/**
|
||||
* Call the tick function.
|
||||
*/
|
||||
void process();
|
||||
|
||||
/**
|
||||
* Return a string description of this event.
|
||||
*/
|
||||
const char *description();
|
||||
};
|
||||
|
||||
TickEvent tickEvent;
|
||||
|
||||
public:
|
||||
/**
|
||||
* Construct a TraceCPU object.
|
||||
*/
|
||||
TraceCPU(const std::string &name,
|
||||
MemInterface *icache_interface,
|
||||
MemInterface *dcache_interface,
|
||||
MemTraceReader *inst_trace,
|
||||
MemTraceReader *data_trace,
|
||||
int icache_ports,
|
||||
int dcache_ports);
|
||||
|
||||
/**
|
||||
* Perform all the accesses for one cycle.
|
||||
*/
|
||||
void tick();
|
||||
|
||||
/**
|
||||
* Handle a completed memory request.
|
||||
*/
|
||||
void completeRequest(MemReqPtr &req);
|
||||
};
|
||||
|
||||
class TraceCompleteEvent : public Event
|
||||
{
|
||||
MemReqPtr req;
|
||||
TraceCPU *tester;
|
||||
|
||||
public:
|
||||
|
||||
TraceCompleteEvent(MemReqPtr &_req, TraceCPU *_tester)
|
||||
: Event(&mainEventQueue), req(_req), tester(_tester)
|
||||
{
|
||||
setFlags(AutoDelete);
|
||||
}
|
||||
|
||||
void process();
|
||||
|
||||
virtual const char *description();
|
||||
};
|
||||
|
||||
#endif //__TRACE_CPU_HH__
|
||||
|
Loading…
Reference in a new issue