Commit graph

4881 commits

Author SHA1 Message Date
Geoffrey Blake
d0b0a55515 O3: Fix offset calculation into storeQueue buffer for store->load forwarding
Calculation of offset to copy from storeQueue[idx].data structure for load to
store forwarding fixed to be difference in bytes between store and load virtual
addresses.  Previous method would induce bug where a load would index into
buffer at the wrong location.
2011-05-23 10:40:21 -05:00
Geoffrey Blake
c223b887fe O3: Fix issue w/wbOutstading being decremented multiple times on blocked cache.
If a split load fails on a blocked cache wbOutstanding can be decremented
twice if the first part of the split load succeeds and the second part fails.
Condition the decrementing on not having completed the first part of the load.
2011-05-23 10:40:19 -05:00
Geoffrey Blake
6dd996aabb O3: Fix issue with interrupts/faults occuring in the middle of a macro-op
This patch fixes two problems with the O3 cpu model. The first is an issue
with an instruction fetch causing a fault on the next address while the
current macro-op is being issued. This happens when the micro-ops exceed
the fetch bandwdith and then on the next cycle the fetch stage attempts
to issue a request to the next line while it still has micro-ops to issue
if the next line faults a fault is attached to a micro-op in the currently
executing macro-op rather than a "nop" from the next instruction block.
This leads to an instruction incorrectly faulting when on fetch when
it had no reason to fault.

A similar problem occurs with interrupts. When an interrupt occurs the
fetch stage nominally stops issuing instructions immediately. This is incorrect
in the case of a macro-op as the current location might not be interruptable.
2011-05-23 10:40:18 -05:00
Tushar Krishna
fc1d2d9679 garnet: use vnet_type from protocol to decide buffer depths
The virtual channels within "response" vnets are made buffers_per_data_vc
deep (default=4), while virtual channels within other vnets are made
buffers_per_ctrl_vc deep (default = 1). This is for accurate power estimates.
2011-05-21 00:40:57 -04:00
Tushar Krishna
3d06ffa7d5 slicc: added vnet_type to MI_example
Forgot to add this to MI_example in my previous patch.
2011-05-20 05:06:43 -04:00
Nathan Binkert
22263f5091 gcc: fix an uninitialized variable warning from G++ 4.5 2011-05-18 11:06:23 -07:00
Tushar Krishna
3ed048e4f5 slicc: added vnet_type field to identify response vnets from others
Identifying response vnets versus other vnets will allow garnet to
determine which vnets will carry data packets, and which will carry
ctrl packets, and use appropriate buffer sizes (since data packets are larger
than ctrl packets). This in turn allows the orion power model to accurately
estimate buffer power.
2011-05-18 03:06:07 -04:00
Tushar Krishna
26eaba4cb5 garnet: rename and rearrange config parameters.
Renamed (message) class to vnet for consistency with rest of ruby.
Moved some parameters specific to fixed/flexible garnet networks into their
corresponding py files.
2011-05-18 03:04:14 -04:00
Ali Saidi
b5160ba2c3 ARM: Generate condition code setting code based on which codes are set.
This change further eliminates cases where condition codes were being read
just so they could be written without change because the instruction in
question was supposed to preserve them. This is done by creating the condition
code code based on the input rather than just doing a simple substitution.
2011-05-13 17:27:02 -05:00
Ali Saidi
05866c82f9 ARM: Construct the predicate test register for more instruction programatically.
If one of the condition codes isn't being used in the execution we should only
read it if the instruction might be dependent on it. With the preeceding changes
there are several more cases where we should dynamically pick instead of assuming
as we did before.
2011-05-13 17:27:02 -05:00
Ali Saidi
401165c778 ARM: Further break up condition code into NZ, C, V bits.
Break up the condition code bits into NZ, C, V registers. These are individually
written and this removes some incorrect dependencies between instructions.
2011-05-13 17:27:01 -05:00
Ali Saidi
e097c4fb18 ARM: Remove the saturating (Q) condition code from the renamed register.
Move the saturating bit (which is also saturating) from the renamed register
that holds the flags to the CPSR miscreg and adds a allows setting it in a
similar way to the FP saturating registers. This removes a dependency in
instructions that don't write, but need to preserve the Q bit.
2011-05-13 17:27:01 -05:00
Ali Saidi
2178859b76 ARM: Break up condition codes into normal flags, saturation, and simd.
This change splits out the condcodes from being one monolithic register
into three blocks that are updated independently. This allows CPUs
to not have to do RMW operations on the flags registers for instructions
that don't write all flags.
2011-05-13 17:27:01 -05:00
Chander Sudanthi
4bf48a11ef Trace: Allow printing ASIDs and selectively tracing based on user/kernel code.
Debug flags are ExecUser, ExecKernel, and ExecAsid. ExecUser and
ExecKernel are set by default when Exec is specified.  Use minus
sign with ExecUser or ExecKernel to remove user or kernel tracing
respectively.
2011-05-13 17:27:00 -05:00
Chander Sudanthi
5299c75e62 ARM: Better RealView/Versatile EB platform support.
Add registers and components to better support the VersatileEB board.
Made the MIDR and SYS_ID register parameters to ArmSystem and RealviewCtrl
respectively.
2011-05-13 17:27:00 -05:00
Geoffrey Blake
b79650ceaa O3: Fix an issue with a load & branch instruction and mem dep squashing
Instructions that load an address and are control instructions can
execute down the wrong path if they were predicted correctly and then
instructions following them are squashed. If an instruction is a
memory and control op use the predicted address for the next PC instead
of just advancing the PC. Without this change NPC is used for the next
instruction, but predPC is used to verify that the branch was successful
so the wrong path is silently executed.
2011-05-13 17:27:00 -05:00
Nathan Binkert
f7b3900c13 stats: delete mysql support
we can add it back within python in some future changeset
2011-05-12 11:19:35 -07:00
Nathan Binkert
1177e7a3c8 stats: move code that loops over all stats into python 2011-05-12 11:19:35 -07:00
Nathan Binkert
35b0c1d391 stats: better expose statistics to python.
Build a python list and dict of all stats and expose flags properly.

--HG--
rename : src/python/m5/stats.py => src/python/m5/stats/__init__.py
2011-05-12 11:19:32 -07:00
Nathan Binkert
9c4c1419a7 work around gcc 4.5 warning 2011-05-09 16:34:11 -04:00
Tushar Krishna
1267ff5949 NetworkTest: added sim_cycles parameter to the network tester.
The network tester terminates after injecting for sim_cycles
(default=1000), instead of having to explicitly pass --maxticks from the
command line as before. If fixed_pkts is enabled, the tester only
injects maxpackets number of packets, else it keeps injecting till sim_cycles.
The tester also works with zero command line arguments now.
2011-05-07 17:43:30 -04:00
Tushar Krishna
770f2ce330 network: added Torus and Pt2Pt topologies 2011-05-07 17:28:15 -04:00
Nilay Vaish
ffaef14466 Trace: Remove the options trace-help and trace-flags
The options trace-help and trace-flags are no longer required. In there place,
the options debug-help and debug-flags have been provided.
2011-05-07 07:38:36 -05:00
Gabe Black
b8889a96b3 X86: Fix the Lldt instructions so they load the ldtr and not the tr. 2011-05-06 01:00:32 -07:00
Korey Sewell
a0415f2b24 ruby: use RubyMemory flag & remove setDebug() functionality
The RubyMemory flag wasnt used in the code, creating large gaps in trace output. Replace cprintfs w/dprintfs
using RubyMemory in memory controller. DPRINTF also deprecate the usage of the setDebug() pure virtual
function in the AbstractMemoryOrCache Class as well the m_debug/cprintf functions in MemoryControl.hh/cc
2011-05-05 02:20:31 -04:00
Ali Saidi
42e7888855 ARM: Add support for loading the a bootloader and configuring parameters for it 2011-05-04 20:38:28 -05:00
Prakash Ramrakhyani
1b505f5291 ARM: Implement WFE/WFI/SEV semantics. 2011-05-04 20:38:28 -05:00
Ali Saidi
ba8d64520e ARM: Add support for MP misc regs and broadcast flushes. 2011-05-04 20:38:28 -05:00
Prakash Ramrakhyani
13574d8b4e ARM: Make GIC handle IPIs and multiple processors. 2011-05-04 20:38:27 -05:00
Ali Saidi
5f73d4ac97 ARM: Add snoop control unit device. 2011-05-04 20:38:27 -05:00
Ali Saidi
afd08879d7 ARM: Add support for some more registers in the real view controller. 2011-05-04 20:38:27 -05:00
Ali Saidi
8aff996db1 Debug: Add a function to cause the simulator to create a checkpoint from GDB. 2011-05-04 20:38:27 -05:00
Ali Saidi
77bea2fb42 CPU: Add some useful debug message to the timing simple cpu. 2011-05-04 20:38:27 -05:00
Ali Saidi
6e634beb8a CPU: Fix a case where timing simple cpu faults can nest.
If we fault, change the state to faulting so that we don't fault again in the same cycle.
2011-05-04 20:38:27 -05:00
Ali Saidi
89e7bcca82 O3: Remove assertion for case that is actually handled in code.
If an nonspeculative instruction has a fault it might not be in the
nonSpecInsts map.
2011-05-04 20:38:27 -05:00
Ali Saidi
974a776b31 Core: Add some documentation about the sim clocks. 2011-05-04 20:38:27 -05:00
Chris Emmons
8dcbf8576e RealView: Fix the 24 and 100MHz clocks which were providing incorrect values. 2011-05-04 20:38:26 -05:00
Ali Saidi
09a2be0c39 O3: Fix a small corner case with the lsq hazard detection logic. 2011-05-04 20:38:26 -05:00
Ali Saidi
48f7fda706 ARM: Add vfpv3 support to native trace. 2011-05-04 20:38:26 -05:00
Ali Saidi
632cf8dd80 ARM: Fix small bug with vcvt instruction 2011-05-04 20:38:26 -05:00
Nathan Binkert
0dffd35741 debug: fix help output 2011-05-04 10:08:08 -04:00
Korey Sewell
dd95bc4d44 ruby: dbg: use system ticks instead of cycles 2011-05-02 00:16:14 -04:00
Brad Beckmann
93a50fc318 network: set the ExtLink bw to 16 bytes
Therefore all links by default are 16 bytes wide and thus work with Garnet's
uniform link bandwidth assumption.
2011-04-28 17:18:14 -07:00
Brad Beckmann
6c7429dbe3 garnet: removed flit_width from Routers 2011-04-28 17:18:14 -07:00
Brad Beckmann
651cfbab03 network: adjusted default endpoint bandwidth
The simple network's endpoint bandwidth value is used to adjust the overall
bandwidth of the network.  Specifically, the ration between endpoint bandwidth
and the MESSAGE_SIZE_MULTIPLIER determines the increase.  By setting the value
to 1000, that means the bandwdith factor specified in the links translates to
the link bandwidth in bytes.  Previously, it was increasing that value by 10.

This patch will likely require a reset of the ruby regression tester stats.
2011-04-28 17:18:14 -07:00
Brad Beckmann
887e2df5a3 network: removed the unused network-wide latency param 2011-04-28 17:18:14 -07:00
Brad Beckmann
491cc1a9f4 network: moved network config params
Moved the buffer_size, endpoint_bandwidth, and adaptive_routing params out of
the top-level parent network object and to only those networks that actually
use those parameters.
2011-04-28 17:18:14 -07:00
Brad Beckmann
8733ed4b7d network: basic link bw for garnet and simple networks
This patch ensures that both Garnet and the simple networks use the bw value
specified in the topology.  To do so, the patch generalizes the specification
of bw for basic links.  This value is then translated to the specific value
used by the simple and Garnet networks.  Since Garent does not support
non-uniformed link bandwidth, the patch also adds a check to ensure all bws are
equal.

--HG--
rename : src/mem/ruby/network/BasicLink.cc => src/mem/ruby/network/simple/SimpleLink.cc
rename : src/mem/ruby/network/BasicLink.hh => src/mem/ruby/network/simple/SimpleLink.hh
rename : src/mem/ruby/network/BasicLink.py => src/mem/ruby/network/simple/SimpleLink.py
2011-04-28 17:18:14 -07:00
Brad Beckmann
40bcbf4253 network: convert links & switches to first class C++ SimObjects
This patch converts links and switches from second class simobjects that were
virtually ignored by the networks (both simple and Garnet) to first class
simobjects that directly correspond to c++ ojbects manipulated by the
topology and network classes.  This is especially true for Garnet, where the
links and switches directly correspond to specific C++ objects.

By making this change, many aspects of the Topology class were simplified.

--HG--
rename : src/mem/ruby/network/Network.cc => src/mem/ruby/network/BasicLink.cc
rename : src/mem/ruby/network/Network.hh => src/mem/ruby/network/BasicLink.hh
rename : src/mem/ruby/network/Network.cc => src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.cc
rename : src/mem/ruby/network/Network.hh => src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.hh
rename : src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.py => src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.py
rename : src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.py => src/mem/ruby/network/garnet/fixed-pipeline/GarnetRouter_d.py
rename : src/mem/ruby/network/Network.cc => src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.cc
rename : src/mem/ruby/network/Network.hh => src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.hh
rename : src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.py => src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.py
rename : src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.py => src/mem/ruby/network/garnet/flexible-pipeline/GarnetRouter.py
2011-04-28 17:18:14 -07:00
Brad Beckmann
bc5eb59605 garnet: cleaned up flexible network header file 2011-04-28 17:18:12 -07:00
Brad Beckmann
cf9ce2cf28 ruby: moved topology to the top network directory
Moved the Topology class to the top network directory because it is shared by
both the simple and Garnet networks.

--HG--
rename : src/mem/ruby/network/simple/Topology.cc => src/mem/ruby/network/Topology.cc
rename : src/mem/ruby/network/simple/Topology.hh => src/mem/ruby/network/Topology.hh
2011-04-28 17:18:12 -07:00
Brad Beckmann
7adb8fa94b ruby: removed dated comment in SimpleNetwork 2011-04-28 17:18:12 -07:00
Nathan Binkert
3e319d6e94 event: fix PythonEvent
order of %includes since they matter for this case
2011-04-28 16:45:17 -07:00
Nilay Vaish
9e3cdbf516 base: include types.hh in base/stats/mysql.hh
Due to certain changes made via changeset 8229, the compilation was failing
in certain cases. The compiler pointed to base/stats/mysql.hh for not naming
a certain types like uint64_t. To rectify this, base/types.hh is being
included in base/stats/mysql.hh.
2011-04-25 12:23:37 -05:00
Gabe Black
0554885eb9 X86: When decoding a memory only inst, fault on reg encodings, don't assert.
This change makes the decoder figure out if an instruction that only supports
memory is using a register encoding and decodes directly to "Unknown" which will
behave appropriately. This prevents other parts of the instruction creation
process from seeing the mismatch and asserting.
2011-04-23 15:02:29 -07:00
Nathan Binkert
2342aa2ebb stats: ensure that stat names are valid 2011-04-20 19:07:46 -07:00
Nathan Binkert
6e9143d36d stats: one more name violation 2011-04-20 19:07:45 -07:00
Nathan Binkert
99fbd18ea5 fix some build problems from prior changesets 2011-04-20 18:45:03 -07:00
Brad Danofsky
46a538ceab stats: add user settable separator string for arrayed stats
Default is '::', so no visible change unless it is overridden
2011-04-20 11:14:52 -07:00
Brad Danofsky
dd38b4b83e scons: Allow the build directory live under an EXTRAS directory 2011-04-20 11:14:51 -07:00
Nathan Binkert
63371c8664 stats: rename stats so they can be used as python expressions 2011-04-19 18:45:21 -07:00
Nathan Binkert
615c5e0eaa python: different import for dealing with demandimport 2011-04-19 11:13:01 -07:00
Nathan Binkert
915f49ae92 unittest: Make unit tests capable of using swig and python, convert stattest 2011-04-15 10:45:11 -07:00
Nathan Binkert
8c97726266 python: cleanup python code so stuff doesn't automatically happen at startup
this allows things to be overridden at startup (e.g. for tests)
2011-04-15 10:44:59 -07:00
Nathan Binkert
3182913e94 scons: make a flexible system for guarding source files
This is similar to guards on mercurial queues and they're used for selecting
which files are compiled into some given object.  We already do something
similar, but it's mostly hard coded for the m5 binary and the m5 library
and I'd like to make it more flexible to better support the unittests
2011-04-15 10:44:44 -07:00
Nathan Binkert
eddac53ff6 trace: reimplement the DTRACE function so it doesn't use a vector
At the same time, rename the trace flags to debug flags since they
have broader usage than simply tracing.  This means that
--trace-flags is now --debug-flags and --trace-help is now --debug-help
2011-04-15 10:44:32 -07:00
Nathan Binkert
f946d7bcdb debug: create a Debug namespace 2011-04-15 10:44:15 -07:00
Nathan Binkert
bbb1392c08 includes: fix up code after sorting 2011-04-15 10:44:14 -07:00
Nathan Binkert
39a055645f includes: sort all includes 2011-04-15 10:44:06 -07:00
Nathan Binkert
07815c3379 region: add a utility class for keeping track of regions of some range
This is basically like the range_map stuff in src/base (range already
exists in Python).  This code is like a set of ranges.  I'm using it
to keep track of changed lines in source code, but it could be use to
keep track of memory ranges and holes in memory regions.  It could
also be used in memory allocation type stuff.  (Though it's not at all
optimized.)
2011-04-15 10:42:32 -07:00
Nathan Binkert
12446e9659 SortedDict: add functions for getting ranges of keys, values, items 2011-04-15 10:38:02 -07:00
Nathan Binkert
1f7f79781e python: figure out if the m5.internal package exists even with demandimport 2011-04-15 10:37:28 -07:00
Nathan Binkert
3c78005c1e refcnt: Update doxygen comments 2011-04-13 09:32:19 -07:00
Nathan Binkert
e748d921fd refcnt: Inline comparison functions 2011-04-13 09:32:18 -07:00
Nathan Binkert
9d94d48a7d main: separate out interact() so it can be used by other functions 2011-04-13 09:32:18 -07:00
Ali Saidi
4b61abe8da ARM: Fix checkpoint restoration in ARM_SE. 2011-04-10 21:02:28 -04:00
Ali Saidi
b9dc954d89 ARM: Get rid of some comments/todos that no longer apply. 2011-04-10 21:02:28 -04:00
Brad Beckmann
95faf1904b ruby: fixes to support more types of RubyRequests 2011-04-06 14:41:41 -07:00
Ali Saidi
d6289507d8 ARM: Include IDE/CF controller by default in PBX model.
Frame buffer and boot linux:
./build/ARM_FS/m5.opt configs/example/fs.py --benchmark=ArmLinuxFrameBuf --kernel=vmlinux.touchkit
Linux from a CF card:
./build/ARM_FS/m5.opt configs/example/fs.py --benchmark=ArmLinuxCflash --kernel=vmlinux.touchkit
Run Android
./build/ARM_FS/m5.opt configs/example/fs.py --benchmark=ArmAndroid --kernel=vmlinux.android
Run MP
./build/ARM_FS/m5.opt configs/example/fs.py --benchmark=ArmLinuxCflash --kernel=vmlinux.mp-2.6.38
2011-04-04 11:42:31 -05:00
Ali Saidi
8af1eeec6f ARM: Use CPU local lock before sending load to mem system.
This change uses the locked_mem.hh header to handle implementing CLREX. It
simplifies the current implementation greatly.
2011-04-04 11:42:29 -05:00
Ali Saidi
6b69890493 ARM: Fix checkpoint restoration into O3 CPU and the way O3 switchCpu works.
This change fixes a small bug in the arm copyRegs() code where some registers
wouldn't be copied if the processor was in a mode other than MODE_USER.
Additionally, this change simplifies the way the O3 switchCpu code works by
utilizing TheISA::copyRegs() to copy the required context information
rather than the adhoc copying that goes on in the CPU model. The current code
makes assumptions about the visibility of int and float registers that aren't
true for all architectures in FS mode.
2011-04-04 11:42:28 -05:00
Ali Saidi
f926fa7711 ARM: Fix bug in MicroLdrNeon templates for initiateAcc(). 2011-04-04 11:42:28 -05:00
William Wang
16fcad3907 ARM: Cleanup and small fixes to some NEON ops to match the spec.
Only certain bits of the cpacr can be written, some must be equal.
Mult instructions that write the same register should do something sane
2011-04-04 11:42:28 -05:00
Ali Saidi
a679cd917a ARM: Cleanup implementation of ITSTATE and put important code in PCState.
Consolidate all code to handle ITSTATE in the PCState object rather than
touching a variety of structures/objects.
2011-04-04 11:42:28 -05:00
Ali Saidi
ac650199ee ARM: Fix m5op parameters bug.
All the m5op parameters are 64 bits, but we were only sending 32 bits;
and the static register indexes were incorrectly specified.
2011-04-04 11:42:28 -05:00
Ali Saidi
be096f91b9 ARM: Tag appropriate instructions as IsReturn 2011-04-04 11:42:27 -05:00
Ali Saidi
55920a5ca7 ARM: Fix table walk going on while ASID changes error 2011-04-04 11:42:27 -05:00
Ali Saidi
5962fecc1d CPU: Remove references to memory copy operations 2011-04-04 11:42:26 -05:00
Ali Saidi
7dde557fdc O3: Tighten memory order violation checking to 16 bytes.
The comment in the code suggests that the checking granularity should be 16
bytes, however in reality the shift by 8 is 256 bytes which seems much
larger than required.
2011-04-04 11:42:23 -05:00
Ali Saidi
ee489a541a IDE: Support x86, Alpha, and ARM use of the IDE controller. 2011-04-04 11:42:23 -05:00
Ali Saidi
c56eb8fb3c ARM: Fix checkpointing case where PL111 is powered off. 2011-04-04 11:42:23 -05:00
Ali Saidi
6fd271ffb3 ARM: Remove debugging warn that was accidently left in. 2011-04-04 11:42:23 -05:00
Ali Saidi
dfdabbd751 ARM: Fix multiplication error in udelay 2011-04-04 11:42:23 -05:00
Brad Beckmann
0788ea7b3b hammer: fixed dma uniproc error
Fixed an error reguarding DMA for uninprocessor systems.  Basically removed an
overly agressive optimization that lead to inconsistent state between the
cache and the directory.
2011-04-01 15:50:23 -07:00
Lisa Hsu
01fc529bb2 CacheMemory: add allocateVoid() that is == allocate() but no return value.
This function duplicates the functionality of allocate() exactly, except that it does not return
a return value.  In protocols where you just want to allocate a block
but do not want that block to be your implicitly passed cache_entry, use this function.
Otherwise, SLICC will complain if you do not consume the pointer returned by allocate(),
and if you do a dummy assignment Entry foo := cache.allocate(address), the C++
compiler will complain of an unused variable.  This is kind of a hack to get around
those issues, but suggestions welcome.
2011-03-31 18:20:12 -07:00
Lisa Hsu
d857105b5a Ruby: Simplify SLICC and Entry/TBE handling.
Before this changeset, all local variables of type Entry and TBE were considered
to be pointers, but an immediate use of said variables would not be automatically
deferenced in SLICC-generated code.  Instead, deferences occurred when such
variables were passed to functions, and were automatically dereferenced in
the bodies of the functions (e.g. the implicitly passed cache_entry).

This is a more general way to do it, which leaves in place the
assumption that parameters to functions and local variables of type AbstractCacheEntry
and TBE are always pointers, but instead of dereferencing to access member variables
on a contextual basis, the dereferencing automatically occurs on a type basis at the
moment a member is being accessed.  So, now, things you can do that you couldn't before
include:

Entry foo := getCacheEntry(address);
cache_entry.DataBlk := foo.DataBlk;

or

cache_entry.DataBlk := getCacheEntry(address).DataBlk;

or even

cache_entry.DataBlk := static_cast(Entry, pointer, cache.lookup(address)).DataBlk;
2011-03-31 17:18:00 -07:00
Lisa Hsu
322b9ca2c5 Ruby: Add new object called WireBuffer to mimic a Wire.
This is a substitute for MessageBuffers between controllers where you don't
want messages to actually go through the Network, because requests/responses can
always get reordered wrt to one another (even if you turn off Randomization and turn on Ordered)
because you are, after all, going through a network with contention. For systems where you model
multiple controllers that are very tightly coupled and do not actually go through a network,
it is a pain to have to write a coherence protocol to account for mixed up request/response orderings
despite the fact that it's completely unrealistic.  This is *not* meant as a substitute for real
MessageBuffers when messages do in fact go over a network.
2011-03-31 17:17:57 -07:00
Lisa Hsu
06fcaf9104 Ruby: have the rubytester pass contextId to Ruby. 2011-03-31 17:17:51 -07:00
Lisa Hsu
c9621cc69b Ruby: enable multiple sequencers in one controller. 2011-03-31 17:17:49 -07:00
Lisa Hsu
225e67f531 Ruby: pass Packet->Req->contextId() to Ruby.
It is useful for Ruby to understand from whence request packets came.
This has all request packets going into Ruby pass the contextId value, if
it exists.  This supplants the old libruby proc_id value passed around in
all the Messages, so I've also removed the unused unsigned proc_id; member
generated by SLICC for all Message types.
2011-03-31 17:17:47 -07:00
Lisa Hsu
f6a0b63d7b Ruby: Bug in SLICC forgot semicolon at end of code. 2011-03-31 12:20:16 -07:00
Korey Sewell
473bc21977 sim: typecast Tick to UTick for eventQ assert 2011-03-29 19:36:36 -04:00
Gabe Black
ccc8ba2033 Power: Fix compilation. 2011-03-29 13:04:19 -04:00
Somayeh Sardashti
c8bbfed937 This patch supports cache flushing in MOESI_hammer 2011-03-28 10:49:45 -05:00
Korey Sewell
e0fdd86fd9 mips: cleanup ISA-specific code
***
(1): get rid of expandForMT function
MIPS is the only ISA that cares about having a piece of ISA state integrate
multiple threads so add constants for MIPS and relieve the other ISAs from having
to define this. Also, InOrder was the only core that was actively calling
this function
* * *
(2): get rid of corespecific type
The CoreSpecific type was used as a proxy to pass in HW specific params to
a MIPS CPU, but since MIPS FS hasnt been touched for awhile, it makes sense
to not force every other ISA to use CoreSpecific as well use a special
reset function to set it. That probably should go in a PowerOn reset fault
 anyway.
2011-03-26 09:23:52 -04:00
Gabe Black
6db65b40c1 Arm: Add in a missing miscRegName. 2011-03-25 00:46:14 -04:00
Gabe Black
475685df49 Arm: Get rid of unused and incomplete setCp15Register and readCp15Register. 2011-03-24 14:39:00 -04:00
Gabe Black
5d09a78dce Arm: Get rid of the unused copyStringArray32 method from Arm process classes. 2011-03-24 14:00:15 -04:00
Gabe Black
57ed5e77fe ISA parser: Set up op_src_decl and op_dest_decl for pc operands. 2011-03-24 13:55:16 -04:00
Tushar Krishna
531f54fb51 This patch fixes a build error in networktest.cc that occurs with gcc4.2 2011-03-22 23:38:09 -04:00
Nilay Vaish
1764ebbf30 Ruby: Remove CacheMsg class from SLICC
The goal of the patch is to do away with the CacheMsg class currently in use
in coherence protocols. In place of CacheMsg, the RubyRequest class will used.
This class is already present in slicc_interface/RubyRequest.hh. In fact,
objects of class CacheMsg are generated by copying values from a RubyRequest
object.
2011-03-22 06:41:54 -05:00
Tushar Krishna
46cce440be This patch makes garnet use the info about active and inactive vnets during allocation and power estimations etc 2011-03-21 22:51:59 -04:00
Tushar Krishna
1b9002eefc fix garnet fleible pipeline 2011-03-21 22:51:59 -04:00
Tushar Krishna
09c3a97a4c This patch adds the network tester for simple and garnet networks.
The tester code is in testers/networktest.
The tester can be invoked by configs/example/ruby_network_test.py.
A dummy coherence protocol called Network_test is also addded for network-only simulations and testing. The protocol takes in messages from the tester and just pushes them into the network in the appropriate vnet, without storing any state.
2011-03-21 22:51:58 -04:00
Nilay Vaish
d7aa794155 SLICC: Remove WakeUp* import calls from ast/__init__.py
I had recently committed a patch that removed the WakeUp*.py files from the
slicc/ast directory. I had forgotten to remove the import  calls for these
files from slicc/ast/__init__.py. This resulted in error while running
regressions on zizzer. This patch does the needful.
2011-03-20 09:23:27 -05:00
Nilay Vaish
611f052e96 Ruby: Convert CacheRequestType to RubyRequestType
This patch converts CacheRequestType to RubyRequestType so that both the
protocol dependent and independent code makes use of the same request type.
2011-03-19 18:34:59 -05:00
Nilay Vaish
2f4276448b Ruby: Convert AccessModeType to RubyAccessMode
This patch converts AccessModeType to RubyAccessMode so that both the
protocol dependent and independent code uses the same access mode.
2011-03-19 18:34:37 -05:00
Brad Beckmann
dd9083115e MOESI_hammer: minor fixes to full-bit dir 2011-03-19 14:17:48 -07:00
Brad Beckmann
541fa1091a Ruby: dma retry fix
This patch fixes the problem where Ruby would fail to call sendRetry on ports
after it nacked the port.  This patch is particularly helpful for bursty dma
requests which often include several packets.
2011-03-19 14:17:48 -07:00
Brad Beckmann
d1cecc2241 RubyPort: minor fixes to trace flag and dprintfs 2011-03-19 14:17:48 -07:00
Brad Beckmann
8e61805a21 ruby: added useful dma progress dprintf 2011-03-19 14:17:48 -07:00
Brad Beckmann
08d73529bc slicc: improved invalid transition message 2011-03-19 14:17:48 -07:00
Brad Beckmann
31d0a421a9 MOESI_hammer: fixed dma bug with shared data 2011-03-19 14:17:48 -07:00
Brad Beckmann
a2e98f191f MOESI_CMP_directory: significant dma bug fixes 2011-03-19 14:17:48 -07:00
Nilay Vaish
18142df5b9 SLICC: Remove external_type for structures
In SLICC, in order to define a type a data type for which it should not
generate any code, the keyword external_type is used. For those data types for
which code should be generated, the keyword structure is used. This patch
eliminates the use of keyword external_type for defining structures. structure
key word can now have an optional attribute external, which would be used for
figuring out whether or not to generate the code for this structure. Also, now
structures can have functions as well data members in them.
2011-03-18 14:12:04 -05:00
Nilay Vaish
3f27ccbb54 SLICC: Remove the keyword wake_up_dependents
In order to add stall and wait facility for protocols, a keyword
wake_up_dependents was introduced. This patch removes the keyword,
instead this functionality is now implemented as function call.
2011-03-18 14:12:03 -05:00
Nilay Vaish
847ba941ea SLICC: Remove the keyword wake_up_all_dependents
In order to add stall and wait facility for protocols, a keyword
wake_up_all_dependents was introduced. This patch removes the keyword,
instead this functionality is now implemented as function call.
2011-03-18 14:12:01 -05:00
Steve Reinhardt
cc14689a86 swig: get rid of m5.internal.random module (swig/random.i)
Thanks to swig this was interfering with the standard Python
random module.  The only function in that module was seed(),
which erroneously called srand48().  Moved the function to
m5.internal.core, renamed it seedRandom(), and made it call
random_mt.init() instead.
2011-03-18 11:47:15 -07:00
Steve Reinhardt
38aa50bb49 base: disable FastAlloc in debug builds by default
FastAlloc's reuse policies can mask allocation bugs, so
we typically want it disabled when debugging.  Set
FORCE_FAST_ALLOC to enable even when debugging, and set
NO_FAST_ALLOC to disable even in non-debug builds.
2011-03-18 11:47:11 -07:00
Ali Saidi
6daf44dae6 Automated merge with ssh://hg@repo.m5sim.org/m5 2011-03-17 19:24:37 -05:00
Chris Emmons
ccaaa98b49 ARM: Add minimal ARM_SE support for m5threads.
Updated some of the assembly code sequences to use armv7 instructions and
coprocessor 15 for storing the TLS pointer.
2011-03-17 19:20:20 -05:00
Ali Saidi
53ab306acc ARM: Fix subtle bug in LDM.
If the instruction faults mid-op the base register shouldn't be written back.
2011-03-17 19:20:20 -05:00
Ali Saidi
4c7a7796ad ARM: Implement the Instruction Set Attribute Registers (ISAR).
The ISAR registers describe which features the processor supports.
Transcribe the values listed in section B5.2.5 of the ARM ARM
into the registers as read-only values
2011-03-17 19:20:20 -05:00
Ali Saidi
5480ec798a ARM: Identify branches as conditional or unconditional and direct or indirect. 2011-03-17 19:20:20 -05:00
Ali Saidi
b754ad85c0 ARM: Fix small bug with VLDM/VSTM instructions. 2011-03-17 19:20:20 -05:00
Ali Saidi
b78be240cf ARM: Detect and skip udelay() functions in linux kernel.
This change speeds up booting, especially in MP cases, by not executing
udelay() on the core but instead skipping ahead tha amount of time that is being
delayed.
2011-03-17 19:20:20 -05:00
Ali Saidi
fe3d790ac8 ARM: Allow conditional quiesce instructions.
This patch prevents not executed conditional instructions marked as
IsQuiesce from stalling the pipeline indefinitely. If the instruction
is not executed the quiesceSkip psuedoinst is called which schedules a
wakes up call to the fetch stage.
2011-03-17 19:20:20 -05:00
Matt Horsnell
031f396c71 ARM: Fix RFE macrop.
This changes the RFE macroop into 3 microops:

URa = [sp]; URb = [sp+4]; // load CPSR,PC values from stack
sp = sp + offset;         // optionally auto-increment
PC = URa; CPSR = URb;     // write to the PC and CPSR.

Importantly:
- writing to PC is handled in the last micro-op.
- loading occurs prior to state changes.
2011-03-17 19:20:19 -05:00
Matt Horsnell
e65f480d62 ARM: Rename registers used as temporary state by microops. 2011-03-17 19:20:19 -05:00
Ali Saidi
799c3da8d0 O3: Send instruction back to fetch on squash to seed predecoder correctly. 2011-03-17 19:20:19 -05:00
Ali Saidi
30143baf7e O3: Cleanup the commitInfo comm struct.
Get rid of unused members and use base types rather than derrived values
where possible to limit amount of state.
2011-03-17 19:20:19 -05:00
Ali Saidi
db35053655 ARM: Previous change didn't end up setting instFlags, this does. 2011-03-17 19:20:19 -05:00
Ali Saidi
a432d8e085 Mem: Fix issue with dirty block being lost when entire block transferred to non-cache.
This change fixes the problem for all the cases we actively use. If you want to try
more creative I/O device attachments (E.g. sharing an L2), this won't work. You
would need another level of caching between the I/O device and the cache
(which you actually need anyway with our current code to make sure writes
propagate). This is required so that you can mark the cache in between as
top level and it won't try to send ownership of a block to the I/O device.
Asserts have been added that should catch any issues.
2011-03-17 19:20:19 -05:00
Ali Saidi
2f40b3b8ae O3: Fix unaligned stores when cache blocked
Without this change the a store can be issued to the cache multiple times.
If this case occurs when the l1 cache is out of mshrs (and thus blocked)
the processor will never make forward progress because each cycle it will
send a single request using the recently freed mshr and not completing the
multipart store. This will continue forever.
2011-03-17 19:20:19 -05:00
Lisa Hsu
c4de6a0522 Ruby: minor bugfix, line did not adhere to some macro usage conventions. 2011-03-17 17:08:35 -07:00
Lisa Hsu
556b5c5488 Ruby: expose a simple mod function in slicc interface. 2011-03-17 17:01:41 -07:00
Gabe Black
02f10fbdc8 SCons: Stop embedding the mercurial revision into the binary.
This causes a lot of rebuilds that could have otherwise possibly been
avoided, and, more annoyingly, a lot of unnecessary rerunning of the
regressions. The benefits of having the revision in the output haven't
materialized, so this change removes it.
2011-03-11 11:27:36 -08:00
Gabe Black
b6ba1a528b Gems: Eliminate the now unused GEMS_ROOT scons variable. 2011-03-11 11:27:26 -08:00
Gabe Black
a78e772929 Ruby: Get rid of the dead ruby tester.
None of the code in the ruby tester directory is compiled or referred to
outside of that directory. This change eliminates it. If it's needed in the
future, it can be revived from the history. In the mean time, this removes
clutter and the only use of the GEMS_ROOT scons variable.
2011-03-11 11:27:16 -08:00
Yi Xiang
d7b5508875 Alpha: Fix the datatypes of some values read from the simulated kernel. 2011-03-08 21:43:11 -08:00
Gabe Black
96e0f3bda5 SCons: Clean up some inconsistent capitalization in scons options. 2011-03-03 23:55:21 -08:00
Gabe Black
07b507d278 X86: Use the npc as the pc when doing a nativetrace, not what M5 considers the pc. 2011-03-02 00:41:44 -08:00
Gabe Black
8966312785 X86: Decode the mysterious and elusive ffreep x87 instruction.
The internet says this instruction was created by accident when an Intel CPU
failed to decode x87 instructions properly. It's been documented on a few rare
occasions and has generally worked to ensure backwards compatability. One
source claims that the gcc toolchain is basically the only thing that emits
it, and that emulators/binary translators like qemu and bochs implement it.

We won't actually implement it here since we're hardly implementing any other
x87 instructions either. If we were to implement it, it would behave the same
as ffree but then also pop the register stack.

http://www.pagetable.com/?p=16
2011-03-02 00:41:38 -08:00
Gabe Black
579c5f0b65 Spelling: Fix the a spelling error by changing mmaped to mmapped.
There may not be a formally correct spelling for the past tense of mmap, but
mmapped is the spelling Google doesn't try to autocorrect. This makes sense
because it mirrors the past tense of map->mapped and not the past tense of
cape->caped.

--HG--
rename : src/arch/alpha/mmaped_ipr.hh => src/arch/alpha/mmapped_ipr.hh
rename : src/arch/arm/mmaped_ipr.hh => src/arch/arm/mmapped_ipr.hh
rename : src/arch/mips/mmaped_ipr.hh => src/arch/mips/mmapped_ipr.hh
rename : src/arch/power/mmaped_ipr.hh => src/arch/power/mmapped_ipr.hh
rename : src/arch/sparc/mmaped_ipr.hh => src/arch/sparc/mmapped_ipr.hh
rename : src/arch/x86/mmaped_ipr.hh => src/arch/x86/mmapped_ipr.hh
2011-03-01 23:18:47 -08:00
Gabe Black
2e4fb3f139 X86: Mark IO reads and writes as non-speculative. 2011-03-01 22:42:59 -08:00
Gabe Black
72d35701e9 X86: Mark prefetches as such in their instruction and request flags. 2011-03-01 22:42:18 -08:00
Nilay Vaish
3a10b200f7 Ruby: Fix DPRINTF bugs in PerfectSwitch and MessageBuffer
At a couple of places in PerfectSwitch.cc and MessageBuffer.cc, DPRINTF()
has not been provided with correct number of arguments. The patch fixes these
bugs.
2011-03-01 15:26:11 -06:00
Gabe Black
993e83ef80 Ruby: Mention that Ruby's bound checking option only applies to Ruby. 2011-03-01 02:59:09 -08:00
Gabe Black
d3214c5c5e X86: If PCI config space is disabled, pass through to regular IO addresses. 2011-02-27 16:25:06 -08:00
Gabe Black
0ce5d31159 X86: Use regular read requests in the walker instead of read exclusive. 2011-02-27 16:24:10 -08:00
Nathan Binkert
586564895f getopt: Remove GPL code.
This code is unused and should never have been committed
2011-02-26 21:43:11 -08:00
Nilay Vaish
a4c038764d Ruby: Remove store buffer
This patch removes the store buffer from Ruby. It is not in use currently.
Since libruby is being and store buffer makes calls to libruby, it is not
possible to maintain it until substantial changes are made.
2011-02-25 17:55:20 -06:00
Nilay Vaish
e7edd270aa Ruby: Remove libruby
This patch removes libruby_internal.hh, libruby.hh and libruby.cc. It moves
the contents to libruby.hh to RubyRequest.hh and RubyRequest.cc files.
2011-02-25 17:54:56 -06:00
Nilay Vaish
6bf7153104 Ruby: Make Address.hh independent of RubySystem
This patch changes Address.hh so that it is not dependent on RubySystem.
This dependence seems unecessary. All those functions that depend on
RubySystem have been moved to Address.cc file.
2011-02-25 17:51:56 -06:00
Nilay Vaish
80b3886475 Ruby: Make DataBlock.hh independent of RubySystem
This patch changes DataBlock.hh so that it is not dependent on RubySystem.
This dependence seems unecessary. All those functions that depende on
RubySystem have been moved to DataBlock.cc file.
2011-02-25 17:51:02 -06:00
Timothy M. Jones
a10685ad1e O3CPU: Fix iqCount and lsqCount SMT fetch policies.
Fixes two of the SMT fetch policies in O3CPU that were returning the count
of instructions in the IQ or LSQ rather than the thread ID to fetch from.
2011-02-25 13:50:29 +00:00
Brad Beckmann
12a05c23b7 ruby: automate permission setting
This patch integrates permissions with cache and memory states, and then
automates the setting of permissions within the generated code.  No longer
does one need to manually set the permissions within the setState funciton.
This patch will faciliate easier functional access support by always correctly
setting permissions for both cache and memory states.

--HG--
rename : src/mem/slicc/ast/EnumDeclAST.py => src/mem/slicc/ast/StateDeclAST.py
rename : src/mem/slicc/ast/TypeFieldEnumAST.py => src/mem/slicc/ast/TypeFieldStateAST.py
2011-02-23 16:41:59 -08:00
Brad Beckmann
7842e95519 MOESI_hammer: cache probe address clean up 2011-02-23 16:41:58 -08:00
Brad Beckmann
3bc33eeaea ruby: cleaned up access permission enum 2011-02-23 16:41:58 -08:00
Brad Beckmann
c09a33e5d5 ruby: removed unsupported protocol files 2011-02-23 16:41:26 -08:00
Korey Sewell
0a74246fb9 inorder: InstSeqNum bug
Because int and not InstSeqNum was used in a couple of places, you can
overflow the int type and thus get wierd bugs when the sequence number
is negative (or some wierd value)
2011-02-23 16:35:18 -05:00
Korey Sewell
3e1ad73d08 inorder: dyn inst initialization
remove constructors that werent being used (it just gets confusing)
use initialization list for all the variables instead of relying on initVars()
function
2011-02-23 16:35:04 -05:00
Korey Sewell
e0a021005d inorder: cache packet handling
-use a pointer to CacheReqPacket instead of PacketPtr so correct destructors
get called on packet deletion
- make sure to delete the packet if the cache blocks the sendTiming request
or for some reason we dont use the packet
- dont overwrite memory requests since in the worst case an instruction will
be replaying a request so no need to keep allocating a new request
- we dont use retryPkt so delete it
- fetch code was split out already, so just assert that this is a memory
reference inst. and that the staticInst is available
2011-02-23 16:30:45 -05:00
Ali Saidi
057598843a Mem: Print out memory when access > 8 bytes 2011-02-23 15:10:50 -06:00
Ali Saidi
2eb19dac65 ARM: Set ITSTATE correctly after FlushPipe 2011-02-23 15:10:50 -06:00
Ali Saidi
916c7f162d ARM: This panic can be hit during misspeculation so it can't exist. 2011-02-23 15:10:50 -06:00
Ali Saidi
1201c5a134 ARM: Bad interworking warn way to noisy when running real code w/misspeculation. 2011-02-23 15:10:50 -06:00
Ali Saidi
f9d4d9df1b O3: When a prefetch causes a fault, don't record it in the inst 2011-02-23 15:10:50 -06:00
Giacomo Gabrielli
7ee2de31c4 ARM: NEON instruction templates modified to set the predicate flag to false when needed. 2011-02-23 15:10:50 -06:00
Ali Saidi
3de8e0a0d4 O3: If there is an outstanding table walk don't let the inst queue sleep.
If there is an outstanding table walk and no other activity in the CPU
it can go to sleep and never wake up. This change makes the instruction
queue always active if the CPU is waiting for a store to translate.

If Gabe changes the way this code works then the below should be removed
as indicated by the todo.
2011-02-23 15:10:49 -06:00
Ali Saidi
326191adc9 ARM: Squash state on FPSCR stride or len write. 2011-02-23 15:10:49 -06:00
Matt Horsnell
bb319a589e ARM: Mark store conditionals as such. 2011-02-23 15:10:49 -06:00
Ali Saidi
7391ea6de6 ARM: Do something for ISB, DSB, DMB 2011-02-23 15:10:49 -06:00
Ali Saidi
ae3d456855 ARM: Fix bug that let two table walks occur in parallel. 2011-02-23 15:10:49 -06:00
Ali Saidi
f05f35df99 Includes: Don't include isa_traits.hh and use the TheISA namespace unless really needed. 2011-02-23 15:10:49 -06:00
Ali Saidi
805ad4ba41 ARM: Make Noop actually decode to a noop and set it's instflags. 2011-02-23 15:10:49 -06:00
Ali Saidi
68bd80794c O3: Fix bug when a squash occurs right before TLB miss returns.
In this case we need to throw away the TLB miss, not assume it was the
one we were waiting for.
2011-02-23 15:10:49 -06:00
Ali Saidi
e572cf93ee ARM: Delete OABI syscall handling.
We only support EABI binaries, so there is no reason to support OABI syscalls.
The loader detects OABI calls and fatal() so there is no reason to even check
here.
2011-02-23 15:10:48 -06:00
Ali Saidi
511c637ab0 CLCD: Fix some serialization bugs with the clcd controller. 2011-02-23 15:10:48 -06:00
Ali Saidi
e2a6275c03 ARM: Add support for read of 100MHz clock in system controller. 2011-02-23 15:10:48 -06:00
Ali Saidi
2157b9976b ARM: Reset simulation statistics when pref counters are reset.
The ARM performance counters are not currently supported by the model.
This patch interprets a 'reset performance counters' command to mean 'reset
the simulator statistics' instead.
2011-02-23 15:10:48 -06:00
Ali Saidi
d63020717c ARM: Adds dummy support for a L2 latency miscreg. 2011-02-23 15:10:48 -06:00
Korey Sewell
78c37b8048 ruby: extend dprintfs for RubyGenerated TraceFlag
"executing" isnt a very descriptive debug message and in going through the
output you get multiple messages that say "executing" but nothing to help
you parse through the code/execution.

So instead, at least print out the name of the action that is taking
place in these functions.
2011-02-23 00:58:42 -05:00
Korey Sewell
67cc52a605 ruby: cleaning up RubyQueue and RubyNetwork dprintfs
Overall, continue to progress Ruby debug messages to more of the normal M5
debug message style
- add a name() to the Ruby Throttle & PerfectSwitch objects so that the debug output
isn't littered w/"global:" everywhere.
- clean up messages that print over multiple lines when possible
- clean up duplicate prints in the message buffer
2011-02-23 00:58:40 -05:00
Brad Beckmann
63a25a56cc m5: merged in hammer fix 2011-02-22 11:16:40 -08:00
Nilay Vaish
77eed184f5 Ruby: Machine Type missing in MOESI CMP directory protocol
In certain actions of the L1 cache controller, while creating an outgoing
message, the machine type was not being set. This results in a
segmentation fault when trace is collected. Joseph Pusudesris provided
his patch for fixing this issue.
2011-02-19 17:32:43 -06:00
Nilay Vaish
293ccb7037 Ruby: clean MOESI CMP directory protocol
The L1 cache controller file contains references to foo and goo queues, which
are not in use at all. These have been removed.
2011-02-19 17:32:00 -06:00
Korey Sewell
66bb732c04 m5: merge inorder/release-notes/make_release changes 2011-02-18 14:35:15 -05:00
Korey Sewell
bc16bbc158 inorder: add names and slot #s to res. dprints 2011-02-18 14:31:31 -05:00
Korey Sewell
64d31e75b9 inorder: ignore nops in execution unit 2011-02-18 14:30:38 -05:00