ARM: Tag appropriate instructions as IsReturn
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55920a5ca7
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@ -81,6 +81,7 @@ let {{
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for (mnem, imm, link) in blxList:
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Name = mnem.capitalize()
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isRasPop = 0
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if imm:
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Name += "Imm"
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# Since we're switching ISAs, the target ISA will be the opposite
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@ -123,7 +124,7 @@ let {{
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instFlags += ["IsCall"]
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else:
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linkStr = ""
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instFlags += ["IsReturn"]
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isRasPop = "op1 == INTREG_LR"
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if imm and link: #blx with imm
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branchStr = '''
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@ -141,7 +142,8 @@ let {{
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"branch": branchStr}
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blxIop = InstObjParams(mnem, Name, base,
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{"code": code, "brTgtCode" : br_tgt_code,
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"predicate_test": predicateTest}, instFlags)
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"predicate_test": predicateTest,
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"is_ras_pop" : isRasPop }, instFlags)
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header_output += declare.subst(blxIop)
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decoder_output += constructor.subst(blxIop)
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exec_output += PredOpExecute.subst(blxIop)
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@ -143,7 +143,8 @@ let {{
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subst(immIopCc)
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def buildRegDataInst(mnem, code, flagType = "logic", suffix = "Reg", \
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buildCc = True, buildNonCc = True, instFlags = []):
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buildCc = True, buildNonCc = True, isRasPop = "0", \
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isBranch = "0", instFlags = []):
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cCode = carryCode[flagType]
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vCode = overflowCode[flagType]
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negBit = 31
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@ -161,13 +162,15 @@ let {{
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}
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regCode = secondOpRe.sub(regOp2, code)
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regIop = InstObjParams(mnem, mnem.capitalize() + suffix, "DataRegOp",
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{"code" : regCode,
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{"code" : regCode, "is_ras_pop" : isRasPop,
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"is_branch" : isBranch,
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"predicate_test": predicateTest}, instFlags)
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regIopCc = InstObjParams(mnem + "s", mnem.capitalize() + suffix + "Cc",
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"DataRegOp",
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{"code" : regCode + regCcCode,
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"predicate_test": condPredicateTest},
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instFlags)
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"predicate_test": condPredicateTest,
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"is_ras_pop" : isRasPop,
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"is_branch" : isBranch}, instFlags)
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def subst(iop):
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global header_output, decoder_output, exec_output
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@ -222,7 +225,7 @@ let {{
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def buildDataInst(mnem, code, flagType = "logic", \
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aiw = True, regRegAiw = True,
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subsPcLr = True):
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subsPcLr = True, isRasPop = "0", isBranch = "0"):
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regRegCode = instCode = code
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if aiw:
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instCode = "AIW" + instCode
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@ -230,7 +233,8 @@ let {{
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regRegCode = "AIW" + regRegCode
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buildImmDataInst(mnem, instCode, flagType)
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buildRegDataInst(mnem, instCode, flagType)
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buildRegDataInst(mnem, instCode, flagType,
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isRasPop = isRasPop, isBranch = isBranch)
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buildRegRegDataInst(mnem, regRegCode, flagType)
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if subsPcLr:
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code += '''
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@ -269,7 +273,8 @@ let {{
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buildDataInst("cmn", "resTemp = Op1 + secondOp;", "add", aiw = False)
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buildDataInst("orr", "Dest = resTemp = Op1 | secondOp;")
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buildDataInst("orn", "Dest = resTemp = Op1 | ~secondOp;", aiw = False)
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buildDataInst("mov", "Dest = resTemp = secondOp;", regRegAiw = False)
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buildDataInst("mov", "Dest = resTemp = secondOp;", regRegAiw = False,
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isRasPop = "op1 == INTREG_LR", isBranch = "dest == INTREG_PC")
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buildDataInst("bic", "Dest = resTemp = Op1 & ~secondOp;")
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buildDataInst("mvn", "Dest = resTemp = ~secondOp;")
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buildDataInst("movt",
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@ -58,6 +58,7 @@ let {{
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self.sign = sign
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self.user = user
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self.flavor = flavor
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self.rasPop = False
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if self.add:
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self.op = " +"
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@ -77,7 +78,7 @@ let {{
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newDecoder,
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newExec) = self.fillTemplates(self.name, self.Name, codeBlobs,
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self.memFlags, instFlags, base,
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wbDecl, pcDecl)
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wbDecl, pcDecl, self.rasPop)
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header_output += newHeader
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decoder_output += newDecoder
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@ -128,6 +129,10 @@ let {{
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else:
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self.wbDecl = "MicroSubiUop(machInst, base, base, imm);"
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if self.add and self.post and self.writeback and not self.sign and \
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not self.user and self.size == 4:
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self.rasPop = True
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class LoadRegInst(LoadInst):
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def __init__(self, *args, **kargs):
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super(LoadRegInst, self).__init__(*args, **kargs)
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@ -48,7 +48,8 @@ let {{
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self.constructTemplate = eval(self.decConstBase + 'Constructor')
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def fillTemplates(self, name, Name, codeBlobs, memFlags, instFlags,
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base = 'Memory', wbDecl = None, pcDecl = None):
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base = 'Memory', wbDecl = None, pcDecl = None,
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rasPop = False):
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# Make sure flags are in lists (convert to lists if not).
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memFlags = makeList(memFlags)
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instFlags = makeList(instFlags)
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@ -85,6 +86,10 @@ let {{
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codeBlobsCopy['use_uops'] = 0
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codeBlobsCopy['use_wb'] = 0
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codeBlobsCopy['use_pc'] = 0
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is_ras_pop = "0"
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if rasPop:
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is_ras_pop = "1"
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codeBlobsCopy['is_ras_pop'] = is_ras_pop
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iop = InstObjParams(name, Name, base,
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codeBlobsCopy, instFlagsCopy)
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@ -102,7 +107,8 @@ let {{
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"acc_name" : Name,
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"use_uops" : use_uops,
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"use_pc" : use_pc,
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"use_wb" : use_wb },
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"use_wb" : use_wb,
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"is_ras_pop" : is_ras_pop },
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['IsMacroop'])
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header_output += self.declareTemplate.subst(iop)
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decoder_output += self.constructTemplate.subst(iop)
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@ -120,6 +120,8 @@ def template BranchRegConstructor {{
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} else {
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flags[IsUncondControl] = true;
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}
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if (%(is_ras_pop)s)
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flags[IsReturn] = true;
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}
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}};
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@ -150,6 +152,8 @@ def template BranchRegCondConstructor {{
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} else {
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flags[IsUncondControl] = true;
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}
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if (%(is_ras_pop)s)
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flags[IsReturn] = true;
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}
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}};
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@ -1188,7 +1188,9 @@ def template LoadRegConstructor {{
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(IntRegIndex)_index)
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{
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%(constructor)s;
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bool conditional = false;
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if (!(condCode == COND_AL || condCode == COND_UC)) {
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conditional = true;
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for (int x = 0; x < _numDestRegs; x++) {
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_srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
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}
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@ -1204,6 +1206,12 @@ def template LoadRegConstructor {{
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uops[1] = new %(wb_decl)s;
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uops[1]->setDelayedCommit();
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uops[2] = new MicroUopRegMov(machInst, INTREG_PC, INTREG_UREG0);
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uops[2]->setFlag(StaticInst::IsControl);
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uops[2]->setFlag(StaticInst::IsIndirectControl);
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if (conditional)
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uops[2]->setFlag(StaticInst::IsCondControl);
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else
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uops[2]->setFlag(StaticInst::IsUncondControl);
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uops[2]->setLastMicroop();
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} else if(_dest == _index) {
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IntRegIndex wbIndexReg = INTREG_UREG0;
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@ -1234,7 +1242,9 @@ def template LoadImmConstructor {{
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(IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm)
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{
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%(constructor)s;
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bool conditional = false;
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if (!(condCode == COND_AL || condCode == COND_UC)) {
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conditional = true;
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for (int x = 0; x < _numDestRegs; x++) {
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_srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
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}
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@ -1249,6 +1259,14 @@ def template LoadImmConstructor {{
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uops[1] = new %(wb_decl)s;
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uops[1]->setDelayedCommit();
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uops[2] = new MicroUopRegMov(machInst, INTREG_PC, INTREG_UREG0);
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uops[2]->setFlag(StaticInst::IsControl);
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uops[2]->setFlag(StaticInst::IsIndirectControl);
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if (conditional)
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uops[2]->setFlag(StaticInst::IsCondControl);
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else
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uops[2]->setFlag(StaticInst::IsUncondControl);
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if (_base == INTREG_SP && _add && _imm == 4 && %(is_ras_pop)s)
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uops[2]->setFlag(StaticInst::IsReturn);
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uops[2]->setLastMicroop();
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} else {
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uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, _imm);
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@ -107,6 +107,19 @@ def template DataRegConstructor {{
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_srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
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}
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}
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if (%(is_branch)s){
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flags[IsControl] = true;
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flags[IsIndirectControl] = true;
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if (condCode == COND_AL || condCode == COND_UC)
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flags[IsCondControl] = true;
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else
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flags[IsUncondControl] = true;
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}
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if (%(is_ras_pop)s) {
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flags[IsReturn] = true;
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}
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}
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}};
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