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Ruby: Convert CacheRequestType to RubyRequestType

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This patch converts CacheRequestType to RubyRequestType so that both the
protocol dependent and independent code makes use of the same request type.
This commit is contained in:
Nilay Vaish 2011-03-19 18:34:59 -05:00
parent 2f4276448b
commit 611f052e96
24 changed files with 103 additions and 184 deletions
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12
src/mem/protocol/MESI_CMP_directory-L1cache.sm
View file

@ -183,15 +183,15 @@ machine(L1Cache, "MSI Directory L1 Cache CMP")
}
}
Event mandatory_request_type_to_event(CacheRequestType type) {
if (type == CacheRequestType:LD) {
Event mandatory_request_type_to_event(RubyRequestType type) {
if (type == RubyRequestType:LD) {
return Event:Load;
} else if (type == CacheRequestType:IFETCH) {
} else if (type == RubyRequestType:IFETCH) {
return Event:Ifetch;
} else if ((type == CacheRequestType:ST) || (type == CacheRequestType:ATOMIC)) {
} else if ((type == RubyRequestType:ST) || (type == RubyRequestType:ATOMIC)) {
return Event:Store;
} else {
error("Invalid CacheRequestType");
error("Invalid RubyRequestType");
}
}
@ -273,7 +273,7 @@ machine(L1Cache, "MSI Directory L1 Cache CMP")
// Check for data access to blocks in I-cache and ifetchs to blocks in D-cache
if (in_msg.Type == CacheRequestType:IFETCH) {
if (in_msg.Type == RubyRequestType:IFETCH) {
// ** INSTRUCTION ACCESS ***
Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress);

10
src/mem/protocol/MI_example-cache.sm
View file

@ -84,15 +84,15 @@ machine(L1Cache, "MI Example L1 Cache")
}
// FUNCTIONS
Event mandatory_request_type_to_event(CacheRequestType type) {
if (type == CacheRequestType:LD) {
Event mandatory_request_type_to_event(RubyRequestType type) {
if (type == RubyRequestType:LD) {
return Event:Load;
} else if (type == CacheRequestType:IFETCH) {
} else if (type == RubyRequestType:IFETCH) {
return Event:Ifetch;
} else if ((type == CacheRequestType:ST) || (type == CacheRequestType:ATOMIC)) {
} else if ((type == RubyRequestType:ST) || (type == RubyRequestType:ATOMIC)) {
return Event:Store;
} else {
error("Invalid CacheRequestType");
error("Invalid RubyRequestType");
}
}

12
src/mem/protocol/MOESI_CMP_directory-L1cache.sm
View file

@ -194,15 +194,15 @@ machine(L1Cache, "Directory protocol")
}
}
Event mandatory_request_type_to_event(CacheRequestType type) {
if (type == CacheRequestType:LD) {
Event mandatory_request_type_to_event(RubyRequestType type) {
if (type == RubyRequestType:LD) {
return Event:Load;
} else if (type == CacheRequestType:IFETCH) {
} else if (type == RubyRequestType:IFETCH) {
return Event:Ifetch;
} else if ((type == CacheRequestType:ST) || (type == CacheRequestType:ATOMIC)) {
} else if ((type == RubyRequestType:ST) || (type == RubyRequestType:ATOMIC)) {
return Event:Store;
} else {
error("Invalid CacheRequestType");
error("Invalid RubyRequestType");
}
}
@ -309,7 +309,7 @@ machine(L1Cache, "Directory protocol")
// Check for data access to blocks in I-cache and ifetchs to blocks in D-cache
if (in_msg.Type == CacheRequestType:IFETCH) {
if (in_msg.Type == RubyRequestType:IFETCH) {
// ** INSTRUCTION ACCESS ***
Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress);

24
src/mem/protocol/MOESI_CMP_token-L1cache.sm
View file

@ -341,31 +341,31 @@ machine(L1Cache, "Token protocol")
}
}
Event mandatory_request_type_to_event(CacheRequestType type) {
if (type == CacheRequestType:LD) {
Event mandatory_request_type_to_event(RubyRequestType type) {
if (type == RubyRequestType:LD) {
return Event:Load;
} else if (type == CacheRequestType:IFETCH) {
} else if (type == RubyRequestType:IFETCH) {
return Event:Ifetch;
} else if (type == CacheRequestType:ST) {
} else if (type == RubyRequestType:ST) {
return Event:Store;
} else if (type == CacheRequestType:ATOMIC) {
} else if (type == RubyRequestType:ATOMIC) {
if (no_mig_atomic) {
return Event:Atomic;
} else {
return Event:Store;
}
} else {
error("Invalid CacheRequestType");
error("Invalid RubyRequestType");
}
}
AccessType cache_request_type_to_access_type(CacheRequestType type) {
if ((type == CacheRequestType:LD) || (type == CacheRequestType:IFETCH)) {
AccessType cache_request_type_to_access_type(RubyRequestType type) {
if ((type == RubyRequestType:LD) || (type == RubyRequestType:IFETCH)) {
return AccessType:Read;
} else if ((type == CacheRequestType:ST) || (type == CacheRequestType:ATOMIC)) {
} else if ((type == RubyRequestType:ST) || (type == RubyRequestType:ATOMIC)) {
return AccessType:Write;
} else {
error("Invalid CacheRequestType");
error("Invalid RubyRequestType");
}
}
@ -629,7 +629,7 @@ machine(L1Cache, "Token protocol")
TBE tbe := L1_TBEs[in_msg.LineAddress];
if (in_msg.Type == CacheRequestType:IFETCH) {
if (in_msg.Type == RubyRequestType:IFETCH) {
// ** INSTRUCTION ACCESS ***
Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress);
@ -1313,7 +1313,7 @@ machine(L1Cache, "Token protocol")
peek(mandatoryQueue_in, CacheMsg) {
tbe.PC := in_msg.ProgramCounter;
tbe.AccessType := cache_request_type_to_access_type(in_msg.Type);
if (in_msg.Type == CacheRequestType:ATOMIC) {
if (in_msg.Type == RubyRequestType:ATOMIC) {
tbe.IsAtomic := true;
}
tbe.Prefetch := in_msg.Prefetch;

14
src/mem/protocol/MOESI_hammer-cache.sm
View file

@ -214,15 +214,15 @@ machine(L1Cache, "AMD Hammer-like protocol")
}
}
Event mandatory_request_type_to_event(CacheRequestType type) {
if (type == CacheRequestType:LD) {
Event mandatory_request_type_to_event(RubyRequestType type) {
if (type == RubyRequestType:LD) {
return Event:Load;
} else if (type == CacheRequestType:IFETCH) {
} else if (type == RubyRequestType:IFETCH) {
return Event:Ifetch;
} else if ((type == CacheRequestType:ST) || (type == CacheRequestType:ATOMIC)) {
} else if ((type == RubyRequestType:ST) || (type == RubyRequestType:ATOMIC)) {
return Event:Store;
} else {
error("Invalid CacheRequestType");
error("Invalid RubyRequestType");
}
}
@ -359,7 +359,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
// Check for data access to blocks in I-cache and ifetchs to blocks in D-cache
TBE tbe := TBEs[in_msg.LineAddress];
if (in_msg.Type == CacheRequestType:IFETCH) {
if (in_msg.Type == RubyRequestType:IFETCH) {
// ** INSTRUCTION ACCESS ***
Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress);
@ -700,7 +700,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
cache_entry.DataBlk);
cache_entry.Dirty := true;
if (in_msg.Type == CacheRequestType:ATOMIC) {
if (in_msg.Type == RubyRequestType:ATOMIC) {
cache_entry.AtomicAccessed := true;
}
}

28
src/mem/protocol/RubySlicc_Exports.sm
View file

@ -103,16 +103,22 @@ enumeration(TransitionResult, desc="...") {
ProtocolStall, desc="Protocol specified stall";
}
// CacheRequestType
enumeration(CacheRequestType, desc="...", default="CacheRequestType_NULL") {
LD, desc="Load";
ST, desc="Store";
ATOMIC, desc="Atomic Load/Store";
IFETCH, desc="Instruction fetch";
IO, desc="I/O";
REPLACEMENT, desc="Replacement";
COMMIT, desc="Commit version";
NULL, desc="Invalid request type";
// RubyRequestType
enumeration(RubyRequestType, desc="...", default="RubyRequestType_NULL") {
LD, desc="Load";
ST, desc="Store";
ATOMIC, desc="Atomic Load/Store";
IFETCH, desc="Instruction fetch";
IO, desc="I/O";
REPLACEMENT, desc="Replacement";
Load_Linked, desc="";
Store_Conditional, desc="";
RMW_Read, desc="";
RMW_Write, desc="";
Locked_RMW_Read, desc="";
Locked_RMW_Write, desc="";
COMMIT, desc="Commit version";
NULL, desc="Invalid request type";
}
enumeration(SequencerRequestType, desc="...", default="SequencerRequestType_NULL") {
@ -211,7 +217,7 @@ enumeration(PrefetchBit, default="PrefetchBit_No", desc="...") {
structure(CacheMsg, desc="...", interface="Message") {
Address LineAddress, desc="Line address for this request";
Address PhysicalAddress, desc="Physical address for this request";
CacheRequestType Type, desc="Type of request (LD, ST, etc)";
RubyRequestType Type, desc="Type of request (LD, ST, etc)";
Address ProgramCounter, desc="Program counter of the instruction that caused the miss";
RubyAccessMode AccessMode, desc="user/supervisor access type";
int Size, desc="size in bytes of access";

8
src/mem/ruby/profiler/AccessTraceForAddress.cc
View file

@ -58,17 +58,17 @@ AccessTraceForAddress::print(std::ostream& out) const
}
void
AccessTraceForAddress::update(CacheRequestType type,
AccessTraceForAddress::update(RubyRequestType type,
RubyAccessMode access_mode, NodeID cpu,
bool sharing_miss)
{
m_touched_by.add(cpu);
m_total++;
if(type == CacheRequestType_ATOMIC) {
if(type == RubyRequestType_ATOMIC) {
m_atomics++;
} else if(type == CacheRequestType_LD){
} else if(type == RubyRequestType_LD){
m_loads++;
} else if (type == CacheRequestType_ST){
} else if (type == RubyRequestType_ST){
m_stores++;
} else {
// ERROR_MSG("Trying to add invalid access to trace");

4
src/mem/ruby/profiler/AccessTraceForAddress.hh
View file

@ -32,7 +32,7 @@
#include <iostream>
#include "mem/protocol/RubyAccessMode.hh"
#include "mem/protocol/CacheRequestType.hh"
#include "mem/protocol/RubyRequestType.hh"
#include "mem/ruby/common/Address.hh"
#include "mem/ruby/common/Global.hh"
#include "mem/ruby/common/Set.hh"
@ -50,7 +50,7 @@ class AccessTraceForAddress
~AccessTraceForAddress();
void setAddress(const Address& addr) { m_addr = addr; }
void update(CacheRequestType type, RubyAccessMode access_mode, NodeID cpu,
void update(RubyRequestType type, RubyAccessMode access_mode, NodeID cpu,
bool sharing_miss);
int getTotal() const;
int getSharing() const { return m_sharing; }

6
src/mem/ruby/profiler/AddressProfiler.cc
View file

@ -257,7 +257,7 @@ AddressProfiler::profileGetX(const Address& datablock, const Address& PC,
m_getx_sharing_histogram.add(num_indirections);
bool indirection_miss = (num_indirections > 0);
addTraceSample(datablock, PC, CacheRequestType_ST, RubyAccessMode(0),
addTraceSample(datablock, PC, RubyRequestType_ST, RubyAccessMode(0),
requestor, indirection_miss);
}
@ -274,13 +274,13 @@ AddressProfiler::profileGetS(const Address& datablock, const Address& PC,
m_gets_sharing_histogram.add(num_indirections);
bool indirection_miss = (num_indirections > 0);
addTraceSample(datablock, PC, CacheRequestType_LD, RubyAccessMode(0),
addTraceSample(datablock, PC, RubyRequestType_LD, RubyAccessMode(0),
requestor, indirection_miss);
}
void
AddressProfiler::addTraceSample(Address data_addr, Address pc_addr,
CacheRequestType type,
RubyRequestType type,
RubyAccessMode access_mode, NodeID id,
bool sharing_miss)
{

2
src/mem/ruby/profiler/AddressProfiler.hh
View file

@ -55,7 +55,7 @@ class AddressProfiler
void clearStats();
void addTraceSample(Address data_addr, Address pc_addr,
CacheRequestType type, RubyAccessMode access_mode,
RubyRequestType type, RubyAccessMode access_mode,
NodeID id, bool sharing_miss);
void profileRetry(const Address& data_addr, AccessType type, int count);
void profileGetX(const Address& datablock, const Address& PC,

12
src/mem/ruby/profiler/CacheProfiler.cc
View file

@ -33,7 +33,7 @@
using namespace std;
CacheProfiler::CacheProfiler(const string& description)
: m_cacheRequestType(int(CacheRequestType_NUM)), m_genericRequestType(int(GenericRequestType_NUM))
: m_cacheRequestType(int(RubyRequestType_NUM)), m_genericRequestType(int(GenericRequestType_NUM))
{
m_description = description;
@ -59,7 +59,7 @@ CacheProfiler::printStats(ostream& out) const
int requests = 0;
for (int i = 0; i < int(CacheRequestType_NUM); i++) {
for (int i = 0; i < int(RubyRequestType_NUM); i++) {
requests += m_cacheRequestType[i];
}
@ -70,10 +70,10 @@ CacheProfiler::printStats(ostream& out) const
assert(m_misses == requests);
if (requests > 0) {
for (int i = 0; i < int(CacheRequestType_NUM); i++) {
for (int i = 0; i < int(RubyRequestType_NUM); i++) {
if (m_cacheRequestType[i] > 0) {
out << description << "_request_type_"
<< CacheRequestType_to_string(CacheRequestType(i))
<< RubyRequestType_to_string(RubyRequestType(i))
<< ": "
<< 100.0 * (double)m_cacheRequestType[i] /
(double)requests
@ -111,7 +111,7 @@ CacheProfiler::printStats(ostream& out) const
void
CacheProfiler::clearStats()
{
for (int i = 0; i < int(CacheRequestType_NUM); i++) {
for (int i = 0; i < int(RubyRequestType_NUM); i++) {
m_cacheRequestType[i] = 0;
}
for (int i = 0; i < int(GenericRequestType_NUM); i++) {
@ -128,7 +128,7 @@ CacheProfiler::clearStats()
}
void
CacheProfiler::addCacheStatSample(CacheRequestType requestType,
CacheProfiler::addCacheStatSample(RubyRequestType requestType,
RubyAccessMode accessType,
PrefetchBit pfBit)
{

4
src/mem/ruby/profiler/CacheProfiler.hh
View file

@ -34,7 +34,7 @@
#include <vector>
#include "mem/protocol/RubyAccessMode.hh"
#include "mem/protocol/CacheRequestType.hh"
#include "mem/protocol/RubyRequestType.hh"
#include "mem/protocol/GenericRequestType.hh"
#include "mem/protocol/PrefetchBit.hh"
#include "mem/ruby/common/Global.hh"
@ -50,7 +50,7 @@ class CacheProfiler
void printStats(std::ostream& out) const;
void clearStats();
void addCacheStatSample(CacheRequestType requestType,
void addCacheStatSample(RubyRequestType requestType,
RubyAccessMode type,
PrefetchBit pfBit);

8
src/mem/ruby/profiler/Profiler.cc
View file

@ -320,7 +320,7 @@ Profiler::printStats(ostream& out, bool short_stats)
out << "prefetch_latency: " << m_allSWPrefetchLatencyHistogram << endl;
for (int i = 0; i < m_SWPrefetchLatencyHistograms.size(); i++) {
if (m_SWPrefetchLatencyHistograms[i].size() > 0) {
out << "prefetch_latency_" << CacheRequestType(i) << ": "
out << "prefetch_latency_" << RubyRequestType(i) << ": "
<< m_SWPrefetchLatencyHistograms[i] << endl;
}
}
@ -500,7 +500,7 @@ Profiler::clearStats()
m_dirFirstResponseToCompleteHistogram.clear(200);
m_dirIncompleteTimes = 0;
m_SWPrefetchLatencyHistograms.resize(CacheRequestType_NUM);
m_SWPrefetchLatencyHistograms.resize(RubyRequestType_NUM);
for (int i = 0; i < m_SWPrefetchLatencyHistograms.size(); i++) {
m_SWPrefetchLatencyHistograms[i].clear(200);
}
@ -537,7 +537,7 @@ Profiler::clearStats()
void
Profiler::addAddressTraceSample(const CacheMsg& msg, NodeID id)
{
if (msg.getType() != CacheRequestType_IFETCH) {
if (msg.getType() != RubyRequestType_IFETCH) {
// Note: The following line should be commented out if you
// want to use the special profiling that is part of the GS320
// protocol
@ -683,7 +683,7 @@ Profiler::missLatencyDir(Time issuedTime,
// non-zero cycle prefetch request
void
Profiler::swPrefetchLatency(Time cycles,
CacheRequestType type,
RubyRequestType type,
const GenericMachineType respondingMach)
{
m_allSWPrefetchLatencyHistogram.add(cycles);

4
src/mem/ruby/profiler/Profiler.hh
View file

@ -53,7 +53,7 @@
#include "base/hashmap.hh"
#include "mem/protocol/RubyAccessMode.hh"
#include "mem/protocol/AccessType.hh"
#include "mem/protocol/CacheRequestType.hh"
#include "mem/protocol/RubyRequestType.hh"
#include "mem/protocol/GenericMachineType.hh"
#include "mem/protocol/GenericRequestType.hh"
#include "mem/protocol/PrefetchBit.hh"
@ -150,7 +150,7 @@ class Profiler : public SimObject, public Consumer
Time completionTime);
void swPrefetchLatency(Time t,
CacheRequestType type,
RubyRequestType type,
const GenericMachineType respondingMach);
void sequencerRequests(int num) { m_sequencer_requests.add(num); }

2
src/mem/ruby/recorder/CacheRecorder.hh
View file

@ -38,7 +38,7 @@
#include <string>
#include <vector>
#include "mem/protocol/CacheRequestType.hh"
#include "mem/protocol/RubyRequestType.hh"
#include "mem/ruby/common/Global.hh"
#include "mem/ruby/system/NodeID.hh"
#include "mem/ruby/recorder/TraceRecord.hh"

2
src/mem/ruby/recorder/Tracer.hh
View file

@ -39,7 +39,7 @@
#include "gzstream.hh"
#include "mem/protocol/CacheRequestType.hh"
#include "mem/protocol/RubyRequestType.hh"
#include "mem/ruby/common/Global.hh"
#include "mem/ruby/system/NodeID.hh"
#include "params/RubyTracer.hh"

63
src/mem/ruby/slicc_interface/RubyRequest.cc
View file

@ -4,69 +4,6 @@
using namespace std;
string
RubyRequestType_to_string(const RubyRequestType& obj)
{
switch(obj) {
case RubyRequestType_IFETCH:
return "IFETCH";
case RubyRequestType_LD:
return "LD";
case RubyRequestType_ST:
return "ST";
case RubyRequestType_Load_Linked:
return "Load_Linked";
case RubyRequestType_Store_Conditional:
return "Store_Conditional";
case RubyRequestType_RMW_Read:
return "RMW_Read";
case RubyRequestType_RMW_Write:
return "RMW_Write";
case RubyRequestType_Locked_RMW_Read:
return "Locked_RMW_Read";
case RubyRequestType_Locked_RMW_Write:
return "Locked_RMW_Write";
case RubyRequestType_NULL:
default:
assert(0);
return "";
}
}
RubyRequestType
string_to_RubyRequestType(string str)
{
if (str == "IFETCH")
return RubyRequestType_IFETCH;
else if (str == "LD")
return RubyRequestType_LD;
else if (str == "ST")
return RubyRequestType_ST;
else if (str == "Locked_Read")
return RubyRequestType_Load_Linked;
else if (str == "Locked_Write")
return RubyRequestType_Store_Conditional;
else if (str == "RMW_Read")
return RubyRequestType_RMW_Read;
else if (str == "RMW_Write")
return RubyRequestType_RMW_Write;
else if (str == "Locked_RMW_Read")
return RubyRequestType_Locked_RMW_Read;
else if (str == "Locked_RMW_Write")
return RubyRequestType_Locked_RMW_Write;
else
assert(0);
return RubyRequestType_NULL;
}
ostream&
operator<<(ostream& out, const RubyRequestType& obj)
{
out << RubyRequestType_to_string(obj);
out << flush;
return out;
}
ostream&
operator<<(ostream& out, const RubyRequest& obj)
{

18
src/mem/ruby/slicc_interface/RubyRequest.hh
View file

@ -33,25 +33,12 @@
#include "mem/packet.hh"
#include "mem/protocol/RubyAccessMode.hh"
#include "mem/protocol/CacheRequestType.hh"
#include "mem/protocol/RubyRequestType.hh"
#include "mem/protocol/Message.hh"
#include "mem/protocol/PrefetchBit.hh"
#include "mem/ruby/common/Address.hh"
typedef void* RubyPortHandle;
enum RubyRequestType {
RubyRequestType_NULL,
RubyRequestType_IFETCH,
RubyRequestType_LD,
RubyRequestType_ST,
RubyRequestType_Load_Linked,
RubyRequestType_Store_Conditional,
RubyRequestType_RMW_Read,
RubyRequestType_RMW_Write,
RubyRequestType_Locked_RMW_Read,
RubyRequestType_Locked_RMW_Write,
RubyRequestType_NUM
};
class RubyRequest
{
@ -87,9 +74,6 @@ class RubyRequest
void print(std::ostream& out) const;
};
std::string RubyRequestType_to_string(const RubyRequestType& obj);
RubyRequestType string_to_RubyRequestType(std::string);
std::ostream& operator<<(std::ostream& out, const RubyRequestType& obj);
std::ostream& operator<<(std::ostream& out, const RubyRequest& obj);
#endif

2
src/mem/ruby/slicc_interface/RubySlicc_Util.hh
View file

@ -37,7 +37,7 @@
#include "mem/protocol/AccessType.hh"
#include "mem/protocol/CacheMsg.hh"
#include "mem/protocol/CacheRequestType.hh"
#include "mem/protocol/RubyRequestType.hh"
#include "mem/protocol/Directory_State.hh"
#include "mem/protocol/GenericRequestType.hh"
#include "mem/protocol/L1Cache_State.hh"

16
src/mem/ruby/system/CacheMemory.cc
View file

@ -159,7 +159,7 @@ CacheMemory::findTagInSetIgnorePermissions(Index cacheSet,
}
bool
CacheMemory::tryCacheAccess(const Address& address, CacheRequestType type,
CacheMemory::tryCacheAccess(const Address& address, RubyRequestType type,
DataBlock*& data_ptr)
{
assert(address == line_address(address));
@ -177,7 +177,7 @@ CacheMemory::tryCacheAccess(const Address& address, CacheRequestType type,
return true;
}
if ((entry->m_Permission == AccessPermission_Read_Only) &&
(type == CacheRequestType_LD || type == CacheRequestType_IFETCH)) {
(type == RubyRequestType_LD || type == RubyRequestType_IFETCH)) {
return true;
}
// The line must not be accessible
@ -187,7 +187,7 @@ CacheMemory::tryCacheAccess(const Address& address, CacheRequestType type,
}
bool
CacheMemory::testCacheAccess(const Address& address, CacheRequestType type,
CacheMemory::testCacheAccess(const Address& address, RubyRequestType type,
DataBlock*& data_ptr)
{
assert(address == line_address(address));
@ -367,18 +367,18 @@ CacheMemory::recordCacheContents(CacheRecorder& tr) const
for (int i = 0; i < m_cache_num_sets; i++) {
for (int j = 0; j < m_cache_assoc; j++) {
AccessPermission perm = m_cache[i][j]->m_Permission;
CacheRequestType request_type = CacheRequestType_NULL;
RubyRequestType request_type = RubyRequestType_NULL;
if (perm == AccessPermission_Read_Only) {
if (m_is_instruction_only_cache) {
request_type = CacheRequestType_IFETCH;
request_type = RubyRequestType_IFETCH;
} else {
request_type = CacheRequestType_LD;
request_type = RubyRequestType_LD;
}
} else if (perm == AccessPermission_Read_Write) {
request_type = CacheRequestType_ST;
request_type = RubyRequestType_ST;
}
if (request_type != CacheRequestType_NULL) {
if (request_type != RubyRequestType_NULL) {
#if 0
tr.addRecord(m_chip_ptr->getID(), m_cache[i][j].m_Address,
Address(0), request_type,

6
src/mem/ruby/system/CacheMemory.hh
View file

@ -36,7 +36,7 @@
#include "base/hashmap.hh"
#include "mem/protocol/AccessPermission.hh"
#include "mem/protocol/CacheMsg.hh"
#include "mem/protocol/CacheRequestType.hh"
#include "mem/protocol/RubyRequestType.hh"
#include "mem/protocol/GenericRequestType.hh"
#include "mem/protocol/MachineType.hh"
#include "mem/ruby/common/Address.hh"
@ -66,11 +66,11 @@ class CacheMemory : public SimObject
void printConfig(std::ostream& out);
// perform a cache access and see if we hit or not. Return true on a hit.
bool tryCacheAccess(const Address& address, CacheRequestType type,
bool tryCacheAccess(const Address& address, RubyRequestType type,
DataBlock*& data_ptr);
// similar to above, but doesn't require full access check
bool testCacheAccess(const Address& address, CacheRequestType type,
bool testCacheAccess(const Address& address, RubyRequestType type,
DataBlock*& data_ptr);
// tests to see if an address is present in the cache

10
src/mem/ruby/system/DMASequencer.cc
View file

@ -64,15 +64,7 @@ DMASequencer::makeRequest(const RubyRequest &request)
case RubyRequestType_ST:
write = true;
break;
case RubyRequestType_NULL:
case RubyRequestType_IFETCH:
case RubyRequestType_Load_Linked:
case RubyRequestType_Store_Conditional:
case RubyRequestType_RMW_Read:
case RubyRequestType_RMW_Write:
case RubyRequestType_Locked_RMW_Read:
case RubyRequestType_Locked_RMW_Write:
case RubyRequestType_NUM:
default:
panic("DMASequencer::makeRequest does not support RubyRequestType");
return RequestStatus_NULL;
}

16
src/mem/ruby/system/Sequencer.cc
View file

@ -604,16 +604,16 @@ Sequencer::makeRequest(const RubyRequest &request)
void
Sequencer::issueRequest(const RubyRequest& request)
{
// TODO: get rid of CacheMsg, CacheRequestType, and
// TODO: get rid of CacheMsg, RubyRequestType, and
// AccessModeTYpe, & have SLICC use RubyRequest and subtypes
// natively
CacheRequestType ctype;
RubyRequestType ctype;
switch(request.type) {
case RubyRequestType_IFETCH:
ctype = CacheRequestType_IFETCH;
ctype = RubyRequestType_IFETCH;
break;
case RubyRequestType_LD:
ctype = CacheRequestType_LD;
ctype = RubyRequestType_LD;
break;
case RubyRequestType_ST:
case RubyRequestType_RMW_Read:
@ -626,7 +626,7 @@ Sequencer::issueRequest(const RubyRequest& request)
//
case RubyRequestType_Locked_RMW_Read:
case RubyRequestType_Locked_RMW_Write:
ctype = CacheRequestType_ST;
ctype = RubyRequestType_ST;
break;
//
// Alpha LL/SC instructions need to be handled carefully by the cache
@ -638,7 +638,7 @@ Sequencer::issueRequest(const RubyRequest& request)
//
case RubyRequestType_Load_Linked:
case RubyRequestType_Store_Conditional:
ctype = CacheRequestType_ATOMIC;
ctype = RubyRequestType_ATOMIC;
break;
default:
assert(0);
@ -685,12 +685,12 @@ Sequencer::issueRequest(const RubyRequest& request)
#if 0
bool
Sequencer::tryCacheAccess(const Address& addr, CacheRequestType type,
Sequencer::tryCacheAccess(const Address& addr, RubyRequestType type,
RubyAccessMode access_mode,
int size, DataBlock*& data_ptr)
{
CacheMemory *cache =
(type == CacheRequestType_IFETCH) ? m_instCache_ptr : m_dataCache_ptr;
(type == RubyRequestType_IFETCH) ? m_instCache_ptr : m_dataCache_ptr;
return cache->tryCacheAccess(line_address(addr), type, data_ptr);
}

4
src/mem/ruby/system/Sequencer.hh
View file

@ -33,7 +33,7 @@
#include "base/hashmap.hh"
#include "mem/protocol/RubyAccessMode.hh"
#include "mem/protocol/CacheRequestType.hh"
#include "mem/protocol/RubyRequestType.hh"
#include "mem/protocol/GenericMachineType.hh"
#include "mem/protocol/PrefetchBit.hh"
#include "mem/ruby/common/Address.hh"
@ -112,7 +112,7 @@ class Sequencer : public RubyPort, public Consumer
void removeRequest(SequencerRequest* request);
private:
bool tryCacheAccess(const Address& addr, CacheRequestType type,
bool tryCacheAccess(const Address& addr, RubyRequestType type,
const Address& pc, RubyAccessMode access_mode,
int size, DataBlock*& data_ptr);
void issueRequest(const RubyRequest& request);