CacheMemory: add allocateVoid() that is == allocate() but no return value.
This function duplicates the functionality of allocate() exactly, except that it does not return a return value. In protocols where you just want to allocate a block but do not want that block to be your implicitly passed cache_entry, use this function. Otherwise, SLICC will complain if you do not consume the pointer returned by allocate(), and if you do a dummy assignment Entry foo := cache.allocate(address), the C++ compiler will complain of an unused variable. This is kind of a hack to get around those issues, but suggestions welcome.
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@ -134,6 +134,7 @@ structure (CacheMemory, external = "yes") {
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bool cacheAvail(Address);
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Address cacheProbe(Address);
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AbstractCacheEntry allocate(Address, AbstractCacheEntry);
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void allocateVoid(Address, AbstractCacheEntry);
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void deallocate(Address);
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AbstractCacheEntry lookup(Address);
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bool isTagPresent(Address);
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@ -83,6 +83,10 @@ class CacheMemory : public SimObject
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// find an unused entry and sets the tag appropriate for the address
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AbstractCacheEntry* allocate(const Address& address, AbstractCacheEntry* new_entry);
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void allocateVoid(const Address& address, AbstractCacheEntry* new_entry)
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{
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allocate(address, new_entry);
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}
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// Explicitly free up this address
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void deallocate(const Address& address);
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@ -54,7 +54,7 @@
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/////////////////////////////////////////////////////////////////////////////
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class Consumer;
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class Message; // I added this and removed Message.hh
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class Message;
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class WireBuffer : public SimObject
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{
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@ -88,7 +88,6 @@ class WireBuffer : public SimObject
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void clearStats() const;
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void printStats(std::ostream& out) const;
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// int m_dummy;
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uint64_t m_msg_counter;
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private:
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@ -28,7 +28,6 @@
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from m5.params import *
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from m5.SimObject import SimObject
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#from Controller import RubyController
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class RubyWireBuffer(SimObject):
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type = 'RubyWireBuffer'
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