O3: Fix unaligned stores when cache blocked

Without this change the a store can be issued to the cache multiple times.
If this case occurs when the l1 cache is out of mshrs (and thus blocked)
the processor will never make forward progress because each cycle it will
send a single request using the recently freed mshr and not completing the
multipart store. This will continue forever.

src/cpu/o3/lsq_unit_impl.hh

@@ -1103,7 +1103,9 @@ LSQUnit<Impl>::recvRetry()
                 dynamic_cast<LSQSenderState *>(retryPkt->senderState);
 
             // Don't finish the store unless this is the last packet.
-            if (!TheISA::HasUnalignedMemAcc || !state->pktToSend) {
+            if (!TheISA::HasUnalignedMemAcc || !state->pktToSend ||
+                    state->pendingPacket == retryPkt) {
+                state->pktToSend = false;
                 storePostSend(retryPkt);
             }
             retryPkt = NULL;