Commit graph

4881 commits

Author SHA1 Message Date
Ali Saidi
9b356adf54 ARM: Fix a memory leak with the table walker. 2011-08-19 15:08:05 -05:00
Ali Saidi
6779bd3e5d Prefetcher: Fix some memory leaks with the prefetcher. 2011-08-19 15:08:05 -05:00
Ali Saidi
b3a058f220 ARM: quiet what can be a very noise CLCD controller. 2011-08-19 15:08:05 -05:00
Gabe Black
f2c89a01d1 InOrder: Make cache_unit.hh include hashmap.hh explicitly, not transitively. 2011-08-16 02:47:15 -07:00
Gabe Black
78a4636a13 O3: Make lsq_unit.hh include arch/isa_traits.hh directly, not transitively. 2011-08-16 02:46:57 -07:00
Nilay Vaish
769c1844f0 Ruby: Initialize some variables. 2011-08-15 12:56:47 -05:00
Gabe Black
0e6dc00497 O3: When squashing, restore the macroop that should be used for fetching. 2011-08-14 17:41:34 -07:00
Gabe Black
ec204f003c O3: Add a pointer to the macroop for a microop in the dyninst. 2011-08-14 04:08:14 -07:00
Gabe Black
1b9de61a71 X86: Use IsSquashAfter if an instruction could affect fetch translation.
Control register operands are set up so that writing to them is serialize
after, serialize before, and non-speculative. These are probably overboard,
but they should usually be safe. Unfortunately there are times when even these
aren't enough. If an instruction modifies state that affects fetch, later
serialized instructions which come after it might have already gone through
fetch and decode by the time it commits. These instructions may have been
translated incorrectly or interpretted incorrectly and need to be destroyed.
This change modifies instructions which will or may have this behavior so that
they use the IsSquashAfter flag when necessary.
2011-08-13 23:03:11 -07:00
Gabe Black
e0043f8dbe O3: At the end of an instruction, force fetchAddr to something sensible.
It's possible (though until now very unlikely) for fetchAddr to get out of
sync with the actual PC of the current instruction. This change forcefull
resets fetchAddr at the end of every instruction.
2011-08-13 13:36:37 -07:00
Gabe Black
96df6bedb7 O3: Stop using the current macroop no matter why you're leaving it.
Until now, the only reason a macroop would be left was because it ended at a
microop marked as the last microop. In O3 with branch prediction, it's
possible for the branch predictor to have entries which originally came from
different instructions which happened to have the same RIP. This could
theoretically happen in many ways, but it was encountered specifically when
different programs in different address spaces ran one after the other in
X86_FS.

What would happen in that case was that the macroop would continue to be
looped over and microops fetched from it until it reached the last microop
even though the macropc had moved out from under it. If things lined up
properly, this could mean that the end bytes of an instruction actually fell
into the instruction sized block of memory after the one in the predecoder.
The fetch loop implicitly assumes that the last instruction sized chunk of
memory processed was the last one needed for the instruction it just finished
executing. It would then tell the predecoder to move to an offset within the
bytes it was given that is larger than those bytes, and that would trip an
assert in the x86 predecoder.

This change fixes this problem by making fetch stop processing the current
macroop if the address it should be fetching from changed when the PC is
updated. That happens when the last microop was reached because the instruction
handled it properly, and it also catches the case where the branch predictor
makes fetch do a macro level branch when it shouldn't.

The check of isLastMicroop is retained because otherwise, a macroop that
branches back to itself would act like a single, long macroop instead of
multiple instances of the same microop. There may be situations (which may
turn out to be purely hypothetical) where that matters.

This also fixes a relatively minor issue where the curMacroop variable would
be set to NULL immediately after seeing that a microop was the last one before
curMacroop was used to build the dyninst. The traceData structure would have a
NULL pointer to the macroop for that microop.
2011-08-09 11:30:43 -07:00
Gabe Black
3989f41261 O3: When waiting to handle an interrupt, let everything drain out.
Before this change, the commit stage would wait until the ROB and store queue
were empty before recognizing an interrupt. The fetch stage would stop
generating instructions at an appropriate point, so commit would then wait
until a valid time to interrupt the instruction stream. Instructions might be
in flight after fetch but not the in the ROB or store queue (in rename, for
instance), so this change makes commit wait until all in flight instructions
are finished.
2011-08-09 03:37:43 -07:00
Nilay Vaish
821dfc1289 BuildEnv: Eliminate RUBY as build environment variable
This patch replaces RUBY with PROTOCOL in all the SConscript files as
the environment variable that decides whether or not certain components
of the simulator are compiled.
2011-08-08 10:50:13 -05:00
Gabe Black
5c0e6e6092 O3: Get rid of the unused addToRemoveList function. 2011-08-07 15:41:10 -07:00
Gabe Black
a9b7931156 O3: Let squashed and deferred instructions issue.
Let squahsed and deferred instructions issue so they don't accumulate and clog
up the CPU.
2011-08-07 15:41:07 -07:00
Ali Saidi
4d83b8a799 O3: Fix uninitialized variable in the tournament branch predictor. 2011-08-07 09:21:49 -07:00
Gabe Black
16882b0483 Translation: Use a pointer type as the template argument.
This allows regular pointers and reference counted pointers without having to
use any shim structures or other tricks.
2011-08-07 09:21:48 -07:00
Nilay Vaish
720c0be620 Ruby: Remove files and includes not in use 2011-08-03 18:25:30 -05:00
Gabe Black
6230668f5e O3: Get rid of the raw ExtMachInst constructor on DynInsts.
This constructor assumes that the ExtMachInst can be decoded directly into a
StaticInst that's useful to execute. With the advent of microcoded
instructions that's no longer true.
2011-08-02 11:51:16 -07:00
Gabe Black
1c68c32cc9 Scons: Make some Action objects fit the abreviated output format. 2011-08-02 03:22:11 -07:00
Nilay Vaish
1b49c56679 Scons: Drop RUBY as compile time option.
This patch drops RUBY as a compile time option. Instead the PROTOCOL option
is used to figure out whether or not to build Ruby. If the specified protocol
is 'None', then Ruby is not compiled.
2011-08-02 00:10:08 -05:00
Gabe Black
206c2e9a0e O3: Implement memory mapped IPRs for O3. 2011-07-31 19:21:17 -07:00
Gabe Black
a42c6ae48d O3: Fix corner case squashing into the microcode ROM.
When fetching from the microcode ROM, if the PC is set so that it isn't in the
cache block that's been fetched the CPU will get stuck. The fetch stage
notices that it's in the ROM so it doesn't try to fetch from the current PC.
It then later notices that it's outside of the current cache block so it skips
generating instructions expecting to continue once the right bytes have been
fetched. This change lets the fetch stage attempt to generate instructions,
and only checks if the bytes it's going to use are valid if it's really going
to use them.
2011-07-30 23:22:53 -07:00
Nilay Vaish
b4152e250d SLICC: Put functions of a controller in its .cc file
Currently, functions associated with a controller go into separate files.
This patch puts all the functions in the controller's .cc file. This should
hopefully take away some time from compilation.
2011-07-27 20:20:53 -05:00
Ali Saidi
147095cb08 Mem: Fix issue with prefetches originating at non-L1 caches getting stale data
Prefetch requests issued from the L2 or below wouldn't check if valid data is
present higher in the system. If a prefetch into the L2 occured at the same
time as writeback from a higher-level cache the dirty data could be replaced
in by unmodified data in memory.
2011-07-15 11:53:35 -05:00
Giacomo Gabrielli
69ef57fd0f O3: Create a pipeline activity viewer for the O3 CPU model.
Implemented a pipeline activity viewer as a python script (util/o3-pipeview.py)
and modified O3 code base to support an extra trace flag (O3PipeView) for
generating traces to be used as inputs by the tool.
2011-07-15 11:53:35 -05:00
Wade Walker
8870a5820a ARM: Fix SWP/SWPB undefined instruction behavior
SWP and SWPB now throw an undefined instruction exception if
SCTLR.SW == 0. This also required the MIDR to be changed
slightly so programs can correctly determine that gem5 supports
the ARM v7 behavior of SWP/SWPB (in ARM v6, SWP/SWPB were
deprecated, but not disabled at CPU startup).
2011-07-15 11:53:34 -05:00
Wade Walker
e6672d1f29 ARM: Add two unimplemented miscellaneous registers.
Adds MISCREG_ID_MMFR2 and removes break on access to MISCREG_CLIDR. Both
registers now return values that are consistent with current ARM
implementations.
2011-07-15 11:53:34 -05:00
Nilay Vaish
dbde1502cd X86: implements copyRegs() function
This patch implements the copyRegs() function for the x86 architecture.
The patch assumes that no side effects other than TLB invalidation need
to be considered while copying the registers. This may not hold true in
future.
2011-07-11 16:52:52 -05:00
Gabe Black
a7dcd19fa0 ISA: Get rid of the unused mem_acc_type template parameter. 2011-07-11 04:47:06 -07:00
Mrinmoy Ghosh
3396fd9e84 Branch predictor: Fixes the tournament branch predictor.
Branch predictor could not predict a branch in a nested loop because:
 1. The global history was not updated after a mispredict squash.
 2. The global history was updated in the fetch stage. The choice predictors
    that were updated  used the changed global history. This is incorrect, as
    it incorporates the state of global history after the branch in
    encountered. Fixed update to choice predictor using the global history
    state before the branch happened.
 3. The global predictor table was also updated using the global history state
    before the branch happened as above.

Additionally, parameters to initialize ctr and history size were reversed.
2011-07-10 12:56:08 -05:00
Geoffrey Blake
c7e7b89058 O3: Fix up pipelining icache accesses in fetch stage to function properly
Fixed up the patch from Yasuko Watanabe that enabled pipelining of fetch accessess to
icache to work with recent changes to main repository.
Also added in ability for fetch stage to delay issuing the fault carrying
nop when a pipeline fetch causes a fault and no fetch bandwidth is available
until the next cycle.
2011-07-10 12:56:08 -05:00
Ali Saidi
f8538f7456 IO: Handle case where ISA Fake device is being used as a fake memory. 2011-07-10 12:56:08 -05:00
Ali Saidi
60579e8d74 O3: Make sure fetch doesn't go off into the weeds during speculation. 2011-07-10 12:56:08 -05:00
Ali Saidi
9751a1d3e7 Config: Add support for a Self.all proxy object 2011-07-10 12:56:08 -05:00
Daniel Johnson
83f91db2cc ARM: Fix mp interrupt bug in GIC.
Missing "!" made multiprocessor interrupts operate incorrectly.
2011-07-10 12:56:08 -05:00
Korey Sewell
678376f0ba alpha:hwrei:rollback for o3
change hwrei back to being a non-control instruction so O3-FS mode will work
add squash in inorder that will catch a hwrei (or any other genric instruction)
that isnt a control inst but changes the PC. Additional testing still needs to be done
for inorder-FS mode but this change will free O3 development back up in the interim
2011-07-07 21:32:49 -04:00
Brad Beckmann
255f82a783 ruby: added generic dma machine 2011-07-06 18:45:15 -07:00
Brad Beckmann
4f83390781 MOESI_hammer: Fixed uniprocessor DMA bug 2011-07-06 18:44:42 -07:00
Nathan Binkert
da1eaaca0e slicc: add a protocol statement and an include statement
All protocols must specify their name
The include statement allows any file to include another file.
2011-07-05 18:30:05 -07:00
Nathan Binkert
831e9b3b7a slicc: cleanup slicc code and make it less verbose 2011-07-05 18:30:05 -07:00
Nathan Binkert
3d252f8e5f grammar: better encapsulation of a grammar and parsing
This makes it possible to use the grammar multiple times and use the multiple
instances concurrently.  This makes implementing an include statement as part
of a grammar possible.
2011-07-05 18:30:04 -07:00
Gabe Black
87b657278d ISAs: Streamline some spots where Mem is used in the ISA descriptions. 2011-07-05 16:52:57 -07:00
Gabe Black
63a934d152 ISA parser: Define operand types with a ctype directly. 2011-07-05 16:52:15 -07:00
Gabe Black
f16179eb21 ISA parser: Simplify operand type handling.
This change simplifies the code surrounding operand type handling and makes it
depend only on the ctype that goes with each operand type. Future changes will
allow defining operand types by their ctypes directly, convert the ISAs over
to that style of definition, and then remove support for the old style. These
changes are to make it easier to use non-builtin types like classes or
structures as the type for operands.
2011-07-05 16:48:18 -07:00
Nilay Vaish
9b85b4b19a Merged with Gabe's recent changes. 2011-07-03 11:38:25 -05:00
Nilay Vaish
5e0851d554 Network_test: Conform it with functional access changes in Ruby
Addition of functional access support to Ruby necessitated some changes to
the way coherence protocols are written. I had forgotten to update the
Network_test protocol. This patch makes those updates.
2011-07-03 11:33:46 -05:00
Gabe Black
3a1428365a ExecContext: Rename the readBytes/writeBytes functions to readMem and writeMem.
readBytes and writeBytes had the word "bytes" in their names because they
accessed blobs of bytes. This distinguished them from the read and write
functions which handled higher level data types. Because those functions don't
exist any more, this change renames readBytes and writeBytes to more general
names, readMem and writeMem, which reflect the fact that they are how you read
and write memory. This also makes their names more consistent with the
register reading/writing functions, although those are still read and set for
some reason.
2011-07-02 22:35:04 -07:00
Gabe Black
2e7426664a ExecContext: Get rid of the now unused read/write templated functions. 2011-07-02 22:34:58 -07:00
Gabe Black
aade13769f ISA: Use readBytes/writeBytes for all instruction level memory operations. 2011-07-02 22:34:29 -07:00