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O3: When squashing, restore the macroop that should be used for fetching.

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This commit is contained in:
Gabe Black 2011-08-14 17:41:34 -07:00
parent ec204f003c
commit 0e6dc00497
4 changed files with 20 additions and 10 deletions
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1
src/cpu/o3/comm.hh
View file

@ -135,6 +135,7 @@ struct TimeBufStruct {
bool branchTaken;
Addr mispredPC;
TheISA::PCState nextPC;
DynInstPtr squashInst;
unsigned branchCount;
};

1
src/cpu/o3/decode_impl.hh
View file

@ -280,6 +280,7 @@ DefaultDecode<Impl>::squash(DynInstPtr &inst, ThreadID tid)
toFetch->decodeInfo[tid].doneSeqNum = inst->seqNum;
toFetch->decodeInfo[tid].nextPC = inst->branchTarget();
toFetch->decodeInfo[tid].branchTaken = inst->pcState().branching();
toFetch->decodeInfo[tid].squashInst = inst;
InstSeqNum squash_seq_num = inst->seqNum;

10
src/cpu/o3/fetch.hh
View file

@ -332,13 +332,15 @@ class DefaultFetch
}
/** Squashes a specific thread and resets the PC. */
inline void doSquash(const TheISA::PCState &newPC, ThreadID tid);
inline void doSquash(const TheISA::PCState &newPC,
const DynInstPtr squashInst, ThreadID tid);
/** Squashes a specific thread and resets the PC. Also tells the CPU to
* remove any instructions between fetch and decode that should be sqaushed.
*/
void squashFromDecode(const TheISA::PCState &newPC,
const InstSeqNum &seq_num, ThreadID tid);
const DynInstPtr squashInst,
const InstSeqNum seq_num, ThreadID tid);
/** Checks if a thread is stalled. */
bool checkStall(ThreadID tid) const;
@ -352,8 +354,8 @@ class DefaultFetch
* remove any instructions that are not in the ROB. The source of this
* squash should be the commit stage.
*/
void squash(const TheISA::PCState &newPC, const InstSeqNum &seq_num,
DynInstPtr &squashInst, ThreadID tid);
void squash(const TheISA::PCState &newPC, const InstSeqNum seq_num,
DynInstPtr squashInst, ThreadID tid);
/** Ticks the fetch stage, processing all inputs signals and fetching
* as many instructions as possible.

18
src/cpu/o3/fetch_impl.hh
View file

@ -746,14 +746,18 @@ DefaultFetch<Impl>::finishTranslation(Fault fault, RequestPtr mem_req)
template <class Impl>
inline void
DefaultFetch<Impl>::doSquash(const TheISA::PCState &newPC, ThreadID tid)
DefaultFetch<Impl>::doSquash(const TheISA::PCState &newPC,
const DynInstPtr squashInst, ThreadID tid)
{
DPRINTF(Fetch, "[tid:%i]: Squashing, setting PC to: %s.\n",
tid, newPC);
pc[tid] = newPC;
fetchOffset[tid] = 0;
macroop[tid] = NULL;
if (squashInst && squashInst->pcState().instAddr() == newPC.instAddr())
macroop[tid] = squashInst->macroop;
else
macroop[tid] = NULL;
predecoder.reset();
// Clear the icache miss if it's outstanding.
@ -786,11 +790,12 @@ DefaultFetch<Impl>::doSquash(const TheISA::PCState &newPC, ThreadID tid)
template<class Impl>
void
DefaultFetch<Impl>::squashFromDecode(const TheISA::PCState &newPC,
const InstSeqNum &seq_num, ThreadID tid)
const DynInstPtr squashInst,
const InstSeqNum seq_num, ThreadID tid)
{
DPRINTF(Fetch, "[tid:%i]: Squashing from decode.\n", tid);
doSquash(newPC, tid);
doSquash(newPC, squashInst, tid);
// Tell the CPU to remove any instructions that are in flight between
// fetch and decode.
@ -866,12 +871,12 @@ DefaultFetch<Impl>::updateFetchStatus()
template <class Impl>
void
DefaultFetch<Impl>::squash(const TheISA::PCState &newPC,
const InstSeqNum &seq_num, DynInstPtr &squashInst,
const InstSeqNum seq_num, DynInstPtr squashInst,
ThreadID tid)
{
DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n", tid);
doSquash(newPC, tid);
doSquash(newPC, squashInst, tid);
// Tell the CPU to remove any instructions that are not in the ROB.
cpu->removeInstsNotInROB(tid);
@ -1052,6 +1057,7 @@ DefaultFetch<Impl>::checkSignalsAndUpdate(ThreadID tid)
DPRINTF(Fetch, "Squashing from decode with PC = %s\n", nextPC);
// Squash unless we're already squashing
squashFromDecode(fromDecode->decodeInfo[tid].nextPC,
fromDecode->decodeInfo[tid].squashInst,
fromDecode->decodeInfo[tid].doneSeqNum,
tid);