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O3: Create a pipeline activity viewer for the O3 CPU model.

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Implemented a pipeline activity viewer as a python script (util/o3-pipeview.py)
and modified O3 code base to support an extra trace flag (O3PipeView) for
generating traces to be used as inputs by the tool.
This commit is contained in:
Giacomo Gabrielli 2011-07-15 11:53:35 -05:00
parent 09914cdf8f
commit 69ef57fd0f
10 changed files with 315 additions and 0 deletions
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1
src/cpu/SConscript
View file

@ -173,6 +173,7 @@ DebugFlag('ExecKernel')
DebugFlag('ExecAsid')
DebugFlag('Fetch')
DebugFlag('IntrControl')
DebugFlag('O3PipeView')
DebugFlag('PCEvent')
DebugFlag('Quiesce')

17
src/cpu/o3/commit_impl.hh
View file

@ -58,6 +58,7 @@
#include "debug/Commit.hh"
#include "debug/CommitRate.hh"
#include "debug/ExecFaulting.hh"
#include "debug/O3PipeView.hh"
#include "params/DerivO3CPU.hh"
#include "sim/faults.hh"
@ -1207,6 +1208,22 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
// Finally clear the head ROB entry.
rob->retireHead(tid);
#if TRACING_ON
// Print info needed by the pipeline activity viewer.
DPRINTFR(O3PipeView, "O3PipeView:fetch:%llu:0x%08llx:%d:%llu:%s\n",
head_inst->fetchTick,
head_inst->instAddr(),
head_inst->microPC(),
head_inst->seqNum,
head_inst->staticInst->disassemble(head_inst->instAddr()));
DPRINTFR(O3PipeView, "O3PipeView:decode:%llu\n", head_inst->decodeTick);
DPRINTFR(O3PipeView, "O3PipeView:rename:%llu\n", head_inst->renameTick);
DPRINTFR(O3PipeView, "O3PipeView:dispatch:%llu\n", head_inst->dispatchTick);
DPRINTFR(O3PipeView, "O3PipeView:issue:%llu\n", head_inst->issueTick);
DPRINTFR(O3PipeView, "O3PipeView:complete:%llu\n", head_inst->completeTick);
DPRINTFR(O3PipeView, "O3PipeView:retire:%llu\n", curTick());
#endif
// If this was a store, record it for this cycle.
if (head_inst->isStore())
committedStores[tid] = true;

4
src/cpu/o3/decode_impl.hh
View file

@ -706,6 +706,10 @@ DefaultDecode<Impl>::decodeInsts(ThreadID tid)
++decodeDecodedInsts;
--insts_available;
#if TRACING_ON
inst->decodeTick = curTick();
#endif
// Ensure that if it was predicted as a branch, it really is a
// branch.
if (inst->readPredTaken() && !inst->isControl()) {

11
src/cpu/o3/dyn_inst.hh
View file

@ -123,6 +123,17 @@ class BaseO3DynInst : public BaseDynInst<Impl>
int _numDestMiscRegs;
public:
#if TRACING_ON
/** Tick records used for the pipeline activity viewer. */
Tick fetchTick;
Tick decodeTick;
Tick renameTick;
Tick dispatchTick;
Tick issueTick;
Tick completeTick;
#endif
/** Reads a misc. register, including any side-effects the read
* might have as defined by the architecture.
*/

9
src/cpu/o3/dyn_inst_impl.hh
View file

@ -85,6 +85,15 @@ BaseO3DynInst<Impl>::initVars()
}
_numDestMiscRegs = 0;
#if TRACING_ON
fetchTick = 0;
decodeTick = 0;
renameTick = 0;
dispatchTick = 0;
issueTick = 0;
completeTick = 0;
#endif
}
template <class Impl>

4
src/cpu/o3/fetch_impl.hh
View file

@ -1312,6 +1312,10 @@ DefaultFetch<Impl>::fetch(bool &status_change)
numInst++;
#if TRACING_ON
instruction->fetchTick = curTick();
#endif
nextPC = thisPC;
// If we're branching after this instruction, quite fetching

8
src/cpu/o3/iew_impl.hh
View file

@ -1147,6 +1147,10 @@ DefaultIEW<Impl>::dispatchInsts(ThreadID tid)
toRename->iewInfo[tid].dispatched++;
++iewDispatchedInsts;
#if TRACING_ON
inst->dispatchTick = curTick();
#endif
}
if (!insts_to_dispatch.empty()) {
@ -1619,6 +1623,10 @@ DefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst)
iewExecutedInsts++;
#endif
#if TRACING_ON
inst->completeTick = curTick();
#endif
//
// Control operations
//

4
src/cpu/o3/inst_queue_impl.hh
View file

@ -857,6 +857,10 @@ InstructionQueue<Impl>::scheduleReadyInsts()
issuing_inst->setIssued();
++total_issued;
#if TRACING_ON
issuing_inst->issueTick = curTick();
#endif
if (!issuing_inst->isMemRef()) {
// Memory instructions can not be freed from the IQ until they
// complete.

4
src/cpu/o3/rename_impl.hh
View file

@ -692,6 +692,10 @@ DefaultRename<Impl>::renameInsts(ThreadID tid)
++renamed_insts;
#if TRACING_ON
inst->renameTick = curTick();
#endif
// Put instruction in rename queue.
toIEW->insts[toIEWIndex] = inst;
++(toIEW->size);

253
util/o3-pipeview.py Executable file
View file

@ -0,0 +1,253 @@
#! /usr/bin/env python
# Copyright (c) 2011 ARM Limited
# All rights reserved
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Giacomo Gabrielli
# Pipeline activity viewer for the O3 CPU model.
import optparse
import os
import sys
def process_trace(trace, outfile, cycle_time, width, color, timestamps,
start_tick, stop_tick, start_sn, stop_sn):
line = None
fields = None
# Skip lines up to region of interest
if start_tick != 0:
while True:
line = trace.readline()
if not line: return
fields = line.split(':')
if fields[0] != 'O3PipeView': continue
if int(fields[2]) >= start_tick: break
elif start_sn != 0:
while True:
line = trace.readline()
if not line: return
fields = line.split(':')
if fields[0] != 'O3PipeView': continue
if fields[1] == 'fetch' and int(fields[5]) >= start_sn: break
else:
line = trace.readline()
if not line: return
fields = line.split(':')
# Skip lines up to next instruction fetch
while fields[0] != 'O3PipeView' or fields[1] != 'fetch':
line = trace.readline()
if not line: return
fields = line.split(':')
# Print header
outfile.write('// f = fetch, d = decode, n = rename, p = dispatch, '
'i = issue, c = complete, r = retire\n\n')
outfile.write(' ' + 'timeline'.center(width) +
' ' + 'tick'.center(15) +
' ' + 'pc.upc'.center(12) +
' ' + 'disasm'.ljust(25) +
' ' + 'seq_num'.center(15))
if timestamps:
outfile.write('timestamps'.center(25))
outfile.write('\n')
# Region of interest
curr_inst = {}
while True:
if fields[0] == 'O3PipeView':
curr_inst[fields[1]] = int(fields[2])
if fields[1] == 'fetch':
if ((stop_tick > 0 and int(fields[2]) > stop_tick) or
(stop_sn > 0 and int(fields[5]) > stop_sn)):
return
(curr_inst['pc'], curr_inst['upc']) = fields[3:5]
curr_inst['sn'] = int(fields[5])
curr_inst['disasm'] = ' '.join(fields[6][:-1].split())
elif fields[1] == 'retire':
print_inst(outfile, curr_inst, cycle_time, width, color,
timestamps)
line = trace.readline()
if not line: return
fields = line.split(':')
def print_inst(outfile, inst, cycle_time, width, color, timestamps):
if color:
from m5.util.terminal import termcap
else:
from m5.util.terminal import no_termcap as termcap
# Pipeline stages
stages = [{'name': 'fetch',
'color': termcap.Blue + termcap.Reverse,
'shorthand': 'f'},
{'name': 'decode',
'color': termcap.Yellow + termcap.Reverse,
'shorthand': 'd'},
{'name': 'rename',
'color': termcap.Magenta + termcap.Reverse,
'shorthand': 'n'},
{'name': 'dispatch',
'color': termcap.Green + termcap.Reverse,
'shorthand': 'p'},
{'name': 'issue',
'color': termcap.Red + termcap.Reverse,
'shorthand': 'i'},
{'name': 'complete',
'color': termcap.Cyan + termcap.Reverse,
'shorthand': 'c'},
{'name': 'retire',
'color': termcap.Blue + termcap.Reverse,
'shorthand': 'r'}]
# Print
time_width = width * cycle_time
base_tick = (inst['fetch'] / time_width) * time_width
num_lines = ((inst['retire'] - inst['fetch']) / time_width) + 1
curr_color = termcap.Normal
for i in range(num_lines):
start_tick = base_tick + i * time_width
end_tick = start_tick + time_width
if num_lines == 1: # compact form
end_tick += (inst['fetch'] - base_tick)
events = []
for stage_idx in range(len(stages)):
tick = inst[stages[stage_idx]['name']]
if tick >= start_tick and tick < end_tick:
events.append((tick % time_width,
stages[stage_idx]['name'],
stage_idx))
events.sort()
outfile.write('[')
pos = 0
if num_lines == 1 and events[0][2] != 0: # event is not fetch
curr_color = stages[events[0][2] - 1]['color']
for event in events:
if (stages[event[2]]['name'] == 'dispatch' and
inst['dispatch'] == inst['issue']):
continue
outfile.write(curr_color + '.' * ((event[0] / cycle_time) - pos))
outfile.write(stages[event[2]]['color'] +
stages[event[2]]['shorthand'])
if event[2] != len(stages) - 1: # event is not retire
curr_color = stages[event[2]]['color']
else:
curr_color = termcap.Normal
pos = (event[0] / cycle_time) + 1
outfile.write(curr_color + '.' * (width - pos) + termcap.Normal +
']-(' + str(base_tick + i * time_width).rjust(15) + ') ')
if i == 0:
outfile.write('%s.%s %s [%s]' % (
inst['pc'].rjust(10),
inst['upc'],
inst['disasm'].ljust(25),
str(inst['sn']).rjust(15)))
if timestamps:
outfile.write(' f=%s, r=%s' % (inst['fetch'], inst['retire']))
outfile.write('\n')
else:
outfile.write('...'.center(12) + '\n')
def validate_range(my_range):
my_range = [int(i) for i in my_range.split(':')]
if (len(my_range) != 2 or
my_range[0] < 0 or
my_range[1] > 0 and my_range[0] >= my_range[1]):
return None
return my_range
def main():
# Parse options
usage = ('%prog [OPTION]... TRACE_FILE')
parser = optparse.OptionParser(usage=usage)
parser.add_option(
'-o',
dest='outfile',
default=os.path.join(os.getcwd(), 'o3-pipeview.out'),
help="output file (default: '%default')")
parser.add_option(
'-t',
dest='tick_range',
default='0:-1',
help="tick range (default: '%default'; -1 == inf.)")
parser.add_option(
'-i',
dest='inst_range',
default='0:-1',
help="instruction range (default: '%default'; -1 == inf.)")
parser.add_option(
'-w',
dest='width',
type='int', default=80,
help="timeline width (default: '%default')")
parser.add_option(
'--color',
action='store_true', default=False,
help="enable colored output (default: '%default')")
parser.add_option(
'-c', '--cycle-time',
type='int', default=1000,
help="CPU cycle time in ticks (default: '%default')")
parser.add_option(
'--timestamps',
action='store_true', default=False,
help="print fetch and retire timestamps (default: '%default')")
(options, args) = parser.parse_args()
if len(args) != 1:
parser.error('incorrect number of arguments')
sys.exit(1)
tick_range = validate_range(options.tick_range)
if not tick_range:
parser.error('invalid range')
sys.exit(1)
inst_range = validate_range(options.inst_range)
if not inst_range:
parser.error('invalid range')
sys.exit(1)
# Process trace
print 'Processing trace... ',
with open(args[0], 'r') as trace:
with open(options.outfile, 'w') as out:
process_trace(trace, out, options.cycle_time, options.width,
options.color, options.timestamps,
*(tick_range + inst_range))
print 'done!'
if __name__ == '__main__':
sys.path.append(os.path.join(
os.path.dirname(os.path.abspath(__file__)),
'..', 'src', 'python'))
main()