gem5/src
Gabe Black a42c6ae48d O3: Fix corner case squashing into the microcode ROM.
When fetching from the microcode ROM, if the PC is set so that it isn't in the
cache block that's been fetched the CPU will get stuck. The fetch stage
notices that it's in the ROM so it doesn't try to fetch from the current PC.
It then later notices that it's outside of the current cache block so it skips
generating instructions expecting to continue once the right bytes have been
fetched. This change lets the fetch stage attempt to generate instructions,
and only checks if the bytes it's going to use are valid if it's really going
to use them.
2011-07-30 23:22:53 -07:00
..
arch ARM: Fix SWP/SWPB undefined instruction behavior 2011-07-15 11:53:34 -05:00
base Loader: Handle bad section names when loading an ELF file. 2011-06-12 23:52:21 -07:00
cpu O3: Fix corner case squashing into the microcode ROM. 2011-07-30 23:22:53 -07:00
dev IO: Handle case where ISA Fake device is being used as a fake memory. 2011-07-10 12:56:08 -05:00
doxygen Fix up doxygen. 2006-08-14 19:25:07 -04:00
kern scons: rename TraceFlags to DebugFlags 2011-06-02 17:36:21 -07:00
mem SLICC: Put functions of a controller in its .cc file 2011-07-27 20:20:53 -05:00
python O3: Make sure fetch doesn't go off into the weeds during speculation. 2011-07-10 12:56:08 -05:00
sim O3: Make sure fetch doesn't go off into the weeds during speculation. 2011-07-10 12:56:08 -05:00
unittest copyright: clean up copyright blocks 2011-06-02 14:36:35 -07:00
Doxyfile Fix up doxygen. 2006-08-14 19:25:07 -04:00
SConscript scons: rename TraceFlags to DebugFlags 2011-06-02 17:36:21 -07:00