Wade Walker 8870a5820a ARM: Fix SWP/SWPB undefined instruction behavior ... SWP and SWPB now throw an undefined instruction exception if SCTLR.SW == 0. This also required the MIDR to be changed slightly so programs can correctly determine that gem5 supports the ARM v7 behavior of SWP/SWPB (in ARM v6, SWP/SWPB were deprecated, but not disabled at CPU startup).		2011-07-15 11:53:34 -05:00
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alpha	alpha:hwrei:rollback for o3	2011-07-07 21:32:49 -04:00
arm	ARM: Fix SWP/SWPB undefined instruction behavior	2011-07-15 11:53:34 -05:00
generic	ExecContext: Rename the readBytes/writeBytes functions to readMem and writeMem.	2011-07-02 22:35:04 -07:00
mips	ISA parser: Define operand types with a ctype directly.	2011-07-05 16:52:15 -07:00
noisa	SCons: Support building without an ISA	2010-11-19 18:00:39 -06:00
power	ISAs: Streamline some spots where Mem is used in the ISA descriptions.	2011-07-05 16:52:57 -07:00
sparc	ISAs: Streamline some spots where Mem is used in the ISA descriptions.	2011-07-05 16:52:57 -07:00
x86	X86: implements copyRegs() function	2011-07-11 16:52:52 -05:00
isa_parser.py	ISA: Get rid of the unused mem_acc_type template parameter.	2011-07-11 04:47:06 -07:00
micro_asm.py	scons: add slicc and ply to sys.path and PYTHONPATH so everyone has access	2009-09-22 15:24:16 -07:00
micro_asm_test.py	Add a second section to make sure the ROM is extended properly.	2007-05-31 22:21:21 +00:00
SConscript	scons: rename TraceFlags to DebugFlags	2011-06-02 17:36:21 -07:00