CPU: Remove references to memory copy operations

src/cpu/base_dyn_inst.hh

@@ -252,12 +252,6 @@ class BaseDynInst : public FastAlloc, public RefCounted
     /** The effective physical address. */
     Addr physEffAddr;
 
-    /** Effective virtual address for a copy source. */
-    Addr copySrcEffAddr;
-
-    /** Effective physical address for a copy source. */
-    Addr copySrcPhysEffAddr;
-
     /** The memory request flags (from translation). */
     unsigned memReqFlags;
 
@@ -499,7 +493,6 @@ class BaseDynInst : public FastAlloc, public RefCounted
     { return staticInst->isStoreConditional(); }
     bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
     bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
-    bool isCopy()         const { return staticInst->isCopy(); }
     bool isInteger()      const { return staticInst->isInteger(); }
     bool isFloating()     const { return staticInst->isFloating(); }
     bool isControl()      const { return staticInst->isControl(); }

src/cpu/inorder/inorder_dyn_inst.hh

@@ -350,7 +350,6 @@ class InOrderDynInst : public FastAlloc, public RefCounted
     { return staticInst->isStoreConditional(); }
     bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
     bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
-    bool isCopy()         const { return staticInst->isCopy(); }
     bool isInteger()      const { return staticInst->isInteger(); }
     bool isFloating()     const { return staticInst->isFloating(); }
     bool isControl()      const { return staticInst->isControl(); }

src/cpu/o3/commit_impl.hh

@@ -1199,9 +1199,6 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
                                  head_inst->renamedDestRegIdx(i));
     }
 
-    if (head_inst->isCopy())
-        panic("Should not commit any copy instructions!");
-
     // Finally clear the head ROB entry.
     rob->retireHead(tid);
 

src/cpu/ozone/lw_back_end_impl.hh

@@ -1205,9 +1205,6 @@ LWBackEnd<Impl>::commitInst(int inst_num)
         inst->traceData = NULL;
     }
 
-    if (inst->isCopy())
-        panic("Should not commit any copy instructions!");
-
     inst->clearDependents();
 
     frontEnd->addFreeRegs(freed_regs);

src/cpu/static_inst.hh

@@ -117,7 +117,6 @@ class StaticInstBase : public RefCounted
         IsIndexed,      ///< Accesses memory with an indexed address computation
         IsInstPrefetch, ///< Instruction-cache prefetch.
         IsDataPrefetch, ///< Data-cache prefetch.
-        IsCopy,         ///< Fast Cache block copy
 
         IsControl,              ///< Control transfer instruction.
         IsDirectControl,        ///< PC relative control transfer.
@@ -228,7 +227,6 @@ class StaticInstBase : public RefCounted
     bool isDataPrefetch() const { return flags[IsDataPrefetch]; }
     bool isPrefetch()     const { return isInstPrefetch() ||
                                          isDataPrefetch(); }
-    bool isCopy()         const { return flags[IsCopy];}
 
     bool isInteger()      const { return flags[IsInteger]; }
     bool isFloating()     const { return flags[IsFloating]; }

src/cpu/thread_state.hh

@@ -200,18 +200,6 @@ struct ThreadState {
 #endif
 
   public:
-    /**
-     * Temporary storage to pass the source address from copy_load to
-     * copy_store.
-     * @todo Remove this temporary when we have a better way to do it.
-     */
-    Addr copySrcAddr;
-    /**
-     * Temp storage for the physical source address of a copy.
-     * @todo Remove this temporary when we have a better way to do it.
-     */
-    Addr copySrcPhysAddr;
-
     /*
      * number of executed instructions, for matching with syscall trace
      * points in EIO files.