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CPU: Fix a case where timing simple cpu faults can nest.

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If we fault, change the state to faulting so that we don't fault again in the same cycle.
This commit is contained in:
Ali Saidi 2011-05-04 20:38:27 -05:00
parent 89e7bcca82
commit 6e634beb8a
2 changed files with 17 additions and 5 deletions
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1
src/cpu/simple/base.hh
View file

@ -124,6 +124,7 @@ class BaseSimpleCPU : public BaseCPU
enum Status {
Idle,
Running,
Faulting,
ITBWaitResponse,
IcacheRetry,
IcacheWaitResponse,

21
src/cpu/simple/timing.cc
View file

@ -725,6 +725,7 @@ TimingSimpleCPU::fetch()
bool needToFetch = !isRomMicroPC(pcState.microPC()) && !curMacroStaticInst;
if (needToFetch) {
_status = Running;
Request *ifetch_req = new Request();
ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0);
setupFetchRequest(ifetch_req);
@ -771,7 +772,20 @@ TimingSimpleCPU::sendFetch(Fault fault, RequestPtr req, ThreadContext *tc)
void
TimingSimpleCPU::advanceInst(Fault fault)
{
if (fault != NoFault || !stayAtPC)
if (_status == Faulting)
return;
if (fault != NoFault) {
advancePC(fault);
DPRINTF(SimpleCPU, "Fault occured, scheduling fetch event\n");
reschedule(fetchEvent, nextCycle(), true);
_status = Faulting;
return;
}
if (!stayAtPC)
advancePC(fault);
if (_status == Running) {
@ -786,8 +800,6 @@ TimingSimpleCPU::advanceInst(Fault fault)
void
TimingSimpleCPU::completeIfetch(PacketPtr pkt)
{
DPRINTF(SimpleCPU, "Complete ICache Fetch\n");
// received a response from the icache: execute the received
// instruction
@ -878,8 +890,7 @@ TimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt)
tickEvent.schedule(pkt, next_tick);
return true;
}
else if (pkt->wasNacked()) {
} else if (pkt->wasNacked()) {
assert(cpu->_status == IcacheWaitResponse);
pkt->reinitNacked();
if (!sendTiming(pkt)) {