ARM: Cleanup and small fixes to some NEON ops to match the spec.
Only certain bits of the cpacr can be written, some must be equal. Mult instructions that write the same register should do something sane
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a679cd917a
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16fcad3907
5 changed files with 39 additions and 28 deletions
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@ -268,19 +268,22 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
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switch (misc_reg) {
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case MISCREG_CPACR:
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{
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CPACR newCpacr = 0;
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CPACR valCpacr = val;
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newCpacr.cp10 = valCpacr.cp10;
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newCpacr.cp11 = valCpacr.cp11;
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//XXX d32dis isn't implemented. The manual says whether or not
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//it works is implementation defined.
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newCpacr.asedis = valCpacr.asedis;
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newVal = newCpacr;
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const uint32_t ones = (uint32_t)(-1);
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CPACR cpacrMask = 0;
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// Only cp10, cp11, and ase are implemented, nothing else should
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// be writable
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cpacrMask.cp10 = ones;
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cpacrMask.cp11 = ones;
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cpacrMask.asedis = ones;
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newVal &= cpacrMask;
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DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
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miscRegName[misc_reg], newVal);
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}
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break;
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case MISCREG_CSSELR:
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warn_once("The csselr register isn't implemented.\n");
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break;
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return;
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case MISCREG_FPSCR:
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{
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const uint32_t ones = (uint32_t)(-1);
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@ -320,6 +323,8 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
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break;
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case MISCREG_FPEXC:
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{
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// vfpv3 architecture, section B.6.1 of DDI04068
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// bit 29 - valid only if fpexc[31] is 0
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const uint32_t fpexcMask = 0x60000000;
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newVal = (newVal & fpexcMask) |
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(miscRegs[MISCREG_FPEXC] & ~fpexcMask);
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@ -349,8 +349,8 @@ let {{
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''')
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buildMult4Inst ("smull", '''resTemp = (int64_t)Reg2.sw *
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(int64_t)Reg3.sw;
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Reg0 = (int32_t)resTemp;
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Reg1 = (int32_t)(resTemp >> 32);
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Reg0 = (int32_t)resTemp;
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''', "llbit")
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buildMult3InstUnCc("smulwb", '''Reg0 = resTemp =
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(Reg1.sw *
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@ -374,16 +374,16 @@ let {{
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''')
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buildMult4InstUnCc("umaal", '''resTemp = Reg2.ud * Reg3.ud +
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Reg0.ud + Reg1.ud;
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Reg0.ud = (uint32_t)resTemp;
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Reg1.ud = (uint32_t)(resTemp >> 32);
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Reg0.ud = (uint32_t)resTemp;
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''')
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buildMult4Inst ("umlal", '''resTemp = Reg2.ud * Reg3.ud + Reg0.ud +
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(Reg1.ud << 32);
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Reg0.ud = (uint32_t)resTemp;
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Reg1.ud = (uint32_t)(resTemp >> 32);
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Reg0.ud = (uint32_t)resTemp;
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''', "llbit")
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buildMult4Inst ("umull", '''resTemp = Reg2.ud * Reg3.ud;
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Reg0 = (uint32_t)resTemp;
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Reg1 = (uint32_t)(resTemp >> 32);
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Reg0 = (uint32_t)resTemp;
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''', "llbit")
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}};
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@ -1761,8 +1761,8 @@ let {{
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}
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}
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'''
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threeEqualRegInst("vshl", "VshlD", "SimdAluOp", allTypes, 2, vshlCode)
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threeEqualRegInst("vshl", "VshlQ", "SimdAluOp", allTypes, 4, vshlCode)
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threeEqualRegInst("vshl", "VshlD", "SimdShiftOp", allTypes, 2, vshlCode)
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threeEqualRegInst("vshl", "VshlQ", "SimdShiftOp", allTypes, 4, vshlCode)
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vrshlCode = '''
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int16_t shiftAmt = (int8_t)srcElem2;
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@ -3204,8 +3204,8 @@ let {{
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substDict = { "targs" : type,
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"class_name" : Name }
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exec_output += NeonExecDeclare.subst(substDict)
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vdupGprInst("vdup", "NVdupDGpr", "SimdAluOp", smallUnsignedTypes, 2)
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vdupGprInst("vdup", "NVdupQGpr", "SimdAluOp", smallUnsignedTypes, 4)
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vdupGprInst("vdup", "NVdupDGpr", "SimdMiscOp", smallUnsignedTypes, 2)
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vdupGprInst("vdup", "NVdupQGpr", "SimdMiscOp", smallUnsignedTypes, 4)
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vmovCode = 'destElem = imm;'
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oneRegImmInst("vmov", "NVmoviD", "SimdMiscOp", ("uint64_t",), 2, vmovCode)
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@ -3309,8 +3309,8 @@ let {{
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}
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}
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'''
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buildVext("vext", "NVextD", "SimdAluOp", ("uint8_t",), 2, vextCode)
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buildVext("vext", "NVextQ", "SimdAluOp", ("uint8_t",), 4, vextCode)
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buildVext("vext", "NVextD", "SimdMiscOp", ("uint8_t",), 2, vextCode)
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buildVext("vext", "NVextQ", "SimdMiscOp", ("uint8_t",), 4, vextCode)
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def buildVtbxl(name, Name, opClass, length, isVtbl):
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global header_output, decoder_output, exec_output
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@ -3366,13 +3366,13 @@ let {{
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decoder_output += RegRegRegOpConstructor.subst(iop)
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exec_output += PredOpExecute.subst(iop)
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buildVtbxl("vtbl", "NVtbl1", "SimdAluOp", 1, "true")
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buildVtbxl("vtbl", "NVtbl2", "SimdAluOp", 2, "true")
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buildVtbxl("vtbl", "NVtbl3", "SimdAluOp", 3, "true")
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buildVtbxl("vtbl", "NVtbl4", "SimdAluOp", 4, "true")
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buildVtbxl("vtbl", "NVtbl1", "SimdMiscOp", 1, "true")
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buildVtbxl("vtbl", "NVtbl2", "SimdMiscOp", 2, "true")
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buildVtbxl("vtbl", "NVtbl3", "SimdMiscOp", 3, "true")
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buildVtbxl("vtbl", "NVtbl4", "SimdMiscOp", 4, "true")
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buildVtbxl("vtbx", "NVtbx1", "SimdAluOp", 1, "false")
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buildVtbxl("vtbx", "NVtbx2", "SimdAluOp", 2, "false")
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buildVtbxl("vtbx", "NVtbx3", "SimdAluOp", 3, "false")
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buildVtbxl("vtbx", "NVtbx4", "SimdAluOp", 4, "false")
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buildVtbxl("vtbx", "NVtbx1", "SimdMiscOp", 1, "false")
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buildVtbxl("vtbx", "NVtbx2", "SimdMiscOp", 2, "false")
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buildVtbxl("vtbx", "NVtbx3", "SimdMiscOp", 3, "false")
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buildVtbxl("vtbx", "NVtbx4", "SimdMiscOp", 4, "false")
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}};
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@ -310,6 +310,7 @@ namespace ArmISA
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Bitfield<23, 22> cp11;
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Bitfield<25, 24> cp12;
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Bitfield<27, 26> cp13;
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Bitfield<29, 28> rsvd;
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Bitfield<30> d32dis;
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Bitfield<31> asedis;
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EndBitUnion(CPACR)
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@ -146,7 +146,12 @@ vfpEnabled(CPACR cpacr, CPSR cpsr)
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static inline bool
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vfpEnabled(CPACR cpacr, CPSR cpsr, FPEXC fpexc)
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{
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return fpexc.en && vfpEnabled(cpacr, cpsr);
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if ((cpacr.cp11 == 0x3) ||
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((cpacr.cp11 == 0x1) && inPrivilegedMode(cpsr)))
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return fpexc.en && vfpEnabled(cpacr, cpsr);
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else
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return fpexc.en && vfpEnabled(cpacr, cpsr) &&
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(cpacr.cp11 == cpacr.cp10);
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}
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static inline bool
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