ARM: Squash state on FPSCR stride or len write.

2011-02-23 15:10:49 -06:00 · 2011-02-23 15:10:49 -06:00 · 326191adc9
parent bb319a589e
commit 326191adc9
1 changed files with 2 additions and 1 deletions
--- a/src/arch/arm/isa/insts/fp.isa
+++ b/src/arch/arm/isa/insts/fp.isa
@ -209,7 +209,8 @@ let {{
                                 { "code": vmsrFpscrCode,
                                   "predicate_test": predicateTest,
                                   "op_class": "SimdFloatMiscOp" },
-                                 ["IsSerializeAfter","IsNonSpeculative"])
+                                 ["IsSerializeAfter","IsNonSpeculative",
+                                  "IsSquashAfter"])
    header_output += FpRegRegOpDeclare.subst(vmsrFpscrIop);
    decoder_output += FpRegRegOpConstructor.subst(vmsrFpscrIop);
    exec_output += PredOpExecute.subst(vmsrFpscrIop);