ARM: Squash state on FPSCR stride or len write.
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1 changed files with 2 additions and 1 deletions
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@ -209,7 +209,8 @@ let {{
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{ "code": vmsrFpscrCode,
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"predicate_test": predicateTest,
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"op_class": "SimdFloatMiscOp" },
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["IsSerializeAfter","IsNonSpeculative"])
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["IsSerializeAfter","IsNonSpeculative",
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"IsSquashAfter"])
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header_output += FpRegRegOpDeclare.subst(vmsrFpscrIop);
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decoder_output += FpRegRegOpConstructor.subst(vmsrFpscrIop);
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exec_output += PredOpExecute.subst(vmsrFpscrIop);
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