O3: Send instruction back to fetch on squash to seed predecoder correctly.
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@ -76,6 +76,12 @@ class Predecoder
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emiIsReady = false;
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}
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void
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reset(const ExtMachInst &old_emi)
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{
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reset();
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}
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// Use this to give data to the predecoder. This should be used
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// when there is control flow.
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void
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@ -83,6 +83,12 @@ namespace ArmISA
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predAddrValid = false;
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}
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void reset(const ExtMachInst &old_emi)
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{
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reset();
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itstate = old_emi.newItstate;
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}
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Predecoder(ThreadContext * _tc) :
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tc(_tc), data(0)
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{
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@ -75,6 +75,12 @@ class Predecoder
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emiIsReady = false;
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}
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void
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reset(const ExtMachInst &old_emi)
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{
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reset();
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}
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//Use this to give data to the predecoder. This should be used
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//when there is control flow.
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void
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@ -82,6 +82,12 @@ class Predecoder
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emiIsReady = false;
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}
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void
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reset(const ExtMachInst &old_emi)
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{
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reset();
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}
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// Use this to give data to the predecoder. This should be used
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// when there is control flow.
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void
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@ -68,12 +68,19 @@ class Predecoder
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}
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void process() {}
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void
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reset()
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{
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emiIsReady = false;
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}
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void
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reset(const ExtMachInst &old_emi)
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{
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reset();
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}
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// Use this to give data to the predecoder. This should be used
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// when there is control flow.
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void
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@ -174,6 +174,12 @@ namespace X86ISA
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state = ResetState;
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}
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void
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reset(const ExtMachInst &old_emi)
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{
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reset();
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}
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ThreadContext * getTC()
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{
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return tc;
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@ -808,8 +808,9 @@ FullO3CPU<Impl>::removeThread(ThreadID tid)
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}
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// Squash Throughout Pipeline
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InstSeqNum squash_seq_num = commit.rob->readHeadInst(tid)->seqNum;
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fetch.squash(0, squash_seq_num, tid);
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DynInstPtr inst = commit.rob->readHeadInst(tid);
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InstSeqNum squash_seq_num = inst->seqNum;
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fetch.squash(0, squash_seq_num, inst, tid);
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decode.squash(tid);
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rename.squash(squash_seq_num, tid);
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iew.squash(tid);
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@ -312,8 +312,8 @@ class DefaultFetch
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* remove any instructions that are not in the ROB. The source of this
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* squash should be the commit stage.
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*/
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void squash(const TheISA::PCState &newPC,
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const InstSeqNum &seq_num, ThreadID tid);
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void squash(const TheISA::PCState &newPC, const InstSeqNum &seq_num,
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DynInstPtr &squashInst, ThreadID tid);
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/** Ticks the fetch stage, processing all inputs signals and fetching
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* as many instructions as possible.
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@ -815,11 +815,14 @@ DefaultFetch<Impl>::updateFetchStatus()
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template <class Impl>
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void
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DefaultFetch<Impl>::squash(const TheISA::PCState &newPC,
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const InstSeqNum &seq_num, ThreadID tid)
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const InstSeqNum &seq_num, DynInstPtr &squashInst,
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ThreadID tid)
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{
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DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n", tid);
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doSquash(newPC, tid);
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if (squashInst)
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predecoder.reset(squashInst->staticInst->machInst);
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// Tell the CPU to remove any instructions that are not in the ROB.
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cpu->removeInstsNotInROB(tid);
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@ -1,4 +1,16 @@
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/*
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* Copyright (c) 2011 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2004-2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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