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Author SHA1 Message Date
Lisa Hsu
c55a467a06 make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered 
across the subclasses. generally make it so that member data is _cpuId and
accessor functions are cpuId(). The ID val comes from the python (default -1 if
none provided), and if it is -1, the index of cpuList will be given. this has
passed util/regress quick and se.py -n4 and fs.py -n4 as well as standard
switch.
 2008-11-02 21:56:57 -05:00
Clint Smullen
95af120e60 CPU: The API change to EventWrapper did not get propagated to the entirety of TimingSimpleCPU. 
The constructor no-longer schedules an event at construction and the implict conversion between int and bool was allowing the old code to compile without warning.

Signed-off By: Ali Saidi
 2008-10-27 18:18:04 -04:00
Lisa Hsu
8788d703f8 s/cpu_id/cpuId in o3 (to be consistent and match style), also fix some typos in 
comments.
 2008-10-23 16:49:17 -04:00
Nathan Binkert
9836d81c2b style: Use the correct m5 style for things relating to interrupts. 2008-10-21 07:12:53 -07:00
Ali Saidi
b760b99f4d O3CPU: Undo Gabe's changes to remove hwrei and simpalcheck from O3 CPU. Removing hwrei causes 
the instruction after the hwrei to be fetched before the ITB/DTB_CM register is updated in a call pal
call sys and thus the translation fails because the user is attempting to access a super page address.

Minimally, it seems as though some sort of fetch stall or refetch after a hwrei is required. I think
this works currently because the hwrei uses the exec context interface, and the o3 stalls when that occurs.

Additionally, these changes don't update the LOCK register and probably break ll/sc. Both o3 changes were
removed since a great deal of manual patching would be required to only remove the hwrei change.
 2008-10-20 16:22:59 -04:00
Gabe Black
809f6cb6d1 CPU: Explain why some code is commented out. 2008-10-12 23:52:02 -07:00
Gabe Black
989fa4fc0f X86: Make the MicroPC type 16 bit. 2008-10-12 20:48:24 -07:00
Gabe Black
0756dbb37a X86: Don't fetch in the simple CPU if you're in the ROM. 2008-10-12 19:32:06 -07:00
Gabe Black
f245358343 Get rid of old RegContext code. 2008-10-12 17:57:46 -07:00
Gabe Black
c9ea0b7349 CPU: Make the highest order bit in the micro pc determine if it's combinational or from the ROM. 2008-10-12 16:59:55 -07:00
Gabe Black
2736086d7c CPU: Create a microcode ROM object in the CPU which is defined by the ISA. 2008-10-12 15:59:21 -07:00
Gabe Black
d0a43ce2b2 X86: Fix the ordering of special physical address ranges. 2008-10-12 14:01:06 -07:00
Gabe Black
557bde43c3 X86: Make APICs communicate through the memory system. 2008-10-12 13:28:54 -07:00
Gabe Black
42ebebf99a X86: Make the local APIC accessible through the memory system directly, and make the timer work. 2008-10-12 11:08:00 -07:00
Gabe Black
d9f9c967fb Turn Interrupts objects into SimObjects. Also, move local APIC state into x86's Interrupts object. 2008-10-12 09:09:56 -07:00
Gabe Black
c4f1cc3b48 CPU: Eliminate the get_vec function. 2008-10-12 08:24:09 -07:00
Gabe Black
0c3848732e CPU: Add a getInterruptController function 2008-10-11 16:13:58 -07:00
Gabe Black
f621b7b81f CPU: Eliminate the simPalCheck funciton. 2008-10-11 12:17:24 -07:00
Gabe Black
da7209ec93 CPU: Eliminate the hwrei function. 2008-10-11 02:27:21 -07:00
Nathan Binkert
94b08bed07 SimObjects: Clean up handling of C++ namespaces. 
Make them easier to express by only having the cxx_type parameter which
has the full namespace name, and drop the cxx_namespace thing.
Add support for multiple levels of namespace.
 2008-10-09 22:19:39 -07:00
Nathan Binkert
e06321091d eventq: convert all usage of events to use the new API. 
For now, there is still a single global event queue, but this is
necessary for making the steps towards a parallelized m5.
 2008-10-09 04:58:24 -07:00
Gabe Black
b66eb3b8d1 O3: Generaize the O3 IMPL class so it isn't split out by ISA. 
--HG--
rename : src/cpu/o3/sparc/cpu_builder.cc => src/cpu/o3/cpu_builder.cc
rename : src/cpu/o3/sparc/dyn_inst.cc => src/cpu/o3/dyn_inst.cc
rename : src/cpu/o3/sparc/impl.hh => src/cpu/o3/impl.hh
rename : src/cpu/o3/sparc/thread_context.cc => src/cpu/o3/thread_context.cc
 2008-10-09 00:10:02 -07:00
Gabe Black
f57c286d2c O3: Generaize the O3 dynamic instruction class so it isn't split out by ISA. 
--HG--
rename : src/cpu/o3/dyn_inst.hh => src/cpu/o3/dyn_inst_decl.hh
rename : src/cpu/o3/alpha/dyn_inst_impl.hh => src/cpu/o3/dyn_inst_impl.hh
 2008-10-09 00:09:26 -07:00
Gabe Black
e09c403d32 O3: Generalize the O3 CPU object so it isn't split out by ISA. 2008-10-09 00:08:50 -07:00
Gabe Black
c5c6ad7ed6 CPU: Fix where setMicroPC was being called instead of setNextMicroPC. 2008-10-09 00:06:05 -07:00
Nathan Binkert
80d9be86e6 gcc: Add extra parens to quell warnings. 
Even though we're not incorrect about operator precedence, let's add
some parens in some particularly confusing places to placate GCC 4.3
so that we don't have to turn the warning off.  Agreed that this is a
bit of a pain for those users who get the order of operations correct,
but it is likely to prevent bugs in certain cases.
 2008-09-27 21:03:49 -07:00
Kevin Lim
b784903207 O3CPU: Fix thread writeback logic. 
Fix the logic in the LSQ that determines if there are any stores to
write back. In the commit stage, check for thread specific writebacks
instead of just any writeback.
 2008-09-26 07:44:07 -07:00
Kevin Lim
712a8ee700 O3CPU: Add a hack to ensure that nextPC is set correctly after syscalls. 
Just check CPU's nextPC before and after syscall and if it changes,
update this instruction's nextPC because the syscall must have changed
the nextPC.
 2008-09-26 07:44:06 -07:00
Nathan Binkert
6efb930e19 gcc: Version 4.3 is pretty anal about shadowing types, placate it. 
In the future, it would be nice to put the O3CPU into its own
namespace so that we don't end up hardcoding pointers to the global
namespace.
 2008-09-22 08:25:57 -07:00
Ali Saidi
3a3e356f4e style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs 2008-09-10 14:26:15 -04:00
Gabe Black
3633a916c2 CPU: Get rid of two more duplicated CPU params. 2008-08-19 21:59:09 -07:00
Richard Strong
8d018aef0f Changed BaseCPU::ProfileEvent's interval member to be of type Tick. This was done to be consistent with its 
python type of a latency.  In addition, the multiple definitions of profile in the different cpu models caused
problems for intialization of the interval value. If a child class's profile value was defined, the parent
BaseCPU::ProfileEvent interval field would be initialized with a garbage value. The fix was to remove the
multiple redifitions of profile in the child CPU classes.
 2008-08-18 10:50:58 -07:00
Nathan Binkert
ee62a0fec8 params: Convert the CPU objects to use the auto generated param structs. 
A whole bunch of stuff has been converted to use the new params stuff, but
the CPU wasn't one of them.  While we're at it, make some things a bit
more stylish. Most of the work was done by Gabe, I just cleaned stuff up
a bit more at the end.
 2008-08-11 12:22:16 -07:00
Nathan Binkert
50ef39af82 sockets: Add a function to disable all listening sockets. 
When invoking several copies of m5 on the same machine at the same
time, there can be a race for TCP ports for the terminal connections
or remote gdb.  Expose a function to disable those ports, and have the
regression scripts disable them.  There are some SimObjects that have
no other function than to be used with ports (NativeTrace and
EtherTap), so they will panic if the ports are disabled.
 2008-08-03 18:19:55 -07:00
Steve Reinhardt
8e7ddce284 Use ReadResp instead of LoadLockedResp for LoadLockedReq responses. 2008-07-15 14:38:51 -04:00
Ali Saidi
a4a7a09e96 Remove delVirtPort() and make getVirtPort() only return cached version. 2008-07-01 10:25:07 -04:00
Ali Saidi
50e3e50e1a Make the cached virtPort have a thread context so it can do everything that a newly created one can. 2008-07-01 10:24:16 -04:00
Ali Saidi
9bd0bfe559 After a checkpoint (and thus a stats reset), the not_idle_fraction/notIdleFraction statistic is really wrong. 
The notIdleFraction statistic isn't updated when the statistics reset, probably because the cpu Status information
was pulled into the atomic and timing cpus. This changeset pulls Status back into the BaseSimpleCPU object. Anyone
care to comment on the odd naming of the Status instance? It shouldn't just be status because that is confusing
with Port::Status, but _status seems a bit strage too.
 2008-07-01 10:24:09 -04:00
Steve Reinhardt
caaac16803 Backed out changeset 94a7bb476fca: caused memory leak. 2008-06-28 13:19:38 -04:00
Steve Reinhardt
6b45238316 Generate more useful error messages for unconnected ports. 
Force all non-default ports to provide a name and an
owner in the constructor.
 2008-06-21 01:04:43 -04:00
Nathan Binkert
67a33eed40 AtomicSimpleCPU: Separate data stalls from instruction stalls. 
Separate simulation of icache stalls and dat stalls.
 2008-06-18 10:15:21 -07:00
Nathan Binkert
163465ac08 ThreadState: Ensure that kernelStats is properly initialized 2008-06-17 21:11:20 -07:00
Nathan Binkert
e3c267a3db port: Clean up default port setup and port switchover code. 2008-06-15 21:34:32 -07:00
Gabe Black
d093fcb079 CPU: Make the simple cpu trace data for loads/stores. 2008-06-12 00:35:50 -04:00
Ali Saidi
8af6dc118c SCons: add comments to SConscript documenting bug workaround 
--HG--
extra : convert_revision : e6cdffe953d56b96c76c7ff14d2dcc3de3ccfcc3
 2008-04-10 15:38:10 -04:00
Ali Saidi
ed27c4c521 SCons: Manually specifying header only directories with Dir() works around the problem 
--HG--
extra : convert_revision : d9713228d934cf4a45114a972603b8bca2bd27d3
 2008-04-08 11:08:26 -04:00
Steve Reinhardt
93ab43288a Don't FastAlloc MSHRs since we don't allocate them on the fly. 
--HG--
extra : convert_revision : 02775cfb460afe6df0df0938c62cccd93a71e775
 2008-03-24 01:08:02 -04:00
Vilas Sridharan
21fd15ad9a O3CPU: Don't call dumpInsts if DEBUG is not defined 
--HG--
extra : convert_revision : 3194bde4c624d118969bfbf92282539963a72245
 2008-03-06 00:27:09 -05:00
Korey Sewell
8fb74c238c Add comments in code to describe bug conditions. 
This should help if somebody gets to the bug
fix before me (or someone else)...

--HG--
extra : convert_revision : 0ae64c58ef4f7b02996f31e9e9e6bfad344719e2
 2008-02-27 17:50:29 -05:00
Korey Sewell
b45cf21a8e Fix Load/Store Queue squashing after a SMT thread is removed but ensuring 
you are squashing from the current instruction # causing the thread exit.

--HG--
extra : convert_revision : ccbeece7dd1d5fee43f30ab19370908972113473
 2008-02-27 16:53:08 -05:00
Korey Sewell
34715cc691 Fix offset in removeThread() function so that float registers start freeing up 
from the right point (#32 usually) instead of restarting at 0 and double-freeing.

Commented out assert line in free_list.hh that will check for when double-free condition
goes bad.

--HG--
extra : convert_revision : 08d5f9b6a874736e487d101e85c22aaa67bf59ae
 2008-02-27 16:48:33 -05:00
Gabe Black
8b4796a367 TLB: Make a TLB base class and put a virtual demapPage function in it. 
--HG--
extra : convert_revision : cc0e62a5a337fd5bf332ad33bed61c0d505a936f
 2008-02-26 23:38:51 -05:00
Ali Saidi
9faec83ac5 CPU: move the PC Events code to a place where the code won't be executed multiple times if an instruction faults. 
--HG--
extra : convert_revision : 19c8e46a4eea206517be7ed4131ab9df0fe00e68
 2008-02-14 16:14:35 -05:00
Steve Reinhardt
9d7a69c582 Fix #include lines for renamed cache files. 
--HG--
extra : convert_revision : b5008115dc5b34958246608757e69a3fa43b85c5
 2008-02-10 14:45:25 -08:00
Stephen Hines
6cc1573923 Make the Event::description() a const function 
--HG--
extra : convert_revision : c7768d54d3f78685e93920069f5485083ca989c0
 2008-02-06 16:32:40 -05:00
Stephen Hines
0ccf9a2c37 Add base ARM code to M5 
--HG--
extra : convert_revision : d811bf87d1a0bfc712942ecd3db1b48fc75257af
 2008-02-05 23:44:13 -05:00
Ke Meng
0b6876a0c0 The reason is that the event is supposed to put the instructions ready to execute for next cycle. And the FUCompletion event has a lower priority than CPU tick event. It is called after the iew->tick() for current cycle has already been executed and the issueToExecuteQueue has already advanced this time. And assume the issueToExecuteLatency is 1, to catch up, the increasement should be made at access(-1) instead of access(0). Otherwise I found it could increase the actual op_latency of the instructions to execute by 1 cycle and potentially put the simulated CPU into a permanent idle state. 
Signed-off by: Ali Saidi <saidi@eecs.umich.edu>

--HG--
extra : convert_revision : dafc16814383e8e8f8320845edf6ab2bcfed1e1d
 2008-01-14 11:47:32 -05:00
Steve Reinhardt
6c5a3ab8b2 Add ReadRespWithInvalidate to handle multi-level coherence situation 
where we defer a response to a read from a far-away cache A, then later
defer a ReadExcl from a cache B on the same bus as us.  We'll assert
MemInhibit in both cases, but in the latter case MemInhibit will keep
the invalidation from reaching cache A.  This special response tells
cache A that it gets the block to satisfy its read, but must immediately
invalidate it.

--HG--
extra : convert_revision : f85c8b47bb30232da37ac861b50a6539dc81161b
 2008-01-02 15:22:38 -08:00
Steve Reinhardt
cde5a79eab Additional comments and helper functions for PrintReq. 
--HG--
extra : convert_revision : 7eadf9b7db8c0289480f771271b6efe2400006d4
 2008-01-02 13:46:22 -08:00
Steve Reinhardt
3952e41ab1 Add functional PrintReq command for memory-system debugging. 
--HG--
extra : convert_revision : 73b753e57c355b7e6873f047ddc8cb371c3136b7
 2008-01-02 12:20:15 -08:00
Ali Saidi
45ea1549c9 Checkpointing: Fix a bug in the simulation script when restoring without standard switch and change some ifs to work with the default port since every port is now connected to something. 
--HG--
extra : convert_revision : 72507cf13e58465291b0dce6322e853bee5a2b89
 2007-12-18 01:52:57 -05:00
Ali Saidi
71909a50de CPU: Update where the simple cpus read their cpu id from the thread context to init() to make sure they read the right value. This fixes a bug with multi-processor full-system configurations. 
--HG--
extra : convert_revision : 4f2801967a271b43817d88e147c2f80c4480b2c3
 2007-12-16 03:48:13 -05:00
Gabe Black
ab598eadbf imported patch pagewalker.patch 
--HG--
extra : convert_revision : 8ddde313f2249e1346fa51372a156f0d2ddc3b8f
 2007-11-21 00:04:15 -08:00
Gabe Black
a12d5975cc Simple CPU fix simple mistake in translateDataWriteAddr. 
--HG--
extra : convert_revision : 6a6a7d05f62d9d9868be0707e4dc186a5f7ecf7d
 2007-11-20 15:37:56 -08:00
Korey Sewell
d09ab2bd22 add thread id to misc. reg functions 
--HG--
extra : convert_revision : 35d073d1279947d943a0290832e09a5268dd0b76
 2007-11-15 20:35:49 -05:00
Korey Sewell
7c076479e4 add MicroPC functions back to thread context 
--HG--
extra : convert_revision : a9cfd2829c4aec191f5f9ec6ce7b5d1dccc92af1
 2007-11-15 20:35:31 -05:00
Korey Sewell
cf9dc4b151 add microPC stuff back in. got deleted on changeset propragation somehow. 
--HG--
extra : convert_revision : 5e89484b2ef21457ffba35ef959df999a28c5676
 2007-11-15 19:48:53 -05:00
Korey Sewell
8f8e7fe08e put the flattenIndex stuff back in O3 AND put fatal() back in faults 
--HG--
extra : convert_revision : 16fb8d7f3fbc5f8f1fc3ed34427c3d90a3125ad0
 2007-11-15 16:38:09 -05:00
Korey Sewell
641ee83e40 add core specific parameter to BaseCPU params 
--HG--
extra : convert_revision : 15c5995e3acf23a45c712891fd06ef273584f7e8
 2007-11-15 14:18:56 -05:00
Korey Sewell
789153dff6 Get MIPS simple regression working. Take out unecessary functions "setShadowSet", "CacheOp" 
--HG--
extra : convert_revision : a9ae8a7e62c27c2db16fd3cfa7a7f0bf5f0bf8ea
 2007-11-15 03:10:41 -05:00
Korey Sewell
375ddf8d25 branch merge 
--HG--
extra : convert_revision : 1c56f3c6f2c50d642d2de5ddde83a55234455cec
 2007-11-15 00:14:20 -05:00
Korey Sewell
2692590049 Add in files from merge-bare-iron, get them compiling in FS and SE mode 
--HG--
extra : convert_revision : d4e19afda897bc3797868b40469ce2ec7ec7d251
 2007-11-13 16:58:16 -05:00
Gabe Black
1048b548fa X86: Separate out the page table walker into it's own cc and hh. 
--HG--
extra : convert_revision : cbc3af01ca3dc911a59224a574007c5c0bcf6042
 2007-11-12 18:06:57 -08:00
Gabe Black
fce45baf17 X86: Work on the page table walker, TLB, and related faults. 
--HG--
extra : convert_revision : 9edde958b7e571c07072785f18f9109f73b8059f
 2007-11-12 14:38:31 -08:00
Gabe Black
f17f3d20be X86: Implement a page table walker. 
--HG--
extra : convert_revision : 36bab5750100318faa9ba7178dc2e38590053aec
 2007-11-12 14:38:24 -08:00
Gabe Black
7a39457d7f X86: Make the micropc available through the thread context objects. 
This is necssary for fault handlers that branch to non-zero micro PCs.

--HG--
extra : convert_revision : c1cb4863d779a9f4a508d0b450e64fb7a985f264
 2007-11-12 14:38:17 -08:00
Ali Saidi
422ab8bec0 TimingSimpleCPU: Add some DPRINTFs when the cpu suspends and resumes. 
--HG--
extra : convert_revision : a305cf9dcaca5ed3b97499a5e24c511f4416125a
 2007-11-08 10:46:41 -05:00
Ali Saidi
cf1c25dbcc AtomicSimpleCPU: Refactor resume() code to have a cleaner control path. 
--HG--
extra : convert_revision : f27bb96850e7fb0252fb1f47c3d0860705c32884
 2007-11-08 10:46:41 -05:00
Ali Saidi
11b931df6a Interrupts: Inline some code and remove duplication. 
--HG--
extra : convert_revision : 0631c601f281bdd2a12ff0d0ae94576780115c2a
 2007-11-08 10:46:41 -05:00
Ali Saidi
e41197a3f8 CPU: Add function to explictly compare thread contexts after copying. 
--HG--
extra : convert_revision : 9b7af59a11202a91409aad7c427b7749cd1d2f12
 2007-11-08 10:46:41 -05:00
Gabe Black
19292d3f06 O3: Remove unneeded variable. 
--HG--
extra : convert_revision : 4624ccd3f08818f4632881d6aca6d1cc343bbdcf
 2007-11-06 12:51:08 -08:00
Steve Reinhardt
4b49bd47f4 String constant const-ness changes to placate g++ 4.2. 
Also some bug fixes in MIPS ISA uncovered by g++ warnings
(Python string compares don't work in C++!).

--HG--
extra : convert_revision : b347cc0108f23890e9b73b3ee96059f0cea96cf6
 2007-10-31 18:04:22 -07:00
Ali Saidi
538fae951b Traceflags: Add SCons function to created a traceflag instead of having one file with them all. 
--HG--
extra : convert_revision : 427f6bd8f050861ace3bc0d354a1afa5fc8319e6
 2007-10-31 01:21:54 -04:00
Gabe Black
93da9eb7f6 CPU: Add functions to the "ExecContext"s that translate a given address. 
--HG--
extra : convert_revision : 7d898c6b6b13094fd05326eaa0b095a3ab132397
 2007-10-22 14:30:45 -07:00
Ali Saidi
8351660273 CPU: Use the ThreadContext cpu id instead of the params cpu id in all cases. 
--HG--
extra : convert_revision : 6d025764682181b1f67df3b1d8d1d59099136df7
 2007-10-18 13:15:08 -04:00
Gabe Black
50e2d20cb8 Merge with head. 
--HG--
extra : convert_revision : 1aa0e4569a7c10e6a395c2c951ac29275b5bcf59
 2007-10-02 23:03:38 -07:00
Gabe Black
a56c651980 Predecoder: Clear out predecoder state on an ITLB fault. 
--HG--
extra : convert_revision : 68f8ff778dbd28ade5070edf5a7d662e7bf0045a
 2007-10-02 22:21:38 -07:00
Gabe Black
7571e8346d CPU: Make the cpuid parameter get set in SE mode as well. 
--HG--
extra : convert_revision : bc47206acb683ebaaa31f57af79b4b8db64e4d31
 2007-10-02 18:33:57 -07:00
Gabe Black
988cdb49f2 CPU: Make the cpus check the pc event queues in SE mode. 
--HG--
extra : convert_revision : 9dc4ea136c3c3f87a73d55e91bc4aae4eba70464
 2007-10-02 18:25:37 -07:00
Gabe Black
3eeda8008d CPU: Make sure the system parameter gets set in the cpu builders. Other parameters need to be fixed as well. 
--HG--
extra : convert_revision : 0401970a79855ee0a96eb29305346ce07b5c98ea
 2007-10-02 18:22:36 -07:00
Ali Saidi
0acf891c32 CPU: fix sparc_fs booting with SimpleTimingCPU. 
--HG--
extra : convert_revision : 3d95f6daa7f0e8e376d1a880f64c056619263885
 2007-10-01 02:55:27 -04:00
Ali Saidi
d2a4f595d6 Update stats for quiesced cycles 
--HG--
extra : convert_revision : 703ba58f156c9f2677b020f05d36bc1e3ae0b9e5
 2007-09-28 13:22:14 -04:00
Ali Saidi
d325f49b70 Rename cycles() function to ticks() 
--HG--
extra : convert_revision : 790eddb793d4f5ba35813d001037bd8601bd76a5
 2007-09-28 13:21:52 -04:00
Ali Saidi
887cd6a273 Update statistics to use cycles properly instead of ticks 
--HG--
extra : convert_revision : 62911280b631ef24720f9ce701d1c19a9b8a9784
 2007-09-28 13:21:30 -04:00
Gabe Black
2dd65dc254 Merge with head. 
--HG--
extra : convert_revision : f331b9cbd82086d63d4f35e18f9e08466c016225
 2007-09-25 20:11:41 -07:00
Gabe Black
032a30f345 SPARC: Fix a stupid mistake which was breaking the SPARC regressions. 
--HG--
extra : convert_revision : 34a11df0d467ea249211dd3aba86bc8d2aea45de
 2007-09-25 20:00:46 -07:00
Gabe Black
418ddf43e6 X86: Get X86_FS to compile. 
--HG--
extra : convert_revision : fb973bcf13648876d5691231845dd47a2be50f01
 2007-09-24 17:39:56 -07:00
Gabe Black
f3f3747431 X86: Put in the foundation for x87 stack based fp registers. 
--HG--
extra : convert_revision : 940f92efd4a9dc59106e991cc6d9836861ab69de
 2007-09-19 18:26:42 -07:00
Gabe Black
26044dca33 X86/StateTrace: Make m5 and statetrace track mmx and xmm registers, and actually compare xmm. 
--HG--
extra : convert_revision : 02c6641200edb133c9bc11f1fdf3c1a0b1c87e77
 2007-09-04 23:39:57 -07:00
Gabe Black
941675690c X86: Get x86 to compile again after the simobject constructor change. 
--HG--
extra : convert_revision : 17a3e16e849bee88892223f0c993b19c15daa554
 2007-08-31 13:02:58 -07:00
Miles Kaufmann
e4eea9ee04 Fix miscellaneous small typos. 
--HG--
extra : convert_revision : bfc0ac8e1c8a5d01d9fa5203184bbf99c8361da3
 2007-08-30 15:16:59 -04:00
Miles Kaufmann
54cc0053f0 params: Deprecate old-style constructors; update most SimObject constructors. 
SimObjects not yet updated:
- Process and subclasses
- BaseCPU and subclasses

The SimObject(const std::string &name) constructor was removed.  Subclasses
that still rely on that behavior must call the parent initializer as
  : SimObject(makeParams(name))

--HG--
extra : convert_revision : d6faddde76e7c3361ebdbd0a7b372a40941c12ed
 2007-08-30 15:16:59 -04:00
Gabe Black
7227ab5f22 Merge with head 
--HG--
extra : convert_revision : cc73b9aaf73e9dacf52f3350fa591e67ca4ccee6
 2007-08-26 21:45:40 -07:00
Gabe Black
80d51650c8 O3 CPU: Remove alignment check from dynamic instruction read/write functions. 
--HG--
extra : convert_revision : e5d415b4bf79353ef3c9f4dc5af09ab4102c55fb
 2007-08-26 20:31:30 -07:00
Gabe Black
24bfda0fdf Simple CPU: Don't trace instructions that fault. Otherwise they show up twice. 
--HG--
extra : convert_revision : 4446d9544d58bdadbd24d8322bb63016a32aa2b8
 2007-08-26 20:29:09 -07:00
Gabe Black
e7e2d5ce90 Simple CPU: Added code that will split requests that cross block boundaries into multiple memory access. 
--HG--
extra : convert_revision : 600f79f32ef30a6e1db951503bcfe8cd332858d1
 2007-08-26 20:27:11 -07:00
Gabe Black
e056e49c45 Simple CPU: Make sure only instructions which complete without faulting are counted. 
--HG--
extra : convert_revision : 01019c7129ed762d8826c3e6519989aa3fc3b5fd
 2007-08-26 20:25:42 -07:00
Gabe Black
537239b278 Address Translation: Make SE mode use an actual TLB/MMU for translation like FS. 
--HG--
extra : convert_revision : a04a30df0b6246e877a1cea35420dbac94b506b1
 2007-08-26 20:24:18 -07:00
Gabe Black
20e0a3792a Merge with head. 
--HG--
extra : convert_revision : 9ef81afcfabd86c9c069204998c987344f03f33e
 2007-08-21 16:19:46 -07:00
Kevin Lim
e1054170b5 o3: Fix for retry ID bug. 
It should be cleared prior to the call to recvRetry.
Add extra DPRINTF statement for clearer debugging output.

--HG--
extra : convert_revision : e2332754743f42d60e159ac89f6fb0fd8b7f57f8
 2007-08-21 16:16:56 -07:00
Gabe Black
92a57edff1 O3: Set up the predicted npc and nnpc for a fault carrying noop so that it doesn't cause a false branch mispredict. 
--HG--
extra : convert_revision : 2820597cc966cd7b128cef0dab48fe05089533d7
 2007-08-13 16:08:58 -07:00
Gabe Black
82f78ebd39 Move the "translate" member functions back into the base o3 class. 
--HG--
extra : convert_revision : 3c480537bf38f74f0f1d72e75c70aa46ba91b759
 2007-08-13 16:01:09 -07:00
Vincentius Robby
ec4000e0e2 Added fastmem option. 
Lets CPU accesses to physical memory bypass Bus.

--HG--
extra : convert_revision : e56e3879de47ee10951a19bfcd8b62b6acdfb30c
 2007-08-08 18:43:12 -04:00
Vincentius Robby
3d40cba8d4 Port, StaticInst: Revert unnecessary changes. 
--HG--
extra : convert_revision : e6ef262bbbc5ad53498e55caac1897e6cc2a61e6
 2007-08-08 14:54:02 -04:00
Vincentius Robby
13d10e844c alpha: Make the TLB cache to actually work. 
Improve MRU checking for StaticInst, Bus, TLB

--HG--
extra : convert_revision : 9116b5655cd2986aeb4205438aad4a0f5a440006
 2007-08-08 14:18:09 -04:00
Gabe Black
0fd999ca40 Merge with head. 
--HG--
extra : convert_revision : ae7b3df573368c29a66d5b027ecad9ffb3a99104
 2007-08-07 15:31:36 -07:00
Gabe Black
fb6cdf09cb X86: Make a microcode branch microop. 
Also some touch up for ruflag.

--HG--
extra : convert_revision : 829947169af25ca6573f53b9430707101c75cc23
 2007-08-07 15:19:26 -07:00
Nathan Binkert
df015f17a4 switching: turn on profiling after a switch if there's an event 
--HG--
extra : convert_revision : 689e5b85c47bb2aaceb7eb38c2a24a2e5b69376c
 2007-08-04 16:11:11 -07:00
Nathan Binkert
e8e1ddd530 SimpleCPU: Add some DPRINTFs 
--HG--
extra : convert_revision : 5fdd5a9595c3e5d6ce5f9e8c9af0a8e6c857551c
 2007-08-04 15:56:48 -07:00
Vincentius Robby
acac5580f2 StaticInst: Fix decode cache initialization. Cache functionality was negated. 
--HG--
extra : convert_revision : fe313718dba8236f3e9bceb49f8c5efccfc06a06
 2007-08-04 14:25:17 -04:00
Gabe Black
8da3e0548e Merge with head. 
--HG--
extra : convert_revision : 444901221e9a0b991213fbcd555f2f5cca67e91b
 2007-08-01 15:12:07 -07:00
Gabe Black
e42524af02 X86: Reorganize the native tracing code. 
Ignore different values or rcx and r11 after a syscall until either the local or remote value changes. Also change the codes organization somewhat.

--HG--
extra : convert_revision : 2c1f69d4e55b443e68bfc7b43e8387b02cf0b6b5
 2007-08-01 12:01:51 -07:00
Gabe Black
4bdabe1254 Add a flag to indicate an instruction triggers a syscall in SE mode. 
--HG--
extra : convert_revision : 1d0b3afdd8254f5b2fb4bbff1fa4a0536f78bb06
 2007-07-31 17:34:08 -07:00
Steve Reinhardt
c4c8a12186 Merge from head. 
--HG--
extra : convert_revision : af16bc685ea28e44b8120f16b72f60a21d68c1e2
 2007-07-31 00:37:07 -04:00
Gabe Black
24ac08daa4 Fix problem with tracer not being initialized. 
--HG--
extra : convert_revision : 09610ad84afa605db2d0eab9945eb9809f297182
 2007-07-30 13:13:11 -07:00
Steve Reinhardt
08474ccf68 Merge Gabe's changes from head. 
--HG--
extra : convert_revision : d00b7b09c7f19bc0e37b385ef7c124f69c0e917f
 2007-07-29 13:25:14 -07:00
Steve Reinhardt
362ff1bceb BsaeCPU: Get rid of some bad DPRINTFs. 
People should never put pointers in DPRINTFs; it messes up
tracediffs.  Plus these used the FullCPU trace flag, which
is not right.

--HG--
extra : convert_revision : 82ed56757da0ad947c165ba205b5f752c85c6667
 2007-07-29 13:22:44 -07:00
Gabe Black
b6395da4ce X86: Fix register ordering. 
The correct order is unintuitively rax, rcx, rdx, rbx, etc, not rax, rbx, rcx, rdx.

--HG--
extra : convert_revision : 3abe6a723a6e30becfe34f8da707ea2ff5d4df77
 2007-07-29 01:28:36 -07:00
Gabe Black
8dd7700482 Turn the instruction tracing code into pluggable sim objects. 
These need to be refined a little still and given parameters.

--HG--
extra : convert_revision : 9a8f5a7bd9dacbebbbd2c235cd890c49a81040d7
 2007-07-28 20:30:43 -07:00
Steve Reinhardt
aaf59949e5 AtomicSimpleCPU: fix inadvertent loss of endian conversion on read. 
--HG--
extra : convert_revision : 367bf2431bf4f4eb7c4d5723816e5db6f7233aed
 2007-07-28 18:00:05 -07:00
Steve Reinhardt
0cbcb715e0 cache/memtest: fixes for functional accesses. 
--HG--
extra : convert_revision : 688ba4d882cad2c96cf44c9e46999f74266e02ee
 2007-07-27 12:46:45 -07:00
Nathan Binkert
f0fef8f850 Merge python and x86 changes with cache branch 
--HG--
extra : convert_revision : e06a950964286604274fba81dcca362d75847233
 2007-07-26 23:15:49 -07:00
Gabe Black
d1e533a1e2 X86: Fix argument register indexing. 
Code was assuming that all argument registers followed in order from ArgumentReg0. There is now an ArgumentReg array which is indexed to find the right index. There is a constant, NumArgumentRegs, which can be used to protect against using an invalid ArgumentReg.

--HG--
extra : convert_revision : f448a3ca4d6adc3fc3323562870f70eec05a8a1f
 2007-07-26 22:13:14 -07:00
Nathan Binkert
abc76f20cb Major changes to how SimObjects are created and initialized. Almost all 
creation and initialization now happens in python.  Parameter objects
are generated and initialized by python.  The .ini file is now solely for
debugging purposes and is not used in construction of the objects in any
way.

--HG--
extra : convert_revision : 7e722873e417cb3d696f2e34c35ff488b7bff4ed
 2007-07-23 21:51:38 -07:00
Steve Reinhardt
97f7ee2e50 Fix WriteReq/StoreCondReq setting in O3. 
--HG--
extra : convert_revision : b41571535f3d1f78df3cb6e48c16de5c7549d87f
 2007-07-23 08:18:51 -07:00
Steve Reinhardt
f67c8b33cc Fix bug with timing snoop upcalls to MemTest object. 
--HG--
extra : convert_revision : 1940a5d231b4f856cf69578f68ea98435824dbd8
 2007-07-15 21:03:12 -07:00
Steve Reinhardt
884807a68a Fix up a bunch of multilevel coherence issues. 
Atomic mode seems to work.  Timing is closer but not there yet.

--HG--
extra : convert_revision : 0dea5c3d4b973d009e9d4a4c21b9cad15961d56f
 2007-07-15 20:11:06 -07:00
Steve Reinhardt
9172876dd7 Fix problem with unset max_loads in memtest. 
Also make default 0, and make that mean run forever.

--HG--
extra : convert_revision : 3e60a52b1c5e334a9ef3d744cf7ee1d851ba4aa9
 2007-07-15 14:32:55 -07:00
Steve Reinhardt
4b68652c87 Couple more minor bug fixes for FS timing mode. 
src/cpu/simple/timing.cc:
    Fix another SC problem.
src/mem/cache/cache_impl.hh:
    Forgot to call makeTimingResponse() on uncached timing responses.

--HG--
extra : convert_revision : 5a5a58ca2053e4e8de2133205bfd37de15eb4209
 2007-07-02 13:57:45 -07:00
Steve Reinhardt
e9c04dad60 Fix a couple LL/SC bugs that only affected timing mode. 
src/cpu/simple/timing.cc:
    Fix swap/stq_c command bug.
src/mem/packet.cc:
    Fix incorrect LoadLockedReq command response field.

--HG--
extra : convert_revision : 7a4523be900bc2c9b1bdf2d372ce55f89ae58ae5
 2007-07-02 09:26:36 -07:00
Steve Reinhardt
3ad761bc8e Make CPU models use new LoadLockedReq/StoreCondReq commands. 
--HG--
extra : convert_revision : ab78d9d1d88c3698edfd653d71c8882e1272b781
 2007-06-30 20:35:42 -07:00
Steve Reinhardt
ee54ad318a Event descriptions should not end in "event" 
(they function as adjectives not nouns)

--HG--
extra : convert_revision : 6506474ff3356ae8c80ed276c3608d8a4680bfdb
 2007-06-30 17:45:58 -07:00
Steve Reinhardt
6ab53415ef Get rid of Packet result field. Error responses are 
now encoded in cmd field.

--HG--
extra : convert_revision : d67819b7e3ee4b9a5bf08541104de0a89485e90b
 2007-06-30 10:16:18 -07:00
Steve Reinhardt
7f3dfa7c09 Merge vm1.(none):/home/stever/bk/newmem-head 
into  vm1.(none):/home/stever/bk/newmem-cache2

--HG--
extra : convert_revision : b1c954c187e3b3172a194396ba63808253121195
 2007-06-28 08:28:58 -07:00
Korey Sewell
e28cbc98a0 o3cpu build for mips 
--HG--
extra : convert_revision : 2c0be7a8c0a54ba5b1b2b69468f788d20abc8452
 2007-06-28 05:30:46 -04:00
Steve Reinhardt
245b0bd9b9 Merge vm1.(none):/home/stever/bk/newmem-head 
into  vm1.(none):/home/stever/bk/newmem-cache2

src/base/traceflags.py:
    Hand merge.

--HG--
extra : convert_revision : 9e7539eeab4220ed7a7237457a8f336f79216924
 2007-06-23 13:26:30 -07:00
Steve Reinhardt
57ff2604e5 Minor fix plus new assertion to catch similar bugs. 
src/cpu/memtest/memtest.cc:
    Need to set packet source field so that response from cache
    doesn't run into assertion failure when copying source to dest.
src/mem/packet.hh:
    Copy source field when copying packets.
    Assert that source is valid before copying it to dest
    when turning packets around.

--HG--
extra : convert_revision : 09e3cfda424aa89fe170e21e955b295746832bf8
 2007-06-23 13:24:33 -07:00
Steve Reinhardt
ed1db23b41 Merge vm1.(none):/home/stever/bk/newmem-head 
into  vm1.(none):/home/stever/bk/newmem-cache2

--HG--
extra : convert_revision : aa50af3094f5d459f75b514179b6e3ec5e0bf1df
 2007-06-22 16:13:53 -07:00
Korey Sewell
753adb38d5 mips import pt. 1 
src/arch/mips/SConscript:
    "mips import pt.1".

--HG--
extra : convert_revision : 2e393341938bebf32fb638a209262d074fad4cc1
 2007-06-22 19:03:42 -04:00
Gabe Black
49490b334a Merge zizzer.eecs.umich.edu:/bk/newmem 
into  ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-o3-micro

src/cpu/o3/fetch_impl.hh:
    hand merge

--HG--
extra : convert_revision : 3f71f3ac2035eec8b6f7bceb6906edb4dd09c045
 2007-06-21 20:35:25 +00:00