arch/alpha/alpha_memory.cc:
cpu/base_dyn_inst.cc:
dev/alpha_console.cc:
dev/pcidev.hh:
dev/sinic.cc:
MachineCheckFaults are now generated by the ISA, rather than being created directly.
--HG--
extra : convert_revision : 34a7da41639e93be21ed70dac681b27480008d19
CPU_MODELS parameter changes.
arch/SConscript:
Fix typo in comment.
cpu/SConscript:
Convert exec signature generator to Action so we can add dependency
on CPU_MODELS environment var.
Print nicer string while we're at it.
Also add some comments.
--HG--
extra : convert_revision : bcb38a7941943cf071dac34cdbb2ece5456b8620
into ewok.(none):/home/gblack/m5/multiarch
SConscript:
arch/alpha/ev5.cc:
dev/alpha_console.cc:
Hand merged
--HG--
extra : convert_revision : 318a671e6803400d3ed086a90e70d6790e4f6b19
arch/alpha/alpha_memory.cc:
arch/alpha/isa/decoder.isa:
Added news where faults are created.
arch/alpha/ev5.cc:
Changed places where a fault was compared to a fault type to use isA rather than ==
arch/alpha/faults.cc:
arch/alpha/faults.hh:
Changed Fault to be a RefCountingPtr
arch/alpha/isa/fp.isa:
Added a new where a FloatEnableFault was created.
arch/alpha/isa/unimp.isa:
arch/alpha/isa/unknown.isa:
Added a new where an UnimplementedFault is created.
base/refcnt.hh:
Added include of stddef.h for the NULL macro
cpu/base_dyn_inst.cc:
Added a new where an UnimplementedOpcodeFault is created.
cpu/o3/alpha_cpu_impl.hh:
Changed places where a fault was compared to a fault type to use isA rather than ==. Also changed fault->name to fault->name()
cpu/o3/regfile.hh:
Added new where UnimplementedOpcodeFaults are created.
cpu/simple/cpu.cc:
Changed places where a fault was compared to a fault type to use isA rather than ==. Also added a new where an Interrupt fault is created.
dev/alpha_console.cc:
Added news where MachineCheckFaults are created.
dev/pcidev.hh:
Added news where MachineCheckFaults are generated.
dev/sinic.cc:
Changed places where a fault was compared to a fault type to use isA rather than ==. Added news where MachineCheckFaults are created. Fixed a problem where m5.fast had unused variables.
kern/kernel_stats.cc:
Commented out where _faults is initialized. This statistic will probably be moved elsewhere in the future.
kern/kernel_stats.hh:
Commented out the declaration of _fault. when fault() is called, the fault increments its own stat.
sim/faults.cc:
sim/faults.hh:
Changed Fault from a FaultBase * to a RefCountingPtr.
--HG--
extra : convert_revision : b40ccfc42482d5a115e111dd897fa378d23c6c7d
CPU_MODELS parameter. For example:
scons CPU_MODELS="SimpleCPU,FullCPU" ALPHA_SE/m5.debug
Unfortunately the option is not sticky due to a scons
bug with saving & restoring ListOption parameters.
SConscript:
Separate out cpu-model-specific files so they can be conditionally
included based on value of new CPU_MODELS parameter.
Most of these are now handled in cpu/SConscript, except for FullCPU
which is still in this file.
arch/SConscript:
The set of CPU-model-specific execute files must now be
determined from the CPU_MODELS parameter, via the new
cpu_models.py file.
Also pass the list of configured CPU models to isa_parser.py.
arch/isa_parser.py:
Move CpuModel definition and objects out to a
separate file so they can be shared with scons.
Global list of CPU models to generate code for is now
controlled by command-line parameters (so we can do
only a subset of the available ones).
build/SConstruct:
Define new CPU_MODELS ListOption.
cpu/static_inst.hh:
Rename static_inst_impl.hh to static_inst_exec_sigs.hh.
--HG--
extra : convert_revision : 163df32a76d4c05900490b2bce4c7962a5e3f614
into zeep.eecs.umich.edu:/z/saidi/work/m5.head
cpu/simple/cpu.cc:
remove initCPU from constructor
dev/alpha_console.cc:
we are panicing, so no need to return a fault
--HG--
extra : convert_revision : 72389ea0c96e91a55f35b884200325224bfb6ed9
Now allocate an array of stacks indexed by cpu number which specify
cpu stacks and are initialized by cpu 0. Othe cpus spin waiting for
their stacks before continuing. This change *REQUIRES* a the new
console code to operate correctly.
arch/alpha/ev5.cc:
Add cpuId to initCPU/initIPR functions
cpu/o3/cpu.cc:
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
Move the cpu initilization into an init() function since it now needs
the CPU id which isn't known at construction
dev/alpha_access.h:
dev/alpha_console.cc:
dev/alpha_console.hh:
instead of the bootstrap variables, add space for 64 cpu stacks in the
alpha access structure.
sim/system.cc:
start all cpus immediately rather than just the first one
--HG--
extra : convert_revision : 28c218af49d885a0f203ada419f16f25d5a3f37b
Start using SCons File objects to avoid fixed paths in
subordinate SConscripts.
SConscript:
Push isa_parser stuff (including .isa scanner) down into
arch/SConscript.
arch/SConscript:
Create a Builder object for .isa files, including existing scanner.
Return file objects generated by isa-specific SConscript
back up to parent.
arch/alpha/SConscript:
arch/mips/SConscript:
arch/sparc/SConscript:
Convert sources to scons File objects, so file names can be specified
relative to the current directory.
Invoke new builder for isa description, and get generated sources from
there (instead of listing them explicitly).
arch/isa_parser.py:
Get rid of third argument ("include_path").
It was a pain to generate this from scons, and it turned out
it's not needed anyway, since the only included file
(decoder.hh) will be in the same directory as the sources.
--HG--
extra : convert_revision : 36861bcef36763f229704d8cb7a642b4486a3581
SConscript:
Include new arch/SConscript file.
arch/isa_specific.hh:
Get rid of unnecessary ISA_INCLUDE() macro and other
things that were used only for that purpose.
build/SConstruct:
Move list of ISAs to env var ALL_ISA_LIST.
--HG--
extra : convert_revision : 612c7ee4279d57209662be88dc577d80fdbd692c
Now that we have decoder.do, add new files so we can start compiling other files
needed for MIPS syscall emulation mode
arch/mips/linux_process.cc:
arch/mips/linux_process.hh:
New MIPS-specific file
--HG--
rename : arch/alpha/linux_process.cc => arch/alpha/alpha_linux_process.cc
rename : arch/alpha/linux_process.hh => arch/alpha/alpha_linux_process.hh
rename : arch/alpha/tru64_process.cc => arch/alpha/alpha_tru64_process.cc
rename : arch/alpha/tru64_process.hh => arch/alpha/alpha_tru64_process.hh
extra : convert_revision : 2bfc27e8772523cbeb95f40684f9a32fe5554f87
-----
uncomment out detailed model ... just commented to supress some compile errors
arch/isa_parser.py:
uncomment out detailed model ... just commented to supress some compile errors
--HG--
extra : convert_revision : e884b9bd47794409f74043ad1aca6dadd1323185
Other compile issues cleaned up.
SConscript:
Changes to compile the new Translating Port.
Split out memtester and eio support, will rework them back in after first getting a simpleCPU to work
arch/alpha/alpha_linux_process.cc:
arch/alpha/alpha_tru64_process.cc:
sim/syscall_emul.cc:
sim/syscall_emul.hh:
Changes to use the new translating Port.
cpu/exec_context.cc:
cpu/exec_context.hh:
Create a translating port in each execution context.
sim/process.cc:
Fix the way we do proxy memory
--HG--
extra : convert_revision : 3d33218fe8b425a5d9ce24757f1112b4aa6001fd
and breaks it into a separate EA and MemAccess templated
from how the Alpha ARch. was coded to do the same thing.
arch/mips/isa/bitfields.isa:
comment change
arch/mips/isa/decoder.isa:
re-structuring of load/store instruction definitions
arch/mips/isa/formats/mem.isa:
Define LoadMemory & Store Memory formats
Use style of formatting & base class similar to what was used for ALPHA
arch/mips/isa/formats/util.isa:
Insert LoadStoreBase function here from alpha/arch/isa/mem.isa
arch/mips/isa/operands.isa:
change shw->sh and uhw->uh
--HG--
extra : convert_revision : 5d85f15f4a600dd4c473a3b4a170ba39cf07fc8a
Redo format for Branches and Jumps ( Must update NNPC not NPC )
Now all branches and jumps look like they auto-generate correctly from isa_parser.py!!!
arch/mips/isa/decoder.isa:
Support for All Jump Instructions ..
arch/mips/isa/formats/branch.isa:
Redo format for Branches and Jumps ( Must update NNPC not NPC )
arch/mips/isa/formats/util.isa:
define clear_exe_inst_hazards for later use
--HG--
extra : convert_revision : 63618ed12ee6ed94c47d29619cc1cab2cbaf5cda
into zizzer.eecs.umich.edu:/z/m5/Bitkeeper/multiarch
arch/alpha/faults.hh:
ur
Using cleaned up fault class deiffinitions
--HG--
extra : convert_revision : a600950d539be2be73358f072aa5426456bf3d2d
arch/alpha/alpha_linux_process.cc:
Added using directive for AlphaISA namespace
arch/alpha/alpha_memory.hh:
arch/alpha/isa/branch.isa:
cpu/pc_event.hh:
Added typedefs for Addr
arch/alpha/alpha_tru64_process.cc:
arch/alpha/arguments.cc:
Added using directive for AlphaISA
arch/alpha/ev5.hh:
Added an include of arch/alpha/isa_traits.hh, and a using directive for the AlphaISA namespace.
arch/alpha/faults.hh:
Added a typedef for the Addr type, and changed the formatting of the faults slightly.
arch/alpha/isa/main.isa:
Untemplatized StaticInst, added a using for namespace AlphaISA to show up in decoder.cc and the exec.ccs, relocated makeNop to decoder.hh
arch/alpha/isa/mem.isa:
Untemplatized StaticInst and StaticInstPtr
arch/alpha/isa/pal.isa:
cpu/base_dyn_inst.cc:
Untemplatized StaticInstPtr
arch/alpha/isa_traits.hh:
Changed variables to be externs instead of static since they are part of a namespace and not a class.
arch/alpha/stacktrace.cc:
Untemplatized StaticInstPtr, and added a using directive for AlphaISA.
arch/alpha/stacktrace.hh:
Added some typedefs for Addr and MachInst, and untemplatized StaticInstPtr
arch/alpha/vtophys.cc:
Added a using directive for AlphaISA
arch/alpha/vtophys.hh:
Added the AlphaISA namespace specifier where needed
arch/isa_parser.py:
Changed the placement of the definition of the decodeInst function to be outside the namespaceInst namespace.
base/loader/object_file.hh:
cpu/o3/bpred_unit.hh:
Added a typedef for Addr
base/loader/symtab.hh:
Added a typedef for Addr, and added a TheISA to Addr in another typedef
base/remote_gdb.cc:
Added a using namespace TheISA, and untemplatized StaticInstPtr
base/remote_gdb.hh:
Added typedefs for Addr and MachInst
cpu/base.cc:
Added TheISA specifier to some variables exported from the isa.
cpu/base.hh:
Added a typedef for Addr, and TheISA to some variables from the ISA
cpu/base_dyn_inst.hh:
Untemplatized StaticInstPtr, and added TheISA specifier to some variables from the ISA.
cpu/exec_context.hh:
Added some typedefs for types from the isa, and added TheISA specifier to some variables from the isa
cpu/exetrace.hh:
Added typedefs for some types from the ISA, and untemplatized StaticInstPtr
cpu/memtest/memtest.cc:
cpu/o3/btb.cc:
dev/baddev.cc:
dev/ide_ctrl.cc:
dev/ide_disk.cc:
dev/isa_fake.cc:
dev/ns_gige.cc:
dev/pciconfigall.cc:
dev/platform.cc:
dev/sinic.cc:
dev/uart8250.cc:
kern/freebsd/freebsd_system.cc:
kern/linux/linux_system.cc:
kern/system_events.cc:
kern/tru64/dump_mbuf.cc:
kern/tru64/tru64_events.cc:
sim/process.cc:
sim/pseudo_inst.cc:
sim/system.cc:
Added using namespace TheISA
cpu/memtest/memtest.hh:
cpu/trace/opt_cpu.hh:
cpu/trace/reader/itx_reader.hh:
dev/ide_disk.hh:
dev/pcidev.hh:
dev/platform.hh:
dev/tsunami.hh:
sim/system.hh:
sim/vptr.hh:
Added typedef for Addr
cpu/o3/2bit_local_pred.hh:
Changed the include to use arch/isa_traits.hh instead of arch/alpha/isa_traits.hh. Added typedef for Addr
cpu/o3/alpha_cpu.hh:
Added typedefs for Addr and IntReg
cpu/o3/alpha_cpu_impl.hh:
Added this-> to setNextPC to fix a problem since it didn't depend on template parameters any more. Removed "typename" where it was no longer needed.
cpu/o3/alpha_dyn_inst.hh:
Cleaned up some typedefs, and untemplatized StaticInst
cpu/o3/alpha_dyn_inst_impl.hh:
untemplatized StaticInstPtr
cpu/o3/alpha_impl.hh:
Fixed up a typedef of MachInst
cpu/o3/bpred_unit_impl.hh:
Added a using TheISA::MachInst to a function
cpu/o3/btb.hh:
Changed an include from arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef for Addr
cpu/o3/commit.hh:
Removed a typedef of Impl::ISA as ISA, since TheISA takes care of this now.
cpu/o3/cpu.cc:
Cleaned up namespace issues
cpu/o3/cpu.hh:
Cleaned up namespace usage
cpu/o3/decode.hh:
Removed typedef of ISA, and changed it to TheISA
cpu/o3/fetch.hh:
Fized up typedefs, and changed ISA to TheISA
cpu/o3/free_list.hh:
Changed include of arch/alpha/isa_traits.hh to arch/isa_traits.hh
cpu/o3/iew.hh:
Removed typedef of ISA
cpu/o3/iew_impl.hh:
Added TheISA namespace specifier to MachInst
cpu/o3/ras.hh:
Changed include from arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef for Addr.
cpu/o3/regfile.hh:
Changed ISA to TheISA, and added some typedefs for Addr, IntReg, FloatReg, and MiscRegFile
cpu/o3/rename.hh:
Changed ISA to TheISA, and added a typedef for RegIndex
cpu/o3/rename_map.hh:
Added an include for arch/isa_traits.hh, and a typedef for RegIndex
cpu/o3/rob.hh:
Added a typedef for RegIndex
cpu/o3/store_set.hh:
cpu/o3/tournament_pred.hh:
Changed an include of arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef of Addr
cpu/ozone/cpu.hh:
Changed ISA into TheISA, and untemplatized StaticInst
cpu/pc_event.cc:
Added namespace specifier TheISA to Addr types
cpu/profile.hh:
kern/kernel_stats.hh:
Added typedef for Addr, and untemplatized StaticInstPtr
cpu/simple/cpu.cc:
Changed using directive from LittleEndianGuest to AlphaISA, which will contain both namespaces. Added TheISA where needed, and untemplatized StaticInst
cpu/simple/cpu.hh:
Added a typedef for MachInst, and untemplatized StaticInst
cpu/static_inst.cc:
Untemplatized StaticInst
cpu/static_inst.hh:
Untemplatized StaticInst by using the TheISA namespace
dev/alpha_console.cc:
Added using namespace AlphaISA
dev/simple_disk.hh:
Added typedef for Addr and fixed up some formatting
dev/sinicreg.hh:
Added TheISA namespace specifier where needed
dev/tsunami.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
Added using namespace TheISA. It might be better for it to be AlphaISA
dev/tsunami_cchip.cc:
Added typedef for TheISA. It might be better for it to be AlphaISA
kern/linux/aligned.hh:
sim/pseudo_inst.hh:
Added TheISA namespace specifier to Addr
kern/linux/linux_threadinfo.hh:
Added typedef for Addr, and TheISA namespace specifier to StackPointerReg
kern/tru64/mbuf.hh:
Added TheISA to Addr type in structs
sim/process.hh:
Added typedefs of Addr, RegFile, and MachInst
sim/syscall_emul.cc:
Added using namespace TheISA, and a cast of VMPageSize to the int type
sim/syscall_emul.hh:
Added typecast for Addr, and TheISA namespace specifier for where needed
--HG--
extra : convert_revision : 91d4f6ca33a73b21c1f1771d74bfdea3b80eff45
leaving dependent code making way for solaris linux syscall emu.
SConscript:
Add two new files for syscall emulation
Add getDesc() function
arch/alpha/alpha_linux_process.cc:
arch/alpha/alpha_tru64_process.cc:
move architecture independent code into kern/linux/linux.(hh|cc)
arch/alpha/alpha_linux_process.hh:
arch/alpha/alpha_tru64_process.hh:
Add getDesc function
kern/linux/linux.hh:
move generi linux syscall emulation code into kern/linux
kern/tru64/tru64.hh:
move generi tru64 syscall emulation code into kern/tru64
sim/process.cc:
sim/process.hh:
Push the function determination and calling stuff down to LiveProcess
and out of the Linux/Tru64 classes respectively
sim/syscall_emul.cc:
sim/syscall_emul.hh:
fnctl implementation was identical in tru64 and linux so moved to generic
--HG--
extra : convert_revision : 103293dbe6fe2f7892de4929d17dc085def77026
Edits to the CPU model may still need to be made to handle branch likely insts...
arch/isa_parser.py:
add a NNPC operand ...
arch/mips/isa/base.isa:
change SPARC to MIPS
arch/mips/isa/decoder.isa:
typo < to >=
arch/mips/isa/formats/basic.isa:
spacing
arch/mips/isa/formats/branch.isa:
add code for branch instructions (still need adjustments for the branch likely)
arch/mips/isa/operands.isa:
support for NNPC and R31
arch/mips/isa_traits.hh:
NNPC Addr variable
--HG--
extra : convert_revision : df03d2a71c36dbc00270c2e3d7882b4f09ed97ad
Now, must create g++ compilable code ...
arch/mips/isa/decoder.isa:
missing a '}' ... edited a few instruction decodings ...
arch/mips/isa/formats.isa:
rearranged #include
arch/mips/isa/formats/branch.isa:
add Branch Likely and Unconditional format
arch/mips/isa/formats/int.isa:
move OperateNopCheckDecode template to another file ...
arch/mips/isa/formats/noop.isa:
change Alpha to Mips in noop.isa
--HG--
extra : convert_revision : 4bf955fa6dffbbc99fb95fee7878f691e3df5424
Switch fault pointers to const pointers to prevent them from accidentally being changed.
Fix some coding style.
arch/alpha/ev5.cc:
cpu/o3/commit_impl.hh:
kern/kernel_stats.hh:
Remove fake fault.
arch/alpha/faults.cc:
Remove fake fault, fix to have normal m5 line length limit, and change pointers to be const pointers so that the default faults aren't changed accidentally.
arch/alpha/faults.hh:
Fix to have normal m5 line length limit, change pointers to const pointers.
sim/faults.cc:
sim/faults.hh:
Remove fake fault, change pointers to const pointers.
--HG--
extra : convert_revision : 01d4600e0d4bdc1d177b32edebc78f86a1bbfe2e
into zamp.eecs.umich.edu:/z/ktlim2/clean/m5-new
arch/alpha/isa/mem.isa:
Hand merge.
--HG--
extra : convert_revision : c557aa4c867d84ab01139e509ee9f2ed05dd8ea0
arch/alpha/isa/mem.isa:
Avoid explicitly declaring the Mem variable. Instead break up the code blocks used to generate the initiate and complete functions. The templates reflect which operands need to be declared for each function (src, dest, or both).
Loads use both the EA code and mem acc code for the initiate, and memacc code and postacc code for the complete.
Stores use both the EA code and mem acc code for the initiate, and only post acc code for the complete.
arch/isa_parser.py:
Remove hack for mem ops.
--HG--
extra : convert_revision : a367797a2cb698762bfc27be1da00bcbe9367150
arch/mips/isa/decoder.isa:
CondBranch format split up into Branch & BranchLikely formats
arch/mips/isa/formats.isa:
include util.isa
arch/mips/isa/formats/branch.isa:
erroneous 'e' at top of code
arch/mips/isa/formats/util.isa:
util.isa
--HG--
extra : convert_revision : 4fc44a05e2838749e66cd70f210e8a718b34cbf3
arch/alpha/ev5.cc:
Took out the unnecessary check for a null Fault pointer.
arch/alpha/isa/mem.isa:
Changed Fault to Fault *, and removed underscores from fault names.
--HG--
extra : convert_revision : 367a58a375f911185ddcc5fc826034af96427461
SConscript:
The new faults.cc file in sim allocates the system wide faults. When these faults are generated through a function interface in the ISA, this file may go away.
arch/alpha/alpha_memory.cc:
Changed Fault to Fault * and took the underscores out of fault names.
arch/alpha/alpha_memory.hh:
Changed Fault to Fault *. Also, added an include for the alpha faults.
arch/alpha/ev5.cc:
Changed the fault_addr array into a fault_addr function. Once all of the faults can be expected to have the same type, fault_addr can go away completely and the info it provided will come from the fault itself. Also, Fault was changed to Fault *, and underscores were taken out of fault names.
arch/alpha/isa/decoder.isa:
Changed Fault to Fault * and took the underscores out fault names.
arch/alpha/isa/fp.isa:
Changed Fault to Fault *, and took the underscores out of fault names.
arch/alpha/isa/main.isa:
Changed Fault to Fault *, removed underscores from fault names, and made an include of the alpha faults show up in all the generated files.
arch/alpha/isa/mem.isa:
Changed Fault to Fault * and removed underscores from fault names.
arch/alpha/isa/unimp.isa:
arch/alpha/isa/unknown.isa:
cpu/exec_context.hh:
cpu/ozone/cpu.hh:
cpu/simple/cpu.cc:
dev/alpha_console.cc:
dev/ide_ctrl.cc:
dev/isa_fake.cc:
dev/pciconfigall.cc:
dev/pcidev.cc:
dev/pcidev.hh:
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
Changed Fault to Fault *, and removed underscores from fault names.
arch/alpha/isa_traits.hh:
Changed the include of arch/alpha/faults.hh to sim/faults.hh, since the alpha faults weren't needed.
cpu/base_dyn_inst.cc:
Changed Fault to Fault *, and removed underscores from fault names. This file probably shouldn't use the Unimplemented Opcode fault.
cpu/base_dyn_inst.hh:
Changed Fault to Fault * and took the underscores out of the fault names.
cpu/exec_context.cc:
cpu/o3/alpha_dyn_inst.hh:
cpu/o3/alpha_dyn_inst_impl.hh:
cpu/o3/fetch.hh:
dev/alpha_console.hh:
dev/baddev.hh:
dev/ide_ctrl.hh:
dev/isa_fake.hh:
dev/ns_gige.hh:
dev/pciconfigall.hh:
dev/sinic.hh:
dev/tsunami_cchip.hh:
dev/tsunami_io.hh:
dev/tsunami_pchip.hh:
dev/uart.hh:
dev/uart8250.hh:
Changed Fault to Fault *.
cpu/o3/alpha_cpu.hh:
Changed Fault to Fault *, removed underscores from fault names.
cpu/o3/alpha_cpu_impl.hh:
Changed Fault to Fault *, removed underscores from fault names, and changed the fault_addr array to the fault_addr function. Once all faults are from the ISA, this function will probably go away.
cpu/o3/commit_impl.hh:
cpu/o3/fetch_impl.hh:
dev/baddev.cc:
Changed Fault to Fault *, and removed underscores from the fault names.
cpu/o3/regfile.hh:
Added an include for the alpha specific faults which will hopefully go away once the ipr stuff is moved, changed Fault to Fault *, and removed the underscores from fault names.
cpu/simple/cpu.hh:
Changed Fault to Fault *
dev/ns_gige.cc:
Changed Fault to Fault *, and removdd underscores from fault names.
dev/sinic.cc:
Changed Fault to Fault *, and removed the underscores from fault names.
dev/uart8250.cc:
Chanted Fault to Fault *, and removed underscores from fault names.
kern/kernel_stats.cc:
Removed underscores from fault names, and from NumFaults.
kern/kernel_stats.hh:
Changed the predeclaration of Fault from an enum to a class, and changd the "fault" function to work with the classes instead of the enum. Once there are no system wide faults anymore, this code will simplify back to something like it was originally.
sim/faults.cc:
This allocates the system wide faults.
sim/faults.hh:
This declares the system wide faults.
sim/syscall_emul.cc:
sim/syscall_emul.hh:
Removed the underscores from fault names.
--HG--
rename : arch/alpha/faults.cc => sim/faults.cc
rename : arch/alpha/faults.hh => sim/faults.hh
extra : convert_revision : 253d39258237333ae8ec4d8047367cb3ea68569d
Should we add a proxy_port that does the v->p address translation?
Should the proxy port return a fault on translation errors, if we add one?
arch/alpha/alpha_linux_process.cc:
Syscalls use a memPort through the CPU now instead of a xc functional memory.
cpu/base.hh:
Add a pointer to the memPort syscalls will use. Should this be a proxy_port that does address translation?
cpu/exec_context.cc:
cpu/exec_context.hh:
Remove functional memory from the exec context
cpu/simple/cpu.cc:
Set the memPort to be used as the syscall port as the dcache port
sim/syscall_emul.cc:
sim/syscall_emul.hh:
Syscalls use a memPort through the CPU now instead of a xc functional memory.
Also, fix the fact that readStringFunctional doesn't return a fault... should proxy_port handle this because it is doing the translation?
--HG--
extra : convert_revision : 1f65318c6594301a75dc4dc0c99fdd436b094a7f
SConscript:
Place the memory objects back in the right place
arch/alpha/isa_desc:
Fix includes to point to the new memory requests
cpu/exec_context.hh:
Exec context now points to memory object, fix the include paths.
Convert to prot_read/prot_write functions instead of read and write.
Convert to new CpuRequestPtr instead of MemReqPtr.
mem/request.hh:
Add back in support for Request Flags (needed by decoder to tag request) Removed the flags that were associated with packets/coherence.
sim/process.hh:
Converted to point to new memory objects
--HG--
extra : convert_revision : a0b95380915d63b53194e2a26336d6adb1a0086b
arch/alpha/isa/mem.isa:
Include methods that allow a memory operation to be split between the part that initiates the access, and the part that completes the access. In these functions the Mem variable is explicitly declared; in the default execute functions, the Mem variable is still handled through %(op_decl)s.
arch/isa_parser.py:
Include recording the type of the memory access variable so that it can be used if it needs to be explicitly declared in a template.
Have memory operands consider themselves neither a source nor a destination to avoid including themselves on the op_src_decl list or the op_dest_decl list.
Record op_src_decl and op_dest_decl lists to allow for declaring only source or destination operands. This is needed for the split memory access methods.
--HG--
extra : convert_revision : f674f7a2f747ae40ba8c3a0933b0337c87ee0b6c
arch/alpha/alpha_linux_process.cc:
add endian conversions for fstat functions
arch/alpha/alpha_tru64_process.cc:
add endian conversions for various functions
sim/byteswap.hh:
for some reason gcc on macos really wants long and unsigned long
Why int32_t and uint32_t isn't sufficient I don't know.
sim/process.cc:
sim/syscall_emul.hh:
endian fixes
--HG--
extra : convert_revision : ce625d5660b70867c43c74fbed856149c0d8cd36
arch/alpha/main.isa to test my files ...
arch/mips/isa/operands.isa:
use sd and ud instead of sdw and udw
--HG--
extra : convert_revision : d66f3fd2c4a4d70e6015f0f1643c400cdfe73055
SConscript:
Moved pseudo_inst.hh from targetarch to full system sources
arch/alpha/SConscript:
Moved pseudo_inst.cc out of the alpha specific sources
arch/alpha/isa/decoder.isa:
The decoder now pulls out the arguments for the pseudo instructions based on the alpha ABI
arch/alpha/isa/main.isa:
Registers 16, 17 and 18 are used to get parameters for the pseudo instructions and can be referred to explicitly
sim/pseudo_inst.cc:
Changed some include paths to reflect that pseudo_inst.hh is now outside of the alpha directory. Also, instead of extracting their parameters directly, they're passed in as regular function arguments.
sim/pseudo_inst.hh:
Changed the function prototypes to include the functions parameters, now that they aren't extracted from the execution context.
--HG--
rename : arch/alpha/pseudo_inst.cc => sim/pseudo_inst.cc
rename : arch/alpha/pseudo_inst.hh => sim/pseudo_inst.hh
extra : convert_revision : 76ce768cf1d8a838aa7b64878a7ab4c4215ac999
SConscript:
Moved isa_fullsys_traits.hh out of targetarch, since the only place it's included, and the only place the comments in the file say it should be included, is in the alpha isa_traits.hh
targetarch/isa_traits.hh is now included through arch/isa_traits.hh
vptr.hh was removed from targetarch, and moved to sim
arch/alpha/pseudo_inst.cc:
Moved vptr.hh from targetarch to sim
base/loader/object_file.hh:
base/loader/symtab.hh:
cpu/base.hh:
dev/ide_disk.cc:
Changed the include of isa_traits.hh from targetarch to arch
cpu/static_inst.hh:
dev/platform.hh:
dev/simple_disk.hh:
kern/tru64/dump_mbuf.cc:
kern/tru64/mbuf.hh:
kern/tru64/tru64_events.cc:
kern/tru64/tru64_system.cc:
kern/tru64/tru64_system.hh:
sim/process.hh:
sim/syscall_emul.hh:
Changed the include of isa_traits.hh from targetarch to arch.
kern/linux/linux_threadinfo.hh:
Changed the include of vptr.hh from targetarch to sim.
sim/byteswap.hh:
Removed the line declaring swap_byte(long), since it ambiguates with swap_byte(int32_t)
sim/vptr.hh:
Fixed the assert in the equals operator.
Changed the AlphaISA namespace reference to TheISA.
Changed arch/alpha/vtophys.hh to targetarch/vtophys.hh, since this file is now for all architectures.
Added an include of arch/isa_traits.hh so that TheISA would be defined.
--HG--
extra : convert_revision : e3c6ac17ed0277cfeba1d35cd63eba66eba5996f
minor change to syntax of 'def operands' in ISA descriptions.
arch/alpha/isa/main.isa:
arch/mips/isa/operands.isa:
arch/sparc/isa/operands.isa:
Change 'def operands' statement to work with new
isa_parser changes.
arch/isa_parser.py:
Merge OperandTraits and OperandDescriptor objects into a
unified hierarchy of Operand objects.
Required a change in the syntax of the 'def operands'
statement in the ISA description.
--HG--
extra : convert_revision : cb43f1607311497ead88ba13953d410ab5bc6a37
arch/isa_parser.py:
Minor cleanup of operand type and traits code:
- build operand size map right away when types are defined
instead of waiting to do it lazily
- check that operand types have been defined before operands
- don't use 'type' as a variable name
- use isinstance() instead of checking for types directly
--HG--
extra : convert_revision : 099c1ee8d490f9c38316749bf87209388c55c971
instruction format functions in ISA description language.
Take advantage of these features to clean up memory
instruction definitions in Alpha.
arch/alpha/isa/decoder.isa:
arch/alpha/isa/mem.isa:
arch/alpha/isa/pal.isa:
Take advantage of new keyword parameters to disambiguate
instruction vs. memory-request flags, and to provide
a default EA calculation for memory ops (since 99% of them
are the same).
arch/isa_parser.py:
Add two new features to instruction format functions:
- Keyword parameters, a la Python.
- List-valued arguments.
Also export makeList() function to Python code blocks,
as this is handy for dealing with flags.
--HG--
extra : convert_revision : 99bbbaa2e765230aa96b6a06ed193793325f9fb0
wrong
arch/alpha/alpha_linux_process.cc:
fix #if. I wonder why my compiler had no issues
--HG--
extra : convert_revision : 880a0442b28811db5ec548ce940060d4b26ec634
arch/alpha/alpha_linux_process.cc:
Add endian conversions to fstat
sim/byteswap.hh:
for some reason I don't understand g++ really wanted a long version defined
even though int32_t should be the same.
--HG--
extra : convert_revision : 5bfe9d3f0b31824fa5a7ae3f51fd0be5ed4d555d
arch/alpha/alpha_linux_process.cc:
arch/alpha/alpha_tru64_process.cc:
fixup for bsd hosts. Some headers are included by default which means that
more variables need TGT_ prefixes and there isn't a stat call (everything
is a stat64 call) so we have to work around that a bit
base/intmath.hh:
base/socket.cc:
this is no longer needed with mac os 10.4
cpu/inst_seq.hh:
just use a uint64_t instead of long long
cpu/o3/inst_queue_impl.hh:
I much cleaner way to get max int
sim/syscall_emul.hh:
fix stat64 problems on *BSD
--HG--
extra : convert_revision : 9eef5f896e083ae1774e818a9765dd83e0305942
Should enable implementation of split-phase timing loads
with new memory model.
May create slight timing differences under FullCPU, as I
believe we were not handling software prefetches correctly
before when the split MemAcc/Exec model was used. I haven't
looked into this in any detail though.
arch/alpha/isa/decoder.isa:
HwLoadStore format split into separate HwLoad and
HwStore formats.
Copy instructions now fall under MiscPrefetch format.
Mem_write_result is now just write_result in store
conditionals.
arch/alpha/isa/mem.isa:
Split MemAccExecute and LoadStoreExecute templates
into separate templates for loads and stores; now
that memory operands are handled differently from
registers, it's impossible to have a single template
serve both.
Also unified the handling of "regular" prefetches
(loads to r31) and "misc" prefetches (e.g., wh64)
under the new scheme. It looks like SW prefetches
were not handled correctly in FullCPU up til now,
since we generated an execute() method for the outer
instruction but didn't generate a proper method for
MemAcc::execute() (instead getting a default no-op
method for that).
arch/alpha/isa/pal.isa:
Split HwLoadStore into separate HwLoad and HwStore
formats to select proper template (see change to
mem.isa in this changeset).
arch/isa_parser.py:
Stop trying to treat memory operands like register
operands, since we never used them in a uniform way
anyway, and it made it impossible to do split-phase
loads as needed for the new CPU model. Now there's no
more 'op_mem_rd', 'op_nonmem_rd', etc.: 'op_rd' just does
register operands, and the template code is responsible
for formulating the call to the memory system. Right now
the only thing exported by InstObjParams is a new attribute
'mem_acc_size' which gives the memory access size in bits,
though more attributes can be added if needed.
Also moved code in findOperands() method to
OperandDescriptorList.__init__(), which is where it belongs.
--HG--
extra : convert_revision : 6d53d07e0c5e828455834ded4395fa40f9146a34
=================================================
-every MIPS32 ISA is represented with some type
of code block.
-any instruction that doesnt have a code block
would be of format WarnUnimpl. Examples of the
ones I am waiting on further info to implement
are the TLB register insts, memory consistency
instructions (ll,sc,etc.) and software debug
insts.
--HG--
extra : convert_revision : 4a26c72e4fa1f63b8689fe2631a7508daf660969
(thanks to Gabe's include feature!).
arch/alpha/isa/main.isa:
Split out into multiple .isa files.
--HG--
extra : convert_revision : 30d8edf74ea194d4a208febf1e66edc72a7dbd5d
arch/isa_parser.py:
Clean up ##include code a bit.
arch/sparc/isa/formats.isa:
arch/sparc/isa/main.isa:
Fix include paths.
--HG--
extra : convert_revision : 0689963c2948e5f1088ecbf2cf6018d29bdaceff
arch/isa_parser.py:
Get rid of "munged name" for operands in C++ code.
That is, "Ra.uq" will now be known in the C++ as "Ra"
rather than "Ra_uq". It wasn't legal to use different
type extensions for the same operand at the same time
anyway, and now it will be easier to refer to explicit
operands in template code if necessary.
--HG--
extra : convert_revision : 9ff41e0201aeefe761743084ecdb34f4b9c84fdb
arch/mips/isa/decoder.isa:
Code for di,ei,seb,seh,clz,and clo ....
Every instruction has a format now (of course these are initial formats are still subject to change!)
arch/mips/isa/formats/branch.isa:
Format Branch in MIPS similar to Alpha Format
--HG--
extra : convert_revision : 2118a1d9668610b1e9f1dea66d878b7b36c1ac7e
arch/alpha/alpha_linux_process.cc:
arch/alpha/alpha_tru64_process.cc:
Replaced the namespace declaration with including arch/alpha/isa_traits.hh
--HG--
extra : convert_revision : 07cb73a9f30f0e165809668f9baff6a3e3f94580
SConscript:
Moved some files out of targetarch. The either no longer need to be there, never needed to be there, or should be referred to directly in arch/alpha due to there strictly alpha content.
arch/alpha/isa_traits.hh:
Added alpha's endianness to it's isa_traits.hh
arch/mips/isa_traits.hh:
Added MIPS endianness to it's isa_traits.hh
arch/sparc/isa_traits.hh:
Added SPARCs endianess to it's isa_traits.hh
build/SConstruct:
Added MIPS as a valid architecture
cpu/exec_context.hh:
Included arch/isa_traits.hh to bring in the endianness of the system.
cpu/o3/alpha_cpu.hh:
Included arch/isa_traits.hh to bring in the systems endianness, and removed the hardcoding of little endianness
cpu/o3/fetch_impl.hh:
kern/freebsd/freebsd_system.cc:
Included arch/isa_traits.hh to bring in the systems endianness, and removed the hardcoding to little endianness.
sim/system.cc:
Included arch/isa_traits.hh to bring in the systems endianness, and removed the hardcoding to little endian.
--HG--
extra : convert_revision : b1ab34b7569db531cd1c74f273b24222e63f9007
The extra class is needed because of the necessisty of an immediate member variable.
Also, added some 'very modest' python code to choose between the IntOp and
the IntImmOp based on the instruction name ...
--HG--
extra : convert_revision : f109c12418202a99b40e270360134e8335739836
arch/mips/isa/formats/int.format:
Looks like Integer Ops with Immediates may not need their own separate class because all those instructions are distinct from
their reg-reg counterparts
--HG--
rename : arch/mips/isa/bitfields.def => arch/mips/isa/bitfields.isa
rename : arch/mips/isa/decoder.def => arch/mips/isa/decoder.isa
rename : arch/mips/isa/formats.def => arch/mips/isa/formats.isa
rename : arch/mips/isa/includes.h => arch/mips/isa/includes.isa
rename : arch/mips/isa/operands.def => arch/mips/isa/operands.isa
extra : convert_revision : 8e354b4232b28c0264d98d333d55ef8b5a6589cc
Output,Format, & Template code needs to be adjusted to correctly take these "decoder.h" inputs ...
--HG--
extra : convert_revision : 3dcde1f2f587e2766fd61231a93d34d1d7727356
arch/alpha/alpha_linux_process.cc:
arch/alpha/alpha_tru64_process.cc:
Added the endianness namespace. This may change.
cpu/exec_context.hh:
Changed the include path for byteswap, and forced LittleEndianness for lack of a better solution.
cpu/o3/alpha_cpu.hh:
Forced LittleEndianness, for lack of a better solution.
cpu/o3/alpha_cpu_impl.hh:
Cleared away some commented out code.
cpu/o3/fetch_impl.hh:
Changed the include patch for byteswap, and forced LittleEndianness for lack of a better solution.
cpu/simple/cpu.cc:
Added an include for byteswap.hh, and fixed the SimpleCPU to LittleEndian. This cpu only does alpha, so that's fine.
dev/disk_image.cc:
Changed the include path of byteswap.hh
kern/freebsd/freebsd_system.cc:
kern/linux/linux_system.cc:
Added an include for byteswap.hh, and forced LittleEndianness for lack of a better solution.
sim/system.cc:
Forced LittleEndianness for lack of a better solution.
--HG--
extra : convert_revision : b95d3e1265a825e04bd77622a3ac09fbac6bd206
Needed in the interim until we port the old model over
to the new interface. Long term we should have a cleaner
solution for controlling which models get compiled in.
SConscript:
Move old FullCPU source file list to separate full_cpu_sources
list so we can choose to not include it in compile.
arch/isa_parser.py:
Hack to avoid generating FullCPU execute files.
Need a better way to control this.
cpu/exetrace.cc:
Don't include old FullCPU-specific headers (apparently
unnecessary anyway--or if not they should be).
--HG--
extra : convert_revision : 00d5a91a9e4d71507404b8c7f4c6e7c7b7ba3853
System object now exists for both fullsys and syscall emulation, as the
latter needs it so that Process objects can find the shared PhysicalMemory
for initialization.
Changes are incomplete: still need to fix up Process (& EioProcess) memory
initialization and syscall emulation code for new mem interface.
arch/alpha/alpha_linux_process.cc:
arch/alpha/alpha_linux_process.hh:
arch/alpha/alpha_tru64_process.cc:
arch/alpha/alpha_tru64_process.hh:
cpu/base.cc:
cpu/base.hh:
Take System argument in constructor.
cpu/exec_context.cc:
Take System argument in constructor.
Merge two constructors into a single one.
cpu/exec_context.hh:
Take System argument in constructor.
Merge two constructors into a single one.
Replace dummy translation with lookup in Process object's page table.
python/m5/objects/Process.py:
Add System parameter to Process object (& subobjects).
python/m5/objects/System.py:
Segregate full-system only Process parameters (most of them!).
sim/process.cc:
Take System argument in constructor.
Move initialization to startup() callback to occur after system & cpus
are initialized.
Generate ProxyMemory object to pass to loader for transparent
virtual page allocation.
sim/process.hh:
Take System argument in constructor.
Move initialization to startup() callback to occur after system & cpus
are initialized.
sim/system.cc:
sim/system.hh:
Enable System object for non-full-system too.
Basically involved putting most of the existing code
inside '#ifdef FULL_SYSTEM'.
Key thing needed for syscall emulation at this point is
the PhysicalMemory object (for Process initialization).
--HG--
extra : convert_revision : f0f34b47bd4f77b502191affd3d03b4d6d9bcdd8
All of the code literals are empty as of now. As much as possible instructions were organized into relevant "formats"
and also references to the tables I used from the MIPS manual were noted via appropriate comments.
--HG--
extra : convert_revision : 9b44fb40e900061a4cdb290b6a5aaceb9750ae13
arch/mips/isa_desc/bitfields.h:
Change from table names to actual bitfield name ...
--HG--
extra : convert_revision : ead69065eb9c3e9c4ea4f67587a6fb07091898ed
- this will decode the instructions but not doing anything to create the C++ object yet
(the 1st of many steps!)
arch/mips/isa_desc/bitfields.h:
initial bitfield constants ... copied some from original alpha bitfields
arch/mips/isa_desc/decoder.h:
decoder function skeleton pt.1
- this will decode the instructions but not doing anything to create the C++ object yet
(the 1st of many steps!)
--HG--
extra : convert_revision : 2b9a0f8160c78b17f9d3d5eaf5af5a4d2f074761
SConscript:
There is a new SConscript in the arch/alpha directory which has the alpha specific files. To add files for an arch, a similar file should be created.
arch/isa_parser.py:
The isa parser now supports include directives. These are done with ##include
build/SConstruct:
The target directory is passed on so that the architecture specific SConscript can have it. Also, sparc was added as a valid architecture type.
arch/alpha/SConscript:
This SConscript adds the alpha specific source
arch/sparc/isa_desc/operands.h:
This sets up the operand types that the sparc isa uses
arch/sparc/isa_traits.cc:
Implementation of sparc specific things, like a register file with windows
build/build_options/default/SPARC_SE:
The default options for a sparc syscall emulation build.
--HG--
extra : convert_revision : 1afedae61dc8cae0d59d3bf1d41420d929be2efd
arch/sparc/isa_desc/bitfields.h:
This file defines the bit fields used by the isa description system
arch/sparc/isa_desc/decoder.h:
This file describes the decoder for the isa description system
arch/sparc/isa_desc/formats.h:
This file declares the instruction formats
arch/sparc/isa_desc/formats/basic.format:
This file implements the "basic" instruction format
arch/sparc/isa_desc/formats/branch.format:
This file implements the "branch" instruction format
arch/sparc/isa_desc/formats/integerop.format:
This file implements the "integerop" instruction format
arch/sparc/isa_desc/formats/mem.format:
This file implements the "mem" instruction format
arch/sparc/isa_desc/formats/noop.format:
This file implements the "noop" instruction format
arch/sparc/isa_desc/formats/trap.format:
This file implements the "trap" instruction format
arch/sparc/isa_desc/includes.h:
This file is all of the inclues that are used by the isa description system
--HG--
extra : convert_revision : 12a2ffe949317b8b57d83263a4261131b9432c2a
arch/alpha/alpha_linux_process.cc:
sim/syscall_emul.cc:
sim/syscall_emul.hh:
Apply patch for syscall emulation provided by Antti Miettinen (apm@brigitte.dna.fi).
--HG--
extra : convert_revision : 37fbc78a927110b7798343afd2c5f37a269e42b4
are more efficient and reduce the number of new/delete calls
arch/alpha/stacktrace.cc:
- Change the StackTrace code so that the class can more easily be
cleaned out and reused to avoid extra allocations.
- Allow trace() to accept a static instruction pointer so it can
determine if the instruction is worth tracing. This is moved from
the CPU.
- provide constants for special meaning PCs (user, console, unknown),
instead of magic numbers
- switch to using kernelSymtab instead of allSymtab which will be
going away
- if the stack adjustment doesn't make any sense, exit and push
unknown so we don't get into an infinite loop or record garbage.
- check to see if we've made too many iterations through the stack
and panic to avoid an infinite loop
arch/alpha/stacktrace.hh:
- Change the StackTrace code so that the class can more easily be
cleaned out and reused to avoid extra allocations.
- Allow trace() to accept a static instruction pointer so it can
determine if the instruction is worth tracing. This is moved from
the CPU.
- provide constants for special meaning PCs (user, console, unknown),
instead of magic numbers
cpu/base.cc:
only clear the profile if we have one
include profile.hh here since base.hh doesn't do it anymore
cpu/base.hh:
no need to include cpu/profile.hh here
cpu/profile.cc:
use ProfileNode pointers instead of objects in the ChildList
Consume a vector of addresses since that's really all we
care about.
cpu/profile.hh:
Keep pointers to ProfileNodes to reduce the size of these structures
keep a StackTrace around so that we may reuse it.
provide consume functions that use the new StackTrace trace interface
one consume function is inline and tries to fastpath the no trace
condition, it calls the outlined consume function if a trace is generated.
cpu/simple/cpu.cc:
include cpu/profile.hh here since base.hh no longer does
use the new FunctionProfile::consume interface
(which contains the tracing functions)
--HG--
extra : convert_revision : 5a1d9265289a75f67a497b322926be1f8c2d8eb3
running SPEC FP codes).
arch/alpha/isa_desc:
Don't warn about non-standard trapping modes more than
once per static instruction. (Had the flag to suppress
these but forgot to check it!)
build/SConstruct:
Add USE_SSE2 option to enable compiling w/SSE2 (important
for getting IEEE-compliant FP on x86).
--HG--
extra : convert_revision : eac69efb28cce7b48035480d8b7cb004782969f4
SConscript:
Get rid of the pc_sample stuff and move to the new profiling stuff
base/traceflags.py:
DPRINTF Stack stuff
cpu/base.cc:
cpu/base.hh:
cpu/exec_context.cc:
cpu/exec_context.hh:
cpu/simple/cpu.cc:
Add profiling stuff
kern/kernel_stats.hh:
Use a smart pointer
sim/system.cc:
sim/system.hh:
Create a new symbol table that has all of the symbols for a
particular system
util/stats/categories.py:
change around the categories, add categories for function
profiling stuff
util/stats/profile.py:
No profile parsing and display code to deal with function
profiling stuff, graph, dot, and text outputs.
--HG--
extra : convert_revision : b3de0cdc8bd468e42647966e2640ae009bda9eb8
Seems to avoid the significant problems on platforms w/o fenv.h.
arch/alpha/isa_desc:
Explicitly handle rounding on FP-to-integer conversions.
Seems to avoid the significant problems on platforms w/o fenv.h.
Get rid of FP "Fast" vs "General" distinction... more headache than
it's worth.
arch/isa_parser.py:
Fix bug with "%s" in C++ templates (must escape properly to
pass through Python string interpolation).
--HG--
extra : convert_revision : de964d764e67e0934ac0ef535f53c974640731fb
build directory instead of being inferred from the name
of the build directory.
Options are passed to C++ via config/*.hh files instead of
via the command line. Build option flags are now always
defined to 0 or 1, so checks must use '#if' rather than
'#ifdef'.
SConscript:
MySQL detection moved to SConstruct.
Add config/*.hh files (via ConfigFile builder).
arch/alpha/alpha_memory.cc:
arch/alpha/ev5.cc:
arch/alpha/ev5.hh:
arch/alpha/isa_traits.hh:
base/fast_alloc.hh:
base/statistics.cc:
base/statistics.hh:
base/stats/events.cc:
base/stats/events.hh:
cpu/base.cc:
cpu/base.hh:
cpu/base_dyn_inst.cc:
cpu/base_dyn_inst.hh:
cpu/exec_context.cc:
cpu/exec_context.hh:
cpu/o3/alpha_cpu.hh:
cpu/o3/alpha_cpu_builder.cc:
cpu/o3/alpha_cpu_impl.hh:
cpu/o3/alpha_dyn_inst.hh:
cpu/o3/alpha_dyn_inst_impl.hh:
cpu/o3/alpha_params.hh:
cpu/o3/commit_impl.hh:
cpu/o3/cpu.cc:
cpu/o3/cpu.hh:
cpu/o3/fetch_impl.hh:
cpu/o3/iew.hh:
cpu/o3/iew_impl.hh:
cpu/o3/regfile.hh:
cpu/o3/rename_impl.hh:
cpu/o3/rob_impl.hh:
cpu/ozone/cpu.hh:
cpu/pc_event.cc:
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
sim/process.cc:
sim/process.hh:
Convert compile flags from def/undef to 0/1.
Set via #include config/*.hh instead of command line.
arch/alpha/isa_desc:
Convert compile flags from def/undef to 0/1.
Set via #include config/*.hh instead of command line.
Revamp fenv.h support... most of the ugliness is hidden
in base/fenv.hh now.
base/mysql.hh:
Fix typo in #ifndef guard.
build/SConstruct:
Build options are set via a build_options file in the
build directory instead of being inferred from the name
of the build directory.
Options are passed to C++ via config/*.hh files instead of
via the command line.
python/SConscript:
Generate m5_build_env directly from scons options
instead of indirectly via CPPDEFINES.
python/m5/convert.py:
Allow '0' and '1' for booleans.
Rewrite toBool to use dict.
base/fenv.hh:
Revamp <fenv.h> support to make it a compile option
(so we can test w/o it even if it's present) and to
make isa_desc cleaner.
--HG--
extra : convert_revision : 8f97dc11185bef5e1865b3269c7341df8525c9ad
code into a function that can be called by the AlphaConsole class.
AlphaConsole will pass in its address.
arch/alpha/ev5.hh:
Move Phys2K0Seg to ev5.hh and fixup the TSUNAMI uncacheable
bits so that they will be converted correctly.
dev/alpha_access.h:
Do not hard code the location of the AlphaConsole
dev/alpha_console.cc:
fixup #includes
tell the system where the alpha console is
sim/system.hh:
Provide a function that will tell the system where the AlphaAccess
structure (device) lives
--HG--
extra : convert_revision : 92d70ca926151a32eebe9925de597459ac58013e
SConscript:
Added kern/freebsd/freebsd_events.cc.
arch/alpha/isa_traits.hh:
Added Argument to support replacement of calibrate_clocks function in FreeBSD.
dev/ns_gige.hh:
Fixed NIC model number typo.
dev/tsunami_io.cc:
Added support for RTC writes and PIC 2 mask reads. Made RTC static member.
dev/tsunami_io.hh:
Made RTC static member.
kern/freebsd/freebsd_system.cc:
Added events to skip functions in FreeBSD.
kern/freebsd/freebsd_system.hh:
Added events to skip certain functions.
--HG--
extra : convert_revision : 8aaca51d3f9b1bb601722a5bae240aae77b445db
kern/linux/sched.hh:
kern/linux/thread_info.hh:
got rid of everything but exactly what we needed
util/categories.py:
newest version from one of my repositories
--HG--
extra : convert_revision : c4328e5938d421d60493c0da07022bfa9e92c404
arch/alpha/alpha_tru64_process.cc:
Sort #includes
Make code more portable. g++ doesn't seem to always like
struct ::stat (and others). So, we typedef stat outside of
the namespace as something else and use the typedef
base/hostinfo.cc:
use snprintf to quell warning
base/inifile.cc:
use strncpy to quell warning
base/stats/events.cc:
don't use strcpy
cpu/beta_cpu/btb.cc:
use FloorLog2 instead of log2
cpu/beta_cpu/comm.hh:
cpu/beta_cpu/inst_queue.hh:
cpu/beta_cpu/sat_counter.hh:
use sim/host.hh instead of stdint.h
--HG--
extra : convert_revision : 59bd9235dda74e72a8b6a70b3f3a981840384f3f
We can now run the SimpleScalar wupwise binary
to completion on the test input.
Didn't have time to do more testing, but I fixed
a major problem w/getdirentries that should help
a lot more programs run.
arch/alpha/alpha_tru64_process.cc:
Add truncate, ftruncate, statfs, and fstatfs.
Add v4.x (pre-F64) stat, fstat, and lstat.
Add setsysinfo (though all it does is provide more
specific warning messages).
Fix subtle but major bug in getdirentries.
sim/syscall_emul.cc:
sim/syscall_emul.hh:
Add truncate, ftruncate, statfs, and fstatfs.
--HG--
extra : convert_revision : 9037393d00dc49b0074a41603ea647587f5a9ec7
SConscript:
arch/isa_parser.py:
cpu/base_dyn_inst.cc:
Remove OOO CPU stuff.
arch/alpha/faults.hh:
Add fake memory fault. This will be removed eventually.
arch/alpha/isa_desc:
Change EA comp and Mem accessor to be const StaticInstPtrs.
cpu/base_dyn_inst.hh:
Update read/write calls to use load queue and store queue indices.
cpu/beta_cpu/alpha_dyn_inst.hh:
Change to const StaticInst in the register accessors.
cpu/beta_cpu/alpha_dyn_inst_impl.hh:
Update syscall code with thread numbers.
cpu/beta_cpu/alpha_full_cpu.hh:
Alter some of the full system code so it will compile without errors.
cpu/beta_cpu/alpha_full_cpu_builder.cc:
Created a DerivAlphaFullCPU class so I can instantiate different CPUs that have different template parameters.
cpu/beta_cpu/alpha_full_cpu_impl.hh:
Update some of the full system code so it compiles.
cpu/beta_cpu/alpha_params.hh:
cpu/beta_cpu/fetch_impl.hh:
Remove asid.
cpu/beta_cpu/comm.hh:
Remove global history field.
cpu/beta_cpu/commit.hh:
Comment out rename map.
cpu/beta_cpu/commit_impl.hh:
Update some of the full system code so it compiles. Also change it so that it handles memory instructions properly.
cpu/beta_cpu/cpu_policy.hh:
Removed IQ from the IEW template parameter to make it more uniform.
cpu/beta_cpu/decode.hh:
Add debug function.
cpu/beta_cpu/decode_impl.hh:
Slight updates for decode in the case where it causes a squash.
cpu/beta_cpu/fetch.hh:
cpu/beta_cpu/rob.hh:
Comment out unneccessary code.
cpu/beta_cpu/full_cpu.cc:
Changed some of the full system code so it compiles. Updated exec contexts and so forth to hopefully make multithreading easier.
cpu/beta_cpu/full_cpu.hh:
Updated some of the full system code to make it compile.
cpu/beta_cpu/iew.cc:
Removed IQ from template parameter to IEW.
cpu/beta_cpu/iew.hh:
Removed IQ from template parameter to IEW. Updated IEW to recognize the Load/Store queue.
cpu/beta_cpu/iew_impl.hh:
New handling of memory instructions through the Load/Store queue.
cpu/beta_cpu/inst_queue.hh:
Updated comment.
cpu/beta_cpu/inst_queue_impl.hh:
Slightly different handling of memory instructions due to Load/Store queue.
cpu/beta_cpu/regfile.hh:
Updated full system code so it compiles.
cpu/beta_cpu/rob_impl.hh:
Moved some code around; no major functional changes.
cpu/ooo_cpu/ooo_cpu.hh:
Slight updates to OOO CPU; still does not work.
cpu/static_inst.hh:
Remove OOO CPU stuff. Change ea comp and mem acc to return const StaticInst.
kern/kernel_stats.hh:
Extra forward declares added due to compile error.
--HG--
extra : convert_revision : 594a7cdbe57f6c2bda7d08856fcd864604a6238e
arch/alpha/alpha_tru64_process.cc:
getdirent isn't implemented by cygwin. panic if this function is
executed. (It shouldn't be too much to emulate it using opendir,
readdir, etc.)
arch/alpha/pseudo_inst.cc:
Use lseek once and read instead pread.
base/intmath.hh:
we want int, long, and long long variations of FloorLog2 instead
of int32_t, int64_t. Otherwise, we leave one out.
base/socket.cc:
Fix define that seems to be for apple
sim/serialize.cc:
don't use the intXX_t stuff, instead, use the real types
so we're sure that we cover all of them.
--HG--
extra : convert_revision : 9fccaff583100b06bbaafd95a162c4e19beed59e
CPU cycle ticks. This allows the user to have CPUs of different
frequencies, and also allows frequencies and latencies that are
not evenly divisible by the CPU frequency. For now, the CPU
frequency is still set to the global frequency, but soon, we'll
hopefully make the global frequency fixed at something like 1THz
and set all other frequencies independently.
arch/alpha/ev5.cc:
The cycles counter is based on the current cpu cycle.
cpu/base_cpu.cc:
frequency isn't the cpu parameter anymore, cycleTime is.
cpu/base_cpu.hh:
frequency isn't the cpu parameter anymore, cycleTime is.
create several public functions for getting the cpu frequency
and the numbers of ticks for a given number of cycles, etc.
cpu/memtest/memtest.cc:
cpu/simple_cpu/simple_cpu.cc:
cpu/simple_cpu/simple_cpu.hh:
cpu/trace/trace_cpu.cc:
Now that ticks aren't cpu cycles, fixup code to advance
by the proper number of ticks.
cpu/memtest/memtest.hh:
cpu/trace/trace_cpu.hh:
Provide a function to get the number of ticks for a given
number of cycles.
dev/alpha_console.cc:
Update for changes in the way that frequencies and latencies are
accessed. Move some stuff to init()
dev/alpha_console.hh:
Need a pointer to the system and the cpu to get the frequency
so we can pass the info to the console code.
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/ethertap.cc:
dev/ide_disk.hh:
dev/ns_gige.cc:
dev/ns_gige.hh:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
dev/ide_disk.cc:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
Add some extra debugging printfs
dev/platform.cc:
dev/sinic.cc:
dev/sinic.hh:
outline the constructor and destructor
dev/platform.hh:
outline the constructor and destructor.
don't keep track of the interrupt frequency. Only provide the
accessor function.
dev/tsunami.cc:
dev/tsunami.hh:
outline the constructor and destructor
Don't set the interrupt frequency here. Get it from the actual device
that does the interrupting.
dev/tsunami_io.cc:
dev/tsunami_io.hh:
Make the interrupt interval a configuration parameter. (And convert
the interval to the new latency/frequency stuff in the python)
kern/linux/linux_system.cc:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
For now, we must get the boot cpu's frequency as a parameter
since allowing the system to have a pointer to the boot cpu would
cause a cycle.
kern/tru64/tru64_system.cc:
For now, we must get the boot cpu's frequency as a parameter
since allowing the system to have a pointer to the boot cpu would
cause a cycle.
python/m5/config.py:
Fix support for cycle_time relative latencies and frequencies.
Add support for getting a NetworkBandwidth or a MemoryBandwidth.
python/m5/objects/BaseCPU.mpy:
All CPUs now have a cycle_time. The default is the global frequency,
but it is now possible to set the global frequency to some large value
(like 1THz) and set each CPU frequency independently.
python/m5/objects/BaseCache.mpy:
python/m5/objects/Ide.mpy:
Make this a Latency parameter
python/m5/objects/BaseSystem.mpy:
We need to pass the boot CPU's frequency to the system
python/m5/objects/Ethernet.mpy:
Update parameter types to use latency and bandwidth types
python/m5/objects/Platform.mpy:
this frequency isn't needed. We get it from the clock interrupt.
python/m5/objects/Tsunami.mpy:
The clock generator should hold the frequency
sim/eventq.hh:
Need to remove this assertion because the writeback event
queue is different from the CPU's event queue which can cause
this assertion to fail.
sim/process.cc:
Fix comment.
sim/system.hh:
Struct member to hold the boot CPU's frequency.
sim/universe.cc:
remove unneeded variable.
--HG--
extra : convert_revision : 51efe4041095234bf458d9b3b0d417f4cae16fdc
millisecond, microsecond, etc. so that the user can explicitly
convert between system ticks and time and know what sorts of
expensive operations are being used for that conversion.
arch/alpha/alpha_tru64_process.cc:
arch/alpha/pseudo_inst.cc:
dev/etherdump.cc:
dev/etherlink.cc:
dev/ns_gige.cc:
dev/sinic.cc:
dev/tsunami_io.cc:
dev/uart.cc:
sim/stat_control.cc:
sim/syscall_emul.hh:
Use the new variables for getting the event clock
dev/etherdump.hh:
delete variables that are no longer needed.
--HG--
extra : convert_revision : d95fc7d44909443e1b7952a24ef822ef051c7cf2
arch/alpha/alpha_tru64_process.cc:
sim/process.cc:
sim/process.hh:
Add an address range for the nxm
sim/syscall_emul.hh:
Check to make sure that if we have an nxm config space that the mmap hasn't grown into it
--HG--
extra : convert_revision : e479e5240080ae488080d228bafea488835d6e77
arch/alpha/alpha_tru64_process.cc:
g++ 3.4 fixes. Must cast to an int prior to returning value.
--HG--
extra : convert_revision : d8ccfd7aa7ca00d9bc2d76cff014b9f142d10640
arch/alpha/alpha_linux_process.cc:
arch/alpha/alpha_tru64_process.cc:
cpu/exec_context.hh:
sim/process.hh:
sim/syscall_emul.cc:
sim/syscall_emul.hh:
Changed all syscalls to use syscall return object
arch/alpha/isa_traits.hh:
Added syscall return object that packages return value and return
status into an object.
sim/process.cc:
renamed variable name to nm so base class function name() can be called
--HG--
extra : convert_revision : 6609c5ffecc9e3519d7a0cd160879fd21d54abfc
cpu/static_inst.hh:
Hand-merge. These execute functions are within an external file in the new CPU case.
--HG--
extra : convert_revision : a34112f471fa31bdd5bb53552ddd704b9571c110
1) Add fault_handler_delay param to FullCPU to wait N cycles after
committing faulting instruction before fetching fault handler.
2) Make hw_rei a serializing instruction (flushes pipe, basically).
arch/alpha/isa_desc:
Make hw_rei a serializing instruction (guarantees previous insts
complete before hw_rei will issue).
--HG--
extra : convert_revision : 704cef65b3869be9eee724055cedb22114a78359
instructions use it (instead of IntALU, as before). Default config
has a single non-pipelined 3-cycle unit. A bit conservative for the
ev6 (some are 1, some are 3).
arch/alpha/isa_desc:
Make hw_mfpr and hw_mtpr use IprAccessOp op class.
cpu/full_cpu/op_class.hh:
Add IprAccess.
--HG--
extra : convert_revision : d4103da3343a586936839e29981fd15d6930d442
particular binary machine instruction and should be immutable after
they are constructed.
cpu/simple_cpu/simple_cpu.hh:
Make StaticInst parameters const.
--HG--
extra : convert_revision : e535fa10c842ce173336323f39d9108c1847f8ba
SConscript:
Include new files.
arch/alpha/isa_desc:
Make the eaCompPtr and memAccPtr non-const so that execute() can be called on them.
arch/alpha/isa_traits.hh:
Add enum for total number of data registers.
arch/isa_parser.py:
base/traceflags.py:
Include new light-weight OoO CPU model.
cpu/base_dyn_inst.cc:
cpu/base_dyn_inst.hh:
Changes to abstract more away from the base dyn inst class.
cpu/beta_cpu/2bit_local_pred.cc:
cpu/beta_cpu/2bit_local_pred.hh:
cpu/beta_cpu/tournament_pred.cc:
cpu/beta_cpu/tournament_pred.hh:
Remove redundant SatCounter class.
cpu/beta_cpu/alpha_dyn_inst.cc:
cpu/beta_cpu/alpha_full_cpu.cc:
cpu/beta_cpu/alpha_full_cpu.hh:
cpu/beta_cpu/bpred_unit.cc:
cpu/beta_cpu/inst_queue.cc:
cpu/beta_cpu/mem_dep_unit.cc:
cpu/beta_cpu/ras.cc:
cpu/beta_cpu/rename_map.cc:
cpu/beta_cpu/rename_map.hh:
cpu/beta_cpu/rob.cc:
Fix for gcc-3.4
cpu/beta_cpu/alpha_dyn_inst.hh:
cpu/beta_cpu/alpha_dyn_inst_impl.hh:
Fixes for gcc-3.4.
Include more variables and functions that are specific to AlphaDynInst which were once in BaseDynInst.
cpu/beta_cpu/alpha_full_cpu_builder.cc:
Make params match the current params inherited from BaseCPU.
cpu/beta_cpu/alpha_full_cpu_impl.hh:
Fixes for gcc-3.4
cpu/beta_cpu/full_cpu.cc:
Use new params pointer in BaseCPU.
Fix for gcc-3.4.
cpu/beta_cpu/full_cpu.hh:
Use new params class from BaseCPU.
cpu/beta_cpu/iew_impl.hh:
Remove unused function.
cpu/simple_cpu/simple_cpu.cc:
Remove unused global variable.
cpu/static_inst.hh:
Include OoODynInst for new lightweight OoO CPU
--HG--
extra : convert_revision : 34d9f2e64ca0313377391e0d059bf09c040286fa
a faulting instruction is the fault handler, which appears as an independent
instruction to the timing model. New code will stall fetch and not fetch the
fault handler as long as there's a faulting instruction in the pipeline (i.e.,
the faulting inst has to commit first).
Also fix Ali's bad-address assertion that doesn't apply to full system.
Added some more debugging support in the process. Hopefully we'll move to the new
cpu model soon and we won't need it anymore.
arch/alpha/alpha_memory.cc:
Reorganize lookup() so we can trace the result of the lookup as well.
arch/alpha/isa_traits.hh:
Add NoopMachInst (so we can insert them in the pipeline on ifetch faults).
base/traceflags.py:
Replace "Dispatch" flag with "Pipeline" (since I added similar
DPRINTFs in other pipe stages).
cpu/exetrace.cc:
Change default for printing mis-speculated instructions to true (since
that's often what we want, and right now you can't change it from the
command line...).
--HG--
extra : convert_revision : a29a98a373076d62bbbb1d6f40ba51ecae436dbc
add dprintf on alignment faults
fix RR benchmark rcS script name
Add Dual test without rcS script
Update Monet to be closer to the real thing
Fix p4/monet configs
Add a way to read the DRIR register with at 32bit access for validation
SConscript:
build/SConstruct:
always use mysql if the libraries are installed
arch/alpha/alpha_memory.cc:
Add a DPRINTF to print alignment faults when they happen
dev/tsunami_cchip.cc:
Add a way to read the DRIR for validation.
--HG--
extra : convert_revision : 8c112c958f36b785390c46e70a889a79c6bea015
address calculation and memory access portions separately.
Not currently used by any CPU models, but Kevin says he needs this.
Also clean up handling of execution tracing for memory accesses
(move it all into isa_desc and out of CPU models).
Got rid of some ancient unused code too.
arch/alpha/isa_desc:
Add execute() methods to EAComp and MemAcc portions of memory
access instructions, to allow CPU models to execute the effective
address calculation and memory access portions separately.
Requires the execution context to remember the effective address
across the two invocations. Added setEA() and getEA() methods to
execution context to support this. A model that does not use the
split execution model can panic if these methods are called.
Also added hook to call traceData->setAddr() after EA computation
on any load or store operation.
arch/isa_parser.py:
Call traceData->setData() on memory writes (stores).
cpu/simple_cpu/simple_cpu.cc:
Get rid of unused code.
cpu/simple_cpu/simple_cpu.hh:
Add (non-functional) setEA() and getEA() methods for new
split memory access execution support.
--HG--
extra : convert_revision : bc2d2c758c4ca753812b9fa81f21038e55929ff0
arch/alpha/pseudo_inst.cc:
rename the context for consistency.
sim/pyconfig/m5config.py:
Add a ParamContext class so that param contexts work with
the new config stuff.
--HG--
extra : convert_revision : 3a6b583a25c86237baca7a2b4eccc9d12f86a384
which is evaluated slightly differently than in previous versions of gcc.
arch/alpha/alpha_linux_process.cc:
Alphabetize includes.
arch/alpha/vptr.hh:
Change the constants that are being used for alpha pagebytes to come from the ISA.
base/random.hh:
cpu/static_inst.cc:
sim/param.cc:
Fix up template syntax.
base/range.hh:
Include iostream for << operator.
base/res_list.hh:
base/statistics.hh:
cpu/simple_cpu/simple_cpu.hh:
cpu/static_inst.hh:
sim/eventq.hh:
sim/param.hh:
Fixup for templated code to resolve different scope lookup in gcc 3.4. This defers the lookup of the
function/variable until actual instantiation time by making it dependent on the templated class/function.
base/trace.cc:
Fix call to new.
base/trace.hh:
Fix up #define to have full path.
cpu/base_cpu.cc:
Fix up call to new.
dev/etherlink.hh:
dev/ns_gige.hh:
dev/sinic.hh:
Fixup for friend class/function declaration. g++ 3.4 no longer allows typedefs to be declared as
a friend class.
dev/pcidev.hh:
Fix up re-definition of access level to params.
kern/linux/linux_syscalls.hh:
kern/tru64/tru64_syscalls.hh:
Fix up header. Fix up template syntax.
sim/serialize.cc:
Include errno.h.
sim/startup.cc:
Change startupq. queue was getting destructed before all things had called ~StartupCallback(), which lead
to a segfault. This puts startupq in global space, and we allocate it ourselves. Other code may be similar
to this and may need changing in the future.
sim/syscall_emul.hh:
Include cpu/exec_context.hh and sim/process.hh, as forward declarations are no longer sufficient.
sim/universe.cc:
Include errno.h
--HG--
extra : convert_revision : e49d08ee89eb06a28351f02bafc028ca6652d5af
base/traceflags.py:
Merge extra new CPU flags
cpu/static_inst.hh:
Include all the execute functions in static_inst_impl.hh
--HG--
extra : convert_revision : 78eb753bf709d37400e7c2418bb35d842d7c3f63
all macros in ev5.hh to inline functions or constant typed
variables and make them follow our style while we're at it.
All of the stuff in this file actually belongs in the ISA
traits code, but this is a first step at getting things done
in the right manner.
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
arch/alpha/ev5.cc:
arch/alpha/isa_desc:
dev/ns_gige.cc:
kern/tru64/tru64_events.cc:
deal with changes in ev5.hh
arch/alpha/ev5.hh:
Macros are nasty, so let's get rid of them. Convert all
all macros to inline functions or constant typed variables.
Make them follow our style while we're at it.
All of the stuff in this file actually belongs in the ISA
traits code, but this is a first step at getting things done
in the right manner.
arch/alpha/isa_traits.hh:
move some of the ev5 specific code into the isa
arch/alpha/vtophys.cc:
base/remote_gdb.cc:
deal with isa addition
cpu/exec_context.hh:
be less isa specific and use the isa traits to figure out
what we can.
dev/alpha_console.cc:
dev/pciconfigall.cc:
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
dev/uart.cc:
deal with changes in ev5.hh
I don't believe this masking is actually necessary. We should
look at removing it later.
dev/ide_ctrl.cc:
sort #includes
deal with changes in ev5.hh
--HG--
extra : convert_revision : c8a3adf0a4b1d198aefe38fc38b295abf289b08a
checkInterrupts variable and use that to determine whether an interrupt
can occur on a given cycle.
arch/alpha/ev5.cc:
XC -> CPU (and xc -> CPU) since we're really talking about a CPU here
Don't use the global check_interrupts variable. Add a per-cpu
checkInterrupts variable and use that to determine whether an interrupt
can occur on a given cycle.
--HG--
extra : convert_revision : be4c0247e5834005c60a45796a222cffd327b64e
arch/alpha/isa_traits.hh:
Move defines to non full system code section so they can
be used elsewhere
cpu/simple_cpu/simple_cpu.cc:
Don't use magic numbers
cpu/simple_cpu/simple_cpu.hh:
simple format nit
--HG--
extra : convert_revision : b8d492218340d41ab9420c6ad1e81a197db1c132
functions instead of preprocessor macros.
arch/alpha/vtophys.cc:
use new constants, functions and structs to clean up the
vtophys code.
arch/alpha/vtophys.hh:
Clean up a little bit and make the protypes match new changes.
base/remote_gdb.cc:
dev/ide_disk.cc:
kern/tru64/tru64_events.cc:
use new constants from isa_traits.hh instead of ones from
old pmap.h
--HG--
extra : convert_revision : 5dce34e3b0c84ba72cefca34e5999b99898edcef
targetarch.
arch/alpha/alpha_memory.cc:
arch/alpha/arguments.cc:
arch/alpha/arguments.hh:
arch/alpha/faults.cc:
arch/alpha/isa_traits.hh:
arch/alpha/osfpal.cc:
arch/alpha/vtophys.cc:
arch/alpha/vtophys.hh:
in the arch/alpha directory we should use arch/alpha, not
targetarch. sort includes while we're here.
--HG--
extra : convert_revision : 99a71540e2997173db5c1072cef910a26acc75b2
instead of using symlink. The symlink broke scons's built-in include
dependency tacking.
Interestingly once it was fixed scons discovered two circular dependency
problems which are also fixed now.
SConscript:
Make targetarch directory in build tree and copy arch/alpha files to it
instead of using symlink. The symlink broke scons's built-in include
dependency tacking.
arch/alpha/ev5.hh:
Get rid of circular #include dependence.
kern/kernel_stats.cc:
Add needed header file.
kern/linux/linux_syscalls.hh:
kern/tru64/tru64_syscalls.hh:
Replace targetarch/syscalls.hh with single template class declaration.
--HG--
extra : convert_revision : b8551623c1d441c6eb8d0651387e97e373128814
arch/alpha/vtophys.cc:
PGOFSET -> ALPHA_PGOFSET to avoid include file problems
base/callback.hh:
Added a class to create a callback from a function
base/intmath.hh:
make FloorLog2 inlined
dev/pcidev.cc:
more work in getting pciconfig space happy with different endiannesses
dev/uart.cc:
used an incorrect size for write uint64_t instead of uint8_t
sim/system.cc:
when writing things into system data structures we need to pay
attention to endianness
--HG--
extra : convert_revision : 52f441b5789c45db30ef2f6fd4975cbc7323a381
Also change to ref counted DynInst.
SConscript:
Add branch predictor, BTB, load store queue, and storesets.
arch/isa_parser.py:
Specify the template parameter for AlphaDynInst
base/traceflags.py:
Add load store queue, store set, and mem dependence unit to the
list of trace flags.
cpu/base_dyn_inst.cc:
Change formating, add in debug statement.
cpu/base_dyn_inst.hh:
Change DynInst to be RefCounted, add flag to clear whether or not this
instruction can commit. This is likely to be removed in the future.
cpu/beta_cpu/alpha_dyn_inst.cc:
AlphaDynInst has been changed to be templated, so now this CC file
is just used to force instantiations of AlphaDynInst.
cpu/beta_cpu/alpha_dyn_inst.hh:
Changed AlphaDynInst to be templated on Impl. Removed some unnecessary
functions.
cpu/beta_cpu/alpha_full_cpu.cc:
AlphaFullCPU has been changed to be templated, so this CC file is now
just used to force instantation of AlphaFullCPU.
cpu/beta_cpu/alpha_full_cpu.hh:
Change AlphaFullCPU to be templated on Impl.
cpu/beta_cpu/alpha_impl.hh:
Update it to reflect AlphaDynInst and AlphaFullCPU being templated
on Impl. Also removed time buffers from here, as they are really
a part of the CPU and are thus in the CPU policy now.
cpu/beta_cpu/alpha_params.hh:
Make AlphaSimpleParams inherit from the BaseFullCPU so that it doesn't
need to specifically declare any parameters that are already in the
BaseFullCPU.
cpu/beta_cpu/comm.hh:
Changed the structure of the time buffer communication structs. Now
they include the size of the packet of instructions it is sending.
Added some parameters to the backwards communication struct, mainly
for squashing.
cpu/beta_cpu/commit.hh:
Update typenames to reflect change in location of time buffer structs.
Update DynInst to DynInstPtr (it is refcounted now).
cpu/beta_cpu/commit_impl.hh:
Formatting changes mainly. Also sends back proper information
on branch mispredicts so that the bpred unit can update itself.
Updated behavior for non-speculative instructions (stores, any
other non-spec instructions): once they reach the head of the ROB,
the ROB signals back to the IQ that it can go ahead and issue the
non-speculative instruction. The instruction itself is updated so that
commit won't try to commit it again until it is done executing.
cpu/beta_cpu/cpu_policy.hh:
Added branch prediction unit, mem dependence prediction unit, load
store queue. Moved time buffer structs from AlphaSimpleImpl to here.
cpu/beta_cpu/decode.hh:
Changed typedefs to reflect change in location of time buffer structs
and also the change from DynInst to ref counted DynInstPtr.
cpu/beta_cpu/decode_impl.hh:
Continues to buffer instructions even while unblocking now. Changed
how it loops through groups of instructions so it can properly block
during the middle of a group of instructions.
cpu/beta_cpu/fetch.hh:
Changed typedefs to reflect change in location of time buffer structs
and the change to ref counted DynInsts. Also added in branch
brediction unit.
cpu/beta_cpu/fetch_impl.hh:
Add in branch prediction. Changed how fetch checks inputs and its
current state to make for easier logic.
cpu/beta_cpu/free_list.cc:
Changed int regs and float regs to logically use one flat namespace.
Future change will be moving them to a single scoreboard to conserve
space.
cpu/beta_cpu/free_list.hh:
Mostly debugging statements. Might be removed for performance in future.
cpu/beta_cpu/full_cpu.cc:
Added in some debugging statements. Updated BaseFullCPU to take
a params object.
cpu/beta_cpu/full_cpu.hh:
Added params class within BaseCPU that other param classes will be
able to inherit from. Updated typedefs to reflect change in location
of time buffer structs and ref counted DynInst.
cpu/beta_cpu/iew.hh:
Updated typedefs to reflect change in location of time buffer structs
and use of ref counted DynInsts.
cpu/beta_cpu/iew_impl.hh:
Added in load store queue, updated iew to be able to execute non-
speculative instructions, instead of having them execute in commit.
cpu/beta_cpu/inst_queue.hh:
Updated change to ref counted DynInsts. Changed inst queue to hold
non-speculative instructions as well, which are issued only when
commit signals backwards that a nonspeculative instruction is at
the head of the ROB.
cpu/beta_cpu/inst_queue_impl.hh:
Updated to allow for non-speculative instructions to be in the inst
queue. Also added some debug functions.
cpu/beta_cpu/regfile.hh:
Added debugging statements, changed formatting.
cpu/beta_cpu/rename.hh:
Updated typedefs, added some functions to clean up code.
cpu/beta_cpu/rename_impl.hh:
Moved some code into functions to make it easier to read.
cpu/beta_cpu/rename_map.cc:
Changed int and float reg behavior to use a single flat namespace. In
the future, the rename maps can be combined to a single rename map to
save space.
cpu/beta_cpu/rename_map.hh:
Added destructor.
cpu/beta_cpu/rob.hh:
Updated it with change from DynInst to ref counted DynInst.
cpu/beta_cpu/rob_impl.hh:
Formatting, updated to use ref counted DynInst.
cpu/static_inst.hh:
Updated forward declaration for AlphaDynInst now that it is templated.
--HG--
extra : convert_revision : 1045f240ee9b6a4bd368e1806aca029ebbdc6dd3
code
arch/alpha/alpha_memory.cc:
Fixed unaligned trap faults
arch/alpha/ev5.cc:
little more verbose faulting information
kern/linux/linux_system.cc:
more descriptive errors, and the correct offsets from symbols
sim/system.cc:
load local pal symbols
--HG--
extra : convert_revision : 0c81badf77321d5e1a060dcae2d42204e5a1fc84
arch/alpha/isa_desc:
whitespace fix.
cpu/simple_cpu/simple_cpu.cc:
Add support to make sure we don't get alignment faults in copies. Warn if we go over an 8k page boundary.
--HG--
extra : convert_revision : 98b38da86a66215d80ea9eb6e6f1f68ee573cb57
arch/alpha/ev5.cc:
set the mode explictly rather than having a bool user/notuser
cpu/simple_cpu/simple_cpu.hh:
there is no class Kernel
kern/kernel_stats.cc:
use cpu_mode_num
kern/kernel_stats.hh:
add interrupt mode and use cpu_mode_num rather than constant
kern/linux/linux_system.cc:
kern/linux/linux_system.hh:
kern/system_events.cc:
kern/system_events.hh:
add events to change the mode to/from interrupt
sim/system.cc:
sim/system.hh:
add a pal symbol table
--HG--
extra : convert_revision : 9d30e826b72122062a5ea12d094f94760e75c66a
SConscript:
Added new CPU files to build.
arch/alpha/isa_desc:
Changed rduniq and wruniq to be nonspeculative because the uniq register is not renamed.
arch/isa_parser.py:
Added new CPU exec method.
base/statistics.hh:
Minor change for namespace conflict. Probably can change back one the new CPU files are cleaned up.
base/traceflags.py:
Added new CPU trace flags.
cpu/static_inst.hh:
Changed static inst to use a file that defines the execute functions.
--HG--
extra : convert_revision : bd4ce34361308280168324817fc1258dd253e519
single place so it's easier to work with.
- Add support for binning kernel/user/idle time separately from
lisa's binning stuff, but make the two compatible.
- KernelStats used to directly implement the pImpl idiom, but
it makes more sense to just remove the level of indirection and
make the exec context have a pointer to the stats.
- Factor common code out of LinuxSystem and Tru64System and put
it into the System base class. While doing that, make all
constructors take a pointer to a parameter struct instead of
naming the parameters individually to make it much easier to add
parameters to these classes.
SConscript:
Move the function tracking and binning stuff around.
arch/alpha/ev5.cc:
kernelStats is now a pointer
arch/alpha/pseudo_inst.cc:
kernelStats is now a pointer
the parameters to the system have been moved into their own
struct
base/trace.hh:
provide a little functor class for wrapping a string that
can allow you to define name() in any scope very simply
for use with DPRINTF
cpu/base_cpu.cc:
New order of arguments for consistency.
cpu/exec_context.cc:
kernelStats no longer has the level of indirection in it,
execContext has the indirection now. so, kernelStats is a pointer.
We also need a pointer to the kernelBinning stuff from the system
and we need to figure out if we want to do binning or not.
Move a whole bunch of code into kern_binning.cc so it's all
in the same place.
cpu/exec_context.hh:
We want pointers to the kernel binning/stats stuff and we'll
have the exec_context and system have the level of indirection
instead of having the extra layer in the kernel stats class.
cpu/simple_cpu/simple_cpu.cc:
call through the exec context to do the special binning
stuff.
kern/kernel_stats.cc:
kern/kernel_stats.hh:
Re-organize the stats stuff and remove the level of indirection
(that was there to simplify building) and move the binning stuff
into its own class/file.
kern/linux/linux_system.cc:
kern/linux/linux_system.hh:
kern/tru64/tru64_system.cc:
kern/tru64/tru64_system.hh:
sim/system.cc:
sim/system.hh:
move lots of common system code into the base system class so
that it can be shared between linux, tru64, and whatever else
we decide to support in the future.
Make the constructor take a pointer to a parameter struct so that
it is easier to pass parameters to the parent.
kern/system_events.cc:
move the majority of the binning code into the Kernel::Binning class
in the kern_binning file
kern/system_events.hh:
FnEvents only need to know the bin
create the Idle start event to find the PCBB of the idle
process when it starts.
kern/tru64/tru64_events.cc:
memCtrl -> memctrl
sim/process.cc:
sim/process.hh:
re-order args for consistency
--HG--
extra : convert_revision : 86cb39738c41fcd680f2aad125c9dde000227b2b
a p4 memory/cpu config
arch/alpha/alpha_memory.cc:
Added code to fault on an unaligned access
arch/alpha/isa_desc:
arch/alpha/pseudo_inst.cc:
arch/alpha/pseudo_inst.hh:
Added m5debug break and m5switchcpu (the latter doesn't work)
--HG--
extra : convert_revision : 409e73adb151600a4fea49f35bf6f503f66fa916
arch/alpha/ev5.hh:
Added max address PAL code can be at
arch/alpha/vtophys.cc:
Check max address pal can be at so we don't do the wrong conversion
if gdb asks for an unaligned access.
--HG--
extra : convert_revision : b44f6a8fcd8582337a7d4033f28137c7e718a6a8
a realworld file.
arch/alpha/isa_desc:
arch/alpha/pseudo_inst.hh:
implement the readfile pseudo instruction that will read a
chunk of a realworld file.
arch/alpha/pseudo_inst.cc:
implement the readfile pseudo instruction that will read a
chunk of a realworld file. The filename is a per system
parameter and comes from the system itself.
kern/linux/linux_system.cc:
sim/system.hh:
Create a per-system readfile parameter for use by the readfile
pseudo instruction. That way each system can get its own file.
--HG--
extra : convert_revision : 941b3a3e20702a6252b219ca66a6d90da2944c50
from the simulator into the simulatee
kern/tru64/dump_mbuf.cc:
rename CopyData -> CopyOut
--HG--
extra : convert_revision : e3ef27a5762dfc495dcb84a372470464c27557d2
arch/alpha/ev5.cc:
cpu/simple_cpu/simple_cpu.cc:
update for new event interface
base/stats/events.cc:
implement the ignore event function which matches sim objects from which
to ignore events.
Make insert event like insert data and make it able to insert many
events in a single transaction with the database.
base/stats/events.hh:
Make it possible to ignore events
sim/sim_object.cc:
make recordEvent a member function of SimObject to implement
the ignore function easily
sim/sim_object.hh:
implement the ignore event stuff in the sim object. This is a
bit of a hack, but an easy place to put it.
--HG--
extra : convert_revision : ba3f25a14ad03662c53fb35514860d69be8cd4f0
arch/alpha/alpha_memory.cc:
arch/alpha/ev5.hh:
Ifdefed TLASER code
arch/alpha/vtophys.cc:
added back some code andrew removed and couldn't remember why.
--HG--
extra : convert_revision : f00d255f7a8a7bdb6e74f061dd014188e3b39e73
Mostly a matter of keeping prefetches to invalid addrs
from messing up VM IPRs. Also discovered that wh64s were
not being treated as prefetches, when they really should be
(for the most part, anyway).
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
- Get rid of intrlock flag for locking VM fault regs (a la EV5);
instead, just don't update regs on VPTE loads (a la EV6).
- Add NO_FAULT MemReq flag to indicate references that should not
cause page faults (i.e., prefetches).
arch/alpha/ev5.cc:
- Get rid of intrlock flag for locking VM fault regs (a la EV5);
instead, just don't update regs on VPTE loads (a la EV6).
- Add Fault trace flag.
arch/alpha/isa_desc:
- Add NO_FAULT MemReq flag to indicate references that should not
cause page faults (i.e., prefetches).
- Mark wh64 as a "data prefetch" instruction so it gets controlled
properly by the FullCPU data prefetch control switch.
- Align wh64 EA in decoder so issue stage doesn't need to worry about it.
arch/alpha/isa_traits.hh:
- Get rid of intrlock flag for locking VM fault regs (a la EV5);
instead, just don't update regs on VPTE loads (a la EV6).
base/traceflags.py:
- Add Fault trace flag.
cpu/simple_cpu/simple_cpu.hh:
- Pass MemReq flags to writeHint() operation.
cpu/static_inst.hh:
Update comment re: prefetches.
--HG--
extra : convert_revision : 62e466b0f4c0ff9961796270fa2e371ec24bcbb6
and started cleaning up config files.
arch/alpha/isa_desc:
Made implementation of cttz and ctlz more compact
base/remote_gdb.cc:
Added comment about PALcode debugger accesses
dev/baddev.cc:
dev/baddev.hh:
dev/ide_ctrl.cc:
dev/ide_ctrl.hh:
dev/pciconfigall.cc:
dev/pciconfigall.hh:
dev/tsunami_cchip.cc:
dev/tsunami_cchip.hh:
dev/tsunami_io.cc:
dev/tsunami_io.hh:
dev/tsunami_pchip.cc:
dev/tsunami_pchip.hh:
dev/tsunami_uart.cc:
dev/tsunami_uart.hh:
Cleaned up includes and changed device from FunctionalMemory to
PioDevice for detailed boot
dev/ns_gige.cc:
The ethernet dev uses two BARs, and the first bars size was being set
incorrectly.
dev/tsunamireg.h:
I don't know why we were using the superpage as the PCI memory addr.
Changed and works correctly with detailed boot.
--HG--
extra : convert_revision : b535e76612cb90b544305dc1aa8c5e0e774564bd
