file name changes ... minor ISA changes
arch/mips/isa/base.isa:
restoring base.isa file ...
arch/mips/isa/formats/basic.isa:
add c++ emacs header
arch/mips/isa/formats/branch.isa:
added branch likely format
arch/mips/isa/formats/int.isa:
small change to python code
--HG--
extra : convert_revision : defd592abb1a724f5f88b19c197b858420e92d17
This commit is contained in:
Korey Sewell
parent
a0cdf213ab
commit
7c9ea671af
4 changed files with 79 additions and 90 deletions
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@ -1,18 +1,21 @@
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// -*- mode:c++ -*-
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////////////////////////////////////////////////////////////////////
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//
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// Base class for sparc instructions, and some support functions
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// Base class for MIPS instructions, and some support functions
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//
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//Outputs to decoder.hh
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output header {{
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/**
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* Base class for all SPARC static instructions.
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*/
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class SparcStaticInst : public StaticInst<SPARCISA>
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class MipsStaticInst : public StaticInst<MIPSISA>
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{
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protected:
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// Constructor.
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SparcStaticInst(const char *mnem, MachInst _machInst, OpClass __opClass)
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MipsStaticInst(const char *mnem, MachInst _machInst, OpClass __opClass)
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: StaticInst<SPARCISA>(mnem, _machInst, __opClass)
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{
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}
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@ -20,12 +23,12 @@ output header {{
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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bool passesCondition(struct {uint8_t c:1; uint8_t v:1; uint8_t z:1; uint8_t n:1} codes, uint8_t condition);
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}};
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//Ouputs to decoder.cc
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output decoder {{
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std::string SparcStaticInst::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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std::string MipsStaticInst::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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std::stringstream ss;
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@ -56,27 +59,5 @@ output decoder {{
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return ss.str();
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}
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bool passesCondition(struct {uint8_t c:1; uint8_t v:1; uint8_t z:1; uint8_t n:1} codes, uint8_t condition)
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{
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switch(condition)
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{
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case 0b1000: return true;
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case 0b0000: return false;
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case 0b1001: return !codes.z;
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case 0b0001: return codes.z;
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case 0b1010: return !(codes.z | (codes.n ^ codes.v));
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case 0b0010: return codes.z | (codes.n ^ codes.v);
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case 0b1011: return !(codes.n ^ codes.v);
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case 0b0011: return (codes.n ^ codes.v);
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case 0b1100: return !(codes.c | codes.z);
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case 0b0100: return (codes.c | codes.z);
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case 0b1101: return !codes.c;
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case 0b0101: return codes.c;
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case 0b1110: return !codes.n;
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case 0b0110: return codes.n;
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case 0b1111: return !codes.v;
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case 0b0111: return codes.v;
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}
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}
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}};
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@ -1,3 +1,4 @@
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// -*- mode:c++ -*-
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// Declarations for execute() methods.
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def template BasicExecDeclare {{
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@ -1,30 +1,9 @@
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// -*- mode:c++ -*-
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e// -*- mode:c++ -*-
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// Copyright (c) 2003-2005 The Regents of The University of Michigan
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// All rights reserved.
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////////////////////////////////////////////////////////////////////
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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// Control transfer instructions
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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output header {{
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@ -37,18 +16,19 @@ output header {{
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* where the disassembly string includes the target address (which
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* may depend on the PC and/or symbol table).
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*/
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class PCDependentDisassembly : public AlphaStaticInst
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class PCDependentDisassembly : public MipsStaticInst
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{
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protected:
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/// Cached program counter from last disassembly
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mutable Addr cachedPC;
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/// Cached symbol table pointer from last disassembly
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mutable const SymbolTable *cachedSymtab;
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/// Constructor
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PCDependentDisassembly(const char *mnem, MachInst _machInst,
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OpClass __opClass)
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: AlphaStaticInst(mnem, _machInst, __opClass),
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: MipsStaticInst(mnem, _machInst, __opClass),
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cachedPC(0), cachedSymtab(0)
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{
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}
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@ -64,13 +44,36 @@ output header {{
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class Branch : public PCDependentDisassembly
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{
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protected:
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/// Displacement to target address (signed).
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int32_t disp;
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/// target address (signed) Displacement .
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int32_t targetOffset;
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/// Constructor.
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Branch(const char *mnem, MachInst _machInst, OpClass __opClass)
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: PCDependentDisassembly(mnem, _machInst, __opClass),
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disp(BRDISP << 2)
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targetOffset(OFFSET << 2)
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{
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}
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Addr branchTarget(Addr branchPC) const;
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std::string
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generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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/**
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* Base class for branches (PC-relative control transfers),
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* conditional or unconditional.
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*/
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class BranchLikely : public PCDependentDisassembly
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{
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protected:
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/// target address (signed) Displacement .
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int32_t targetOffset;
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/// Constructor.
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Branch(const char *mnem, MachInst _machInst, OpClass __opClass)
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: PCDependentDisassembly(mnem, _machInst, __opClass),
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targetOffset(OFFSET << 2)
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{
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}
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@ -82,7 +85,7 @@ output header {{
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/**
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* Base class for jumps (register-indirect control transfers). In
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* the Alpha ISA, these are always unconditional.
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* the Mips ISA, these are always unconditional.
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*/
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class Jump : public PCDependentDisassembly
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{
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@ -95,7 +98,7 @@ output header {{
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/// Constructor
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Jump(const char *mnem, MachInst _machInst, OpClass __opClass)
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: PCDependentDisassembly(mnem, _machInst, __opClass),
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disp(BRDISP)
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disp(OFFSET)
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{
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}
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@ -204,12 +207,12 @@ output decoder {{
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}};
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def template JumpOrBranchDecode {{
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return (RA == 31)
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? (StaticInst<AlphaISA> *)new %(class_name)s(machInst)
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: (StaticInst<AlphaISA> *)new %(class_name)sAndLink(machInst);
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return (RD == 0)
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? (StaticInst<MipsISA> *)new %(class_name)s(machInst)
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: (StaticInst<MipsISA> *)new %(class_name)sAndLink(machInst);
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}};
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def format CondBranch(code) {{
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def format Branch(code) {{
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code = 'bool cond;\n' + code + '\nif (cond) NPC = NPC + disp;\n';
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iop = InstObjParams(name, Name, 'Branch', CodeBlock(code),
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('IsDirectControl', 'IsCondControl'))
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@ -219,31 +222,18 @@ def format CondBranch(code) {{
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exec_output = BasicExecute.subst(iop)
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}};
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let {{
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def UncondCtrlBase(name, Name, base_class, npc_expr, flags):
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# Declare basic control transfer w/o link (i.e. link reg is R31)
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nolink_code = 'NPC = %s;\n' % npc_expr
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nolink_iop = InstObjParams(name, Name, base_class,
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CodeBlock(nolink_code), flags)
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header_output = BasicDeclare.subst(nolink_iop)
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decoder_output = BasicConstructor.subst(nolink_iop)
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exec_output = BasicExecute.subst(nolink_iop)
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# Generate declaration of '*AndLink' version, append to decls
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link_code = 'Ra = NPC & ~3;\n' + nolink_code
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link_iop = InstObjParams(name, Name + 'AndLink', base_class,
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CodeBlock(link_code), flags)
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header_output += BasicDeclare.subst(link_iop)
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decoder_output += BasicConstructor.subst(link_iop)
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exec_output += BasicExecute.subst(link_iop)
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# need to use link_iop for the decode template since it is expecting
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# the shorter version of class_name (w/o "AndLink")
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return (header_output, decoder_output,
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JumpOrBranchDecode.subst(nolink_iop), exec_output)
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def format BranchLikely(code) {{
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code = 'bool cond;\n' + code + '\nif (cond) NPC = NPC + disp;\n';
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iop = InstObjParams(name, Name, 'Branch', CodeBlock(code),
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('IsDirectControl', 'IsCondControl'))
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header_output = BasicDeclare.subst(iop)
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decoder_output = BasicConstructor.subst(iop)
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decode_block = BasicDecode.subst(iop)
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exec_output = BasicExecute.subst(iop)
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}};
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def format UncondBranch(*flags) {{
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flags += ('IsUncondControl', 'IsDirectControl')
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(header_output, decoder_output, decode_block, exec_output) = \
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@ -1,8 +1,11 @@
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// -*- mode:c++ -*-
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////////////////////////////////////////////////////////////////////
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//
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// Integer operate instructions
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//
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//Outputs to decoder.hh
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output header {{
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/**
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* Base class for integer operations.
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@ -12,7 +15,7 @@ output header {{
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protected:
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/// Constructor
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IntegerOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
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IntOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
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MipsStaticInst(mnem, _machInst, __opClass)
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{
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}
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@ -26,7 +29,7 @@ output header {{
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uint16_t imm;
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/// Constructor
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IntegerOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
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IntImmOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
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MipsStaticInst(mnem, _machInst, __opClass),imm(INTIMM)
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{
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}
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@ -36,6 +39,7 @@ output header {{
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}};
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//Outputs to decoder.cc
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output decoder {{
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std::string IntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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}
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}};
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// Primary format for integer operate instructions:
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// integer & FP operate instructions use Rd as dest, so check for
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// Rd == 0 to detect nops
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def template OperateNopCheckDecode {{
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{
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MipsStaticInst *i = new %(class_name)s(machInst);
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if (RD == 0) {
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i = makeNop(i);
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}
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return i;
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}
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}};
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//Used by decoder.isa
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def format IntOp(code, *opt_flags) {{
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orig_code = code
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cblk = CodeBlock(code)
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# Figure out if we are creating a IntImmOp or a IntOp
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# by looking at the instruction name
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iop = InstObjParams(name, Name, 'IntOp', cblk, opt_flags)
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strlen = len(name)
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if name[strlen-1] == 'i' or name[strlen-2:] == 'iu':
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iop = InstObjParams(name, Name, 'IntOp', cblk, opt_flags)
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else:
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iop = InstObjParams(name, Name, 'IntImmOp', cblk, opt_flags)
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iop = InstObjParams(name, Name, 'IntImmOp', cblk, opt_flags)
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header_output = BasicDeclare.subst(iop)
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decoder_output = BasicConstructor.subst(iop)
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