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Merge gblack@m5.eecs.umich.edu:/bk/multiarch

Browse source 
into  ewok.(none):/home/gblack/m5/multiarch

--HG--
extra : convert_revision : d8626acb2686e123ad0bb6cf94e85c992657470d
This commit is contained in:
Gabe Black 2006-02-16 01:25:48 -05:00
parent 7f17f1f2df 10c79efe55
commit b161d2a731
59 changed files with 798 additions and 616 deletions
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1
SConscript
View file

@ -209,6 +209,7 @@ base_sources = Split('''
sim/configfile.cc
sim/debug.cc
sim/eventq.cc
sim/faults.cc
sim/main.cc
sim/param.cc
sim/profile.cc

38
arch/alpha/alpha_memory.cc
View file

@ -303,7 +303,7 @@ AlphaITB::fault(Addr pc, ExecContext *xc) const
}
Fault
Fault *
AlphaITB::translate(MemReqPtr &req) const
{
InternalProcReg *ipr = req->xc->regs.ipr;
@ -312,7 +312,7 @@ AlphaITB::translate(MemReqPtr &req) const
// strip off PAL PC marker (lsb is 1)
req->paddr = (req->vaddr & ~3) & PAddrImplMask;
hits++;
return No_Fault;
return NoFault;
}
if (req->flags & PHYSICAL) {
@ -322,7 +322,7 @@ AlphaITB::translate(MemReqPtr &req) const
if (!validVirtualAddress(req->vaddr)) {
fault(req->vaddr, req->xc);
acv++;
return ITB_Acv_Fault;
return ItbAcvFault;
}
@ -339,7 +339,7 @@ AlphaITB::translate(MemReqPtr &req) const
AlphaISA::mode_kernel) {
fault(req->vaddr, req->xc);
acv++;
return ITB_Acv_Fault;
return ItbAcvFault;
}
req->paddr = req->vaddr & PAddrImplMask;
@ -360,7 +360,7 @@ AlphaITB::translate(MemReqPtr &req) const
if (!pte) {
fault(req->vaddr, req->xc);
misses++;
return ITB_Fault_Fault;
return ItbPageFault;
}
req->paddr = (pte->ppn << AlphaISA::PageShift) +
@ -371,7 +371,7 @@ AlphaITB::translate(MemReqPtr &req) const
// instruction access fault
fault(req->vaddr, req->xc);
acv++;
return ITB_Acv_Fault;
return ItbAcvFault;
}
hits++;
@ -380,11 +380,11 @@ AlphaITB::translate(MemReqPtr &req) const
// check that the physical address is ok (catch bad physical addresses)
if (req->paddr & ~PAddrImplMask)
return Machine_Check_Fault;
return MachineCheckFault;
checkCacheability(req);
return No_Fault;
return NoFault;
}
///////////////////////////////////////////////////////////////////////
@ -493,7 +493,7 @@ AlphaDTB::fault(MemReqPtr &req, uint64_t flags) const
}
}
Fault
Fault *
AlphaDTB::translate(MemReqPtr &req, bool write) const
{
RegFile *regs = &req->xc->regs;
@ -511,7 +511,7 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const
fault(req, write ? MM_STAT_WR_MASK : 0);
DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->vaddr,
req->size);
return Alignment_Fault;
return AlignmentFault;
}
if (pc & 0x1) {
@ -530,7 +530,7 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const
MM_STAT_ACV_MASK);
if (write) { write_acv++; } else { read_acv++; }
return DTB_Fault_Fault;
return DtbPageFault;
}
// Check for "superpage" mapping
@ -547,7 +547,7 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const
fault(req, ((write ? MM_STAT_WR_MASK : 0) |
MM_STAT_ACV_MASK));
if (write) { write_acv++; } else { read_acv++; }
return DTB_Acv_Fault;
return DtbAcvFault;
}
req->paddr = req->vaddr & PAddrImplMask;
@ -575,7 +575,7 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const
fault(req, (write ? MM_STAT_WR_MASK : 0) |
MM_STAT_DTB_MISS_MASK);
if (write) { write_misses++; } else { read_misses++; }
return (req->flags & VPTE) ? Pdtb_Miss_Fault : Ndtb_Miss_Fault;
return (req->flags & VPTE) ? (Fault *)PDtbMissFault : (Fault *)NDtbMissFault;
}
req->paddr = (pte->ppn << AlphaISA::PageShift) +
@ -588,25 +588,25 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const
MM_STAT_ACV_MASK |
(pte->fonw ? MM_STAT_FONW_MASK : 0));
write_acv++;
return DTB_Fault_Fault;
return DtbPageFault;
}
if (pte->fonw) {
fault(req, MM_STAT_WR_MASK |
MM_STAT_FONW_MASK);
write_acv++;
return DTB_Fault_Fault;
return DtbPageFault;
}
} else {
if (!(pte->xre & MODE2MASK(mode))) {
fault(req, MM_STAT_ACV_MASK |
(pte->fonr ? MM_STAT_FONR_MASK : 0));
read_acv++;
return DTB_Acv_Fault;
return DtbAcvFault;
}
if (pte->fonr) {
fault(req, MM_STAT_FONR_MASK);
read_acv++;
return DTB_Fault_Fault;
return DtbPageFault;
}
}
}
@ -619,11 +619,11 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const
// check that the physical address is ok (catch bad physical addresses)
if (req->paddr & ~PAddrImplMask)
return Machine_Check_Fault;
return MachineCheckFault;
checkCacheability(req);
return No_Fault;
return NoFault;
}
AlphaISA::PTE &

5
arch/alpha/alpha_memory.hh
View file

@ -32,6 +32,7 @@
#include <map>
#include "arch/alpha/isa_traits.hh"
#include "arch/alpha/faults.hh"
#include "base/statistics.hh"
#include "mem/mem_req.hh"
#include "sim/sim_object.hh"
@ -93,7 +94,7 @@ class AlphaITB : public AlphaTLB
AlphaITB(const std::string &name, int size);
virtual void regStats();
Fault translate(MemReqPtr &req) const;
Fault * translate(MemReqPtr &req) const;
};
class AlphaDTB : public AlphaTLB
@ -119,7 +120,7 @@ class AlphaDTB : public AlphaTLB
AlphaDTB(const std::string &name, int size);
virtual void regStats();
Fault translate(MemReqPtr &req, bool write) const;
Fault * translate(MemReqPtr &req, bool write) const;
};
#endif // __ALPHA_MEMORY_HH__

81
arch/alpha/ev5.cc
View file

@ -76,7 +76,7 @@ AlphaISA::initCPU(RegFile *regs)
// CPU comes up with PAL regs enabled
swap_palshadow(regs, true);
regs->pc = regs->ipr[IPR_PAL_BASE] + fault_addr[Reset_Fault];
regs->pc = regs->ipr[IPR_PAL_BASE] + fault_addr(ResetFault);
regs->npc = regs->pc + sizeof(MachInst);
}
@ -84,25 +84,16 @@ AlphaISA::initCPU(RegFile *regs)
//
// alpha exceptions - value equals trap address, update with MD_FAULT_TYPE
//
Addr
AlphaISA::fault_addr[Num_Faults] = {
0x0000, /* No_Fault */
0x0001, /* Reset_Fault */
0x0401, /* Machine_Check_Fault */
0x0501, /* Arithmetic_Fault */
0x0101, /* Interrupt_Fault */
0x0201, /* Ndtb_Miss_Fault */
0x0281, /* Pdtb_Miss_Fault */
0x0301, /* Alignment_Fault */
0x0381, /* DTB_Fault_Fault */
0x0381, /* DTB_Acv_Fault */
0x0181, /* ITB_Miss_Fault */
0x0181, /* ITB_Fault_Fault */
0x0081, /* ITB_Acv_Fault */
0x0481, /* Unimplemented_Opcode_Fault */
0x0581, /* Fen_Fault */
0x2001, /* Pal_Fault */
0x0501, /* Integer_Overflow_Fault: maps to Arithmetic_Fault */
const Addr
AlphaISA::fault_addr(Fault * fault)
{
//Check for the system wide faults
if(fault == NoFault) return 0x0000;
else if(fault == MachineCheckFault) return 0x0401;
else if(fault == AlignmentFault) return 0x0301;
else if(fault == FakeMemFault) return 0x0000;
//Deal with the alpha specific faults
return ((AlphaFault*)fault)->vect;
};
const int AlphaISA::reg_redir[AlphaISA::NumIntRegs] = {
@ -168,7 +159,7 @@ AlphaISA::processInterrupts(CPU *cpu)
if (ipl && ipl > ipr[IPR_IPLR]) {
ipr[IPR_ISR] = summary;
ipr[IPR_INTID] = ipl;
cpu->trap(Interrupt_Fault);
cpu->trap(InterruptFault);
DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
ipr[IPR_IPLR], ipl, summary);
}
@ -187,25 +178,25 @@ AlphaISA::zeroRegisters(CPU *cpu)
}
void
ExecContext::ev5_trap(Fault fault)
ExecContext::ev5_trap(Fault * fault)
{
DPRINTF(Fault, "Fault %s at PC: %#x\n", FaultName(fault), regs.pc);
cpu->recordEvent(csprintf("Fault %s", FaultName(fault)));
DPRINTF(Fault, "Fault %s at PC: %#x\n", fault ? fault->name : "none", regs.pc);
cpu->recordEvent(csprintf("Fault %s", fault ? fault->name : "none"));
assert(!misspeculating());
kernelStats->fault(fault);
if (fault == Arithmetic_Fault)
if (fault == ArithmeticFault)
panic("Arithmetic traps are unimplemented!");
AlphaISA::InternalProcReg *ipr = regs.ipr;
// exception restart address
if (fault != Interrupt_Fault || !inPalMode())
if (fault != InterruptFault || !inPalMode())
ipr[AlphaISA::IPR_EXC_ADDR] = regs.pc;
if (fault == Pal_Fault || fault == Arithmetic_Fault /* ||
fault == Interrupt_Fault && !inPalMode() */) {
if (fault == PalFault || fault == ArithmeticFault /* ||
fault == InterruptFault && !inPalMode() */) {
// traps... skip faulting instruction
ipr[AlphaISA::IPR_EXC_ADDR] += 4;
}
@ -213,22 +204,22 @@ ExecContext::ev5_trap(Fault fault)
if (!inPalMode())
AlphaISA::swap_palshadow(&regs, true);
regs.pc = ipr[AlphaISA::IPR_PAL_BASE] + AlphaISA::fault_addr[fault];
regs.pc = ipr[AlphaISA::IPR_PAL_BASE] + AlphaISA::fault_addr(fault);
regs.npc = regs.pc + sizeof(MachInst);
}
void
AlphaISA::intr_post(RegFile *regs, Fault fault, Addr pc)
AlphaISA::intr_post(RegFile *regs, Fault * fault, Addr pc)
{
InternalProcReg *ipr = regs->ipr;
bool use_pc = (fault == No_Fault);
bool use_pc = (fault == NoFault);
if (fault == Arithmetic_Fault)
if (fault == ArithmeticFault)
panic("arithmetic faults NYI...");
// compute exception restart address
if (use_pc || fault == Pal_Fault || fault == Arithmetic_Fault) {
if (use_pc || fault == PalFault || fault == ArithmeticFault) {
// traps... skip faulting instruction
ipr[IPR_EXC_ADDR] = regs->pc + 4;
} else {
@ -238,20 +229,20 @@ AlphaISA::intr_post(RegFile *regs, Fault fault, Addr pc)
// jump to expection address (PAL PC bit set here as well...)
if (!use_pc)
regs->npc = ipr[IPR_PAL_BASE] + fault_addr[fault];
regs->npc = ipr[IPR_PAL_BASE] + fault_addr(fault);
else
regs->npc = ipr[IPR_PAL_BASE] + pc;
// that's it! (orders of magnitude less painful than x86)
}
Fault
Fault *
ExecContext::hwrei()
{
uint64_t *ipr = regs.ipr;
if (!inPalMode())
return Unimplemented_Opcode_Fault;
return UnimplementedOpcodeFault;
setNextPC(ipr[AlphaISA::IPR_EXC_ADDR]);
@ -265,11 +256,11 @@ ExecContext::hwrei()
}
// FIXME: XXX check for interrupts? XXX
return No_Fault;
return NoFault;
}
uint64_t
ExecContext::readIpr(int idx, Fault &fault)
ExecContext::readIpr(int idx, Fault * &fault)
{
uint64_t *ipr = regs.ipr;
uint64_t retval = 0; // return value, default 0
@ -363,12 +354,12 @@ ExecContext::readIpr(int idx, Fault &fault)
case AlphaISA::IPR_DTB_IAP:
case AlphaISA::IPR_ITB_IA:
case AlphaISA::IPR_ITB_IAP:
fault = Unimplemented_Opcode_Fault;
fault = UnimplementedOpcodeFault;
break;
default:
// invalid IPR
fault = Unimplemented_Opcode_Fault;
fault = UnimplementedOpcodeFault;
break;
}
@ -380,14 +371,14 @@ ExecContext::readIpr(int idx, Fault &fault)
int break_ipl = -1;
#endif
Fault
Fault *
ExecContext::setIpr(int idx, uint64_t val)
{
uint64_t *ipr = regs.ipr;
uint64_t old;
if (misspeculating())
return No_Fault;
return NoFault;
switch (idx) {
case AlphaISA::IPR_PALtemp0:
@ -533,7 +524,7 @@ ExecContext::setIpr(int idx, uint64_t val)
case AlphaISA::IPR_ITB_PTE_TEMP:
case AlphaISA::IPR_DTB_PTE_TEMP:
// read-only registers
return Unimplemented_Opcode_Fault;
return UnimplementedOpcodeFault;
case AlphaISA::IPR_HWINT_CLR:
case AlphaISA::IPR_SL_XMIT:
@ -635,11 +626,11 @@ ExecContext::setIpr(int idx, uint64_t val)
default:
// invalid IPR
return Unimplemented_Opcode_Fault;
return UnimplementedOpcodeFault;
}
// no error...
return No_Fault;
return NoFault;
}
/**

64
arch/alpha/faults.cc
View file

@ -28,34 +28,40 @@
#include "arch/alpha/faults.hh"
namespace {
const char *
fault_name[Num_Faults] = {
"none",
"reset",
"mchk",
"arith",
"interrupt",
"dtb_miss_single",
"dtb_miss_double",
"unalign",
"dfault",
"dfault",
"itbmiss",
"itbmiss",
"iaccvio",
"opdec",
"fen",
"pal",
};
}
ResetFaultType * ResetFault = new ResetFaultType("reset", 1, 0x0001);
ArithmeticFaultType * ArithmeticFault = new ArithmeticFaultType("arith", 3, 0x0501);
InterruptFaultType * InterruptFault = new InterruptFaultType("interrupt", 4, 0x0101);
NDtbMissFaultType * NDtbMissFault = new NDtbMissFaultType("dtb_miss_single", 5, 0x0201);
PDtbMissFaultType * PDtbMissFault = new PDtbMissFaultType("dtb_miss_double", 6, 0x0281);
DtbPageFaultType * DtbPageFault = new DtbPageFaultType("dfault", 8, 0x0381);
DtbAcvFaultType * DtbAcvFault = new DtbAcvFaultType("dfault", 9, 0x0381);
ItbMissFaultType * ItbMissFault = new ItbMissFaultType("itbmiss", 10, 0x0181);
ItbPageFaultType * ItbPageFault = new ItbPageFaultType("itbmiss", 11, 0x0181);
ItbAcvFaultType * ItbAcvFault = new ItbAcvFaultType("iaccvio", 12, 0x0081);
UnimplementedOpcodeFaultType * UnimplementedOpcodeFault = new UnimplementedOpcodeFaultType("opdec", 13, 0x0481);
FloatEnableFaultType * FloatEnableFault = new FloatEnableFaultType("fen", 14, 0x0581);
PalFaultType * PalFault = new PalFaultType("pal", 15, 0x2001);
IntegerOverflowFaultType * IntegerOverflowFault = new IntegerOverflowFaultType("intover", 16, 0x0501);
const char *
FaultName(int index)
{
if (index < 0 || index >= Num_Faults)
return 0;
return fault_name[index];
}
Fault ** ListOfFaults[] = {
(Fault **)&NoFault,
(Fault **)&ResetFault,
(Fault **)&MachineCheckFault,
(Fault **)&ArithmeticFault,
(Fault **)&InterruptFault,
(Fault **)&NDtbMissFault,
(Fault **)&PDtbMissFault,
(Fault **)&AlignmentFault,
(Fault **)&DtbPageFault,
(Fault **)&DtbAcvFault,
(Fault **)&ItbMissFault,
(Fault **)&ItbPageFault,
(Fault **)&ItbAcvFault,
(Fault **)&UnimplementedOpcodeFault,
(Fault **)&FloatEnableFault,
(Fault **)&PalFault,
(Fault **)&IntegerOverflowFault,
(Fault **)&FakeMemFault
};
int NumFaults = sizeof(ListOfFaults) / sizeof(Fault **);

120
arch/alpha/faults.hh
View file

@ -26,32 +26,104 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __FAULTS_HH__
#define __FAULTS_HH__
#ifndef __ALPHA_FAULTS_HH__
#define __ALPHA_FAULTS_HH__
enum Fault {
No_Fault,
Reset_Fault, // processor reset
Machine_Check_Fault, // machine check (also internal S/W fault)
Arithmetic_Fault, // FP exception
Interrupt_Fault, // external interrupt
Ndtb_Miss_Fault, // DTB miss
Pdtb_Miss_Fault, // nested DTB miss
Alignment_Fault, // unaligned access
DTB_Fault_Fault, // DTB page fault
DTB_Acv_Fault, // DTB access violation
ITB_Miss_Fault, // ITB miss
ITB_Fault_Fault, // ITB page fault
ITB_Acv_Fault, // ITB access violation
Unimplemented_Opcode_Fault, // invalid/unimplemented instruction
Fen_Fault, // FP not-enabled fault
Pal_Fault, // call_pal S/W interrupt
Integer_Overflow_Fault,
Fake_Mem_Fault,
Num_Faults // number of faults
#include "sim/faults.hh"
#include "arch/isa_traits.hh" //For the Addr type
class AlphaFault : public Fault
{
public:
AlphaFault(char * newName, int newId, Addr newVect) : Fault(newName, newId), vect(newVect) {;}
TheISA::Addr vect;
};
const char *
FaultName(int index);
extern class ResetFaultType : public AlphaFault
{
public:
ResetFaultType(char * newName, int newId, Addr newVect) : AlphaFault(newName, newId, newVect) {;}
} * ResetFault;
extern class ArithmeticFaultType : public AlphaFault
{
public:
ArithmeticFaultType(char * newName, int newId, Addr newVect) : AlphaFault(newName, newId, newVect) {;}
} * ArithmeticFault;
extern class InterruptFaultType : public AlphaFault
{
public:
InterruptFaultType(char * newName, int newId, Addr newVect) : AlphaFault(newName, newId, newVect) {;}
} * InterruptFault;
extern class NDtbMissFaultType : public AlphaFault
{
public:
NDtbMissFaultType(char * newName, int newId, Addr newVect) : AlphaFault(newName, newId, newVect) {;}
} * NDtbMissFault;
extern class PDtbMissFaultType : public AlphaFault
{
public:
PDtbMissFaultType(char * newName, int newId, Addr newVect) : AlphaFault(newName, newId, newVect) {;}
} * PDtbMissFault;
extern class DtbPageFaultType : public AlphaFault
{
public:
DtbPageFaultType(char * newName, int newId, Addr newVect) : AlphaFault(newName, newId, newVect) {;}
} * DtbPageFault;
extern class DtbAcvFaultType : public AlphaFault
{
public:
DtbAcvFaultType(char * newName, int newId, Addr newVect) : AlphaFault(newName, newId, newVect) {;}
} * DtbAcvFault;
extern class ItbMissFaultType : public AlphaFault
{
public:
ItbMissFaultType(char * newName, int newId, Addr newVect) : AlphaFault(newName, newId, newVect) {;}
} * ItbMissFault;
extern class ItbPageFaultType : public AlphaFault
{
public:
ItbPageFaultType(char * newName, int newId, Addr newVect) : AlphaFault(newName, newId, newVect) {;}
} * ItbPageFault;
extern class ItbAcvFaultType : public AlphaFault
{
public:
ItbAcvFaultType(char * newName, int newId, Addr newVect) : AlphaFault(newName, newId, newVect) {;}
} * ItbAcvFault;
extern class UnimplementedOpcodeFaultType : public AlphaFault
{
public:
UnimplementedOpcodeFaultType(char * newName, int newId, Addr newVect) : AlphaFault(newName, newId, newVect) {;}
} * UnimplementedOpcodeFault;
extern class FloatEnableFaultType : public AlphaFault
{
public:
FloatEnableFaultType(char * newName, int newId, Addr newVect) : AlphaFault(newName, newId, newVect) {;}
} * FloatEnableFault;
extern class PalFaultType : public AlphaFault
{
public:
PalFaultType(char * newName, int newId, Addr newVect) : AlphaFault(newName, newId, newVect) {;}
} * PalFault;
extern class IntegerOverflowFaultType : public AlphaFault
{
public:
IntegerOverflowFaultType(char * newName, int newId, Addr newVect) : AlphaFault(newName, newId, newVect) {;}
} * IntegerOverflowFault;
extern Fault ** ListOfFaults[];
extern int NumFaults;
#endif // __FAULTS_HH__

26
arch/alpha/isa/decoder.isa
View file

@ -98,7 +98,7 @@ decode OPCODE default Unknown::unknown() {
// signed overflow occurs when operands have same sign
// and sign of result does not match.
if (Ra.sl<31:> == Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
fault = Integer_Overflow_Fault;
fault = IntegerOverflowFault;
Rc.sl = tmp;
}});
0x02: s4addl({{ Rc.sl = (Ra.sl << 2) + Rb_or_imm.sl; }});
@ -110,7 +110,7 @@ decode OPCODE default Unknown::unknown() {
// signed overflow occurs when operands have same sign
// and sign of result does not match.
if (Ra<63:> == Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
fault = Integer_Overflow_Fault;
fault = IntegerOverflowFault;
Rc = tmp;
}});
0x22: s4addq({{ Rc = (Ra << 2) + Rb_or_imm; }});
@ -124,7 +124,7 @@ decode OPCODE default Unknown::unknown() {
// sign bit of the subtrahend (Rb), i.e., if the initial
// signs are the *same* then no overflow can occur
if (Ra.sl<31:> != Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
fault = Integer_Overflow_Fault;
fault = IntegerOverflowFault;
Rc.sl = tmp;
}});
0x0b: s4subl({{ Rc.sl = (Ra.sl << 2) - Rb_or_imm.sl; }});
@ -138,7 +138,7 @@ decode OPCODE default Unknown::unknown() {
// sign bit of the subtrahend (Rb), i.e., if the initial
// signs are the *same* then no overflow can occur
if (Ra<63:> != Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
fault = Integer_Overflow_Fault;
fault = IntegerOverflowFault;
Rc = tmp;
}});
0x2b: s4subq({{ Rc = (Ra << 2) - Rb_or_imm; }});
@ -299,7 +299,7 @@ decode OPCODE default Unknown::unknown() {
// checking the upper 33 bits for all 0s or all 1s.
uint64_t sign_bits = tmp<63:31>;
if (sign_bits != 0 && sign_bits != mask(33))
fault = Integer_Overflow_Fault;
fault = IntegerOverflowFault;
Rc.sl = tmp<31:0>;
}}, IntMultOp);
0x60: mulqv({{
@ -310,7 +310,7 @@ decode OPCODE default Unknown::unknown() {
// the lower 64
if (!((hi == 0 && lo<63:> == 0) ||
(hi == mask(64) && lo<63:> == 1)))
fault = Integer_Overflow_Fault;
fault = IntegerOverflowFault;
Rc = lo;
}}, IntMultOp);
}
@ -427,19 +427,19 @@ decode OPCODE default Unknown::unknown() {
#if SS_COMPATIBLE_FP
0x0b: sqrts({{
if (Fb < 0.0)
fault = Arithmetic_Fault;
fault = ArithmeticFault;
Fc = sqrt(Fb);
}}, FloatSqrtOp);
#else
0x0b: sqrts({{
if (Fb.sf < 0.0)
fault = Arithmetic_Fault;
fault = ArithmeticFault;
Fc.sf = sqrt(Fb.sf);
}}, FloatSqrtOp);
#endif
0x2b: sqrtt({{
if (Fb < 0.0)
fault = Arithmetic_Fault;
fault = ArithmeticFault;
Fc = sqrt(Fb);
}}, FloatSqrtOp);
}
@ -570,7 +570,7 @@ decode OPCODE default Unknown::unknown() {
// checking the upper 33 bits for all 0s or all 1s.
uint64_t sign_bits = Fb.uq<63:31>;
if (sign_bits != 0 && sign_bits != mask(33))
fault = Integer_Overflow_Fault;
fault = IntegerOverflowFault;
Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29);
}});
@ -673,7 +673,7 @@ decode OPCODE default Unknown::unknown() {
&& xc->readIpr(AlphaISA::IPR_ICM, fault) != AlphaISA::mode_kernel)) {
// invalid pal function code, or attempt to do privileged
// PAL call in non-kernel mode
fault = Unimplemented_Opcode_Fault;
fault = UnimplementedOpcodeFault;
}
else {
// check to see if simulator wants to do something special
@ -729,7 +729,7 @@ decode OPCODE default Unknown::unknown() {
0x19: hw_mfpr({{
// this instruction is only valid in PAL mode
if (!xc->inPalMode()) {
fault = Unimplemented_Opcode_Fault;
fault = UnimplementedOpcodeFault;
}
else {
Ra = xc->readIpr(ipr_index, fault);
@ -738,7 +738,7 @@ decode OPCODE default Unknown::unknown() {
0x1d: hw_mtpr({{
// this instruction is only valid in PAL mode
if (!xc->inPalMode()) {
fault = Unimplemented_Opcode_Fault;
fault = UnimplementedOpcodeFault;
}
else {
xc->setIpr(ipr_index, Ra);

26
arch/alpha/isa/fp.isa
View file

@ -29,21 +29,21 @@
output exec {{
/// Check "FP enabled" machine status bit. Called when executing any FP
/// instruction in full-system mode.
/// @retval Full-system mode: No_Fault if FP is enabled, Fen_Fault
/// if not. Non-full-system mode: always returns No_Fault.
/// @retval Full-system mode: NoFault if FP is enabled, FenFault
/// if not. Non-full-system mode: always returns NoFault.
#if FULL_SYSTEM
inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
inline Fault * checkFpEnableFault(%(CPU_exec_context)s *xc)
{
Fault fault = No_Fault; // dummy... this ipr access should not fault
Fault * fault = NoFault; // dummy... this ipr access should not fault
if (!EV5::ICSR_FPE(xc->readIpr(AlphaISA::IPR_ICSR, fault))) {
fault = Fen_Fault;
fault = FloatEnableFault;
}
return fault;
}
#else
inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
inline Fault * checkFpEnableFault(%(CPU_exec_context)s *xc)
{
return No_Fault;
return NoFault;
}
#endif
}};
@ -199,7 +199,7 @@ output decoder {{
// FP instruction class execute method template. Handles non-standard
// rounding modes.
def template FloatingPointExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Fault * %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
if (trappingMode != Imprecise && !warnedOnTrapping) {
@ -208,7 +208,7 @@ def template FloatingPointExecute {{
warnedOnTrapping = true;
}
Fault fault = No_Fault;
Fault * fault = NoFault;
%(fp_enable_check)s;
%(op_decl)s;
@ -230,7 +230,7 @@ def template FloatingPointExecute {{
%(code)s;
#endif
if (fault == No_Fault) {
if (fault == NoFault) {
%(op_wb)s;
}
@ -242,7 +242,7 @@ def template FloatingPointExecute {{
// rounding mode control is needed. Like BasicExecute, but includes
// check & warning for non-standard trapping mode.
def template FPFixedRoundingExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Fault * %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
if (trappingMode != Imprecise && !warnedOnTrapping) {
@ -251,14 +251,14 @@ def template FPFixedRoundingExecute {{
warnedOnTrapping = true;
}
Fault fault = No_Fault;
Fault * fault = NoFault;
%(fp_enable_check)s;
%(op_decl)s;
%(op_rd)s;
%(code)s;
if (fault == No_Fault) {
if (fault == NoFault) {
%(op_wb)s;
}

13
arch/alpha/isa/main.isa
View file

@ -33,6 +33,7 @@ output header {{
#include "config/ss_compatible_fp.hh"
#include "cpu/static_inst.hh"
#include "arch/alpha/faults.hh"
#include "mem/mem_req.hh" // some constructors use MemReq flags
}};
@ -253,7 +254,7 @@ output decoder {{
// Declarations for execute() methods.
def template BasicExecDeclare {{
Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const;
Fault * execute(%(CPU_exec_context)s *, Trace::InstRecord *) const;
}};
// Basic instruction class declaration template.
@ -282,17 +283,17 @@ def template BasicConstructor {{
// Basic instruction class execute method template.
def template BasicExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Fault * %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Fault fault = No_Fault;
Fault * fault = NoFault;
%(fp_enable_check)s;
%(op_decl)s;
%(op_rd)s;
%(code)s;
if (fault == No_Fault) {
if (fault == NoFault) {
%(op_wb)s;
}
@ -377,10 +378,10 @@ output decoder {{
}};
output exec {{
Fault
Fault *
Nop::execute(%(CPU_exec_context)s *, Trace::InstRecord *) const
{
return No_Fault;
return NoFault;
}
}};

62
arch/alpha/isa/mem.isa
View file

@ -208,19 +208,19 @@ def template LoadStoreConstructor {{
def template EACompExecute {{
Fault
Fault *
%(class_name)s::EAComp::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = No_Fault;
Fault * fault = NoFault;
%(fp_enable_check)s;
%(op_decl)s;
%(op_rd)s;
%(code)s;
if (fault == No_Fault) {
if (fault == NoFault) {
%(op_wb)s;
xc->setEA(EA);
}
@ -230,24 +230,24 @@ def template EACompExecute {{
}};
def template LoadMemAccExecute {{
Fault
Fault *
%(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = No_Fault;
Fault * fault = NoFault;
%(fp_enable_check)s;
%(op_decl)s;
%(op_rd)s;
EA = xc->getEA();
if (fault == No_Fault) {
if (fault == NoFault) {
fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
%(code)s;
}
if (fault == No_Fault) {
if (fault == NoFault) {
%(op_wb)s;
}
@ -257,23 +257,23 @@ def template LoadMemAccExecute {{
def template LoadExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Fault * %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = No_Fault;
Fault * fault = NoFault;
%(fp_enable_check)s;
%(op_decl)s;
%(op_rd)s;
%(ea_code)s;
if (fault == No_Fault) {
if (fault == NoFault) {
fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
%(memacc_code)s;
}
if (fault == No_Fault) {
if (fault == NoFault) {
%(op_wb)s;
}
@ -331,12 +331,12 @@ def template LoadCompleteAcc {{
def template StoreMemAccExecute {{
Fault
Fault *
%(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = No_Fault;
Fault * fault = NoFault;
uint64_t write_result = 0;
%(fp_enable_check)s;
@ -344,21 +344,21 @@ def template StoreMemAccExecute {{
%(op_rd)s;
EA = xc->getEA();
if (fault == No_Fault) {
if (fault == NoFault) {
%(code)s;
}
if (fault == No_Fault) {
if (fault == NoFault) {
fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
memAccessFlags, &write_result);
if (traceData) { traceData->setData(Mem); }
}
if (fault == No_Fault) {
if (fault == NoFault) {
%(postacc_code)s;
}
if (fault == No_Fault) {
if (fault == NoFault) {
%(op_wb)s;
}
@ -368,11 +368,11 @@ def template StoreMemAccExecute {{
def template StoreExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Fault * %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = No_Fault;
Fault * fault = NoFault;
uint64_t write_result = 0;
%(fp_enable_check)s;
@ -380,21 +380,21 @@ def template StoreExecute {{
%(op_rd)s;
%(ea_code)s;
if (fault == No_Fault) {
if (fault == NoFault) {
%(memacc_code)s;
}
if (fault == No_Fault) {
if (fault == NoFault) {
fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
memAccessFlags, &write_result);
if (traceData) { traceData->setData(Mem); }
}
if (fault == No_Fault) {
if (fault == NoFault) {
%(postacc_code)s;
}
if (fault == No_Fault) {
if (fault == NoFault) {
%(op_wb)s;
}
@ -458,42 +458,42 @@ def template StoreCompleteAcc {{
def template MiscMemAccExecute {{
Fault %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
Fault * %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = No_Fault;
Fault * fault = NoFault;
%(fp_enable_check)s;
%(op_decl)s;
%(op_rd)s;
EA = xc->getEA();
if (fault == No_Fault) {
if (fault == NoFault) {
%(code)s;
}
return No_Fault;
return NoFault;
}
}};
def template MiscExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Fault * %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = No_Fault;
Fault * fault = NoFault;
%(fp_enable_check)s;
%(op_decl)s;
%(op_rd)s;
%(ea_code)s;
if (fault == No_Fault) {
if (fault == NoFault) {
%(memacc_code)s;
}
return No_Fault;
return NoFault;
}
}};

8
arch/alpha/isa/unimp.isa
View file

@ -105,16 +105,16 @@ output decoder {{
}};
output exec {{
Fault
Fault *
FailUnimplemented::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
panic("attempt to execute unimplemented instruction '%s' "
"(inst 0x%08x, opcode 0x%x)", mnemonic, machInst, OPCODE);
return Unimplemented_Opcode_Fault;
return UnimplementedOpcodeFault;
}
Fault
Fault *
WarnUnimplemented::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
@ -123,7 +123,7 @@ output exec {{
warned = true;
}
return No_Fault;
return NoFault;
}
}};

4
arch/alpha/isa/unknown.isa
View file

@ -36,13 +36,13 @@ output decoder {{
}};
output exec {{
Fault
Fault *
Unknown::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
panic("attempt to execute unknown instruction "
"(inst 0x%08x, opcode 0x%x)", machInst, OPCODE);
return Unimplemented_Opcode_Fault;
return UnimplementedOpcodeFault;
}
}};

3
arch/alpha/isa_traits.hh
View file

@ -32,10 +32,11 @@
namespace LittleEndianGuest {}
using namespace LittleEndianGuest;
#include "arch/alpha/faults.hh"
//#include "arch/alpha/faults.hh"
#include "base/misc.hh"
#include "config/full_system.hh"
#include "sim/host.hh"
#include "sim/faults.hh"
class FastCPU;
class FullCPU;

32
cpu/base_dyn_inst.cc
View file

@ -113,7 +113,7 @@ BaseDynInst<Impl>::initVars()
asid = 0;
// Initialize the fault to be unimplemented opcode.
fault = Unimplemented_Opcode_Fault;
fault = UnimplementedOpcodeFault;
++instcount;
@ -142,12 +142,12 @@ BaseDynInst<Impl>::prefetch(Addr addr, unsigned flags)
req->asid = asid;
// Prefetches never cause faults.
fault = No_Fault;
fault = NoFault;
// note this is a local, not BaseDynInst::fault
Fault trans_fault = xc->translateDataReadReq(req);
Fault * trans_fault = xc->translateDataReadReq(req);
if (trans_fault == No_Fault && !(req->flags & UNCACHEABLE)) {
if (trans_fault == NoFault && !(req->flags & UNCACHEABLE)) {
// It's a valid address to cacheable space. Record key MemReq
// parameters so we can generate another one just like it for
// the timing access without calling translate() again (which
@ -188,7 +188,7 @@ BaseDynInst<Impl>::writeHint(Addr addr, int size, unsigned flags)
fault = xc->translateDataWriteReq(req);
if (fault == No_Fault && !(req->flags & UNCACHEABLE)) {
if (fault == NoFault && !(req->flags & UNCACHEABLE)) {
// Record key MemReq parameters so we can generate another one
// just like it for the timing access without calling translate()
// again (which might mess up the TLB).
@ -208,16 +208,16 @@ BaseDynInst<Impl>::writeHint(Addr addr, int size, unsigned flags)
* @todo Need to find a way to get the cache block size here.
*/
template <class Impl>
Fault
Fault *
BaseDynInst<Impl>::copySrcTranslate(Addr src)
{
MemReqPtr req = new MemReq(src, xc, 64);
req->asid = asid;
// translate to physical address
Fault fault = xc->translateDataReadReq(req);
Fault * fault = xc->translateDataReadReq(req);
if (fault == No_Fault) {
if (fault == NoFault) {
xc->copySrcAddr = src;
xc->copySrcPhysAddr = req->paddr;
} else {
@ -231,7 +231,7 @@ BaseDynInst<Impl>::copySrcTranslate(Addr src)
* @todo Need to find a way to get the cache block size here.
*/
template <class Impl>
Fault
Fault *
BaseDynInst<Impl>::copy(Addr dest)
{
uint8_t data[64];
@ -241,9 +241,9 @@ BaseDynInst<Impl>::copy(Addr dest)
req->asid = asid;
// translate to physical address
Fault fault = xc->translateDataWriteReq(req);
Fault * fault = xc->translateDataWriteReq(req);
if (fault == No_Fault) {
if (fault == NoFault) {
Addr dest_addr = req->paddr;
// Need to read straight from memory since we have more than 8 bytes.
req->paddr = xc->copySrcPhysAddr;
@ -277,10 +277,10 @@ BaseDynInst<Impl>::dump(std::string &outstring)
#if 0
template <class Impl>
Fault
Fault *
BaseDynInst<Impl>::mem_access(mem_cmd cmd, Addr addr, void *p, int nbytes)
{
Fault fault;
Fault * fault;
// check alignments, even speculative this test should always pass
if ((nbytes & nbytes - 1) != 0 || (addr & nbytes - 1) != 0) {
@ -292,7 +292,7 @@ BaseDynInst<Impl>::mem_access(mem_cmd cmd, Addr addr, void *p, int nbytes)
#if 0
panic("unaligned access. Cycle = %n", curTick);
#endif
return No_Fault;
return NoFault;
}
MemReqPtr req = new MemReq(addr, thread, nbytes);
@ -303,7 +303,7 @@ BaseDynInst<Impl>::mem_access(mem_cmd cmd, Addr addr, void *p, int nbytes)
case Write:
fault = spec_mem->write(req, (uint8_t *)p);
if (fault != No_Fault)
if (fault != NoFault)
break;
specMemWrite = true;
@ -325,7 +325,7 @@ BaseDynInst<Impl>::mem_access(mem_cmd cmd, Addr addr, void *p, int nbytes)
break;
default:
fault = Machine_Check_Fault;
fault = MachineCheckFault;
break;
}

24
cpu/base_dyn_inst.hh
View file

@ -89,16 +89,16 @@ class BaseDynInst : public FastAlloc, public RefCounted
Trace::InstRecord *traceData;
template <class T>
Fault read(Addr addr, T &data, unsigned flags);
Fault * read(Addr addr, T &data, unsigned flags);
template <class T>
Fault write(T data, Addr addr, unsigned flags,
Fault * write(T data, Addr addr, unsigned flags,
uint64_t *res);
void prefetch(Addr addr, unsigned flags);
void writeHint(Addr addr, int size, unsigned flags);
Fault copySrcTranslate(Addr src);
Fault copy(Addr dest);
Fault * copySrcTranslate(Addr src);
Fault * copy(Addr dest);
/** @todo: Consider making this private. */
public:
@ -154,7 +154,7 @@ class BaseDynInst : public FastAlloc, public RefCounted
ExecContext *xc;
/** The kind of fault this instruction has generated. */
Fault fault;
Fault * fault;
/** The effective virtual address (lds & stores only). */
Addr effAddr;
@ -225,7 +225,7 @@ class BaseDynInst : public FastAlloc, public RefCounted
public:
void
trace_mem(Fault fault, // last fault
trace_mem(Fault * fault, // last fault
MemCmd cmd, // last command
Addr addr, // virtual address of access
void *p, // memory accessed
@ -238,7 +238,7 @@ class BaseDynInst : public FastAlloc, public RefCounted
void dump(std::string &outstring);
/** Returns the fault type. */
Fault getFault() { return fault; }
Fault * getFault() { return fault; }
/** Checks whether or not this instruction has had its branch target
* calculated yet. For now it is not utilized and is hacked to be
@ -447,7 +447,7 @@ class BaseDynInst : public FastAlloc, public RefCounted
template<class Impl>
template<class T>
inline Fault
inline Fault *
BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
{
MemReqPtr req = new MemReq(addr, xc, sizeof(T), flags);
@ -472,7 +472,7 @@ BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
req->paddr = req->vaddr;
#endif
if (fault == No_Fault) {
if (fault == NoFault) {
fault = cpu->read(req, data, lqIdx);
} else {
// Return a fixed value to keep simulation deterministic even
@ -490,7 +490,7 @@ BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
template<class Impl>
template<class T>
inline Fault
inline Fault *
BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
{
if (traceData) {
@ -520,14 +520,14 @@ BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
req->paddr = req->vaddr;
#endif
if (fault == No_Fault) {
if (fault == NoFault) {
fault = cpu->write(req, data, sqIdx);
}
if (res) {
// always return some result to keep misspeculated paths
// (which will ignore faults) deterministic
*res = (fault == No_Fault) ? req->result : 0;
*res = (fault == NoFault) ? req->result : 0;
}
return fault;

2
cpu/exec_context.cc
View file

@ -221,7 +221,7 @@ ExecContext::regStats(const string &name)
}
void
ExecContext::trap(Fault fault)
ExecContext::trap(Fault * fault)
{
//TheISA::trap(fault); //One possible way to do it...

36
cpu/exec_context.hh
View file

@ -206,17 +206,17 @@ class ExecContext
int getInstAsid() { return regs.instAsid(); }
int getDataAsid() { return regs.dataAsid(); }
Fault translateInstReq(MemReqPtr &req)
Fault * translateInstReq(MemReqPtr &req)
{
return itb->translate(req);
}
Fault translateDataReadReq(MemReqPtr &req)
Fault * translateDataReadReq(MemReqPtr &req)
{
return dtb->translate(req, false);
}
Fault translateDataWriteReq(MemReqPtr &req)
Fault * translateDataWriteReq(MemReqPtr &req)
{
return dtb->translate(req, true);
}
@ -231,7 +231,7 @@ class ExecContext
int getInstAsid() { return asid; }
int getDataAsid() { return asid; }
Fault dummyTranslation(MemReqPtr &req)
Fault * dummyTranslation(MemReqPtr &req)
{
#if 0
assert((req->vaddr >> 48 & 0xffff) == 0);
@ -240,17 +240,17 @@ class ExecContext
// put the asid in the upper 16 bits of the paddr
req->paddr = req->vaddr & ~((Addr)0xffff << sizeof(Addr) * 8 - 16);
req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16;
return No_Fault;
return NoFault;
}
Fault translateInstReq(MemReqPtr &req)
Fault * translateInstReq(MemReqPtr &req)
{
return dummyTranslation(req);
}
Fault translateDataReadReq(MemReqPtr &req)
Fault * translateDataReadReq(MemReqPtr &req)
{
return dummyTranslation(req);
}
Fault translateDataWriteReq(MemReqPtr &req)
Fault * translateDataWriteReq(MemReqPtr &req)
{
return dummyTranslation(req);
}
@ -258,7 +258,7 @@ class ExecContext
#endif
template <class T>
Fault read(MemReqPtr &req, T &data)
Fault * read(MemReqPtr &req, T &data)
{
#if FULL_SYSTEM && defined(TARGET_ALPHA)
if (req->flags & LOCKED) {
@ -268,14 +268,14 @@ class ExecContext
}
#endif
Fault error;
Fault * error;
error = mem->read(req, data);
data = LittleEndianGuest::gtoh(data);
return error;
}
template <class T>
Fault write(MemReqPtr &req, T &data)
Fault * write(MemReqPtr &req, T &data)
{
#if FULL_SYSTEM && defined(TARGET_ALPHA)
@ -301,7 +301,7 @@ class ExecContext
<< "on cpu " << req->xc->cpu_id
<< std::endl;
}
return No_Fault;
return NoFault;
}
else req->xc->storeCondFailures = 0;
}
@ -333,7 +333,7 @@ class ExecContext
inst = new_inst;
}
Fault instRead(MemReqPtr &req)
Fault * instRead(MemReqPtr &req)
{
return mem->read(req, inst);
}
@ -412,13 +412,13 @@ class ExecContext
}
#if FULL_SYSTEM
uint64_t readIpr(int idx, Fault &fault);
Fault setIpr(int idx, uint64_t val);
uint64_t readIpr(int idx, Fault * &fault);
Fault * setIpr(int idx, uint64_t val);
int readIntrFlag() { return regs.intrflag; }
void setIntrFlag(int val) { regs.intrflag = val; }
Fault hwrei();
Fault * hwrei();
bool inPalMode() { return AlphaISA::PcPAL(regs.pc); }
void ev5_trap(Fault fault);
void ev5_trap(Fault * fault);
bool simPalCheck(int palFunc);
#endif
@ -428,7 +428,7 @@ class ExecContext
* @todo How to do this properly so it's dependent upon ISA only?
*/
void trap(Fault fault);
void trap(Fault * fault);
#if !FULL_SYSTEM
IntReg getSyscallArg(int i)

38
cpu/o3/alpha_cpu.hh
View file

@ -62,23 +62,23 @@ class AlphaFullCPU : public FullO3CPU<Impl>
// void clear_interrupt(int int_num, int index);
// void clear_interrupts();
Fault translateInstReq(MemReqPtr &req)
Fault * translateInstReq(MemReqPtr &req)
{
return itb->translate(req);
}
Fault translateDataReadReq(MemReqPtr &req)
Fault * translateDataReadReq(MemReqPtr &req)
{
return dtb->translate(req, false);
}
Fault translateDataWriteReq(MemReqPtr &req)
Fault * translateDataWriteReq(MemReqPtr &req)
{
return dtb->translate(req, true);
}
#else
Fault dummyTranslation(MemReqPtr &req)
Fault * dummyTranslation(MemReqPtr &req)
{
#if 0
assert((req->vaddr >> 48 & 0xffff) == 0);
@ -87,20 +87,20 @@ class AlphaFullCPU : public FullO3CPU<Impl>
// put the asid in the upper 16 bits of the paddr
req->paddr = req->vaddr & ~((Addr)0xffff << sizeof(Addr) * 8 - 16);
req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16;
return No_Fault;
return NoFault;
}
Fault translateInstReq(MemReqPtr &req)
Fault * translateInstReq(MemReqPtr &req)
{
return dummyTranslation(req);
}
Fault translateDataReadReq(MemReqPtr &req)
Fault * translateDataReadReq(MemReqPtr &req)
{
return dummyTranslation(req);
}
Fault translateDataWriteReq(MemReqPtr &req)
Fault * translateDataWriteReq(MemReqPtr &req)
{
return dummyTranslation(req);
}
@ -135,16 +135,16 @@ class AlphaFullCPU : public FullO3CPU<Impl>
// look like.
#if FULL_SYSTEM
uint64_t *getIpr();
uint64_t readIpr(int idx, Fault &fault);
Fault setIpr(int idx, uint64_t val);
uint64_t readIpr(int idx, Fault * &fault);
Fault * setIpr(int idx, uint64_t val);
int readIntrFlag();
void setIntrFlag(int val);
Fault hwrei();
Fault * hwrei();
bool inPalMode() { return AlphaISA::PcPAL(this->regFile.readPC()); }
bool inPalMode(uint64_t PC)
{ return AlphaISA::PcPAL(PC); }
void trap(Fault fault);
void trap(Fault * fault);
bool simPalCheck(int palFunc);
void processInterrupts();
@ -197,7 +197,7 @@ class AlphaFullCPU : public FullO3CPU<Impl>
bool palShadowEnabled;
// Not sure this is used anywhere.
void intr_post(RegFile *regs, Fault fault, Addr pc);
void intr_post(RegFile *regs, Fault * fault, Addr pc);
// Actually used within exec files. Implement properly.
void swapPALShadow(bool use_shadow);
// Called by CPU constructor. Can implement as I please.
@ -210,7 +210,7 @@ class AlphaFullCPU : public FullO3CPU<Impl>
template <class T>
Fault read(MemReqPtr &req, T &data)
Fault * read(MemReqPtr &req, T &data)
{
#if FULL_SYSTEM && defined(TARGET_ALPHA)
if (req->flags & LOCKED) {
@ -220,20 +220,20 @@ class AlphaFullCPU : public FullO3CPU<Impl>
}
#endif
Fault error;
Fault * error;
error = this->mem->read(req, data);
data = gtoh(data);
return error;
}
template <class T>
Fault read(MemReqPtr &req, T &data, int load_idx)
Fault * read(MemReqPtr &req, T &data, int load_idx)
{
return this->iew.ldstQueue.read(req, data, load_idx);
}
template <class T>
Fault write(MemReqPtr &req, T &data)
Fault * write(MemReqPtr &req, T &data)
{
#if FULL_SYSTEM && defined(TARGET_ALPHA)
@ -259,7 +259,7 @@ class AlphaFullCPU : public FullO3CPU<Impl>
<< "on cpu " << this->cpu_id
<< std::endl;
}
return No_Fault;
return NoFault;
}
else req->xc->storeCondFailures = 0;
}
@ -283,7 +283,7 @@ class AlphaFullCPU : public FullO3CPU<Impl>
}
template <class T>
Fault write(MemReqPtr &req, T &data, int store_idx)
Fault * write(MemReqPtr &req, T &data, int store_idx)
{
return this->iew.ldstQueue.write(req, data, store_idx);
}

26
cpu/o3/alpha_cpu_impl.hh
View file

@ -246,13 +246,13 @@ AlphaFullCPU<Impl>::getIpr()
template <class Impl>
uint64_t
AlphaFullCPU<Impl>::readIpr(int idx, Fault &fault)
AlphaFullCPU<Impl>::readIpr(int idx, Fault * &fault)
{
return this->regFile.readIpr(idx, fault);
}
template <class Impl>
Fault
Fault *
AlphaFullCPU<Impl>::setIpr(int idx, uint64_t val)
{
return this->regFile.setIpr(idx, val);
@ -274,13 +274,13 @@ AlphaFullCPU<Impl>::setIntrFlag(int val)
// Can force commit stage to squash and stuff.
template <class Impl>
Fault
Fault *
AlphaFullCPU<Impl>::hwrei()
{
uint64_t *ipr = getIpr();
if (!inPalMode())
return Unimplemented_Opcode_Fault;
return UnimplementedOpcodeFault;
setNextPC(ipr[AlphaISA::IPR_EXC_ADDR]);
@ -292,7 +292,7 @@ AlphaFullCPU<Impl>::hwrei()
this->checkInterrupts = true;
// FIXME: XXX check for interrupts? XXX
return No_Fault;
return NoFault;
}
template <class Impl>
@ -323,28 +323,28 @@ AlphaFullCPU<Impl>::simPalCheck(int palFunc)
// stage.
template <class Impl>
void
AlphaFullCPU<Impl>::trap(Fault fault)
AlphaFullCPU<Impl>::trap(Fault * fault)
{
// Keep in mind that a trap may be initiated by fetch if there's a TLB
// miss
uint64_t PC = this->commit.readCommitPC();
DPRINTF(Fault, "Fault %s\n", FaultName(fault));
this->recordEvent(csprintf("Fault %s", FaultName(fault)));
DPRINTF(Fault, "Fault %s\n", fault ? fault->name : "name");
this->recordEvent(csprintf("Fault %s", fault ? fault->name : "name"));
// kernelStats.fault(fault);
if (fault == Arithmetic_Fault)
if (fault == ArithmeticFault)
panic("Arithmetic traps are unimplemented!");
typename AlphaISA::InternalProcReg *ipr = getIpr();
// exception restart address - Get the commit PC
if (fault != Interrupt_Fault || !inPalMode(PC))
if (fault != InterruptFault || !inPalMode(PC))
ipr[AlphaISA::IPR_EXC_ADDR] = PC;
if (fault == Pal_Fault || fault == Arithmetic_Fault /* ||
fault == Interrupt_Fault && !PC_PAL(regs.pc) */) {
if (fault == PalFault || fault == ArithmeticFault /* ||
fault == InterruptFault && !PC_PAL(regs.pc) */) {
// traps... skip faulting instruction
ipr[AlphaISA::IPR_EXC_ADDR] += 4;
}
@ -353,7 +353,7 @@ AlphaFullCPU<Impl>::trap(Fault fault)
swapPALShadow(true);
this->regFile.setPC( ipr[AlphaISA::IPR_PAL_BASE] +
AlphaISA::fault_addr[fault] );
AlphaISA::fault_addr(fault) );
this->regFile.setNextPC(PC + sizeof(MachInst));
}

14
cpu/o3/alpha_dyn_inst.hh
View file

@ -74,7 +74,7 @@ class AlphaDynInst : public BaseDynInst<Impl>
AlphaDynInst(StaticInstPtr<AlphaISA> &_staticInst);
/** Executes the instruction.*/
Fault execute()
Fault * execute()
{
return this->fault = this->staticInst->execute(this, this->traceData);
}
@ -87,13 +87,13 @@ class AlphaDynInst : public BaseDynInst<Impl>
void setFpcr(uint64_t val);
#if FULL_SYSTEM
uint64_t readIpr(int idx, Fault &fault);
Fault setIpr(int idx, uint64_t val);
Fault hwrei();
uint64_t readIpr(int idx, Fault * &fault);
Fault * setIpr(int idx, uint64_t val);
Fault * hwrei();
int readIntrFlag();
void setIntrFlag(int val);
bool inPalMode();
void trap(Fault fault);
void trap(Fault * fault);
bool simPalCheck(int palFunc);
#else
void syscall();
@ -220,12 +220,12 @@ class AlphaDynInst : public BaseDynInst<Impl>
}
public:
Fault calcEA()
Fault * calcEA()
{
return this->staticInst->eaCompInst()->execute(this, this->traceData);
}
Fault memAccess()
Fault * memAccess()
{
return this->staticInst->memAccInst()->execute(this, this->traceData);
}

8
cpu/o3/alpha_dyn_inst_impl.hh
View file

@ -98,20 +98,20 @@ AlphaDynInst<Impl>::setFpcr(uint64_t val)
#if FULL_SYSTEM
template <class Impl>
uint64_t
AlphaDynInst<Impl>::readIpr(int idx, Fault &fault)
AlphaDynInst<Impl>::readIpr(int idx, Fault * &fault)
{
return this->cpu->readIpr(idx, fault);
}
template <class Impl>
Fault
Fault *
AlphaDynInst<Impl>::setIpr(int idx, uint64_t val)
{
return this->cpu->setIpr(idx, val);
}
template <class Impl>
Fault
Fault *
AlphaDynInst<Impl>::hwrei()
{
return this->cpu->hwrei();
@ -140,7 +140,7 @@ AlphaDynInst<Impl>::inPalMode()
template <class Impl>
void
AlphaDynInst<Impl>::trap(Fault fault)
AlphaDynInst<Impl>::trap(Fault * fault)
{
this->cpu->trap(fault);
}

4
cpu/o3/commit_impl.hh
View file

@ -393,9 +393,9 @@ SimpleCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
}
// Check if the instruction caused a fault. If so, trap.
Fault inst_fault = head_inst->getFault();
Fault * inst_fault = head_inst->getFault();
if (inst_fault != No_Fault && inst_fault != Fake_Mem_Fault) {
if (inst_fault != NoFault && inst_fault != FakeMemFault) {
if (!head_inst->isNop()) {
#if FULL_SYSTEM
cpu->trap(inst_fault);

2
cpu/o3/fetch.hh
View file

@ -123,7 +123,7 @@ class SimpleFetch
* @param fetch_PC The PC address that is being fetched from.
* @return Any fault that occured.
*/
Fault fetchCacheLine(Addr fetch_PC);
Fault * fetchCacheLine(Addr fetch_PC);
inline void doSquash(const Addr &new_PC);

14
cpu/o3/fetch_impl.hh
View file

@ -221,7 +221,7 @@ SimpleFetch<Impl>::lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC)
}
template <class Impl>
Fault
Fault *
SimpleFetch<Impl>::fetchCacheLine(Addr fetch_PC)
{
// Check if the instruction exists within the cache.
@ -236,7 +236,7 @@ SimpleFetch<Impl>::fetchCacheLine(Addr fetch_PC)
unsigned flags = 0;
#endif // FULL_SYSTEM
Fault fault = No_Fault;
Fault * fault = NoFault;
// Align the fetch PC so it's at the start of a cache block.
fetch_PC = icacheBlockAlignPC(fetch_PC);
@ -258,7 +258,7 @@ SimpleFetch<Impl>::fetchCacheLine(Addr fetch_PC)
// If translation was successful, attempt to read the first
// instruction.
if (fault == No_Fault) {
if (fault == NoFault) {
DPRINTF(Fetch, "Fetch: Doing instruction read.\n");
fault = cpu->mem->read(memReq, cacheData);
// This read may change when the mem interface changes.
@ -268,7 +268,7 @@ SimpleFetch<Impl>::fetchCacheLine(Addr fetch_PC)
// Now do the timing access to see whether or not the instruction
// exists within the cache.
if (icacheInterface && fault == No_Fault) {
if (icacheInterface && fault == NoFault) {
DPRINTF(Fetch, "Fetch: Doing timing memory access.\n");
memReq->completionEvent = NULL;
@ -468,7 +468,7 @@ SimpleFetch<Impl>::fetch()
Addr fetch_PC = cpu->readPC();
// Fault code for memory access.
Fault fault = No_Fault;
Fault * fault = NoFault;
// If returning from the delay of a cache miss, then update the status
// to running, otherwise do the cache access. Possibly move this up
@ -506,7 +506,7 @@ SimpleFetch<Impl>::fetch()
unsigned offset = fetch_PC & cacheBlkMask;
unsigned fetched;
if (fault == No_Fault) {
if (fault == NoFault) {
// If the read of the first instruction was successful, then grab the
// instructions from the rest of the cache line and put them into the
// queue heading to decode.
@ -582,7 +582,7 @@ SimpleFetch<Impl>::fetch()
// Or might want to leave setting the PC to the main CPU, with fetch
// only changing the nextPC (will require correct determination of
// next PC).
if (fault == No_Fault) {
if (fault == NoFault) {
DPRINTF(Fetch, "Fetch: Setting PC to %08p.\n", next_PC);
cpu->setPC(next_PC);
cpu->setNextPC(next_PC + instSize);

19
cpu/o3/regfile.hh
View file

@ -32,6 +32,7 @@
// @todo: Destructor
#include "arch/alpha/isa_traits.hh"
#include "arch/alpha/faults.hh"
#include "base/trace.hh"
#include "config/full_system.hh"
#include "cpu/o3/comm.hh"
@ -211,8 +212,8 @@ class PhysRegFile
}
#if FULL_SYSTEM
uint64_t readIpr(int idx, Fault &fault);
Fault setIpr(int idx, uint64_t val);
uint64_t readIpr(int idx, Fault * &fault);
Fault * setIpr(int idx, uint64_t val);
InternalProcReg *getIpr() { return ipr; }
int readIntrFlag() { return intrflag; }
void setIntrFlag(int val) { intrflag = val; }
@ -275,7 +276,7 @@ PhysRegFile<Impl>::PhysRegFile(unsigned _numPhysicalIntRegs,
//the DynInst level.
template <class Impl>
uint64_t
PhysRegFile<Impl>::readIpr(int idx, Fault &fault)
PhysRegFile<Impl>::readIpr(int idx, Fault * &fault)
{
uint64_t retval = 0; // return value, default 0
@ -368,12 +369,12 @@ PhysRegFile<Impl>::readIpr(int idx, Fault &fault)
case ISA::IPR_DTB_IAP:
case ISA::IPR_ITB_IA:
case ISA::IPR_ITB_IAP:
fault = Unimplemented_Opcode_Fault;
fault = UnimplementedOpcodeFault;
break;
default:
// invalid IPR
fault = Unimplemented_Opcode_Fault;
fault = UnimplementedOpcodeFault;
break;
}
@ -383,7 +384,7 @@ PhysRegFile<Impl>::readIpr(int idx, Fault &fault)
extern int break_ipl;
template <class Impl>
Fault
Fault *
PhysRegFile<Impl>::setIpr(int idx, uint64_t val)
{
uint64_t old;
@ -521,7 +522,7 @@ PhysRegFile<Impl>::setIpr(int idx, uint64_t val)
case ISA::IPR_ITB_PTE_TEMP:
case ISA::IPR_DTB_PTE_TEMP:
// read-only registers
return Unimplemented_Opcode_Fault;
return UnimplementedOpcodeFault;
case ISA::IPR_HWINT_CLR:
case ISA::IPR_SL_XMIT:
@ -623,11 +624,11 @@ PhysRegFile<Impl>::setIpr(int idx, uint64_t val)
default:
// invalid IPR
return Unimplemented_Opcode_Fault;
return UnimplementedOpcodeFault;
}
// no error...
return No_Fault;
return NoFault;
}
#endif // #if FULL_SYSTEM

54
cpu/ozone/cpu.hh
View file

@ -286,17 +286,17 @@ class OoOCPU : public BaseCPU
int getInstAsid() { return xc->regs.instAsid(); }
int getDataAsid() { return xc->regs.dataAsid(); }
Fault translateInstReq(MemReqPtr &req)
Fault * translateInstReq(MemReqPtr &req)
{
return itb->translate(req);
}
Fault translateDataReadReq(MemReqPtr &req)
Fault * translateDataReadReq(MemReqPtr &req)
{
return dtb->translate(req, false);
}
Fault translateDataWriteReq(MemReqPtr &req)
Fault * translateDataWriteReq(MemReqPtr &req)
{
return dtb->translate(req, true);
}
@ -311,7 +311,7 @@ class OoOCPU : public BaseCPU
int getInstAsid() { return xc->asid; }
int getDataAsid() { return xc->asid; }
Fault dummyTranslation(MemReqPtr &req)
Fault * dummyTranslation(MemReqPtr &req)
{
#if 0
assert((req->vaddr >> 48 & 0xffff) == 0);
@ -320,17 +320,17 @@ class OoOCPU : public BaseCPU
// put the asid in the upper 16 bits of the paddr
req->paddr = req->vaddr & ~((Addr)0xffff << sizeof(Addr) * 8 - 16);
req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16;
return No_Fault;
return NoFault;
}
Fault translateInstReq(MemReqPtr &req)
Fault * translateInstReq(MemReqPtr &req)
{
return dummyTranslation(req);
}
Fault translateDataReadReq(MemReqPtr &req)
Fault * translateDataReadReq(MemReqPtr &req)
{
return dummyTranslation(req);
}
Fault translateDataWriteReq(MemReqPtr &req)
Fault * translateDataWriteReq(MemReqPtr &req)
{
return dummyTranslation(req);
}
@ -338,10 +338,10 @@ class OoOCPU : public BaseCPU
#endif
template <class T>
Fault read(Addr addr, T &data, unsigned flags, DynInstPtr inst);
Fault * read(Addr addr, T &data, unsigned flags, DynInstPtr inst);
template <class T>
Fault write(T data, Addr addr, unsigned flags,
Fault * write(T data, Addr addr, unsigned flags,
uint64_t *res, DynInstPtr inst);
void prefetch(Addr addr, unsigned flags)
@ -354,9 +354,9 @@ class OoOCPU : public BaseCPU
// need to do this...
}
Fault copySrcTranslate(Addr src);
Fault * copySrcTranslate(Addr src);
Fault copy(Addr dest);
Fault * copy(Addr dest);
private:
bool executeInst(DynInstPtr &inst);
@ -369,7 +369,7 @@ class OoOCPU : public BaseCPU
bool getOneInst();
Fault fetchCacheLine();
Fault * fetchCacheLine();
InstSeqNum getAndIncrementInstSeq();
@ -512,13 +512,13 @@ class OoOCPU : public BaseCPU
void setFpcr(uint64_t val) { xc->setFpcr(val); }
#if FULL_SYSTEM
uint64_t readIpr(int idx, Fault &fault) { return xc->readIpr(idx, fault); }
Fault setIpr(int idx, uint64_t val) { return xc->setIpr(idx, val); }
Fault hwrei() { return xc->hwrei(); }
uint64_t readIpr(int idx, Fault * &fault) { return xc->readIpr(idx, fault); }
Fault * setIpr(int idx, uint64_t val) { return xc->setIpr(idx, val); }
Fault * hwrei() { return xc->hwrei(); }
int readIntrFlag() { return xc->readIntrFlag(); }
void setIntrFlag(int val) { xc->setIntrFlag(val); }
bool inPalMode() { return xc->inPalMode(); }
void ev5_trap(Fault fault) { xc->ev5_trap(fault); }
void ev5_trap(Fault * fault) { xc->ev5_trap(fault); }
bool simPalCheck(int palFunc) { return xc->simPalCheck(palFunc); }
#else
void syscall() { xc->syscall(); }
@ -531,7 +531,7 @@ class OoOCPU : public BaseCPU
// precise architected memory state accessor macros
template <class Impl>
template <class T>
Fault
Fault *
OoOCPU<Impl>::read(Addr addr, T &data, unsigned flags, DynInstPtr inst)
{
MemReqPtr readReq = new MemReq();
@ -542,21 +542,21 @@ OoOCPU<Impl>::read(Addr addr, T &data, unsigned flags, DynInstPtr inst)
readReq->reset(addr, sizeof(T), flags);
// translate to physical address - This might be an ISA impl call
Fault fault = translateDataReadReq(readReq);
Fault * fault = translateDataReadReq(readReq);
// do functional access
if (fault == No_Fault)
if (fault == NoFault)
fault = xc->mem->read(readReq, data);
#if 0
if (traceData) {
traceData->setAddr(addr);
if (fault == No_Fault)
if (fault == NoFault)
traceData->setData(data);
}
#endif
// if we have a cache, do cache access too
if (fault == No_Fault && dcacheInterface) {
if (fault == NoFault && dcacheInterface) {
readReq->cmd = Read;
readReq->completionEvent = NULL;
readReq->time = curTick;
@ -576,7 +576,7 @@ OoOCPU<Impl>::read(Addr addr, T &data, unsigned flags, DynInstPtr inst)
template <class Impl>
template <class T>
Fault
Fault *
OoOCPU<Impl>::write(T data, Addr addr, unsigned flags,
uint64_t *res, DynInstPtr inst)
{
@ -595,13 +595,13 @@ OoOCPU<Impl>::write(T data, Addr addr, unsigned flags,
writeReq->reset(addr, sizeof(T), flags);
// translate to physical address
Fault fault = translateDataWriteReq(writeReq);
Fault * fault = translateDataWriteReq(writeReq);
// do functional access
if (fault == No_Fault)
if (fault == NoFault)
fault = xc->write(writeReq, data);
if (fault == No_Fault && dcacheInterface) {
if (fault == NoFault && dcacheInterface) {
writeReq->cmd = Write;
memcpy(writeReq->data,(uint8_t *)&data,writeReq->size);
writeReq->completionEvent = NULL;
@ -614,7 +614,7 @@ OoOCPU<Impl>::write(T data, Addr addr, unsigned flags,
}
}
if (res && (fault == No_Fault))
if (res && (fault == NoFault))
*res = writeReq->result;
if (!dcacheInterface && (writeReq->flags & UNCACHEABLE))

78
cpu/simple/cpu.cc
View file

@ -312,7 +312,7 @@ change_thread_state(int thread_number, int activate, int priority)
{
}
Fault
Fault *
SimpleCPU::copySrcTranslate(Addr src)
{
static bool no_warn = true;
@ -332,11 +332,11 @@ SimpleCPU::copySrcTranslate(Addr src)
memReq->reset(src & ~(blk_size - 1), blk_size);
// translate to physical address
Fault fault = xc->translateDataReadReq(memReq);
Fault * fault = xc->translateDataReadReq(memReq);
assert(fault != Alignment_Fault);
assert(fault != AlignmentFault);
if (fault == No_Fault) {
if (fault == NoFault) {
xc->copySrcAddr = src;
xc->copySrcPhysAddr = memReq->paddr + offset;
} else {
@ -346,7 +346,7 @@ SimpleCPU::copySrcTranslate(Addr src)
return fault;
}
Fault
Fault *
SimpleCPU::copy(Addr dest)
{
static bool no_warn = true;
@ -367,11 +367,11 @@ SimpleCPU::copy(Addr dest)
memReq->reset(dest & ~(blk_size -1), blk_size);
// translate to physical address
Fault fault = xc->translateDataWriteReq(memReq);
Fault * fault = xc->translateDataWriteReq(memReq);
assert(fault != Alignment_Fault);
assert(fault != AlignmentFault);
if (fault == No_Fault) {
if (fault == NoFault) {
Addr dest_addr = memReq->paddr + offset;
// Need to read straight from memory since we have more than 8 bytes.
memReq->paddr = xc->copySrcPhysAddr;
@ -394,11 +394,11 @@ SimpleCPU::copy(Addr dest)
// precise architected memory state accessor macros
template <class T>
Fault
Fault *
SimpleCPU::read(Addr addr, T &data, unsigned flags)
{
if (status() == DcacheMissStall || status() == DcacheMissSwitch) {
Fault fault = xc->read(memReq,data);
Fault * fault = xc->read(memReq,data);
if (traceData) {
traceData->setAddr(addr);
@ -409,10 +409,10 @@ SimpleCPU::read(Addr addr, T &data, unsigned flags)
memReq->reset(addr, sizeof(T), flags);
// translate to physical address
Fault fault = xc->translateDataReadReq(memReq);
Fault * fault = xc->translateDataReadReq(memReq);
// if we have a cache, do cache access too
if (fault == No_Fault && dcacheInterface) {
if (fault == NoFault && dcacheInterface) {
memReq->cmd = Read;
memReq->completionEvent = NULL;
memReq->time = curTick;
@ -432,7 +432,7 @@ SimpleCPU::read(Addr addr, T &data, unsigned flags)
fault = xc->read(memReq, data);
}
} else if(fault == No_Fault) {
} else if(fault == NoFault) {
// do functional access
fault = xc->read(memReq, data);
@ -447,32 +447,32 @@ SimpleCPU::read(Addr addr, T &data, unsigned flags)
#ifndef DOXYGEN_SHOULD_SKIP_THIS
template
Fault
Fault *
SimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
template
Fault
Fault *
SimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
template
Fault
Fault *
SimpleCPU::read(Addr addr, uint16_t &data, unsigned flags);
template
Fault
Fault *
SimpleCPU::read(Addr addr, uint8_t &data, unsigned flags);
#endif //DOXYGEN_SHOULD_SKIP_THIS
template<>
Fault
Fault *
SimpleCPU::read(Addr addr, double &data, unsigned flags)
{
return read(addr, *(uint64_t*)&data, flags);
}
template<>
Fault
Fault *
SimpleCPU::read(Addr addr, float &data, unsigned flags)
{
return read(addr, *(uint32_t*)&data, flags);
@ -480,7 +480,7 @@ SimpleCPU::read(Addr addr, float &data, unsigned flags)
template<>
Fault
Fault *
SimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
{
return read(addr, (uint32_t&)data, flags);
@ -488,19 +488,19 @@ SimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
template <class T>
Fault
Fault *
SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
{
memReq->reset(addr, sizeof(T), flags);
// translate to physical address
Fault fault = xc->translateDataWriteReq(memReq);
Fault * fault = xc->translateDataWriteReq(memReq);
// do functional access
if (fault == No_Fault)
if (fault == NoFault)
fault = xc->write(memReq, data);
if (fault == No_Fault && dcacheInterface) {
if (fault == NoFault && dcacheInterface) {
memReq->cmd = Write;
memcpy(memReq->data,(uint8_t *)&data,memReq->size);
memReq->completionEvent = NULL;
@ -519,7 +519,7 @@ SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
}
}
if (res && (fault == No_Fault))
if (res && (fault == NoFault))
*res = memReq->result;
if (!dcacheInterface && (memReq->flags & UNCACHEABLE))
@ -531,32 +531,32 @@ SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
#ifndef DOXYGEN_SHOULD_SKIP_THIS
template
Fault
Fault *
SimpleCPU::write(uint64_t data, Addr addr, unsigned flags, uint64_t *res);
template
Fault
Fault *
SimpleCPU::write(uint32_t data, Addr addr, unsigned flags, uint64_t *res);
template
Fault
Fault *
SimpleCPU::write(uint16_t data, Addr addr, unsigned flags, uint64_t *res);
template
Fault
Fault *
SimpleCPU::write(uint8_t data, Addr addr, unsigned flags, uint64_t *res);
#endif //DOXYGEN_SHOULD_SKIP_THIS
template<>
Fault
Fault *
SimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
{
return write(*(uint64_t*)&data, addr, flags, res);
}
template<>
Fault
Fault *
SimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
{
return write(*(uint32_t*)&data, addr, flags, res);
@ -564,7 +564,7 @@ SimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
template<>
Fault
Fault *
SimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
{
return write((uint32_t)data, addr, flags, res);
@ -638,7 +638,7 @@ SimpleCPU::tick()
traceData = NULL;
Fault fault = No_Fault;
Fault * fault = NoFault;
#if FULL_SYSTEM
if (checkInterrupts && check_interrupts() && !xc->inPalMode() &&
@ -675,7 +675,7 @@ SimpleCPU::tick()
if (ipl && ipl > xc->regs.ipr[TheISA::IPR_IPLR]) {
ipr[TheISA::IPR_ISR] = summary;
ipr[TheISA::IPR_INTID] = ipl;
xc->ev5_trap(Interrupt_Fault);
xc->ev5_trap(InterruptFault);
DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
ipr[TheISA::IPR_IPLR], ipl, summary);
@ -713,10 +713,10 @@ SimpleCPU::tick()
fault = xc->translateInstReq(memReq);
if (fault == No_Fault)
if (fault == NoFault)
fault = xc->mem->read(memReq, inst);
if (icacheInterface && fault == No_Fault) {
if (icacheInterface && fault == NoFault) {
memReq->completionEvent = NULL;
memReq->time = curTick;
@ -738,7 +738,7 @@ SimpleCPU::tick()
// If we've got a valid instruction (i.e., no fault on instruction
// fetch), then execute it.
if (fault == No_Fault) {
if (fault == NoFault) {
// keep an instruction count
numInst++;
@ -795,9 +795,9 @@ SimpleCPU::tick()
traceFunctions(xc->regs.pc);
} // if (fault == No_Fault)
} // if (fault == NoFault)
if (fault != No_Fault) {
if (fault != NoFault) {
#if FULL_SYSTEM
xc->ev5_trap(fault);
#else // !FULL_SYSTEM

16
cpu/simple/cpu.hh
View file

@ -234,10 +234,10 @@ class SimpleCPU : public BaseCPU
virtual void unserialize(Checkpoint *cp, const std::string &section);
template <class T>
Fault read(Addr addr, T &data, unsigned flags);
Fault * read(Addr addr, T &data, unsigned flags);
template <class T>
Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
Fault * write(T data, Addr addr, unsigned flags, uint64_t *res);
// These functions are only used in CPU models that split
// effective address computation from the actual memory access.
@ -254,9 +254,9 @@ class SimpleCPU : public BaseCPU
// need to do this...
}
Fault copySrcTranslate(Addr src);
Fault * copySrcTranslate(Addr src);
Fault copy(Addr dest);
Fault * copy(Addr dest);
// The register accessor methods provide the index of the
// instruction's operand (e.g., 0 or 1), not the architectural
@ -325,13 +325,13 @@ class SimpleCPU : public BaseCPU
void setFpcr(uint64_t val) { xc->setFpcr(val); }
#if FULL_SYSTEM
uint64_t readIpr(int idx, Fault &fault) { return xc->readIpr(idx, fault); }
Fault setIpr(int idx, uint64_t val) { return xc->setIpr(idx, val); }
Fault hwrei() { return xc->hwrei(); }
uint64_t readIpr(int idx, Fault * &fault) { return xc->readIpr(idx, fault); }
Fault * setIpr(int idx, uint64_t val) { return xc->setIpr(idx, val); }
Fault * hwrei() { return xc->hwrei(); }
int readIntrFlag() { return xc->readIntrFlag(); }
void setIntrFlag(int val) { xc->setIntrFlag(val); }
bool inPalMode() { return xc->inPalMode(); }
void ev5_trap(Fault fault) { xc->ev5_trap(fault); }
void ev5_trap(Fault * fault) { xc->ev5_trap(fault); }
bool simPalCheck(int palFunc) { return xc->simPalCheck(palFunc); }
#else
void syscall() { xc->syscall(); }

14
dev/alpha_console.cc
View file

@ -99,7 +99,7 @@ AlphaConsole::startup()
alphaAccess->intrClockFrequency = platform->intrFrequency();
}
Fault
Fault *
AlphaConsole::read(MemReqPtr &req, uint8_t *data)
{
memset(data, 0, req->size);
@ -183,13 +183,13 @@ AlphaConsole::read(MemReqPtr &req, uint8_t *data)
}
break;
default:
return Machine_Check_Fault;
return MachineCheckFault;
}
return No_Fault;
return NoFault;
}
Fault
Fault *
AlphaConsole::write(MemReqPtr &req, const uint8_t *data)
{
uint64_t val;
@ -203,7 +203,7 @@ AlphaConsole::write(MemReqPtr &req, const uint8_t *data)
val = *(uint64_t *)data;
break;
default:
return Machine_Check_Fault;
return MachineCheckFault;
}
Addr daddr = req->paddr - (addr & EV5::PAddrImplMask);
@ -256,10 +256,10 @@ AlphaConsole::write(MemReqPtr &req, const uint8_t *data)
break;
default:
return Machine_Check_Fault;
return MachineCheckFault;
}
return No_Fault;
return NoFault;
}
Tick

4
dev/alpha_console.hh
View file

@ -110,8 +110,8 @@ class AlphaConsole : public PioDevice
/**
* memory mapped reads and writes
*/
virtual Fault read(MemReqPtr &req, uint8_t *data);
virtual Fault write(MemReqPtr &req, const uint8_t *data);
virtual Fault * read(MemReqPtr &req, uint8_t *data);
virtual Fault * write(MemReqPtr &req, const uint8_t *data);
/**
* standard serialization routines for checkpointing

8
dev/baddev.cc
View file

@ -61,19 +61,19 @@ BadDevice::BadDevice(const string &name, Addr a, MemoryController *mmu,
}
Fault
Fault *
BadDevice::read(MemReqPtr &req, uint8_t *data)
{
panic("Device %s not imlpmented\n", devname);
return No_Fault;
return NoFault;
}
Fault
Fault *
BadDevice::write(MemReqPtr &req, const uint8_t *data)
{
panic("Device %s not imlpmented\n", devname);
return No_Fault;
return NoFault;
}
Tick

4
dev/baddev.hh
View file

@ -71,7 +71,7 @@ class BadDevice : public PioDevice
* @param data A pointer to write the read data to.
* @return The fault condition of the access.
*/
virtual Fault read(MemReqPtr &req, uint8_t *data);
virtual Fault * read(MemReqPtr &req, uint8_t *data);
/**
* On a write event we just panic aand hopefully print a
@ -80,7 +80,7 @@ class BadDevice : public PioDevice
* @param data The data to write.
* @return The fault condition of the access.
*/
virtual Fault write(MemReqPtr &req, const uint8_t *data);
virtual Fault * write(MemReqPtr &req, const uint8_t *data);
/**
* Return how long this access will take.

14
dev/ide_ctrl.cc
View file

@ -390,7 +390,7 @@ IdeController::writeConfig(int offset, int size, const uint8_t *data)
}
}
Fault
Fault *
IdeController::read(MemReqPtr &req, uint8_t *data)
{
Addr offset;
@ -401,7 +401,7 @@ IdeController::read(MemReqPtr &req, uint8_t *data)
parseAddr(req->paddr, offset, channel, reg_type);
if (!io_enabled)
return No_Fault;
return NoFault;
switch (reg_type) {
case BMI_BLOCK:
@ -457,10 +457,10 @@ IdeController::read(MemReqPtr &req, uint8_t *data)
DPRINTF(IdeCtrl, "read from offset: %#x size: %#x data: %#x\n",
offset, req->size, *(uint32_t*)data);
return No_Fault;
return NoFault;
}
Fault
Fault *
IdeController::write(MemReqPtr &req, const uint8_t *data)
{
Addr offset;
@ -472,12 +472,12 @@ IdeController::write(MemReqPtr &req, const uint8_t *data)
parseAddr(req->paddr, offset, channel, reg_type);
if (!io_enabled)
return No_Fault;
return NoFault;
switch (reg_type) {
case BMI_BLOCK:
if (!bm_enabled)
return No_Fault;
return NoFault;
switch (offset) {
// Bus master IDE command register
@ -627,7 +627,7 @@ IdeController::write(MemReqPtr &req, const uint8_t *data)
DPRINTF(IdeCtrl, "write to offset: %#x size: %#x data: %#x\n",
offset, req->size, *(uint32_t*)data);
return No_Fault;
return NoFault;
}
////

4
dev/ide_ctrl.hh
View file

@ -213,7 +213,7 @@ class IdeController : public PciDev
* @param data Return the field read.
* @return The fault condition of the access.
*/
virtual Fault read(MemReqPtr &req, uint8_t *data);
virtual Fault * read(MemReqPtr &req, uint8_t *data);
/**
* Write to the mmapped I/O control registers.
@ -221,7 +221,7 @@ class IdeController : public PciDev
* @param data The data to write.
* @return The fault condition of the access.
*/
virtual Fault write(MemReqPtr &req, const uint8_t *data);
virtual Fault * write(MemReqPtr &req, const uint8_t *data);
/**
* Serialize this object to the given output stream.

16
dev/isa_fake.cc
View file

@ -59,7 +59,7 @@ IsaFake::IsaFake(const string &name, Addr a, MemoryController *mmu,
}
}
Fault
Fault *
IsaFake::read(MemReqPtr &req, uint8_t *data)
{
DPRINTF(Tsunami, "read va=%#x size=%d\n",
@ -73,26 +73,26 @@ IsaFake::read(MemReqPtr &req, uint8_t *data)
case sizeof(uint64_t):
*(uint64_t*)data = 0xFFFFFFFFFFFFFFFFULL;
return No_Fault;
return NoFault;
case sizeof(uint32_t):
*(uint32_t*)data = 0xFFFFFFFF;
return No_Fault;
return NoFault;
case sizeof(uint16_t):
*(uint16_t*)data = 0xFFFF;
return No_Fault;
return NoFault;
case sizeof(uint8_t):
*(uint8_t*)data = 0xFF;
return No_Fault;
return NoFault;
default:
panic("invalid access size(?) for PCI configspace!\n");
}
DPRINTFN("Isa FakeSMC ERROR: read daddr=%#x size=%d\n", daddr, req->size);
return No_Fault;
return NoFault;
}
Fault
Fault *
IsaFake::write(MemReqPtr &req, const uint8_t *data)
{
DPRINTF(Tsunami, "write - va=%#x size=%d \n",
@ -100,7 +100,7 @@ IsaFake::write(MemReqPtr &req, const uint8_t *data)
//:Addr daddr = (req->paddr & addr_mask) >> 6;
return No_Fault;
return NoFault;
}
Tick

4
dev/isa_fake.hh
View file

@ -65,14 +65,14 @@ class IsaFake : public PioDevice
* @param req The memory request.
* @param data Where to put the data.
*/
virtual Fault read(MemReqPtr &req, uint8_t *data);
virtual Fault * read(MemReqPtr &req, uint8_t *data);
/**
* All writes are simply ignored.
* @param req The memory request.
* @param data the data to not write.
*/
virtual Fault write(MemReqPtr &req, const uint8_t *data);
virtual Fault * write(MemReqPtr &req, const uint8_t *data);
/**
* Return how long this access will take.

14
dev/ns_gige.cc
View file

@ -558,7 +558,7 @@ NSGigE::writeConfig(int offset, int size, const uint8_t* data)
* This reads the device registers, which are detailed in the NS83820
* spec sheet
*/
Fault
Fault *
NSGigE::read(MemReqPtr &req, uint8_t *data)
{
assert(ioEnable);
@ -575,14 +575,14 @@ NSGigE::read(MemReqPtr &req, uint8_t *data)
panic("Accessing reserved register");
} else if (daddr > RESERVED && daddr <= 0x3FC) {
readConfig(daddr & 0xff, req->size, data);
return No_Fault;
return NoFault;
} else if (daddr >= MIB_START && daddr <= MIB_END) {
// don't implement all the MIB's. hopefully the kernel
// doesn't actually DEPEND upon their values
// MIB are just hardware stats keepers
uint32_t &reg = *(uint32_t *) data;
reg = 0;
return No_Fault;
return NoFault;
} else if (daddr > 0x3FC)
panic("Something is messed up!\n");
@ -784,10 +784,10 @@ NSGigE::read(MemReqPtr &req, uint8_t *data)
daddr, req->size);
}
return No_Fault;
return NoFault;
}
Fault
Fault *
NSGigE::write(MemReqPtr &req, const uint8_t *data)
{
assert(ioEnable);
@ -800,7 +800,7 @@ NSGigE::write(MemReqPtr &req, const uint8_t *data)
panic("Accessing reserved register");
} else if (daddr > RESERVED && daddr <= 0x3FC) {
writeConfig(daddr & 0xff, req->size, data);
return No_Fault;
return NoFault;
} else if (daddr > 0x3FC)
panic("Something is messed up!\n");
@ -1203,7 +1203,7 @@ NSGigE::write(MemReqPtr &req, const uint8_t *data)
panic("Invalid Request Size");
}
return No_Fault;
return NoFault;
}
void

4
dev/ns_gige.hh
View file

@ -408,8 +408,8 @@ class NSGigE : public PciDev
virtual void writeConfig(int offset, int size, const uint8_t *data);
virtual void readConfig(int offset, int size, uint8_t *data);
virtual Fault read(MemReqPtr &req, uint8_t *data);
virtual Fault write(MemReqPtr &req, const uint8_t *data);
virtual Fault * read(MemReqPtr &req, uint8_t *data);
virtual Fault * write(MemReqPtr &req, const uint8_t *data);
bool cpuIntrPending() const;
void cpuIntrAck() { cpuIntrClear(); }

18
dev/pciconfigall.cc
View file

@ -95,7 +95,7 @@ PciConfigAll::startup()
}
Fault
Fault *
PciConfigAll::read(MemReqPtr &req, uint8_t *data)
{
@ -112,16 +112,16 @@ PciConfigAll::read(MemReqPtr &req, uint8_t *data)
switch (req->size) {
// case sizeof(uint64_t):
// *(uint64_t*)data = 0xFFFFFFFFFFFFFFFF;
// return No_Fault;
// return NoFault;
case sizeof(uint32_t):
*(uint32_t*)data = 0xFFFFFFFF;
return No_Fault;
return NoFault;
case sizeof(uint16_t):
*(uint16_t*)data = 0xFFFF;
return No_Fault;
return NoFault;
case sizeof(uint8_t):
*(uint8_t*)data = 0xFF;
return No_Fault;
return NoFault;
default:
panic("invalid access size(?) for PCI configspace!\n");
}
@ -131,7 +131,7 @@ PciConfigAll::read(MemReqPtr &req, uint8_t *data)
case sizeof(uint16_t):
case sizeof(uint8_t):
devices[device][func]->readConfig(reg, req->size, data);
return No_Fault;
return NoFault;
default:
panic("invalid access size(?) for PCI configspace!\n");
}
@ -140,10 +140,10 @@ PciConfigAll::read(MemReqPtr &req, uint8_t *data)
DPRINTFN("PCI Configspace ERROR: read daddr=%#x size=%d\n",
daddr, req->size);
return No_Fault;
return NoFault;
}
Fault
Fault *
PciConfigAll::write(MemReqPtr &req, const uint8_t *data)
{
Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask));
@ -164,7 +164,7 @@ PciConfigAll::write(MemReqPtr &req, const uint8_t *data)
devices[device][func]->writeConfig(reg, req->size, data);
return No_Fault;
return NoFault;
}
void

4
dev/pciconfigall.hh
View file

@ -103,7 +103,7 @@ class PciConfigAll : public PioDevice
* @param data Return the field read.
* @return The fault condition of the access.
*/
virtual Fault read(MemReqPtr &req, uint8_t *data);
virtual Fault * read(MemReqPtr &req, uint8_t *data);
/**
* Write to PCI config spcae. If the device does not exit the simulator
@ -114,7 +114,7 @@ class PciConfigAll : public PioDevice
* @return The fault condition of the access.
*/
virtual Fault write(MemReqPtr &req, const uint8_t *data);
virtual Fault * write(MemReqPtr &req, const uint8_t *data);
/**
* Start up function to check if more than one person is using an interrupt line

32
dev/pcidev.cc
View file

@ -70,59 +70,59 @@ PciDev::PciDev(Params *p)
p->configSpace->registerDevice(p->deviceNum, p->functionNum, this);
}
Fault
Fault *
PciDev::read(MemReqPtr &req, uint8_t *data)
{ return No_Fault; }
{ return NoFault; }
Fault
Fault *
PciDev::write(MemReqPtr &req, const uint8_t *data)
{ return No_Fault; }
{ return NoFault; }
Fault
Fault *
PciDev::readBar0(MemReqPtr &req, Addr daddr, uint8_t *data)
{ panic("not implemented"); }
Fault
Fault *
PciDev::readBar1(MemReqPtr &req, Addr daddr, uint8_t *data)
{ panic("not implemented"); }
Fault
Fault *
PciDev::readBar2(MemReqPtr &req, Addr daddr, uint8_t *data)
{ panic("not implemented"); }
Fault
Fault *
PciDev::readBar3(MemReqPtr &req, Addr daddr, uint8_t *data)
{ panic("not implemented"); }
Fault
Fault *
PciDev::readBar4(MemReqPtr &req, Addr daddr, uint8_t *data)
{ panic("not implemented"); }
Fault
Fault *
PciDev::readBar5(MemReqPtr &req, Addr daddr, uint8_t *data)
{ panic("not implemented"); }
Fault
Fault *
PciDev::writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data)
{ panic("not implemented"); }
Fault
Fault *
PciDev::writeBar1(MemReqPtr &req, Addr daddr, const uint8_t *data)
{ panic("not implemented"); }
Fault
Fault *
PciDev::writeBar2(MemReqPtr &req, Addr daddr, const uint8_t *data)
{ panic("not implemented"); }
Fault
Fault *
PciDev::writeBar3(MemReqPtr &req, Addr daddr, const uint8_t *data)
{ panic("not implemented"); }
Fault
Fault *
PciDev::writeBar4(MemReqPtr &req, Addr daddr, const uint8_t *data)
{ panic("not implemented"); }
Fault
Fault *
PciDev::writeBar5(MemReqPtr &req, Addr daddr, const uint8_t *data)
{ panic("not implemented"); }

40
dev/pcidev.hh
View file

@ -189,37 +189,37 @@ class PciDev : public DmaDevice
*/
PciDev(Params *params);
virtual Fault read(MemReqPtr &req, uint8_t *data);
virtual Fault write(MemReqPtr &req, const uint8_t *data);
virtual Fault * read(MemReqPtr &req, uint8_t *data);
virtual Fault * write(MemReqPtr &req, const uint8_t *data);
public:
/**
* Implement the read/write as BAR accesses
*/
Fault readBar(MemReqPtr &req, uint8_t *data);
Fault writeBar(MemReqPtr &req, const uint8_t *data);
Fault * readBar(MemReqPtr &req, uint8_t *data);
Fault * writeBar(MemReqPtr &req, const uint8_t *data);
public:
/**
* Read from a specific BAR
*/
virtual Fault readBar0(MemReqPtr &req, Addr daddr, uint8_t *data);
virtual Fault readBar1(MemReqPtr &req, Addr daddr, uint8_t *data);
virtual Fault readBar2(MemReqPtr &req, Addr daddr, uint8_t *data);
virtual Fault readBar3(MemReqPtr &req, Addr daddr, uint8_t *data);
virtual Fault readBar4(MemReqPtr &req, Addr daddr, uint8_t *data);
virtual Fault readBar5(MemReqPtr &req, Addr daddr, uint8_t *data);
virtual Fault * readBar0(MemReqPtr &req, Addr daddr, uint8_t *data);
virtual Fault * readBar1(MemReqPtr &req, Addr daddr, uint8_t *data);
virtual Fault * readBar2(MemReqPtr &req, Addr daddr, uint8_t *data);
virtual Fault * readBar3(MemReqPtr &req, Addr daddr, uint8_t *data);
virtual Fault * readBar4(MemReqPtr &req, Addr daddr, uint8_t *data);
virtual Fault * readBar5(MemReqPtr &req, Addr daddr, uint8_t *data);
public:
/**
* Write to a specific BAR
*/
virtual Fault writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data);
virtual Fault writeBar1(MemReqPtr &req, Addr daddr, const uint8_t *data);
virtual Fault writeBar2(MemReqPtr &req, Addr daddr, const uint8_t *data);
virtual Fault writeBar3(MemReqPtr &req, Addr daddr, const uint8_t *data);
virtual Fault writeBar4(MemReqPtr &req, Addr daddr, const uint8_t *data);
virtual Fault writeBar5(MemReqPtr &req, Addr daddr, const uint8_t *data);
virtual Fault * writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data);
virtual Fault * writeBar1(MemReqPtr &req, Addr daddr, const uint8_t *data);
virtual Fault * writeBar2(MemReqPtr &req, Addr daddr, const uint8_t *data);
virtual Fault * writeBar3(MemReqPtr &req, Addr daddr, const uint8_t *data);
virtual Fault * writeBar4(MemReqPtr &req, Addr daddr, const uint8_t *data);
virtual Fault * writeBar5(MemReqPtr &req, Addr daddr, const uint8_t *data);
public:
/**
@ -257,7 +257,7 @@ class PciDev : public DmaDevice
virtual void unserialize(Checkpoint *cp, const std::string &section);
};
inline Fault
inline Fault *
PciDev::readBar(MemReqPtr &req, uint8_t *data)
{
if (isBAR(req->paddr, 0))
@ -272,10 +272,10 @@ PciDev::readBar(MemReqPtr &req, uint8_t *data)
return readBar4(req, req->paddr - BARAddrs[4], data);
if (isBAR(req->paddr, 5))
return readBar5(req, req->paddr - BARAddrs[5], data);
return Machine_Check_Fault;
return MachineCheckFault;
}
inline Fault
inline Fault *
PciDev::writeBar(MemReqPtr &req, const uint8_t *data)
{
if (isBAR(req->paddr, 0))
@ -290,7 +290,7 @@ PciDev::writeBar(MemReqPtr &req, const uint8_t *data)
return writeBar4(req, req->paddr - BARAddrs[4], data);
if (isBAR(req->paddr, 5))
return writeBar5(req, req->paddr - BARAddrs[5], data);
return Machine_Check_Fault;
return MachineCheckFault;
}
#endif // __DEV_PCIDEV_HH__

28
dev/sinic.cc
View file

@ -361,23 +361,23 @@ Device::prepareWrite(int cpu, int index)
/**
* I/O read of device register
*/
Fault
Fault *
Device::read(MemReqPtr &req, uint8_t *data)
{
assert(config.command & PCI_CMD_MSE);
Fault fault = readBar(req, data);
Fault * fault = readBar(req, data);
if (fault == Machine_Check_Fault) {
if (fault == MachineCheckFault) {
panic("address does not map to a BAR pa=%#x va=%#x size=%d",
req->paddr, req->vaddr, req->size);
return Machine_Check_Fault;
return MachineCheckFault;
}
return fault;
}
Fault
Fault *
Device::readBar0(MemReqPtr &req, Addr daddr, uint8_t *data)
{
int cpu = (req->xc->regs.ipr[TheISA::IPR_PALtemp16] >> 8) & 0xff;
@ -421,13 +421,13 @@ Device::readBar0(MemReqPtr &req, Addr daddr, uint8_t *data)
if (raddr == Regs::IntrStatus)
devIntrClear();
return No_Fault;
return NoFault;
}
/**
* IPR read of device register
*/
Fault
Fault *
Device::iprRead(Addr daddr, int cpu, uint64_t &result)
{
if (!regValid(daddr))
@ -451,29 +451,29 @@ Device::iprRead(Addr daddr, int cpu, uint64_t &result)
DPRINTF(EthernetPIO, "IPR read %s: cpu=%s da=%#x val=%#x\n",
info.name, cpu, result);
return No_Fault;
return NoFault;
}
/**
* I/O write of device register
*/
Fault
Fault *
Device::write(MemReqPtr &req, const uint8_t *data)
{
assert(config.command & PCI_CMD_MSE);
Fault fault = writeBar(req, data);
Fault * fault = writeBar(req, data);
if (fault == Machine_Check_Fault) {
if (fault == MachineCheckFault) {
panic("address does not map to a BAR pa=%#x va=%#x size=%d",
req->paddr, req->vaddr, req->size);
return Machine_Check_Fault;
return MachineCheckFault;
}
return fault;
}
Fault
Fault *
Device::writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data)
{
int cpu = (req->xc->regs.ipr[TheISA::IPR_PALtemp16] >> 8) & 0xff;
@ -508,7 +508,7 @@ Device::writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data)
if (!pioDelayWrite || !info.delay_write)
regWrite(daddr, cpu, data);
return No_Fault;
return NoFault;
}
void

10
dev/sinic.hh
View file

@ -271,15 +271,15 @@ class Device : public Base
* Memory Interface
*/
public:
virtual Fault read(MemReqPtr &req, uint8_t *data);
virtual Fault write(MemReqPtr &req, const uint8_t *data);
virtual Fault * read(MemReqPtr &req, uint8_t *data);
virtual Fault * write(MemReqPtr &req, const uint8_t *data);
void prepareIO(int cpu, int index);
void prepareRead(int cpu, int index);
void prepareWrite(int cpu, int index);
Fault iprRead(Addr daddr, int cpu, uint64_t &result);
Fault readBar0(MemReqPtr &req, Addr daddr, uint8_t *data);
Fault writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data);
Fault * iprRead(Addr daddr, int cpu, uint64_t &result);
Fault * readBar0(MemReqPtr &req, Addr daddr, uint8_t *data);
Fault * writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data);
void regWrite(Addr daddr, int cpu, const uint8_t *data);
Tick cacheAccess(MemReqPtr &req);

68
dev/tsunami_cchip.cc
View file

@ -76,7 +76,7 @@ TsunamiCChip::TsunamiCChip(const string &name, Tsunami *t, Addr a,
tsunami->cchip = this;
}
Fault
Fault *
TsunamiCChip::read(MemReqPtr &req, uint8_t *data)
{
DPRINTF(Tsunami, "read va=%#x size=%d\n", req->vaddr, req->size);
@ -92,81 +92,81 @@ TsunamiCChip::read(MemReqPtr &req, uint8_t *data)
if (daddr & TSDEV_CC_BDIMS)
{
*(uint64_t*)data = dim[(daddr >> 4) & 0x3F];
return No_Fault;
return NoFault;
}
if (daddr & TSDEV_CC_BDIRS)
{
*(uint64_t*)data = dir[(daddr >> 4) & 0x3F];
return No_Fault;
return NoFault;
}
switch(regnum) {
case TSDEV_CC_CSR:
*(uint64_t*)data = 0x0;
return No_Fault;
return NoFault;
case TSDEV_CC_MTR:
panic("TSDEV_CC_MTR not implemeted\n");
return No_Fault;
return NoFault;
case TSDEV_CC_MISC:
*(uint64_t*)data = (ipint << 8) & 0xF |
(itint << 4) & 0xF |
(xc->cpu_id & 0x3);
return No_Fault;
return NoFault;
case TSDEV_CC_AAR0:
case TSDEV_CC_AAR1:
case TSDEV_CC_AAR2:
case TSDEV_CC_AAR3:
*(uint64_t*)data = 0;
return No_Fault;
return NoFault;
case TSDEV_CC_DIM0:
*(uint64_t*)data = dim[0];
return No_Fault;
return NoFault;
case TSDEV_CC_DIM1:
*(uint64_t*)data = dim[1];
return No_Fault;
return NoFault;
case TSDEV_CC_DIM2:
*(uint64_t*)data = dim[2];
return No_Fault;
return NoFault;
case TSDEV_CC_DIM3:
*(uint64_t*)data = dim[3];
return No_Fault;
return NoFault;
case TSDEV_CC_DIR0:
*(uint64_t*)data = dir[0];
return No_Fault;
return NoFault;
case TSDEV_CC_DIR1:
*(uint64_t*)data = dir[1];
return No_Fault;
return NoFault;
case TSDEV_CC_DIR2:
*(uint64_t*)data = dir[2];
return No_Fault;
return NoFault;
case TSDEV_CC_DIR3:
*(uint64_t*)data = dir[3];
return No_Fault;
return NoFault;
case TSDEV_CC_DRIR:
*(uint64_t*)data = drir;
return No_Fault;
return NoFault;
case TSDEV_CC_PRBEN:
panic("TSDEV_CC_PRBEN not implemented\n");
return No_Fault;
return NoFault;
case TSDEV_CC_IIC0:
case TSDEV_CC_IIC1:
case TSDEV_CC_IIC2:
case TSDEV_CC_IIC3:
panic("TSDEV_CC_IICx not implemented\n");
return No_Fault;
return NoFault;
case TSDEV_CC_MPR0:
case TSDEV_CC_MPR1:
case TSDEV_CC_MPR2:
case TSDEV_CC_MPR3:
panic("TSDEV_CC_MPRx not implemented\n");
return No_Fault;
return NoFault;
case TSDEV_CC_IPIR:
*(uint64_t*)data = ipint;
return No_Fault;
return NoFault;
case TSDEV_CC_ITIR:
*(uint64_t*)data = itint;
return No_Fault;
return NoFault;
default:
panic("default in cchip read reached, accessing 0x%x\n");
} // uint64_t
@ -179,7 +179,7 @@ TsunamiCChip::read(MemReqPtr &req, uint8_t *data)
*(uint32_t*)data = drir;
} else
panic("invalid access size(?) for tsunami register!\n");
return No_Fault;
return NoFault;
case sizeof(uint16_t):
case sizeof(uint8_t):
default:
@ -187,10 +187,10 @@ TsunamiCChip::read(MemReqPtr &req, uint8_t *data)
}
DPRINTFN("Tsunami CChip ERROR: read regnum=%#x size=%d\n", regnum, req->size);
return No_Fault;
return NoFault;
}
Fault
Fault *
TsunamiCChip::write(MemReqPtr &req, const uint8_t *data)
{
DPRINTF(Tsunami, "write - va=%#x value=%#x size=%d \n",
@ -243,16 +243,16 @@ TsunamiCChip::write(MemReqPtr &req, const uint8_t *data)
}
}
return No_Fault;
return NoFault;
}
switch(regnum) {
case TSDEV_CC_CSR:
panic("TSDEV_CC_CSR write\n");
return No_Fault;
return NoFault;
case TSDEV_CC_MTR:
panic("TSDEV_CC_MTR write not implemented\n");
return No_Fault;
return NoFault;
case TSDEV_CC_MISC:
uint64_t ipreq;
ipreq = (*(uint64_t*)data >> 12) & 0xF;
@ -285,13 +285,13 @@ TsunamiCChip::write(MemReqPtr &req, const uint8_t *data)
if(!supportedWrite)
panic("TSDEV_CC_MISC write not implemented\n");
return No_Fault;
return NoFault;
case TSDEV_CC_AAR0:
case TSDEV_CC_AAR1:
case TSDEV_CC_AAR2:
case TSDEV_CC_AAR3:
panic("TSDEV_CC_AARx write not implemeted\n");
return No_Fault;
return NoFault;
case TSDEV_CC_DIM0:
case TSDEV_CC_DIM1:
case TSDEV_CC_DIM2:
@ -341,7 +341,7 @@ TsunamiCChip::write(MemReqPtr &req, const uint8_t *data)
}
}
return No_Fault;
return NoFault;
case TSDEV_CC_DIR0:
case TSDEV_CC_DIR1:
case TSDEV_CC_DIR2:
@ -363,13 +363,13 @@ TsunamiCChip::write(MemReqPtr &req, const uint8_t *data)
panic("TSDEV_CC_MPRx write not implemented\n");
case TSDEV_CC_IPIR:
clearIPI(*(uint64_t*)data);
return No_Fault;
return NoFault;
case TSDEV_CC_ITIR:
clearITI(*(uint64_t*)data);
return No_Fault;
return NoFault;
case TSDEV_CC_IPIQ:
reqIPI(*(uint64_t*)data);
return No_Fault;
return NoFault;
default:
panic("default in cchip read reached, accessing 0x%x\n");
}
@ -384,7 +384,7 @@ TsunamiCChip::write(MemReqPtr &req, const uint8_t *data)
DPRINTFN("Tsunami ERROR: write daddr=%#x size=%d\n", daddr, req->size);
return No_Fault;
return NoFault;
}
void

4
dev/tsunami_cchip.hh
View file

@ -105,7 +105,7 @@ class TsunamiCChip : public PioDevice
* @param data A pointer to write the read data to.
* @return The fault condition of the access.
*/
virtual Fault read(MemReqPtr &req, uint8_t *data);
virtual Fault * read(MemReqPtr &req, uint8_t *data);
/**
@ -114,7 +114,7 @@ class TsunamiCChip : public PioDevice
* @param data The data to write.
* @return The fault condition of the access.
*/
virtual Fault write(MemReqPtr &req, const uint8_t *data);
virtual Fault * write(MemReqPtr &req, const uint8_t *data);
/**
* post an RTC interrupt to the CPU

70
dev/tsunami_io.cc
View file

@ -444,7 +444,7 @@ TsunamiIO::frequency() const
return Clock::Frequency / clockInterval;
}
Fault
Fault *
TsunamiIO::read(MemReqPtr &req, uint8_t *data)
{
DPRINTF(Tsunami, "io read va=%#x size=%d IOPorrt=%#x\n",
@ -459,38 +459,38 @@ TsunamiIO::read(MemReqPtr &req, uint8_t *data)
// PIC1 mask read
case TSDEV_PIC1_MASK:
*(uint8_t*)data = ~mask1;
return No_Fault;
return NoFault;
case TSDEV_PIC2_MASK:
*(uint8_t*)data = ~mask2;
return No_Fault;
return NoFault;
case TSDEV_PIC1_ISR:
// !!! If this is modified 64bit case needs to be too
// Pal code has to do a 64 bit physical read because there is
// no load physical byte instruction
*(uint8_t*)data = picr;
return No_Fault;
return NoFault;
case TSDEV_PIC2_ISR:
// PIC2 not implemnted... just return 0
*(uint8_t*)data = 0x00;
return No_Fault;
return NoFault;
case TSDEV_TMR0_DATA:
pitimer.counter0.read(data);
return No_Fault;
return NoFault;
case TSDEV_TMR1_DATA:
pitimer.counter1.read(data);
return No_Fault;
return NoFault;
case TSDEV_TMR2_DATA:
pitimer.counter2.read(data);
return No_Fault;
return NoFault;
case TSDEV_RTC_DATA:
rtc.readData(data);
return No_Fault;
return NoFault;
case TSDEV_CTRL_PORTB:
if (pitimer.counter2.outputHigh())
*data = PORTB_SPKR_HIGH;
else
*data = 0x00;
return No_Fault;
return NoFault;
default:
panic("I/O Read - va%#x size %d\n", req->vaddr, req->size);
}
@ -506,7 +506,7 @@ TsunamiIO::read(MemReqPtr &req, uint8_t *data)
// Pal code has to do a 64 bit physical read because there is
// no load physical byte instruction
*(uint64_t*)data = (uint64_t)picr;
return No_Fault;
return NoFault;
default:
panic("I/O Read - invalid size - va %#x size %d\n",
req->vaddr, req->size);
@ -518,10 +518,10 @@ TsunamiIO::read(MemReqPtr &req, uint8_t *data)
}
panic("I/O Read - va%#x size %d\n", req->vaddr, req->size);
return No_Fault;
return NoFault;
}
Fault
Fault *
TsunamiIO::write(MemReqPtr &req, const uint8_t *data)
{
@ -550,63 +550,63 @@ TsunamiIO::write(MemReqPtr &req, const uint8_t *data)
tsunami->cchip->clearDRIR(55);
DPRINTF(Tsunami, "clearing pic interrupt\n");
}
return No_Fault;
return NoFault;
case TSDEV_PIC2_MASK:
mask2 = *(uint8_t*)data;
//PIC2 Not implemented to interrupt
return No_Fault;
return NoFault;
case TSDEV_PIC1_ACK:
// clear the interrupt on the PIC
picr &= ~(1 << (*(uint8_t*)data & 0xF));
if (!(picr & mask1))
tsunami->cchip->clearDRIR(55);
return No_Fault;
return NoFault;
case TSDEV_DMA1_CMND:
return No_Fault;
return NoFault;
case TSDEV_DMA2_CMND:
return No_Fault;
return NoFault;
case TSDEV_DMA1_MMASK:
return No_Fault;
return NoFault;
case TSDEV_DMA2_MMASK:
return No_Fault;
return NoFault;
case TSDEV_PIC2_ACK:
return No_Fault;
return NoFault;
case TSDEV_DMA1_RESET:
return No_Fault;
return NoFault;
case TSDEV_DMA2_RESET:
return No_Fault;
return NoFault;
case TSDEV_DMA1_MODE:
mode1 = *(uint8_t*)data;
return No_Fault;
return NoFault;
case TSDEV_DMA2_MODE:
mode2 = *(uint8_t*)data;
return No_Fault;
return NoFault;
case TSDEV_DMA1_MASK:
case TSDEV_DMA2_MASK:
return No_Fault;
return NoFault;
case TSDEV_TMR0_DATA:
pitimer.counter0.write(data);
return No_Fault;
return NoFault;
case TSDEV_TMR1_DATA:
pitimer.counter1.write(data);
return No_Fault;
return NoFault;
case TSDEV_TMR2_DATA:
pitimer.counter2.write(data);
return No_Fault;
return NoFault;
case TSDEV_TMR_CTRL:
pitimer.writeControl(data);
return No_Fault;
return NoFault;
case TSDEV_RTC_ADDR:
rtc.writeAddr(data);
return No_Fault;
return NoFault;
case TSDEV_KBD:
return No_Fault;
return NoFault;
case TSDEV_RTC_DATA:
rtc.writeData(data);
return No_Fault;
return NoFault;
case TSDEV_CTRL_PORTB:
// System Control Port B not implemented
return No_Fault;
return NoFault;
default:
panic("I/O Write - va%#x size %d data %#x\n", req->vaddr, req->size, (int)*data);
}
@ -619,7 +619,7 @@ TsunamiIO::write(MemReqPtr &req, const uint8_t *data)
}
return No_Fault;
return NoFault;
}
void

4
dev/tsunami_io.hh
View file

@ -330,7 +330,7 @@ class TsunamiIO : public PioDevice
* @param data A pointer to write the read data to.
* @return The fault condition of the access.
*/
virtual Fault read(MemReqPtr &req, uint8_t *data);
virtual Fault * read(MemReqPtr &req, uint8_t *data);
/**
* Process a write to one of the devices we emulate.
@ -338,7 +338,7 @@ class TsunamiIO : public PioDevice
* @param data The data to write.
* @return The fault condition of the access.
*/
virtual Fault write(MemReqPtr &req, const uint8_t *data);
virtual Fault * write(MemReqPtr &req, const uint8_t *data);
/**
* Post an PIC interrupt to the CPU via the CChip

70
dev/tsunami_pchip.cc
View file

@ -76,7 +76,7 @@ TsunamiPChip::TsunamiPChip(const string &name, Tsunami *t, Addr a,
tsunami->pchip = this;
}
Fault
Fault *
TsunamiPChip::read(MemReqPtr &req, uint8_t *data)
{
DPRINTF(Tsunami, "read va=%#x size=%d\n",
@ -90,60 +90,60 @@ TsunamiPChip::read(MemReqPtr &req, uint8_t *data)
switch(daddr) {
case TSDEV_PC_WSBA0:
*(uint64_t*)data = wsba[0];
return No_Fault;
return NoFault;
case TSDEV_PC_WSBA1:
*(uint64_t*)data = wsba[1];
return No_Fault;
return NoFault;
case TSDEV_PC_WSBA2:
*(uint64_t*)data = wsba[2];
return No_Fault;
return NoFault;
case TSDEV_PC_WSBA3:
*(uint64_t*)data = wsba[3];
return No_Fault;
return NoFault;
case TSDEV_PC_WSM0:
*(uint64_t*)data = wsm[0];
return No_Fault;
return NoFault;
case TSDEV_PC_WSM1:
*(uint64_t*)data = wsm[1];
return No_Fault;
return NoFault;
case TSDEV_PC_WSM2:
*(uint64_t*)data = wsm[2];
return No_Fault;
return NoFault;
case TSDEV_PC_WSM3:
*(uint64_t*)data = wsm[3];
return No_Fault;
return NoFault;
case TSDEV_PC_TBA0:
*(uint64_t*)data = tba[0];
return No_Fault;
return NoFault;
case TSDEV_PC_TBA1:
*(uint64_t*)data = tba[1];
return No_Fault;
return NoFault;
case TSDEV_PC_TBA2:
*(uint64_t*)data = tba[2];
return No_Fault;
return NoFault;
case TSDEV_PC_TBA3:
*(uint64_t*)data = tba[3];
return No_Fault;
return NoFault;
case TSDEV_PC_PCTL:
*(uint64_t*)data = pctl;
return No_Fault;
return NoFault;
case TSDEV_PC_PLAT:
panic("PC_PLAT not implemented\n");
case TSDEV_PC_RES:
panic("PC_RES not implemented\n");
case TSDEV_PC_PERROR:
*(uint64_t*)data = 0x00;
return No_Fault;
return NoFault;
case TSDEV_PC_PERRMASK:
*(uint64_t*)data = 0x00;
return No_Fault;
return NoFault;
case TSDEV_PC_PERRSET:
panic("PC_PERRSET not implemented\n");
case TSDEV_PC_TLBIV:
panic("PC_TLBIV not implemented\n");
case TSDEV_PC_TLBIA:
*(uint64_t*)data = 0x00; // shouldn't be readable, but linux
return No_Fault;
return NoFault;
case TSDEV_PC_PMONCTL:
panic("PC_PMONCTL not implemented\n");
case TSDEV_PC_PMONCNT:
@ -162,10 +162,10 @@ TsunamiPChip::read(MemReqPtr &req, uint8_t *data)
}
DPRINTFN("Tsunami PChip ERROR: read daddr=%#x size=%d\n", daddr, req->size);
return No_Fault;
return NoFault;
}
Fault
Fault *
TsunamiPChip::write(MemReqPtr &req, const uint8_t *data)
{
DPRINTF(Tsunami, "write - va=%#x size=%d \n",
@ -179,49 +179,49 @@ TsunamiPChip::write(MemReqPtr &req, const uint8_t *data)
switch(daddr) {
case TSDEV_PC_WSBA0:
wsba[0] = *(uint64_t*)data;
return No_Fault;
return NoFault;
case TSDEV_PC_WSBA1:
wsba[1] = *(uint64_t*)data;
return No_Fault;
return NoFault;
case TSDEV_PC_WSBA2:
wsba[2] = *(uint64_t*)data;
return No_Fault;
return NoFault;
case TSDEV_PC_WSBA3:
wsba[3] = *(uint64_t*)data;
return No_Fault;
return NoFault;
case TSDEV_PC_WSM0:
wsm[0] = *(uint64_t*)data;
return No_Fault;
return NoFault;
case TSDEV_PC_WSM1:
wsm[1] = *(uint64_t*)data;
return No_Fault;
return NoFault;
case TSDEV_PC_WSM2:
wsm[2] = *(uint64_t*)data;
return No_Fault;
return NoFault;
case TSDEV_PC_WSM3:
wsm[3] = *(uint64_t*)data;
return No_Fault;
return NoFault;
case TSDEV_PC_TBA0:
tba[0] = *(uint64_t*)data;
return No_Fault;
return NoFault;
case TSDEV_PC_TBA1:
tba[1] = *(uint64_t*)data;
return No_Fault;
return NoFault;
case TSDEV_PC_TBA2:
tba[2] = *(uint64_t*)data;
return No_Fault;
return NoFault;
case TSDEV_PC_TBA3:
tba[3] = *(uint64_t*)data;
return No_Fault;
return NoFault;
case TSDEV_PC_PCTL:
pctl = *(uint64_t*)data;
return No_Fault;
return NoFault;
case TSDEV_PC_PLAT:
panic("PC_PLAT not implemented\n");
case TSDEV_PC_RES:
panic("PC_RES not implemented\n");
case TSDEV_PC_PERROR:
return No_Fault;
return NoFault;
case TSDEV_PC_PERRMASK:
panic("PC_PERRMASK not implemented\n");
case TSDEV_PC_PERRSET:
@ -229,7 +229,7 @@ TsunamiPChip::write(MemReqPtr &req, const uint8_t *data)
case TSDEV_PC_TLBIV:
panic("PC_TLBIV not implemented\n");
case TSDEV_PC_TLBIA:
return No_Fault; // value ignored, supposted to invalidate SG TLB
return NoFault; // value ignored, supposted to invalidate SG TLB
case TSDEV_PC_PMONCTL:
panic("PC_PMONCTL not implemented\n");
case TSDEV_PC_PMONCNT:
@ -249,7 +249,7 @@ TsunamiPChip::write(MemReqPtr &req, const uint8_t *data)
DPRINTFN("Tsunami ERROR: write daddr=%#x size=%d\n", daddr, req->size);
return No_Fault;
return NoFault;
}
#define DMA_ADDR_MASK ULL(0x3ffffffff)

4
dev/tsunami_pchip.hh
View file

@ -99,7 +99,7 @@ class TsunamiPChip : public PioDevice
* @param data A pointer to write the read data to.
* @return The fault condition of the access.
*/
virtual Fault read(MemReqPtr &req, uint8_t *data);
virtual Fault * read(MemReqPtr &req, uint8_t *data);
/**
* Process a write to the PChip.
@ -107,7 +107,7 @@ class TsunamiPChip : public PioDevice
* @param data The data to write.
* @return The fault condition of the access.
*/
virtual Fault write(MemReqPtr &req, const uint8_t *data);
virtual Fault * write(MemReqPtr &req, const uint8_t *data);
/**
* Serialize this object to the given output stream.

4
dev/uart.hh
View file

@ -57,8 +57,8 @@ class Uart : public PioDevice
Addr a, Addr s, HierParams *hier, Bus *bus, Tick pio_latency,
Platform *p);
virtual Fault read(MemReqPtr &req, uint8_t *data) = 0;
virtual Fault write(MemReqPtr &req, const uint8_t *data) = 0;
virtual Fault * read(MemReqPtr &req, uint8_t *data) = 0;
virtual Fault * write(MemReqPtr &req, const uint8_t *data) = 0;
/**

8
dev/uart8250.cc
View file

@ -111,7 +111,7 @@ Uart8250::Uart8250(const string &name, SimConsole *c, MemoryController *mmu,
}
Fault
Fault *
Uart8250::read(MemReqPtr &req, uint8_t *data)
{
Addr daddr = req->paddr - (addr & EV5::PAddrImplMask);
@ -183,11 +183,11 @@ Uart8250::read(MemReqPtr &req, uint8_t *data)
break;
}
return No_Fault;
return NoFault;
}
Fault
Fault *
Uart8250::write(MemReqPtr &req, const uint8_t *data)
{
Addr daddr = req->paddr - (addr & EV5::PAddrImplMask);
@ -255,7 +255,7 @@ Uart8250::write(MemReqPtr &req, const uint8_t *data)
panic("Tried to access a UART port that doesn't exist\n");
break;
}
return No_Fault;
return NoFault;
}
void

4
dev/uart8250.hh
View file

@ -82,8 +82,8 @@ class Uart8250 : public Uart
Addr a, Addr s, HierParams *hier, Bus *pio_bus, Tick pio_latency,
Platform *p);
virtual Fault read(MemReqPtr &req, uint8_t *data);
virtual Fault write(MemReqPtr &req, const uint8_t *data);
virtual Fault * read(MemReqPtr &req, uint8_t *data);
virtual Fault * write(MemReqPtr &req, const uint8_t *data);
/**

6
kern/kernel_stats.cc
View file

@ -137,14 +137,14 @@ Statistics::regStats(const string &_name)
}
_faults
.init(Num_Faults)
.init(NumFaults)
.name(name() + ".faults")
.desc("number of faults")
.flags(total | pdf | nozero | nonan)
;
for (int i = 1; i < Num_Faults; ++i) {
const char *str = FaultName(i);
for (int i = 1; i < NumFaults; ++i) {
const char *str = (*ListOfFaults[i])->name;
if (str)
_faults.subname(i, str);
}

11
kern/kernel_stats.hh
View file

@ -41,7 +41,7 @@ class ExecContext;
class FnEvent;
// What does kernel stats expect is included?
class System;
enum Fault;
class Fault;
namespace Kernel {
@ -176,7 +176,14 @@ class Statistics : public Serializable
void ivlb() { _ivlb++; }
void ivle() { _ivle++; }
void hwrei() { _hwrei++; }
void fault(Fault fault) { _faults[fault]++; }
void fault(Fault * fault)
{
if(fault == NoFault) _faults[0]++;
else if(fault == MachineCheckFault) _faults[2]++;
else if(fault == AlignmentFault) _faults[7]++;
else if(fault == FakeMemFault) _faults[17]++;
else _faults[fault->id]++;
}// FIXME: When there are no generic system fault objects, this will go back to _faults[fault]++; }
void swpipl(int ipl);
void mode(cpu_mode newmode);
void context(Addr oldpcbb, Addr newpcbb);

36
sim/faults.cc Normal file
View file

@ -0,0 +1,36 @@
/*
* Copyright (c) 2003-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "sim/faults.hh"
NoFaultType * NoFault = new NoFaultType("none");
MachineCheckFaultType * MachineCheckFault = new MachineCheckFaultType("mchk");
AlignmentFaultType * AlignmentFault = new AlignmentFaultType("unalign");
//This needs to not exist
FakeMemFaultType * FakeMemFault = new FakeMemFaultType("fakemem");

65
sim/faults.hh Normal file
View file

@ -0,0 +1,65 @@
/*
* Copyright (c) 2003-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __FAULTS_HH__
#define __FAULTS_HH__
class Fault
{
public:
Fault(char * newName, int newId = 0) : name(newName), id(newId) {;}
const char * name;
int id;
};
extern class NoFaultType : public Fault
{
public:
NoFaultType(char * newName) : Fault(newName) {;}
} * NoFault;
extern class MachineCheckFaultType : public Fault
{
public:
MachineCheckFaultType(char * newName) : Fault(newName) {;}
} * MachineCheckFault;
extern class AlignmentFaultType : public Fault
{
public:
AlignmentFaultType(char * newName) : Fault(newName) {;}
} * AlignmentFault;
extern class FakeMemFaultType : public Fault
{
public:
FakeMemFaultType(char * newName) : Fault(newName) {;}
} * FakeMemFault;
#endif // __FAULTS_HH__

10
sim/syscall_emul.cc
View file

@ -191,7 +191,7 @@ unlinkFunc(SyscallDesc *desc, int num, Process *p, ExecContext *xc)
{
string path;
if (xc->mem->readString(path, xc->getSyscallArg(0)) != No_Fault)
if (xc->mem->readString(path, xc->getSyscallArg(0)) != NoFault)
return (TheISA::IntReg)-EFAULT;
int result = unlink(path.c_str());
@ -203,12 +203,12 @@ renameFunc(SyscallDesc *desc, int num, Process *p, ExecContext *xc)
{
string old_name;
if (xc->mem->readString(old_name, xc->getSyscallArg(0)) != No_Fault)
if (xc->mem->readString(old_name, xc->getSyscallArg(0)) != NoFault)
return -EFAULT;
string new_name;
if (xc->mem->readString(new_name, xc->getSyscallArg(1)) != No_Fault)
if (xc->mem->readString(new_name, xc->getSyscallArg(1)) != NoFault)
return -EFAULT;
int64_t result = rename(old_name.c_str(), new_name.c_str());
@ -220,7 +220,7 @@ truncateFunc(SyscallDesc *desc, int num, Process *p, ExecContext *xc)
{
string path;
if (xc->mem->readString(path, xc->getSyscallArg(0)) != No_Fault)
if (xc->mem->readString(path, xc->getSyscallArg(0)) != NoFault)
return -EFAULT;
off_t length = xc->getSyscallArg(1);
@ -248,7 +248,7 @@ chownFunc(SyscallDesc *desc, int num, Process *p, ExecContext *xc)
{
string path;
if (xc->mem->readString(path, xc->getSyscallArg(0)) != No_Fault)
if (xc->mem->readString(path, xc->getSyscallArg(0)) != NoFault)
return -EFAULT;
/* XXX endianess */

14
sim/syscall_emul.hh
View file

@ -317,7 +317,7 @@ openFunc(SyscallDesc *desc, int callnum, Process *process,
{
std::string path;
if (xc->mem->readString(path, xc->getSyscallArg(0)) != No_Fault)
if (xc->mem->readString(path, xc->getSyscallArg(0)) != NoFault)
return -EFAULT;
if (path == "/dev/sysdev0") {
@ -364,7 +364,7 @@ chmodFunc(SyscallDesc *desc, int callnum, Process *process,
{
std::string path;
if (xc->mem->readString(path, xc->getSyscallArg(0)) != No_Fault)
if (xc->mem->readString(path, xc->getSyscallArg(0)) != NoFault)
return -EFAULT;
uint32_t mode = xc->getSyscallArg(1);
@ -417,7 +417,7 @@ statFunc(SyscallDesc *desc, int callnum, Process *process,
{
std::string path;
if (xc->mem->readString(path, xc->getSyscallArg(0)) != No_Fault)
if (xc->mem->readString(path, xc->getSyscallArg(0)) != NoFault)
return -EFAULT;
struct stat hostBuf;
@ -469,7 +469,7 @@ lstatFunc(SyscallDesc *desc, int callnum, Process *process,
{
std::string path;
if (xc->mem->readString(path, xc->getSyscallArg(0)) != No_Fault)
if (xc->mem->readString(path, xc->getSyscallArg(0)) != NoFault)
return -EFAULT;
struct stat hostBuf;
@ -491,7 +491,7 @@ lstat64Func(SyscallDesc *desc, int callnum, Process *process,
{
std::string path;
if (xc->mem->readString(path, xc->getSyscallArg(0)) != No_Fault)
if (xc->mem->readString(path, xc->getSyscallArg(0)) != NoFault)
return -EFAULT;
#if BSD_HOST
@ -542,7 +542,7 @@ statfsFunc(SyscallDesc *desc, int callnum, Process *process,
{
std::string path;
if (xc->mem->readString(path, xc->getSyscallArg(0)) != No_Fault)
if (xc->mem->readString(path, xc->getSyscallArg(0)) != NoFault)
return -EFAULT;
struct statfs hostBuf;
@ -716,7 +716,7 @@ utimesFunc(SyscallDesc *desc, int callnum, Process *process,
{
std::string path;
if (xc->mem->readString(path, xc->getSyscallArg(0)) != No_Fault)
if (xc->mem->readString(path, xc->getSyscallArg(0)) != NoFault)
return -EFAULT;
TypedBufferArg<typename OS::timeval [2]> tp(xc->getSyscallArg(1));