MachineCheckFaults and AlignmentFaults are now generated by the ISA, rather than being created directly.

arch/alpha/alpha_memory.cc:
cpu/base_dyn_inst.cc:
dev/alpha_console.cc:
dev/pcidev.hh:
dev/sinic.cc:
    MachineCheckFaults are now generated by the ISA, rather than being created directly.

--HG--
extra : convert_revision : 34a7da41639e93be21ed70dac681b27480008d19

arch/alpha/alpha_memory.cc

@@ -380,7 +380,7 @@ AlphaITB::translate(MemReqPtr &req) const
 
     // check that the physical address is ok (catch bad physical addresses)
     if (req->paddr & ~PAddrImplMask)
-        return new MachineCheckFault;
+        return genMachineCheckFault();
 
     checkCacheability(req);
 
@@ -511,7 +511,7 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const
         fault(req, write ? MM_STAT_WR_MASK : 0);
         DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->vaddr,
                 req->size);
-        return new AlignmentFault;
+        return genAlignmentFault();
     }
 
     if (pc & 0x1) {
@@ -621,7 +621,7 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const
 
     // check that the physical address is ok (catch bad physical addresses)
     if (req->paddr & ~PAddrImplMask)
-        return new MachineCheckFault;
+        return genMachineCheckFault();
 
     checkCacheability(req);
 

arch/alpha/faults.cc

@@ -32,6 +32,10 @@ FaultName AlphaFault::_name = "alphafault";
 FaultVect AlphaFault::_vect = 0x0000;
 FaultStat AlphaFault::_stat;
 
+FaultVect AlphaMachineCheckFault::_vect = 0x0401;
+
+FaultVect AlphaAlignmentFault::_vect = 0x0301;
+
 FaultName ResetFault::_name = "reset";
 FaultVect ResetFault::_vect = 0x0001;
 FaultStat ResetFault::_stat;

arch/alpha/faults.hh

@@ -31,7 +31,7 @@
 
 #include "sim/faults.hh"
 
-// The reasoning behind the name and vect functions is in sim/faults.hh
+// The design of the "name" and "vect" functions is in sim/faults.hh
 
 typedef const Addr FaultVect;
 
@@ -47,6 +47,32 @@ class AlphaFault : public FaultBase
     virtual FaultStat & stat() {return _stat;}
 };
 
+class AlphaMachineCheckFault : public MachineCheckFault
+{
+  private:
+    static FaultVect _vect;
+  public:
+    FaultVect vect() {return _vect;}
+};
+
+class AlphaAlignmentFault : public AlignmentFault
+{
+  private:
+    static FaultVect _vect;
+  public:
+    FaultVect vect() {return _vect;}
+};
+
+static inline Fault genMachineCheckFault()
+{
+    return new AlphaMachineCheckFault;
+}
+
+static inline Fault genAlignmentFault()
+{
+    return new AlphaAlignmentFault;
+}
+
 class ResetFault : public AlphaFault
 {
   private:
@@ -215,7 +241,4 @@ class IntegerOverflowFault : public AlphaFault
     FaultStat & stat() {return _stat;}
 };
 
-//Fault * ListOfFaults[];
-//int NumFaults;
-
 #endif // __FAULTS_HH__

cpu/base_dyn_inst.cc

@@ -45,6 +45,7 @@
 #include "cpu/o3/alpha_cpu.hh"
 
 using namespace std;
+using namespace TheISA;
 
 #define NOHASH
 #ifndef NOHASH
@@ -325,7 +326,7 @@ BaseDynInst<Impl>::mem_access(mem_cmd cmd, Addr addr, void *p, int nbytes)
         break;
 
       default:
-        fault = MachineCheckFault;
+        fault = genMachineCheckFault();
         break;
     }
 

dev/alpha_console.cc

@@ -182,7 +182,7 @@ AlphaConsole::read(MemReqPtr &req, uint8_t *data)
             }
             break;
         default:
-            return new MachineCheckFault;
+            return genMachineCheckFault();
     }
 
     return NoFault;
@@ -202,7 +202,7 @@ AlphaConsole::write(MemReqPtr &req, const uint8_t *data)
         val = *(uint64_t *)data;
         break;
       default:
-        return new MachineCheckFault;
+        return genMachineCheckFault();
     }
 
     Addr daddr = req->paddr - (addr & EV5::PAddrImplMask);

dev/pcidev.hh

@@ -260,6 +260,7 @@ class PciDev : public DmaDevice
 inline Fault
 PciDev::readBar(MemReqPtr &req, uint8_t *data)
 {
+    using namespace TheISA;
     if (isBAR(req->paddr, 0))
         return readBar0(req, req->paddr - BARAddrs[0], data);
     if (isBAR(req->paddr, 1))
@@ -272,12 +273,13 @@ PciDev::readBar(MemReqPtr &req, uint8_t *data)
         return readBar4(req, req->paddr - BARAddrs[4], data);
     if (isBAR(req->paddr, 5))
         return readBar5(req, req->paddr - BARAddrs[5], data);
-    return new MachineCheckFault;
+    return genMachineCheckFault();
 }
 
 inline Fault
 PciDev::writeBar(MemReqPtr &req, const uint8_t *data)
 {
+    using namespace TheISA;
     if (isBAR(req->paddr, 0))
         return writeBar0(req, req->paddr - BARAddrs[0], data);
     if (isBAR(req->paddr, 1))
@@ -290,7 +292,7 @@ PciDev::writeBar(MemReqPtr &req, const uint8_t *data)
         return writeBar4(req, req->paddr - BARAddrs[4], data);
     if (isBAR(req->paddr, 5))
         return writeBar5(req, req->paddr - BARAddrs[5], data);
-    return new MachineCheckFault;
+    return genMachineCheckFault();
 }
 
 #endif // __DEV_PCIDEV_HH__

dev/sinic.cc

@@ -363,11 +363,11 @@ Device::read(MemReqPtr &req, uint8_t *data)
     assert(config.command & PCI_CMD_MSE);
     Fault fault = readBar(req, data);
 
-    if (fault->isA<MachineCheckFault>()) {
+    if (fault->isMachineCheckFault()) {
         panic("address does not map to a BAR pa=%#x va=%#x size=%d",
               req->paddr, req->vaddr, req->size);
 
-        return new MachineCheckFault;
+        return genMachineCheckFault();
     }
 
     return fault;
@@ -459,11 +459,11 @@ Device::write(MemReqPtr &req, const uint8_t *data)
     assert(config.command & PCI_CMD_MSE);
     Fault fault = writeBar(req, data);
 
-    if (fault->isA<MachineCheckFault>()) {
+    if (fault->isMachineCheckFault()) {
         panic("address does not map to a BAR pa=%#x va=%#x size=%d",
               req->paddr, req->vaddr, req->size);
 
-        return new MachineCheckFault;
+        return genMachineCheckFault();
     }
 
     return fault;